Multi-scale clue fusion device based on memristor and multi-stimulus competition system

Abstract

The invention belongs to the related technical field of bionic circuit design, and discloses a memristor-based multi-scale clue fusion device and a multi-stimulus competition system, and the fusion device comprises a state generation module which comprises a volatile memristor, a positive correlation mapping circuit and a state comparison circuit; the stimulation intensity processing module comprises a memristor circuit, a subtraction circuit and a stimulation comparison circuit; the situation correlation processing module comprises a situation gating circuit, a memristor, a situation comparison circuit, a latch and a shaping circuit; the state feedback module comprises a state gating circuit; and the fusion module is used for carrying out weighted summation on the voltage and outputting a fusion saliency voltage. Based on the above design, the processing process of the organism on the multi-scale information can be reflected more truly, the real perceptibility of the organism on stimulation under the comprehensive influence of the multi-scale information is obtained, and the bionic accuracy is provided. Moreover, the memristor is introduced, so that the processing speed of the device can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field related to bionic circuit design, and more specifically, relates to a multi-scale clue fusion device and a multi-stimulus competition system based on a memristor. Background Art

[0002] In complex dynamic environments, organisms rely on multi-scale information (such as physical stimulus intensity, contextual relevance, and internal state) to selectively process information and thus perform adaptive behaviors. This adaptive perceptual processing mechanism is an important part of the cognitive process and has important implications for artificial systems simulating biological intelligence. However, traditional artificial circuits often have difficulty processing multi-scale and multi-dimensional input information simultaneously and making quick and accurate choices under limited resources. In addition, although existing digital logic-based systems have high accuracy in information processing, they are limited in energy consumption, integration, and real-time adaptability to dynamic information. Summary of the Invention

[0003] In response to the above-mentioned defects or improvement needs of the existing technology, the present invention provides a multi-scale cue fusion device and a multi-stimulus competition system based on memristors, the purpose of which is to quickly and accurately simulate the real perception of an organism to stimuli under the comprehensive influence of multi-scale information, and provide bionic accuracy.

[0004] To achieve the above objectives, according to a first aspect of the present invention, a multi-scale clue fusion device based on a memristor is provided, comprising:

[0005] A state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. The memristor VM1 is configured to receive a reward voltage and is in a high-resistance state when no reward voltage is present, with its resistance gradually decreasing when the reward voltage is applied. The positive correlation mapping circuit is configured to map the VM1 resistance to a voltage. The comparison circuit is configured to compare the mapped voltage with a state threshold voltage and output a starvation state voltage. The output is a high level when the mapped voltage exceeds the state threshold voltage, and a low level otherwise.

[0006] A stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit; wherein: the memristor circuit is used to adjust the memristor M1 according to the starvation state voltage; when the starvation state voltage is high, M1 is set to a low resistance state to output a high level; otherwise, M1 is reset to a high resistance state to output a low level; the subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1; the stimulation comparison circuit has an adjustable threshold voltage that is positively correlated with the voltage difference, is used to receive the stimulation voltage and compare it with the adjustable threshold voltage, and outputs a physical intensity voltage that is positively correlated with the stimulation voltage when the stimulation voltage is greater than the adjustable threshold voltage; otherwise, the physical intensity voltage remains low;

[0007] A context-relevance processing module includes a context-gating circuit, a memristor M2, a context-comparison circuit, a latch, and a shaping circuit; wherein: the context-gating circuit is used to receive a context voltage and is controlled by a physical strength voltage; the context-comparison circuit is used to compare the output voltage of M2 with a set context threshold voltage; when the context-gating circuit is turned on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage, and outputs a context-relevance voltage;

[0008] A state feedback module includes a state gating circuit that receives a physical strength voltage and is controlled by a starvation state voltage, and outputs an internal state voltage when the state gating circuit is turned on;

[0009] The fusion module is used to perform weighted summation on the physical intensity voltage, the context relevance voltage, and the internal state voltage, and output a fused saliency voltage.

[0010] Optionally, in the state generation module, the positive correlation mapping circuit includes an operational amplifier OP3, a resistor R7, and a voltage calculation module ABM1, wherein the voltage calculation module ABM1 is used to calculate the voltage difference between different input voltages; the state comparison circuit includes an operational amplifier OP4; wherein,

[0011] The first terminal of the memristor VM1 and the second terminal of the voltage calculation module ABM1 are respectively used to connect the reward voltage V i The second end of the memristor VM1 is connected to the first end of the resistor R7 and the negative input end of the operational amplifier OP3 respectively. The positive input end of the operational amplifier OP3 is grounded. The output end of the operational amplifier OP3 is connected to the second end of the resistor R7 and the first end of the voltage calculation module ABM1 respectively. The output end of the voltage calculation module ABM1 is connected to the positive input end of the operational amplifier OP4. The negative input end of the operational amplifier OP4 is connected to the state threshold voltage V th s The output terminal of the operational amplifier OP4 outputs a starvation state voltage.

[0012] Optionally, in the stimulation intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is a NOT gate; wherein,

[0013] The first input of adder A1 and the input of logic gate D1 are connected to the starvation state voltage respectively. The output of logic gate D1 is connected to the gate of NMOS tube N1. The drain of NMOS tube N1 is connected to the memristor reset voltage V rThe source of the NMOS tube N1 is connected to the second input terminal of the adder A1, the output terminal of the adder A1 is connected to the first terminal of the memristor M1, and the second terminal of the memristor M1 is connected to the subtraction circuit.

[0014] Optionally, in the stimulation intensity processing module, the subtraction circuit includes a resistor R1, a resistor R2, a resistor R3 and an operational amplifier OP1, and the stimulation comparison circuit includes an NMOS transistor N2, a resistor R4, a resistor R5 and a PMOS transistor P1; wherein,

[0015] The second end of the memristor M1 and the first end of the resistor R1 are respectively connected to the negative input terminal of the operational amplifier OP1, the second end of the resistor R1 is connected to the output terminal of the operational amplifier OP1, the second end of the resistor R2 and the first end of the resistor R3 are both connected to the positive input terminal of the first amplifier OP1, and the first end of the resistor R2 is used to connect the stimulation threshold voltage V th_p , the second end of the resistor R3 is grounded;

[0016] The source of NMOS tube N2 is connected to the output of operational amplifier OP1, and the gate of NMOS tube N2 and the source of PMOS tube P1 are used to access the stimulation voltage V s1 The drain of the NMOS tube N2 and the gate of the PMOS tube P1 are connected to the first end of the resistor R4, the second end of the resistor R4 is grounded, the drain of the PMOS tube P1 is connected to the first end of the resistor R5, and the second end of the resistor R5 is grounded; the drain of the PMOS tube P1 outputs a physical strength voltage.

[0017] Optionally, in the context correlation processing module, the context gating circuit includes a logic gate D2, a PMOS transistor P2, and an NMOS transistor N3; the logic gate D2 is a NOT gate; the context comparison circuit includes a resistor R6 and an operational amplifier OP2; wherein,

[0018] The input of logic gate D2 and the gate of NMOS transistor N3 are connected to the physical strength voltage. The output of logic gate D2 is connected to the gate of PMOS transistor P2. The drain of NMOS transistor N3 and the source of PMOS transistor P2 are respectively used to connect to the context voltage V c The source of the NMOS tube N3 and the drain of the PMOS tube P2 are connected to the first end of the memristor M2. The second end of the memristor M2 and the first end of the resistor R6 are respectively connected to the positive input end of the operational amplifier OP2. The second end of the resistor R6 is grounded. The negative input end of the operational amplifier OP2 is used to access the context threshold voltage V th_c , the output end of the operational amplifier OP2 is connected to the latch.

[0019] Optionally, in the state feedback module, the state gating circuit includes a logic gate D6, an NMOS transistor N4, and a PMOS transistor P3; the logic gate D6 is a NOT gate; wherein,

[0020] The input end of the logic gate D6 and the gate of the NMOS transistor N4 are both connected to the starvation state voltage. The gate of the PMOS transistor P3 is connected to the output end of the logic gate D6. The drain of the NMOS transistor N4 and the source of the PMOS transistor P3 are respectively used to connect to the physical strength voltage. The source of the NMOS transistor N4 and the drain of the PMOS transistor P3 are connected to output the internal state voltage.

[0021] According to a second aspect of the present invention, a multi-stimulus competition system based on a memristor is provided, which includes at least two multi-scale clue fusion devices and a comparison device, wherein:

[0022] The multi-scale clue fusion device is any of the multi-scale clue fusion devices described above, and different multi-scale clue fusion devices share the same state generation module;

[0023] The comparison device is used to compare the fusion saliency voltages output by each multi-scale cue fusion device in pairs and output the comparison result.

[0024] Optionally, the comparison device includes a subtractor, a window comparator module and a result output module; wherein,

[0025] The subtractor is used to subtract the first fused saliency voltage from the second fused saliency voltage; the first fused saliency voltage and the second fused saliency voltage are fused saliency voltages output by any two multi-scale cue fusion devices;

[0026] The window comparator module receives the output voltage of the subtractor and identifies the interval in which the output voltage of the subtractor is located, and outputs an interval level signal of the corresponding interval according to the different intervals in which the output voltage is located;

[0027] The result output module receives the interval level signal and generates a voltage signal reflecting the difference between the two fused significance voltages.

[0028] Optionally, the window comparator module includes NMOS tubes N9 to NMOS tubes N 13 , resistor R 14 ~Resistor R 17 and PMOS tube P7; among which,

[0029] The output of the subtractor is connected to the gate of the NMOS tube N9 and the NMOS tube N 11 The gate of the NMOS tube N9 is connected to the source of the NMOS tube N9, which is used to access the -1V voltage. The drain of the NMOS tube N9 is connected to the resistor R 14 The first end and the NMOS tube N 10 The gate is connected to the resistor R 14 The second end of the resistor R 16 The first end of the resistor R 15The second end of the PMOS tube P7 and the source of the PMOS tube P7 are used to access the 1V voltage, and the NMOS tube N 10 The drain and resistor R 16 The second end of the NMOS tube N 10 The source of NMOS tube N 11 The source of NMOS tube N 12 The source of NMOS tube N 13 The source of NMOS tube is grounded. 11 The drain, resistor R 15 The first end of the PMOS tube P7, the gate of the NMOS tube N 12 The gate of the PMOS tube P7 is connected to the drain of the NMOS tube N 12 The drain of NMOS tube N 13 The gate of NMOS tube N 13 The drain and resistor R 17 The second end of the resistor R 17 The first end is used to access the 1V voltage; the resistor R 16 The second end of the resistor R 17 The second end outputs the interval second level signal.

[0030] Optionally, the result output module includes a logic gate D 13 ~Logic Gate D 18 、NMOS tube N 14 ~NMOS tube N 16 , resistor R 18 ~Resistor R 20 ;Logic gate D 13 ~Logic Gate D 16 AND gate, logic gate D 17 、D 18 is a NOT gate; among them,

[0031] Logic Gate D 13 The two input terminals of the logic gate D are connected to the first level signal of the interval and the second level signal of the interval respectively. 17 The input terminal of the logic gate D is connected to the first level signal of the interval. 18 The input terminal of the logic gate D is connected to the second level signal of the interval. 14 The first input terminal of the logic gate D 13 The output of the logic gate D 14 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 15 The first input terminal of the logic gate D 17 The output of the logic gate D 15The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 16 The first input terminal of the logic gate D 18 The output of the logic gate D 16 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 14 The output end of the NMOS tube N 14 The gate of logic gate D 15 The output end of the NMOS tube N 15 The gate of logic gate D 16 The output end of the NMOS tube N 16 The gate of NMOS tube N 14 The drain of the NMOS tube is used to access the first driving voltage V1. 15 The drain of the NMOS tube is used to access the second driving voltage V2. 16 The drain of the NMOS tube is used to access the third driving voltage V3. 14 The source and resistor R 18 The second end of the resistor R 18 The first end of the NMOS tube is grounded, 15 The source and resistor R 19 The second end of the resistor R 19 The first end of the NMOS tube is grounded, 16 The source and resistor R 20 The second end of the resistor R 20 The first end of the NMOS tube is grounded, 14 The source output first inhibits the output voltage V inhibition , NMOS tube N 15 The source outputs the second winning output voltage V win_2 , NMOS tube N 16 The source output first wins the output voltage V win_1 , if the first suppression output voltage V inhibition =High level, indicating that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V l , V h ], if the second winning output voltage V win_2 High level, indicating that the second fusion significance voltage is greater than the first fusion significance voltage + V h , if the first winning output voltage V win_1 High level, indicating that the first fusion significance voltage is greater than the second fusion significance voltage + V l , V l 、Vh are the interval division values determined by the window comparator module.

[0032] In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:

[0033] 1. The present invention provides a multi-scale cue fusion device based on a memristor, which includes a state generation module, a stimulus intensity processing module, a context relevance processing module, a state feedback module, and a fusion module. The state generation module mainly simulates the effect of rewards on internal states. Different internal states result in different degrees of perception of external stimuli by the organism. The stimulus intensity processing module mainly simulates the effect of internal states on the organism's perception of the intensity of external physical stimuli. The context relevance processing module mainly simulates context relevance, thereby simulating the influence of the organism's perception of external stimuli under different environments. The state feedback module mainly simulates the cumulative effect of internal states on the organism's final perception of stimulus intensity. Based on the above design, the mutual influence of multi-scale signals can be reflected, thereby more realistically reflecting the organism's processing process of multi-scale information, obtaining the organism's true perception of stimuli under the comprehensive influence of multi-scale information, and providing biomimetic accuracy. In addition, the present invention introduces a memristor, whose superior storage and computing integration capabilities can accelerate the device's signal processing process, thereby improving the device's processing speed.

[0034] 2. The present invention provides a multi-stimulus competition system based on memristors, which simulates which stimulus an organism tends to respond to under a variety of different stimuli. This can be applied in different scenarios, greatly improving the adaptability and anti-interference ability of bionic sensing circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 1 is a schematic diagram of a framework of a multi-scale clue fusion device based on a memristor in one embodiment of the present invention;

[0036] Figure 2 is a circuit diagram of a state generation module in one embodiment of the present invention;

[0037] Figure 3 is a circuit diagram of a stimulation intensity processing module in one embodiment of the present invention;

[0038] Figure 4 is a circuit diagram of a context relevance processing module in one embodiment of the present invention;

[0039] Figure 5 is a circuit diagram of a state feedback module in one embodiment of the present invention;

[0040] Figure 6 1 is a schematic diagram of a framework of a multi-stimulus competition system based on a memristor in one embodiment of the present invention;

[0041] Figure 7 is a circuit diagram of a comparison device in one embodiment of the present invention;

[0042] Figure 8 is a specific circuit connection diagram of a multi-stimulus competition system based on a memristor in one embodiment of the present invention;

[0043] Figure 9 are the stimulation voltage and context voltage input under two different stimulation conditions in one embodiment of the present invention;

[0044] Figure 10 The input is Figure 9 The signal shown corresponds to the multi-scale signal generated inside the multi-scale cue fusion device;

[0045] Figure 11 The input is Figure 9 The competition output results of the multi-stimulus competition system after the signal is shown. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0047] The present invention provides a multi-scale cue fusion device based on memristors. This device comprehensively considers the interplay of external physical stimuli, contextual stimuli, and internal states, thereby simulating the stimulus intensity ultimately perceived by an organism under multiple signals. External physical stimuli refer to signals in the environment that directly act on the organism's senses and trigger a response, such as ringtones, food, or electric shocks. Contextual stimuli are stimuli associated with a specific scene or background. They typically do not directly trigger a single response, but instead provide contextual cues for behavior or memory, such as a familiar room layout. Internal states refer to physiological or psychological states within an organism that influence responses to external stimuli, such as hunger, anxiety, and fatigue.

[0048] like Figure 1 FIG2 is a schematic diagram of a framework of a multi-scale cue fusion device based on a memristor in an embodiment of the present invention, which mainly includes a state generation module, a stimulus intensity processing module, a context relevance processing module, a state feedback module and a fusion module.

[0049] The state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. The memristor VM1 is used to receive a reward voltage. When there is no reward voltage, it is in a high-resistance state and its resistance gradually decreases when the reward voltage is applied. The positive correlation mapping circuit is used to map the resistance of VM1 into a voltage. The comparison circuit is used to compare the mapped voltage with a state threshold voltage and output a starvation state voltage. When the mapped voltage exceeds the state threshold voltage, the output is a high level, otherwise it is a low level.

[0050] Specifically, the state generation module simulates the effect of rewards on internal states. Different internal states lead to different levels of perception of external stimuli. The reward voltage is a signal that can weaken the organism's sensitivity to external stimuli. If the reward voltage persists long enough, the organism will not even perceive the external stimulus.

[0051] The working mechanism of the state generation module is that when there is no reward, the hunger state voltage output by the module is high. When a sufficiently large reward voltage is input and the duration of the reward voltage reaches a certain level, the hunger state voltage will change from high to low, and the high and low levels will reflect whether the reward is effective.

[0052] In the state generation module, a volatile memristor VM1 is introduced, and a positive correlation mapping circuit and a state comparison circuit are designed. In the absence of a reward voltage, the volatile memristor VM1 is in a high-impedance state (reset state) and can spontaneously reset to its original high-impedance state when the reward voltage is removed. When a reward voltage is applied, the resistance of the volatile memristor VM1 gradually decreases, reflecting the cumulative effect of the continuous reward. The positive correlation mapping circuit maps the resistance of VM1 to a voltage, creating a positive correlation between voltage and resistance. As the resistance of the volatile memristor VM1 decreases, the mapped voltage output by the positive correlation mapping circuit also decreases. The comparison circuit compares the mapped voltage with the state threshold voltage and outputs a starvation-state voltage. In the absence of a reward voltage, the volatile memristor VM1 is in a high-impedance state, the mapped voltage is higher than the state threshold voltage, and the starvation-state voltage is high. Only when a reward is applied and sustained for a certain period of time, until the resistance of the volatile memristor VM1 gradually decreases, causing the mapped voltage to drop below the state threshold voltage, does the starvation-state voltage transition from high to low. Once the reward voltage is removed, the starvation-state voltage jumps back from low to high. A high level indicates that no valid reward has been generated, while a low level indicates that a valid reward has been generated. Whether the reward is valid reflects the organism's internal state and influences its ultimate stimulus perception.

[0053] A stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit; wherein: the memristor circuit is used to adjust the memristor M1 according to the starvation state voltage. When the starvation state voltage is high, M1 is set to a low-resistance state to output a high level; otherwise, M1 is reset to a high-resistance state to output a low level; the subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1; the adjustable threshold voltage of the stimulation comparison circuit is positively correlated with the voltage difference, and is used to receive the stimulation voltage and compare it with the adjustable threshold voltage. When the stimulation voltage is greater than the adjustable threshold voltage, a physical intensity voltage positively correlated with the stimulation voltage is output; otherwise, the physical intensity voltage remains at a low level.

[0054] Specifically, the stimulus intensity processing module mainly simulates the impact of internal state on the organism's perception of the intensity of external physical stimuli.

[0055] The working mechanism of the stimulation intensity processing module is that when there is no effective reward, the internal state of the organism basically does not affect the organism's perception of external physical stimulation, and the physical intensity voltage output by the stimulation intensity processing module is basically equivalent to the stimulation voltage it receives. When there is an effective reward, the organism's perception of external physical stimulation is suppressed by the internal state of the organism, and the physical intensity voltage output by the stimulation intensity processing module is small or even no output.

[0056] The stimulation intensity processing module specifically incorporates a memristor circuit, a subtraction circuit, and a stimulation comparison circuit. The memristor circuit is used to adjust the output voltage of memristor M1 based on the hunger state voltage. This, in turn, adjusts the voltage difference between the set voltage and M1's output voltage, which in turn adjusts the adjustable threshold voltage of the comparison circuit, ultimately outputting different physical intensity voltages.

[0057] When there is no effective reward, the hunger state voltage is high. At this time, M1 is set to a low-resistance state, and its output voltage is high. The subtraction circuit subtracts the set voltage from the M1 output voltage. Therefore, the voltage difference output by the subtraction circuit is small, and the adjustable threshold voltage is positively correlated with the voltage difference. The smaller the voltage difference, the smaller the adjustable threshold voltage. Therefore, when the adjustable threshold voltage is small, a smaller stimulation voltage can also pass through the stimulation intensity processing module and output a physical intensity voltage that is basically the same as the received stimulation voltage intensity.

[0058] When there is a valid reward, the hunger state voltage is low. At this time, M1 is reset to a high-impedance state, and its output voltage is low. The subtraction circuit subtracts the set voltage from the M1 output voltage. Therefore, the voltage difference output by the subtraction circuit is large, and the adjustable threshold voltage is positively correlated with the voltage difference. The larger the voltage difference, the larger the adjustable threshold voltage. Therefore, when the adjustable threshold voltage is large, the smaller stimulation voltage cannot pass through the stimulation intensity processing module. That is, when there is a valid reward, it will affect the organism's perception of external stimulation. Only when the external stimulation is large enough will the stimulation intensity processing module output a physical intensity voltage.

[0059] A context-relevance processing module includes a context-gating circuit, a memristor M2, a context-comparison circuit, a latch, and a shaping circuit; wherein: the context-gating circuit is used to receive a context voltage and is controlled by a physical strength voltage; the context-comparison circuit is used to compare the output voltage of M2 with a set context threshold voltage; when the context-gating circuit is turned on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage, and outputs a context-relevance voltage.

[0060] Specifically, the context relevance processing module mainly simulates context relevance, thereby simulating the perceptual influence of an organism on external stimuli in different environments.

[0061] The working mechanism of the context-relevance processing module is that when the stimulus intensity processing module is able to generate a physical intensity voltage, the organism's final perception of the stimulus will also be superimposed with the influence of the context signal, that is, the context-relevance processing module will generate a context-relevance voltage as a perception gain.

[0062] The context-relevance processing module incorporates a context-gating circuit, a memristor M2, a context comparison circuit, a latch, and a shaping circuit. The context-gating circuit receives a context voltage and is controlled by the physical intensity voltage. When both the physical intensity voltage and the context voltage are present, the context-gating circuit is turned on, and the context voltage is applied to the memristor M2, setting the memristor M2 to a low resistance state. The memristor M2 outputs a high level, and the memristor M2 output voltage is greater than the context threshold voltage. The context comparator outputs a high level. This high level is latched by the latch and then logically ANDed with the original physical intensity voltage to achieve shaping, outputting a context-relevance voltage with the same waveform as the original physical intensity voltage. If the stimulus intensity processing module does not sense the physical intensity voltage, the context-relevance processing module also does not output a context-relevance voltage. It should be noted that because context signals typically persist for a long time, the memristor M2 can be a non-volatile memristor with long-term memory. Once the context voltage sets the memristor M2 to a low resistance state, its state remains unchanged.

[0063] The state feedback module includes a state gating circuit that receives the physical strength voltage and is controlled by the starvation state voltage. When the state gating circuit is turned on, the internal state voltage is output.

[0064] Specifically, the state feedback module mainly simulates the superimposed influence of the internal state on the organism's final perception of stimulus intensity.

[0065] The working mechanism of the state feedback module is that when there is no valid reward, the state feedback module generates an internal state voltage that enhances the final stimulus perception. When there is a valid reward, the state feedback module will not have an enhancing effect on the final stimulus perception.

[0066] In the state feedback module, a state gating circuit is introduced. When there is no valid reward, the hunger state voltage is high, the state gating circuit is turned on, and the state feedback module outputs an internal state voltage that is positively correlated with the physical strength voltage. When there is a valid reward, the hunger state voltage is low, the state gating circuit is turned off, and the state feedback module has no output.

[0067] The fusion module is used to perform weighted summation on the physical intensity voltage, the context relevance voltage, and the internal state voltage, and output a fused saliency voltage.

[0068] Specifically, the fusion module mainly fuses the voltages output by the above modules to obtain the final fusion saliency voltage, which reflects the intensity of the organism's final perception of external physical stimuli under certain circumstances and reward conditions.

[0069] In one embodiment, if Figure 2As shown, in the state generation module, its positive correlation mapping circuit includes an operational amplifier OP3, a resistor R7, and a voltage calculation module ABM1. The voltage calculation module ABM1 is used to calculate the voltage difference between different input voltages; its state comparison circuit includes an operational amplifier OP4.

[0070] The specific circuit connection is as follows: the first end of the memristor VM1 and the second end of the voltage calculation module ABM1 are respectively used to access the reward voltage V i The second end of the memristor VM1 is connected to the first end of the resistor R7 and the negative input end of the operational amplifier OP3 respectively. The positive input end of the operational amplifier OP3 is grounded. The output end of the operational amplifier OP3 is connected to the second end of the resistor R7 and the first end of the voltage calculation module ABM1 respectively. The output end of the voltage calculation module ABM1 is connected to the positive input end of the operational amplifier OP4. The negative input end of the operational amplifier OP4 is connected to the state threshold voltage V th_s The output terminal of the operational amplifier OP4 outputs a starvation state voltage.

[0071] Its specific working principle is: if there is no reward voltage V i , the memristor VM1 is in high impedance state, its output voltage is high, the operational amplifier OP3 outputs a low level, the voltage calculation module ABM1 outputs a high level, and the operational amplifier OP4 outputs a high level; if the reward voltage V i , the resistance of the memristor VM1 gradually decreases, and the voltage at its output terminal gradually decreases until the operational amplifier OP3 outputs a high level, the voltage calculation module ABM1 outputs a low level, and the operational amplifier OP4 outputs a low level; if the reward is revoked, the memristor VM1 spontaneously recovers to a high-impedance state, the voltage at its output terminal is higher, the operational amplifier OP3 outputs a low level, the voltage calculation module ABM1 outputs a high level, and the operational amplifier OP4 outputs a high level.

[0072] In one embodiment, if Figure 3 As shown, in the stimulation intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is a NOT gate.

[0073] The specific circuit connection is as follows: the first input terminal of adder A1 and the input terminal of logic gate D1 are respectively connected to the starvation state voltage, the output terminal of logic gate D1 is connected to the gate of NMOS tube N1, and the drain of NMOS tube N1 is connected to the memristor reset voltage V r The source of the NMOS tube N1 is connected to the second input terminal of the adder A1, the output terminal of the adder A1 is connected to the first terminal of the memristor M1, and the second terminal of the memristor M1 is connected to the subtraction circuit.

[0074] The specific working principle is: when the voltage in the starvation state is high, the NMOS tube N1 is turned off and the reset voltage V is not connected.r , the starvation state voltage sets the memristor M1 to a low resistance state, and its output voltage is high; when the starvation state voltage is low, the NMOS tube N1 is turned on and the reset voltage V r (negative voltage), the memristor M1 is reset to a high-resistance state, and the voltage at its output terminal is low.

[0075] In one embodiment, continue as Figure 3 As shown, in the stimulation intensity processing module, the subtraction circuit includes resistors R1, R2, R3 and operational amplifier OP1, and the stimulation comparison circuit includes NMOS transistor N2, resistors R4, R5 and PMOS transistor P1.

[0076] The specific circuit connection is as follows: the second end of the memristor M1 and the first end of the resistor R1 are respectively connected to the negative input terminal of the operational amplifier OP1, the second end of the resistor R1 is connected to the output terminal of the operational amplifier OP1, the second end of the resistor R2 and the first end of the resistor R3 are both connected to the positive input terminal of the first amplifier OP1, and the first end of the resistor R2 is used to connect to the stimulation threshold voltage V th_p The second end of the resistor R3 is grounded; the source of the NMOS tube N2 is connected to the output end of the operational amplifier OP1, and the gate of the NMOS tube N2 and the source of the PMOS tube P1 are used to access the stimulus voltage V s1 The drain of the NMOS tube N2 and the gate of the PMOS tube P1 are connected to the first end of the resistor R4, the second end of the resistor R4 is grounded, the drain of the PMOS tube P1 is connected to the first end of the resistor R5, and the second end of the resistor R5 is grounded; the drain of the PMOS tube P1 outputs a physical strength voltage.

[0077] Its specific working principle is: when the memristor M1 outputs a low level, the voltage difference output by the operational amplifier OP1 is large, resulting in a higher source potential of the NMOS tube N2, and then making the adjustable threshold voltage of the NMOS tube N2 larger. Therefore, only a larger stimulation voltage can turn on the NMOS tube N2 and output a positively correlated physical strength voltage, and a smaller stimulation voltage cannot stimulate the generation of a positively correlated physical strength voltage; when the memristor M1 outputs a high level, the voltage difference output by the operational amplifier OP1 is small, resulting in a lower source potential of the NMOS tube N2, and then making the adjustable threshold voltage of the NMOS tube N2 smaller. Therefore, a smaller stimulation voltage can also turn on the NMOS tube N2 and output a positively correlated physical strength voltage.

[0078] In one embodiment, if Figure 4 As shown, in the context correlation processing module, the context gating circuit includes a logic gate D2, a PMOS transistor P2, and an NMOS transistor N3; the logic gate D2 is a NOT gate; and the context comparison circuit includes a resistor R6 and an operational amplifier OP2.

[0079] The specific circuit connection is as follows: the input end of the logic gate D2 and the gate of the NMOS tube N3 are connected to the physical strength voltage, the output end of the logic gate D2 is connected to the gate of the PMOS tube P2, and the drain of the NMOS tube N3 and the source of the PMOS tube P2 are respectively used to connect to the context voltage V c1 The source of the NMOS tube N3 and the drain of the PMOS tube P2 are connected to the first end of the memristor M2. The second end of the memristor M2 and the first end of the resistor R6 are respectively connected to the positive input end of the operational amplifier OP2. The second end of the resistor R6 is grounded. The negative input end of the operational amplifier OP2 is used to access the context threshold voltage V th c , the output end of the operational amplifier OP2 is connected to the latch.

[0080] The specific working principle is as follows: the initial state of the memristor M2 is the reset state, that is, the high impedance state, and its output is low level, and the operational amplifier OP2 outputs a low level; when the physical strength voltage turns on the context gate circuit, the context voltage V c The memristor M2 is set to a low resistance state, and its output is high level, and the operational amplifier OP2 outputs a high level.

[0081] Furthermore, in the context relevance processing module, the latch uses an SR trigger, which includes logic gates D3 and D4, and the shaping circuit includes logic gate D5; logic gates D3 and D4 are both NOR gates, and logic gate D5 is an AND gate. The output of operational amplifier OP2 is connected to the first input of logic gate D3; the second input of logic gate D3 is connected to the output of logic gate D4 and the second input of logic gate D5, the second input of logic gate D5 obtains the physical strength voltage, the output of logic gate D3 is connected to the first input of logic gate D4, and the second input of logic gate D4 is connected to the trigger reset voltage V rst The output of logic gate D5 outputs a context-dependent voltage.

[0082] In one embodiment, if Figure 5 As shown, in the state feedback module, the state gating circuit includes a logic gate D6, an NMOS transistor N4 and a PMOS transistor P3; the logic gate D6 is a NOT gate.

[0083] The specific circuit connection is as follows: the input end of the logic gate D6 and the gate of the NMOS tube N4 are both connected to the starvation state voltage, the gate of the PMOS tube P3 is connected to the output end of the logic gate D6, the drain of the NMOS tube N4 and the source of the PMOS tube P3 are respectively used to connect to the physical strength voltage, and the source of the NMOS tube N4 and the drain of the PMOS tube P3 are connected to output the internal state voltage.

[0084] Its specific working principle is: when the starvation state voltage is at a high level, the state gating circuit is turned on, the physical strength voltage passes through the state gating circuit, and outputs an internal state voltage positively correlated with it; when the starvation state voltage is at a low level, the state gating circuit is turned off, and the internal state voltage is empty at this time.

[0085] In one embodiment, the fusion module may be a weighted adder A3 , wherein the physical intensity voltage, the contextual relevance voltage, and the internal state voltage are input into the three input terminals of the adder A3 respectively, and the fusion saliency voltage is output after weighted summation.

[0086] The present invention also provides a multi-stimulus competition system based on a memristor, which can simulate which stimulus an organism is more inclined to respond to when faced with multiple different external stimuli.

[0087] like Figure 6 The figure shows a schematic diagram of the framework of a memristor-based multi-stimulus competition system in one embodiment of the present invention. The system includes at least two multi-scale cue fusion devices as described above and a comparison device. The different multi-scale cue fusion devices share the same state generation module. The comparison device is used to perform pairwise comparisons of the fused saliency voltages output by the multi-scale cue fusion devices and output the comparison results.

[0088] In one embodiment, only the magnitude relationship of the fused significance voltages may be determined, that is, only their relative magnitudes need to be determined. In this case, only a simple comparison circuit needs to be provided to achieve this.

[0089] Taking into account that in actual situations, when the fusion significance voltages obtained from two stimuli are relatively close, there is a certain randomness in which stimulus is responded to. Therefore, in some embodiments, a subtractor, a window comparator module and a result output module are set in the comparison device, and three comparison results can be obtained, namely, the two fusion significance voltages are close, the first fusion significance voltage is significantly larger, or the second fusion significance voltage is significantly larger.

[0090] Specifically, the subtractor is used to subtract the first fusion saliency voltage from the second fusion saliency voltage; the first fusion saliency voltage and the second fusion saliency voltage are fusion saliency voltages output by any two multi-scale cue fusion devices; the window comparator module receives the output voltage of the subtractor and identifies the interval in which the output voltage of the subtractor is located, and outputs an interval level signal corresponding to the interval according to the different intervals; the result output module receives the interval level signal and generates a voltage signal reflecting the difference between the two fusion saliency voltages.

[0091] Specifically, refer to Figure 7 As shown, the window comparator module includes NMOS tubes N9 to NMOS tubes N 13 , resistor R 14~Resistor R 17 And PMOS tube P7.

[0092] The specific circuit connection is: the output end of the subtractor is connected to the gate of the NMOS tube N9, the NMOS tube N 11 The gate of the NMOS tube N9 is connected to the source of the NMOS tube N9, which is used to access the -1V voltage. The drain of the NMOS tube N9 is connected to the resistor R 14 The first end and the NMOS tube N 10 The gate is connected to the resistor R 14 The second end of the resistor R 16 The first end of the resistor R 15 The second end of the PMOS tube P7 and the source of the PMOS tube P7 are used to access the 1V voltage, and the NMOS tube N 10 The drain and resistor R 16 The second end of the NMOS tube N 10 The source of NMOS tube N 11 The source of NMOS tube N 12 The source of NMOS tube N 13 The source of NMOS tube is grounded. 11 The drain, resistor R 15 The first end of the PMOS tube P7, the gate of the NMOS tube N 12 The gate of the PMOS tube P7 is connected to the drain of the NMOS tube N 12 The drain of NMOS tube N 13 The gate of NMOS tube N 13 The drain and resistor R 17 The second end of the resistor R 17 The first end is used to access the 1V voltage; the resistor R 16 The second end of the resistor R 17 The second end outputs the interval second level signal.

[0093] Its specific working principle is: by adjusting the resistance R 14 and resistor R 15 The value of V can be used to adjust the interval division value l 、V h , let △V = the difference between the second fusion significance voltage and the first fusion significance voltage, if -V l ≤△V≤V h , indicating that the two are relatively close, then the first level signal in the interval is high level, and the second level signal in the interval is high level; if △V<-V l , indicating that the first fusion significance voltage is significantly larger, then the first level signal in the interval is low level, and the second level signal in the interval is high level; if △V>-V h, indicating that the second fusion significance voltage is significantly larger, the second level signal in the interval is low, and the first level signal in the interval is high. The difference in the interval level signals reflects the competition result.

[0094] In one embodiment, continue to refer to Figure 7 As shown, the result output module includes logic gate D 13 ~Logic Gate D 18 、NMOS tube N 14 ~NMOS tube N 16 , resistor R 18 ~Resistor R 20 ;Logic gate D 13 ~Logic Gate D 16 AND gate, logic gate D 17 、D 18 It is a NOT gate.

[0095] The specific circuit connection is: logic gate D 13 The two input terminals of the logic gate D are connected to the first level signal of the interval and the second level signal of the interval respectively. 17 The input terminal of the logic gate D is connected to the first level signal of the interval. 18 The input terminal of the logic gate D is connected to the second level signal of the interval. 14 The first input terminal of the logic gate D 13 The output of the logic gate D 14 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 15 The first input terminal of the logic gate D 17 The output of the logic gate D 15 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 16 The first input terminal of the logic gate D 18 The output of the logic gate D 16 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 14 The output end of the NMOS tube N 14 The gate of the logic gate D 15 The output end of the NMOS tube N 15 The gate of the logic gate D 16 The output end of the NMOS tube N 16 The gate of NMOS tube N 14 The drain of the NMOS tube is used to access the first driving voltage V1. 15The drain of the NMOS tube is used to access the second driving voltage V2. 16 The drain of the NMOS tube is used to access the third driving voltage V3. 14 The source and resistor R 18 The second end of the resistor R 18 The first end of the NMOS tube is grounded, 15 The source and resistor R 19 The second end of the resistor R 19 The first end of the NMOS tube is grounded, 16 The source and resistor R 20 The second end of the resistor R 20 The first end of the NMOS tube is grounded, 14 The source output first inhibits the output voltage V inhibition , NMOS tube N 15 The source outputs the second winning output voltage V win_2 , NMOS tube N 16 The source output first wins the output voltage V win_1 , if the first suppression output voltage V inhibition =High level, indicating that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V l , V h ], if the second winning output voltage V win_2 High level, indicating that the second fusion significance voltage is greater than the first fusion significance voltage + V h , if the first winning output voltage V win_1 High level, indicating that the first fusion significance voltage is greater than the second fusion significance voltage + V l , V l 、V h are the interval division values determined by the window comparator module.

[0096] Its specific working principle is: If -V l ≤△V≤V h , indicating that the two are close, the first level signal in the interval is high, and the second level signal in the interval is high. At this time, the logic gate D 13 Output high level, through logic gate D 14 Reshape and output the first suppressed output voltage V inhibition , at this time, the other two output terminals have no output; if △V<-V l , indicating that the first fusion significance voltage is significantly larger, the first level signal in the interval is low, and the second level signal in the interval is high. At this time, the logic gate D 18 Output high level, through logic gate D 16 Perform shaping and output the first winning output voltage V win_1At this time, the other two output terminals have no output; if △V>-V h , indicating that the second fusion significance voltage is significantly larger, the second level signal in the interval is low, and the first level signal in the interval is high. At this time, the logic gate D 17 Output high level, through logic gate D 15 Reshape and output the second winning output voltage V win_2 , at this time, the other two output terminals have no output.

[0097] like Figure 8 FIG2 is a specific circuit connection diagram of a memristor-based multi-stimulus competition system according to an embodiment of the present invention. In order to distinguish between the two multi-scale cue fusion devices, the components in the different devices are labeled differently.

[0098] like Figure 9 The figure shows the stimulation voltage and situation voltage input under two different stimulation conditions in one embodiment of the present invention, wherein V s1 is the stimulus voltage input under the first stimulus, V c1 is the context voltage associated with the first stimulus; V s2 is the stimulation voltage input under the second stimulation, V c2 is the contextual voltage associated with the second stimulus.

[0099] like Figure 10 The input is shown as Figure 9 The signal shown corresponds to the multi-scale signal generated inside the multi-scale clue fusion device, where V s1_p and V s2_p are the physical stimulus intensity signals of the first stimulus and the second stimulus, V s1_c and V s2_c are the context-related signals of the first and second stimuli, V s1_s and V s2_s are the internal state signals for the first and second stimuli, respectively.

[0100] like Figure 11 The input is shown as Figure 9 The competition output results of the multi-stimulus competition system after the signal shown are as follows. It can be seen that within the time of 0 to 3s, the first stimulus wins, and the organism tends to respond to the first stimulus. Within the time of 3s to 4s, the two stimuli are relatively close, and the organism's response has a certain degree of randomness. Within the time of 4s to 8s, the second stimulus wins, and the organism tends to respond to the second stimulus.

[0101] The technical features of the above-described embodiments may be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. It should be noted that the phrases "in one embodiment," "for example," "and another example," etc., of the present invention are intended to illustrate the present invention and are not intended to limit the present invention.

[0102] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A multi-scale clue fusion device based on memristor, characterized in that: include; A state generation module includes a volatile memristor VM1, a positive correlation mapping circuit, and a state comparison circuit. The memristor VM1 is configured to receive a reward voltage and is in a high-resistance state when no reward voltage is present, with its resistance gradually decreasing when the reward voltage is applied. The positive correlation mapping circuit is configured to map the VM1 resistance to a voltage. The comparison circuit is configured to compare the mapped voltage with a state threshold voltage and output a starvation state voltage. The output is a high level when the mapped voltage exceeds the state threshold voltage, and a low level otherwise. A stimulation intensity processing module includes a memristor circuit, a subtraction circuit, and a stimulation comparison circuit; wherein: the memristor circuit is used to adjust the memristor M1 according to the starvation state voltage; when the starvation state voltage is high, M1 is set to a low resistance state to output a high level; otherwise, M1 is reset to a high resistance state to output a low level; the subtraction circuit calculates the voltage difference between the set voltage and the output voltage of M1; the stimulation comparison circuit has an adjustable threshold voltage that is positively correlated with the voltage difference, is used to receive the stimulation voltage and compare it with the adjustable threshold voltage, and outputs a physical intensity voltage that is positively correlated with the stimulation voltage when the stimulation voltage is greater than the adjustable threshold voltage; otherwise, the physical intensity voltage remains low; A context-relevance processing module includes a context-gating circuit, a memristor M2, a context-comparison circuit, a latch, and a shaping circuit; wherein: the context-gating circuit is used to receive a context voltage and is controlled by a physical strength voltage; the context-comparison circuit is used to compare the output voltage of M2 with a set context threshold voltage; when the context-gating circuit is turned on, the context voltage is applied to M2; if the context voltage does not reach the set threshold, M2 is in a high-impedance state, and the context comparator outputs a low level; otherwise, M2 is set to a low-impedance state, and the context comparator outputs a high level; the latch latches the output voltage of the context comparator; the shaping circuit performs a logical AND operation on the latch output voltage and the physical strength voltage, and outputs a context-relevance voltage; A state feedback module includes a state gating circuit that receives a physical strength voltage and is controlled by a starvation state voltage, and outputs an internal state voltage when the state gating circuit is turned on; The fusion module is used to perform weighted summation on the physical intensity voltage, the context relevance voltage, and the internal state voltage, and output a fused saliency voltage.

2. The multi-scale clue fusion device based on memristor according to claim 1, characterized in that: In the state generation module, the positive correlation mapping circuit includes an operational amplifier OP3, a resistor R7, and a voltage calculation module ABM1. The voltage calculation module ABM1 is used to calculate the voltage difference between different input voltages; the state comparison circuit includes an operational amplifier OP4; wherein, The first terminal of the memristor VM1 and the second terminal of the voltage calculation module ABM1 are respectively used to connect the reward voltage V i The second end of the memristor VM1 is connected to the first end of the resistor R7 and the negative input end of the operational amplifier OP3 respectively. The positive input end of the operational amplifier OP3 is grounded. The output end of the operational amplifier OP3 is connected to the second end of the resistor R7 and the first end of the voltage calculation module ABM1 respectively. The output end of the voltage calculation module ABM1 is connected to the positive input end of the operational amplifier OP4. The negative input end of the operational amplifier OP4 is connected to the state threshold voltage V th_s The output terminal of the operational amplifier OP4 outputs a starvation state voltage.

3. The multi-scale clue fusion device based on memristor according to claim 1, characterized in that: In the stimulation intensity processing module, the memristor circuit includes an adder A1, a logic gate D1, a memristor M1, and an NMOS transistor N1; the logic gate D1 is a NOT gate; wherein, The first input of adder A1 and the input of logic gate D1 are connected to the starvation state voltage respectively. The output of logic gate D1 is connected to the gate of NMOS tube N1. The drain of NMOS tube N1 is connected to the memristor reset voltage V r The source of the NMOS tube N1 is connected to the second input terminal of the adder A1, the output terminal of the adder A1 is connected to the first terminal of the memristor M1, and the second terminal of the memristor M1 is connected to the subtraction circuit.

4. The multi-scale clue fusion device based on memristor according to claim 3, characterized in that: In the stimulation intensity processing module, the subtraction circuit includes resistors R1, R2, R3 and operational amplifier OP1, and the stimulation comparison circuit includes NMOS transistor N2, resistors R4, R5 and PMOS transistor P1; wherein, The second end of the memristor M1 and the first end of the resistor R1 are respectively connected to the negative input terminal of the operational amplifier OP1, the second end of the resistor R1 is connected to the output terminal of the operational amplifier OP1, the second end of the resistor R2 and the first end of the resistor R3 are both connected to the positive input terminal of the first amplifier OP1, and the first end of the resistor R2 is used to connect the stimulation threshold voltage V th_p , the second end of the resistor R3 is grounded; The source of NMOS tube N2 is connected to the output of operational amplifier OP1, and the gate of NMOS tube N2 and the source of PMOS tube P1 are used to access the stimulation voltage V s1 The drain of the NMOS tube N2 and the gate of the PMOS tube P1 are connected to the first end of the resistor R4, the second end of the resistor R4 is grounded, the drain of the PMOS tube P1 is connected to the first end of the resistor R5, and the second end of the resistor R5 is grounded; the drain of the PMOS tube P1 outputs a physical strength voltage.

5. The multi-scale clue fusion device based on memristor according to claim 1, characterized in that: In the context relevance processing module, the context gating circuit includes a logic gate D2, a PMOS transistor P2, and an NMOS transistor N3; the logic gate D2 is a NOT gate; the context comparison circuit includes a resistor R6 and an operational amplifier OP2; wherein, The input of logic gate D2 and the gate of NMOS transistor N3 are connected to the physical strength voltage. The output of logic gate D2 is connected to the gate of PMOS transistor P2. The drain of NMOS transistor N3 and the source of PMOS transistor P2 are respectively used to connect to the context voltage V c The source of the NMOS tube N3 and the drain of the PMOS tube P2 are connected to the first end of the memristor M2. The second end of the memristor M2 and the first end of the resistor R6 are respectively connected to the positive input end of the operational amplifier OP2. The second end of the resistor R6 is grounded. The negative input end of the operational amplifier OP2 is used to access the context threshold voltage V th_c , the output end of the operational amplifier OP2 is connected to the latch.

6. The multi-scale clue fusion device based on memristor according to claim 1, characterized in that: In the state feedback module, the state gating circuit includes a logic gate D6, an NMOS transistor N4, and a PMOS transistor P3; the logic gate D6 is a NOT gate; wherein, The input end of the logic gate D6 and the gate of the NMOS transistor N4 are both connected to the starvation state voltage. The gate of the PMOS transistor P3 is connected to the output end of the logic gate D6. The drain of the NMOS transistor N4 and the source of the PMOS transistor P3 are respectively used to connect to the physical strength voltage. The source of the NMOS transistor N4 and the drain of the PMOS transistor P3 are connected to output the internal state voltage.

7. A multi-stimulus competition system based on memristor, characterized in that: It includes at least two multi-scale clue fusion devices and a comparison device, wherein, The multi-scale clue fusion device is the multi-scale clue fusion device according to any one of claims 1 to 6, and different multi-scale clue fusion devices share the same state generation module; The comparison device is used to compare the fusion saliency voltages output by each multi-scale cue fusion device in pairs and output the comparison result.

8. The memristor-based multi-stimulus competition system according to claim 7, wherein: The comparison device includes a subtractor, a window comparator module and a result output module; wherein, The subtractor is used to subtract the first fused saliency voltage from the second fused saliency voltage; the first fused saliency voltage and the second fused saliency voltage are fused saliency voltages output by any two multi-scale cue fusion devices; The window comparator module receives the output voltage of the subtractor and identifies the interval in which the output voltage of the subtractor is located, and outputs an interval level signal of the corresponding interval according to the different intervals in which the output voltage is located; The result output module receives the interval level signal and generates a voltage signal reflecting the difference between the two fused significance voltages.

9. The memristor-based multi-stimulus competition system according to claim 8, wherein: The window comparator module includes NMOS tubes N9 to NMOS tubes N 13 , resistor R 14 ~Resistor R 17 and PMOS tube P7; among which, The output of the subtractor is connected to the gate of the NMOS tube N9 and the NMOS tube N 11 The gate of the NMOS tube N9 is connected to the source of the NMOS tube N9, which is used to access the -1V voltage. The drain of the NMOS tube N9 is connected to the resistor R 14 The first end and the NMOS tube N 10 The gate is connected to the resistor R 14 The second end of the resistor R 16 The first end of the resistor R 15 The second end of the PMOS tube P7 and the source of the PMOS tube P7 are used to access the 1V voltage, and the NMOS tube N 10 The drain and resistor R 16 The second end of the NMOS tube N 10 The source of NMOS tube N 11 The source of NMOS tube N 12 The source of NMOS tube N 13 The source of NMOS tube is grounded. 11 The drain, resistor R 15 The first end of the PMOS tube P7, the gate of the NMOS tube N 12 The gate of the PMOS tube P7 is connected to the drain of the NMOS tube N 12 The drain of NMOS tube N 13 The gate of NMOS tube N 13 The drain and resistor R 17 The second end of the resistor R 17 The first end is used to access the 1V voltage; the resistor R 16 The second end of the resistor R 17 The second end outputs the interval second level signal.

10. The memristor-based multi-stimulus competition system according to claim 9, wherein: The result output module includes logic gate D 13 ~Logic Gate D 18 、NMOS tube N 14 ~NMOS tube N 16 , resistor R 18 ~Resistor R 20 ;Logic gate D 13 ~Logic Gate D 16 AND gate, logic gate D 17 、D 18 is a NOT gate; among them, Logic Gate D 13 The two input terminals of the logic gate D are connected to the first level signal of the interval and the second level signal of the interval respectively. 17 The input terminal of the logic gate D is connected to the first level signal of the interval. 18 The input terminal of the logic gate D is connected to the second level signal of the interval. 14 The first input terminal of the logic gate D 13 The output of the logic gate D 14 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 15 The first input terminal of the logic gate D 17 The output of the logic gate D 15 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 16 The first input terminal of the logic gate D 18 The output of the logic gate D 16 The second input terminal and the third input terminal of the logic gate D are respectively connected to the physical intensity voltage generated by the two multi-scale clue fusion devices currently performing pairwise comparison. 14 The output end of the NMOS tube N 14 The gate of logic gate D 15 The output end of the NMOS tube N 15 The gate of the logic gate D 16 The output end of the NMOS tube N 16 The gate of NMOS tube N 14 The drain of the NMOS tube is used to access the first driving voltage V1. 15 The drain of the NMOS tube is used to access the second driving voltage V2. 16 The drain of the NMOS tube is used to access the third driving voltage V3. 14 The source and resistor R 18 The second end of the resistor R 18 The first end of the NMOS tube is grounded, 15 The source and resistor R 19 The second end of the resistor R 19 The first end of the NMOS tube is grounded, 16 The source and resistor R 20 The second end of the resistor R 20 The first end of the NMOS tube is grounded, 14 The source output first inhibits the output voltage V inhibition , NMOS tube N 15 The source outputs the second winning output voltage V win_2 , NMOS tube N 16 The source output first wins the output voltage V win_1 , if the first suppression output voltage V inhibition =High level, indicating that the difference between the second fusion significance voltage and the first fusion significance voltage is within the set range [-V l , V h ], if the second winning output voltage V win_2 High level, indicating that the second fusion significance voltage is greater than the first fusion significance voltage + V h , if the first winning output voltage V win_1 High level, indicating that the first fusion significance voltage is greater than the second fusion significance voltage + V l , V l 、V h are the interval division values determined by the window comparator module.

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