Three-dimensional memory device

Abstract

The invention provides a three-dimensional memory device. The three-dimensional memory device comprises a plurality of word lines, bit lines, a coding circuit, a sensing circuit and a three-dimensional memory array. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays and is used for storing first to fourth neural network data related to at least one neural network model. Each two-dimensional memory array is coupled to a plurality of word lines and a plurality of bit lines, and is used for receiving a first input voltage and a second input voltage and respectively outputting a first output current and a second output current. The plurality of coding circuits are respectively coupled to the plurality of two-dimensional memory arrays and are used for respectively generating a first input voltage and a second input voltage according to the first neural network data and the second neural network data. The plurality of sensing circuits are respectively coupled to the plurality of two-dimensional memory arrays and are used for respectively generating third neural network data and fourth neural network data according to the first output current and the second output current.

Description

Technical Field

[0001] The present disclosure relates to data storage technology in a three-dimensional memory device, and more particularly to a three-dimensional memory device that transmits signals through two different signal paths to store twice as much data. Background Art

[0002] With the advancement of memory technology, three-dimensional memory devices, with their lower per-bit cost, have gradually replaced traditional planar memory and are now being applied in many fields. Furthermore, to address the significant time and energy required by processors to read data from memory, in-memory computing (IMC) technology has also gained increasing attention. Using IMC, operations can be performed directly in memory, thereby improving the speed and efficiency of data retrieval.

[0003] A three-dimensional memory device includes a memory array with a large number of memory cells, each with a corresponding impedance. By adjusting the impedance of each memory cell, the three-dimensional memory device can store data (i.e., neurons) in neural network models for use in artificial intelligence technology.

[0004] However, with the development of artificial intelligence technology, the amount of data required to be stored during the calculation process is becoming increasingly large. Therefore, how to increase the storage capacity of three-dimensional memory devices for data in neural network models is one of the issues in this field. Summary of the Invention

[0005] One aspect of the present disclosure provides a three-dimensional memory device comprising a plurality of word lines, a plurality of bit lines, a three-dimensional memory array, a plurality of encoding circuits, and a plurality of sensing circuits. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays for storing first neural network data, second neural network data, third neural network data, and fourth neural network data associated with at least one neural network model. Each two-dimensional memory array is coupled to a plurality of word lines and a plurality of bit lines for receiving a first input voltage and outputting a first output current, and for receiving a second input voltage and outputting a second output current. A plurality of encoding circuits are respectively coupled to the plurality of two-dimensional memory arrays for generating a first input voltage and a second input voltage according to the first neural network data and the second neural network data, respectively. A plurality of sensing circuits are respectively coupled to the plurality of two-dimensional memory arrays for generating a third neural network data and a fourth neural network data according to the first output current and the second output current, respectively.

[0006] In some embodiments of the three-dimensional memory device disclosed herein, the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, and the third neural network data is associated with a (K+1)-th neural network layer in the first neural network model; and the second neural network data is associated with an M-th neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with an (M+1)-th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

[0007] In some embodiments of the three-dimensional memory device disclosed herein that stores data related to different neural network models, a first two-dimensional memory array among a plurality of two-dimensional memory arrays is coupled to two of the sensing circuits among a plurality of sensing circuits, a second two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two of the encoding circuits among a plurality of encoding circuits, and the two of the sensing circuits among the plurality of sensing circuits are respectively coupled to the two of the encoding circuits among the plurality of encoding circuits, and are respectively used to: input the third neural network data of the first two-dimensional memory array into the second two-dimensional memory array as the first neural network data of the second two-dimensional memory array; and input the fourth neural network data of the first two-dimensional memory array into the second two-dimensional memory array as the second neural network data of the second two-dimensional memory array.

[0008] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to different neural network models, multiple two-dimensional memory arrays all receive first neural network data via multiple word lines and second neural network data via multiple bit lines, and multiple two-dimensional memory arrays all transmit third neural network data via multiple bit lines and fourth neural network data via multiple word lines.

[0009] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to different neural network models, a portion of multiple two-dimensional memory arrays receives first neural network data via multiple word lines, receives second neural network data via multiple bit lines, transmits third neural network data via multiple bit lines, and transmits fourth neural network data via multiple word lines, and another portion of the multiple two-dimensional memory arrays receives first neural network data via multiple bit lines, receives second neural network data via multiple word lines, transmits third neural network data via multiple word lines, and transmits fourth neural network data via multiple bit lines.

[0010] In some embodiments of the three-dimensional memory device of the present disclosure, the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is identical to the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model. K is a positive integer.

[0011] In some embodiments of the three-dimensional memory device disclosed herein that stores data related to the same neural network model, a first two-dimensional memory array among a plurality of two-dimensional memory arrays is coupled to a first sensing circuit and a second sensing circuit among a plurality of sensing circuits, and is coupled to a first encoding circuit and a second encoding circuit among a plurality of encoding circuits. The first encoding circuit is configured to receive first neural network data, the first sensing circuit is coupled to the second encoding circuit and is configured to transmit third neural network data as second neural network data to the first two-dimensional memory array, and the second sensing circuit is configured to transmit fourth neural network data to a second two-dimensional memory array among the plurality of two-dimensional memory arrays as first neural network data for the second two-dimensional memory array.

[0012] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to the same neural network model, multiple two-dimensional memory arrays all receive first neural network data via multiple word lines and second neural network data via multiple bit lines, and multiple two-dimensional memory arrays all transmit third neural network data via multiple bit lines and fourth neural network data via multiple word lines.

[0013] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to the same neural network model, a portion of multiple two-dimensional memory arrays receives first neural network data via multiple word lines, transmits third neural network data via multiple bit lines and receives second neural network data, and then transmits fourth neural network data via multiple word lines, and another portion of the multiple two-dimensional memory arrays receives first neural network data via multiple bit lines, transmits third neural network data via multiple word lines and receives second neural network data, and then transmits fourth neural network data via multiple bit lines.

[0014] Another aspect of the present disclosure provides a three-dimensional memory device comprising a plurality of word lines, a plurality of bit lines, a three-dimensional memory array, a plurality of encoding circuits, and a plurality of sensing circuits. The three-dimensional memory array comprises a plurality of two-dimensional memory arrays. The plurality of two-dimensional memory arrays each comprises a plurality of sub-arrays of the same size for storing first neural network data, second neural network data, third neural network data, and fourth neural network data associated with at least one neural network model. The plurality of sub-arrays are coupled to the plurality of word lines and the plurality of bit lines for receiving a plurality of first input voltages and outputting a plurality of first output currents, and for receiving a plurality of second input voltages and outputting a plurality of second output currents. The plurality of encoding circuits are respectively coupled to the plurality of sub-arrays for generating a plurality of first input voltages and a plurality of second input voltages according to the first neural network data and the second neural network data, respectively. The plurality of sensing circuits are respectively coupled to the plurality of sub-arrays for generating a third neural network data and a fourth neural network data according to the sum of the plurality of first output currents and the sum of the plurality of second output currents, respectively.

[0015] In some embodiments of the three-dimensional memory device disclosed herein, the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, and the third neural network data is associated with a (K+1)-th neural network layer in the first neural network model; and the second neural network data is associated with an M-th neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with an (M+1)-th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

[0016] In some embodiments of the three-dimensional memory device of the present disclosure for storing data related to different neural network models, multiple first sub-arrays among the multiple sub-arrays are each coupled to two of the sensing circuits among the multiple sensing circuits, multiple second sub-arrays among the multiple sub-arrays are each coupled to two of the encoding circuits among the multiple encoding circuits, and the multiple sensing circuits coupled to the multiple first sub-arrays are coupled to the multiple encoding circuits coupled to the multiple second sub-arrays, so as to: input the third neural network data of the multiple first sub-arrays to the multiple second sub-arrays as the first neural network data of the multiple second sub-arrays; and input the fourth neural network data of the multiple first sub-arrays to the multiple second sub-arrays as the second neural network data of the multiple second sub-arrays.

[0017] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to different neural network models, multiple sub-arrays all receive first neural network data via multiple word lines and second neural network data via multiple bit lines, and multiple sub-arrays all transmit third neural network data via multiple bit lines and fourth neural network data via multiple word lines.

[0018] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to different neural network models, a portion of multiple sub-arrays receives first neural network data via multiple word lines, receives second neural network data via multiple bit lines, transmits third neural network data via multiple bit lines, and transmits fourth neural network data via multiple word lines, and another portion of the multiple sub-arrays receives first neural network data via multiple bit lines, receives second neural network data via multiple word lines, transmits third neural network data via multiple word lines, and transmits fourth neural network data via multiple bit lines.

[0019] In some embodiments of the three-dimensional memory device of the present disclosure, the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is identical to the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model. K is a positive integer.

[0020] In some embodiments of the three-dimensional memory device for storing data related to the same neural network model disclosed herein, a plurality of first sub-arrays among a plurality of sub-arrays are coupled to a plurality of first sensing circuits and a plurality of second sensing circuits among a plurality of sensing circuits, and coupled to a plurality of first encoding circuits and a plurality of second encoding circuits among a plurality of encoding circuits. The plurality of first encoding circuits are configured to receive first neural network data, the plurality of first sensing circuits are coupled to the plurality of second encoding circuits to transmit third neural network data as second neural network data to the plurality of first sub-arrays, and the plurality of second sensing circuits are configured to transmit fourth neural network data to a plurality of second sub-arrays among the plurality of sub-arrays as first neural network data for the plurality of second sub-arrays.

[0021] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to the same neural network model, multiple sub-arrays all receive first neural network data via multiple word lines and second neural network data via multiple bit lines, and multiple sub-arrays all transmit third neural network data via multiple bit lines and fourth neural network data via multiple word lines.

[0022] In some embodiments of the three-dimensional memory device of the present disclosure that stores data related to the same neural network model, a portion of multiple sub-arrays receives first neural network data via multiple word lines, transmits third neural network data via multiple bit lines and receives second neural network data, and then transmits fourth neural network data via multiple word lines, and another portion of the multiple sub-arrays receives first neural network data via multiple bit lines, transmits third neural network data via multiple word lines and receives second neural network data, and then transmits fourth neural network data via multiple bit lines.

[0023] In some embodiments of the three-dimensional memory device disclosed herein, the first neural network data, the second neural network data, the third neural network data, and the fourth neural network data are different from each other and are all related to a neural network layer in one of the neural network models of the at least one neural network model.

[0024] In some embodiments of the three-dimensional memory device disclosed herein that stores data related to the same neural network layer of the same neural network model, multiple sub-arrays all receive first neural network data via multiple word lines and second neural network data via multiple bit lines, and multiple sub-arrays all transmit third neural network data via multiple bit lines and fourth neural network data via multiple word lines.

[0025] Through the three-dimensional memory devices of the two embodiments of the present disclosure, signals can be transmitted in different directions in the memory array to achieve the function of storing two types of neural network data, thereby improving the storage capacity of the three-dimensional memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the following descriptions of the accompanying drawings are given:

[0027] Figure 1 is a perspective schematic diagram of a three-dimensional memory device according to some embodiments of the present disclosure;

[0028] Figure 2A is a schematic diagram of an encoding circuit, a sensing circuit, and a two-dimensional memory array according to some examples;

[0029] Figure 2B is a schematic diagram of the internal structure and current path of a two-dimensional memory array according to some embodiments of the present disclosure;

[0030] Figure 2C is a schematic diagram of a neural network according to some embodiments of the present disclosure;

[0031] Figure 2D is a schematic diagram of the internal structure and current path of a two-dimensional memory array according to some embodiments of the present disclosure;

[0032] Figure 3A is a circuit diagram of a two-dimensional memory array according to some embodiments of the present disclosure;

[0033] Figure 3B is a circuit diagram of a two-dimensional memory array according to some other embodiments of the present disclosure;

[0034] Figure 3Cis a circuit diagram of a two-dimensional memory array according to some further embodiments of the present disclosure;

[0035] Figure 4A A schematic diagram of a two-dimensional memory array storing neural network data according to some embodiments of the present disclosure;

[0036] Figure 4B A schematic diagram of a two-dimensional memory array storing neural network data according to some other embodiments of the present disclosure;

[0037] Figure 4C Schematic diagram of a two-dimensional memory array storing neural network data according to some further embodiments of the present disclosure;

[0038] Figure 5 is a schematic diagram illustrating the relationship between a two-dimensional memory array and a sub-array according to some embodiments of the present disclosure;

[0039] Figure 6A A schematic diagram of storing neural network data in a subarray according to some embodiments of the present disclosure;

[0040] Figure 6B Schematic diagram of storing neural network data in a sub-array according to some other embodiments of the present disclosure;

[0041] Figure 6C FIG. 1 is a schematic diagram of a sub-array storing neural network data according to some other embodiments of the present disclosure; and

[0042] Figure 6D Schematic diagram of storing neural network data in a sub-array according to some further embodiments of the present disclosure.

[0043] Description of Reference Numerals

[0044] 100: Three-dimensional memory device

[0045] 110: Three-dimensional memory array

[0046] 111_1 to 111_p: Two-dimensional memory array

[0047] 111_1A to 111_1J: subarrays

[0048] 120: Encoding circuit

[0049] 130: Sensing circuit

[0050] 140: Processing circuit

[0051] V, V1~Vn: input voltage

[0052] I, I1~Im: output current

[0053] A1~An, B1~Bm: neural network data

[0054] C1~Cm, D1~Dn: neural network data

[0055] G11~G1m, G21~G2m: memory unit

[0056] Gn1~Gnm: memory cells

[0057] W11~W1m,W21~W2m:Impedance / weight

[0058] Wn1~Wnm:Impedance / weight

[0059] WL1~WLn: word lines

[0060] BL1~BLm: bit lines DETAILED DESCRIPTION

[0061] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0062] In the present disclosure, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. Unless otherwise specified in the text, "one" and "the" may refer to a single or multiple elements. It will be further understood that "comprising", "including", "having" and similar words used herein indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude the one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof described therein or in addition thereto.

[0063] Figure 1 3D memory device 100 according to some embodiments of the present disclosure is shown in FIG. In some embodiments, 3D memory device 100 includes a 3D memory array 110, a plurality of encoding circuits 120, a plurality of sensing circuits 130, a plurality of processing circuits 140, word lines WL1-WLn, and bit lines BL1-BLm. It should be noted that for the sake of simplicity, Figure 1 The word lines WL1 -WLn and the bit lines BL1 -BLm (which will be described in subsequent paragraphs and drawings) are omitted, and only one encoding circuit 120 , one sensing circuit 130 , and one processing circuit 140 are illustrated.

[0064] The three-dimensional memory array 110 is coupled between the encoding circuit 120 and the sensing circuit 130 to receive an input voltage V from the encoding circuit 120 and transmit an output current I to the sensing circuit 130. In some embodiments, the three-dimensional memory array 110 includes two-dimensional memory arrays 111_1-111_p, where p is a positive integer. The planes of the two-dimensional memory arrays 111_1-111_p are along a plane direction (e.g., Figure 1 ) and extends along another specific direction (for example, Figure 1 The two members are arranged in the direction Y) to form a three-dimensional structure.

[0065] In some embodiments, the three-dimensional memory array 110 can be implemented by a volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), a non-volatile memory (e.g., magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM)), or a combination thereof.

[0066] In some embodiments, the two-dimensional memory arrays 111_1 to 111_p each include a plurality of memory cells (eg, Figure 1 The internal structure of the memory cell will be described in detail in subsequent paragraphs.

[0067] The encoding circuit 120 is coupled to the two-dimensional memory arrays 111_1-111_p and the processing circuit 140 in the three-dimensional memory array 110, and is used to receive the neural network data A1-An, B1-Bm from the processing circuit 140, and transmit a corresponding input voltage V to the two-dimensional memory arrays 111_1-111_p according to the neural network data A1-An, B1-Bm.

[0068] The sensing circuit 130 is coupled to the two-dimensional memory arrays 111_1-111_p and the processing circuit 140 in the three-dimensional memory array 110. The sensing circuit 130 receives the output current I from the two-dimensional memory arrays 111_1-111_p, calculates corresponding neural network data C1-Cm, D1-Dn based on the current I, and transmits the neural network data C1-Cm, D1-Dn to the processing circuit 140.

[0069] The processing circuit 140 is coupled to the encoding circuit 120 and the sensing circuit 130 for transmitting the neural network data A1 -An, B1 -Bm to the encoding circuit 120 and receiving the neural network data C1 -Cm, D1 -Dn from the sensing circuit 130 .

[0070] Since the two-dimensional memory arrays 111_1 to 111_p are coupled to each encoding circuit 120 and each sensing circuit 130 in a similar manner, for the sake of simplicity, Figure 2A Only the connection relationship between the two-dimensional memory array 111_1 and the encoding circuit 120 and the sensing circuit 130 is described. Figure 2A FIG2 is a schematic diagram illustrating an encoding circuit 120, a sensing circuit 130, and a two-dimensional memory array 111_1 according to some examples. In some embodiments, the two-dimensional memory array 111_1 includes memory cells G11-G1m, G21-G2m, ..., Gn1-Gnm, and the memory cells G11-G1m, G21-G2m, ..., Gn1-Gnm are arranged in a square array having m rows and n columns, where m and n are positive integers.

[0071] like Figure 2A As shown, after receiving the neural network data A1-An, the encoding circuit 120 generates corresponding input voltages V1-Vn according to the neural network data A1-An to the two-dimensional memory array 111_1. Subsequently, the two-dimensional memory array 111_1 generates output currents I1-Im to the sensing circuit 130. After receiving the output currents I1-Im, the sensing circuit 130 generates corresponding neural network data C1-Cm based on the output currents I1-Im.

[0072] For details about the internal structure and current path of the two-dimensional memory array 111_1, please refer to Figure 2B . Figure 2B FIG. 1 is a schematic diagram illustrating the internal structure and current paths of a two-dimensional memory array 1111 according to some embodiments of the present disclosure.

[0073] In some embodiments, memory cells G11-G1m, G21-G2m, ..., Gn1-Gnm have impedances W11-W1m, W21-W2m, ..., Wn1-Wnm, respectively. In operation, when input voltages V1-Vn are input to the two-dimensional memory array 111_1 from word lines WL1-WLn, the two-dimensional memory array 111_1 generates a portion of output current I1 on bit line BL1 based on input voltage V1 (corresponding to neural network data A1) and the impedance W11 of memory cell G11. It generates another portion of output current I1 on bit line BL1 based on input voltage V2 (corresponding to neural network data A2) and the impedance W21 of memory cell G21, and so on. Therefore, the input of input voltages V1-Vn (corresponding to neural network data A1-An) generates n portions of output current I1 on bit line BL1. The sum of these n portions is the output current I1 (corresponding to neural network data C1).

[0074] Similarly, two-dimensional memory array 111_1 generates a portion of output current I2 on bit line BL2 based on input voltage V1 (corresponding to neural network data A1) and impedance W12 of memory cell G12. It generates another portion of output current I2 on bit line BL2 based on input voltage V2 (corresponding to neural network data A2) and impedance W22 of memory cell G22, and so on. Therefore, input voltages V1-Vn (corresponding to neural network data A1-An) generate n portions of output current I2 on bit line BL2, and the sum of these n portions is output current I2 (corresponding to neural network data C2). Output currents I3-Im (corresponding to neural network data C3-Cm) are generated in a similar manner to output currents I1 and I2 and are not further described here for the sake of brevity.

[0075] The corresponding relationship between input voltage V1~Vn, impedance W11~W1m, W21~W2m, ..., Wn1~Wnm and output current I1~Im can be used to implement the calculation between two adjacent neural network layers in the neural network model. Please refer to Figure 2B and Figure 2C , Figure 2C Schematic diagram of a neural network according to some embodiments of the present disclosure.

[0076] exist Figure 2C In the embodiment, the neural network data A1-An are stored in the neurons of the Kth neural network layer, and the neural network data C1-Cm are stored in the neurons of the (K+1)th neural network layer. The neural network data of a neuron in the current layer is the sum of the neural network data of all neurons in the previous layer multiplied by the corresponding weights. For example, in Figure 2CIn the embodiment, neural network data C1 is the sum of neural network data A1-An multiplied by weights W11, W21, ..., Wn1, respectively; neural network data C2 is the sum of neural network data A1-An multiplied by weights W12, W22, ..., Wn2 (not shown for simplicity), respectively, and so on. Therefore, the calculation of neural network data C1-Cm can be expressed as the following <Formula 1>:

[0077]

[0078] because Figure 2B and Figure 2C The calculation method for the neural network data C1~Cm is the same, so Figure 2B The impedances W11, W21, ..., Wn1 in the Figure 2C The weights W11, W21, ..., Wn1 in the neural network model are realized, thereby realizing the function of storing the neural network data in the Kth neural network layer.

[0079] In some embodiments, the two-dimensional memory array 111_1 can receive neural network data through word lines WL1-WLn and output neural network data through bit lines BL1-BLm, or can receive neural network data through bit lines BL1-BLm and output neural network data through word lines WL1-WLn. Figure 2D , Figure 2D FIG. 1 is a schematic diagram illustrating the internal structure and current paths of a two-dimensional memory array 111_1 according to some embodiments of the present disclosure.

[0080] exist Figure 2D In the embodiment of the present invention, the two-dimensional memory array 111_1 receives the neural network data B1 from the bit line BL1, and generates a portion of the neural network data D1 on the word line WL1 according to the neural network data B1 and the impedance W11 of the memory cell G11; receives the neural network data B2 from the bit line BL2, and generates another portion of the neural network data D1 on the word line WL1 according to the neural network data B2 and the impedance W12 of the memory cell G12, and so on. Therefore, the input of the neural network data B1~Bm will generate m portions of the neural network data D1 on the word line WL1, and the sum of these m portions is the neural network data D1, and so on. Therefore, the neural network data Dn can be calculated based on the neural network data B1~Bm received by the bit lines BL1~BLm and the impedance of each neural network data on the path of the word line WLn (such as Figure 2D shown).

[0081] Therefore, with Figure 2B Similar to the embodiment, Figure 2DThe corresponding relationship between the neural network data B1~Bm, impedances W11~W1m, W21~W2m, ..., Wn1~Wnm and neural network data D1~Dn in the neural network model can also be used to implement the calculation between two adjacent neural network layers in the neural network model (for example, Figure 2C The neural network model in Figure 2 shows that the calculation of the neural network data D1 to Dn can be expressed as follows:

[0082]

[0083] In summary, the two-dimensional memory array 1111 can store two different data in the same two-dimensional memory array by receiving / outputting neural network data using word lines / bit lines respectively, and receiving / outputting neural network data using bit lines / word lines respectively.

[0084] For the implementation of memory cells G11 to G1m, G21 to G2m, ..., Gn1 to Gnm, please refer to Figure 3A to Figure 3C . Figures 3A to 3C FIG. 1 is a circuit diagram of a two-dimensional memory array 1111 according to some different embodiments of the present disclosure.

[0085] In some embodiments, the memory cells G11-G1m, G21-G2m, ..., Gn1-Gnm can be connected by lateral and vertical conductive lines (eg, word lines and bit lines) to form a cross-point type array. Figure 3A In the embodiment, memory cells G11-G13 and memory cells G21-G23, G31-G33 (not labeled for simplicity) are coupled to adjacent memory cells via horizontal and vertical conductive lines, respectively, and each memory cell (i.e., each intersection of the cross-point array) is implemented as a circuit including a resistor.

[0086] In other embodiments, the memory cells G11-Glm, G21-G2m, ..., Gn1-Gnm can also be connected by horizontal and vertical wires, and their conduction conditions can be controlled by additional wires to form a logic NOR gate array. Figure 3B In the embodiment, memory cells G11-G13 and memory cells G21-G23, G31-G33 (not labeled for simplicity) are coupled to adjacent memory cells via lateral and vertical conductive lines, and each memory cell is implemented as a circuit comprising a resistor and a capacitor. Furthermore, the control terminals of memory cells in the same column of the memory array are connected to an additional conductive line to control whether they are conductive.

[0087] and Figure 3B Similar, in Figure 3C In the embodiment, the memory cells G11-G13 and the memory cells G21-G23, G31-G33 also form a logic NOR gate array. The difference is that, Figure 3C Each memory cell in the CMOS is implemented as a circuit including an inductor and a capacitor.

[0088] It should be noted that Figures 3A to 3C The implementations of memory cells G11-G13, G21-G23, and G31-G33 are merely examples and are not intended to limit the present disclosure. As long as the circuit structure of the memory cell satisfies the conditions of a cross-point array or a logic NOR gate array, other implementations of the memory cell are within the scope of the present disclosure.

[0089] Figure 4A FIG2 is a schematic diagram illustrating two-dimensional memory arrays 111_1 and 111_2 storing neural network data according to some embodiments of the present disclosure. It should be noted that for the sake of simplicity, Figures 4A to 4C and 6A to 6D The word lines and bit lines connected to each two-dimensional memory array are omitted in the figure. When the encoding circuit 120 is connected to the left or right side of the two-dimensional memory array, it means that the two-dimensional memory array receives neural network data via word lines. When the encoding circuit 120 is connected to the top or bottom side of the two-dimensional memory array, it means that the two-dimensional memory array receives neural network data via bit lines. When the sensing circuit 130 is connected to the left or right side of the two-dimensional memory array, it means that the two-dimensional memory array transmits neural network data via word lines. When the sensing circuit 130 is connected to the top or bottom side of the two-dimensional memory array, it means that the two-dimensional memory array transmits neural network data via bit lines.

[0090] exist Figure 4A In an embodiment, a two-dimensional memory array 111_1 is coupled to a two-dimensional memory array 111_2 via a set of encoding circuits 120, sensing circuits 130, and processing circuits 140 to store neural network data associated with the Kth neural network layer of a first neural network model. Specifically, after encoding circuit 120 inputs the neural network data associated with the Kth neural network layer of the first neural network model into two-dimensional memory array 111_1, the sensing circuit 130 calculates neural network data associated with the (K+1)th neural network layer of the first neural network model through weighting and summation within two-dimensional memory array 111_1. This data is then used as neural network data input to two-dimensional memory array 111_2 via processing circuit 140 for subsequent calculations.

[0091] Similarly, the two-dimensional memory array 111_2 is also coupled to the two-dimensional memory array 111_3 through a set of encoding circuits 120, sensing circuits 130 and processing circuits 140, and calculates the neural network data related to the (K+2)th neural network layer of the first neural network model in a manner similar to the two-dimensional memory array 111_1, thereby storing the neural network data related to the (K+1)th neural network layer of the first neural network model.

[0092] In addition, the two-dimensional memory array 111_1 is also coupled to the two-dimensional memory array 111_2 through another set of encoding circuits 120, sensing circuits 130 and processing circuits 140 to store neural network data related to the K-th neural network layer of the second neural network model; the two-dimensional memory array 111_2 is also coupled to the two-dimensional memory array 111_3 through another set of encoding circuits 120, sensing circuits 130 and processing circuits 140 to store neural network data related to the (K+1)-th neural network layer of the second neural network model.

[0093] Therefore, each two-dimensional memory array can store two sets of data through two connection methods. The connection method and data transmission method of the two-dimensional memory arrays 111_3 to 111_p are similar to those of the two-dimensional memory arrays 111_1 and 111_2, and will not be repeated here.

[0094] In some embodiments, the two-dimensional memory arrays 111_1 to 111_p receive neural network data related to the first neural network model via word lines and transmit neural network data related to the first neural network model via bit lines (e.g., Figure 4A In addition, the two-dimensional memory array 111_1-111_p further receives the neural network data related to the second neural network model via the bit lines and transmits the neural network data related to the second neural network model via the word lines (as shown in the upper half of FIG. Figure 4A to store the second set of data.

[0095] Figure 4B Schematic diagram of two-dimensional memory arrays 111_1 and 111_2 storing neural network data according to some other embodiments of the present disclosure. Figure 4A resemblance, Figure 4B The two-dimensional memory array 111_1 is also used to store the neural network data related to the Kth neural network layer of the first neural network model and the neural network data related to the Kth neural network layer of the second neural network model, and the two-dimensional memory array 111_2 is also used to store the neural network data related to the (K+1)th neural network layer of the first neural network model and the neural network data related to the (K+1)th neural network layer of the second neural network model.

[0096] and Figure 4A The difference is that in Figure 4B In an embodiment, a portion of the two-dimensional memory array 111_1~111_p can receive neural network data related to the first neural network model through word lines, and then transmit the neural network data related to the first neural network model through bit lines, while another portion can receive neural network data related to the first neural network model through bit lines, and then transmit the neural network data related to the first neural network model through word lines to store the first set of data.

[0097] For example, if Figure 4B As shown in the upper half of the figure, the two-dimensional memory array 111_1 receives the neural network data of the Kth neural network layer related to the first neural network model via the word line, and then transmits the neural network data related to the (K+1)th neural network layer of the first neural network model via the bit line, while the two-dimensional memory array 111_2 receives the neural network data related to the (K+1)th neural network layer of the first neural network model via the bit line, and then transmits the neural network data related to the (K+2)th neural network layer of the first neural network model via the word line.

[0098] Therefore, when the two-dimensional memory arrays 111_1 to 111_p store the neural network data related to the second neural network model (i.e., the second set of data), a portion of the two-dimensional memory array can also receive the neural network data via the bit lines and then transmit the neural network data via the word lines, and another portion of the two-dimensional memory array can receive the neural network data via the word lines and then transmit the neural network data via the bit lines.

[0099] Continue Figure 4B In the embodiment shown, the two-dimensional memory array 111_1 receives neural network data related to the Kth neural network layer of the second neural network model via the bit line, and then transmits neural network data related to the (K+1)th neural network layer of the second neural network model via the word line, while the two-dimensional memory array 111_2 receives neural network data related to the (K+1)th neural network layer of the second neural network model via the word line, and then transmits neural network data related to the (K+2)th neural network layer of the second neural network model via the bit line.

[0100] It should be noted that although Figure 4A 、 Figure 4BThe two-dimensional memory arrays 111_1-111_p described above are used to store neural network data associated with the same neural network layer in two neural network models, but the present disclosure is not limited thereto. In some embodiments, the two-dimensional memory arrays 111_1-111_p may store neural network data associated with different neural network layers in the two neural network models. For example, the two-dimensional memory array 111_1 may store neural network data associated with the first neural network layer of the first neural network model and the fifth neural network layer of the second neural network model.

[0101] In addition, the two-dimensional memory arrays 111_1 to 111_p in the present disclosure are not limited to storing neural network data associated with two neural network models. In some embodiments, each two-dimensional memory array is used to store neural network data associated with two adjacent neural network layers in a neural network model.

[0102] Please refer to Figure 4C , Figure 4C FIG. 1 is a schematic diagram illustrating a two-dimensional memory array 111_1 storing neural network data according to some further embodiments of the present disclosure.

[0103] exist Figure 4C In this embodiment, the two-dimensional memory array 111_1 first utilizes a first set of encoding circuits 120 and sensing circuits 130 to receive neural network data associated with the Kth neural network layer of the first neural network model via word lines, and then transmits neural network data associated with the (K+1)th neural network layer via bit lines. Next, the processing circuit 140 transmits the neural network data associated with the (K+1)th neural network layer to the second set of encoding circuits 120 and sensing circuits 130 of the two-dimensional memory array 111_1, allowing the two-dimensional memory array 111_1 to receive neural network data associated with the (K+1)th neural network layer via bit lines, and then transmit neural network data associated with the (K+2)th neural network layer to the two-dimensional memory array 111_2 via word lines. This configuration enables a two-dimensional memory array to store neural network data associated with two adjacent neural network layers of a neural network model.

[0104] It should be noted that although Figure 4CThe two-dimensional memory array 111_1 in FIG. 1 is shown as first receiving neural network data via word lines, then transmitting neural network data (i.e., the first set of data) via bit lines, then receiving neural network data via bit lines, then transmitting neural network data (i.e., the second set of data) via word lines, but the present disclosure is not limited thereto. In some embodiments, a portion of the two-dimensional memory arrays 111_1-111_p may first receive / transmit the first set of neural network data via word lines / bit lines, then receive / transmit the second set of neural network data via bit lines / word lines, while another portion may first receive / transmit the first set of neural network data via bit lines / word lines, then receive / transmit the second set of neural network data via word lines / bit lines.

[0105] Figure 5 FIG2 is a schematic diagram illustrating the relationship between two-dimensional memory array 111_1 and sub-arrays 111_1A to 111_1J according to some embodiments of the present disclosure. In some embodiments, two-dimensional memory array 111_1 (or other two-dimensional memory arrays in three-dimensional memory array 110 ) can be divided into multiple sub-arrays of equal size to store neural network data.

[0106] In some embodiments, the total size of the sub-arrays can be equal to the size of the two-dimensional memory array. For example, the sub-arrays 111_1A to 111_1D are all 4×4 arrays, and their total size is equal to the 8×8 two-dimensional memory array 111_1.

[0107] In other embodiments, the sum of the sizes of the partitioned sub-arrays can be larger than the size of the partitioned two-dimensional memory array. For example, sub-arrays 111_1E to 111_1J are all 3×5 arrays, and their sum is larger than the 8×8 two-dimensional memory array 111_1. In this case, the voltages received by the extra rows and columns in the array are set to 0.

[0108] Figure 6A FIG. 1 is a schematic diagram illustrating subarrays 111_1A to 111_1C storing neural network data according to some embodiments of the present disclosure. In some embodiments, Figure 6A The sub-arrays 111_1A to 111_1C are used to realize Figure 2A The two-dimensional memory array 111_1 in.

[0109] Specifically, each of subarrays 111_1A-111_1C is connected to a set of encoding circuits 120 and sensing circuits 130, and these three sensing circuits 130 are connected to a processing circuit 140 to sum the neural network data output by the three sensing circuits 130 to obtain neural network data associated with the Kth neural network layer of the first neural network model. Furthermore, each of subarrays 111_1A-111_1C is further connected to another set of encoding circuits 120 and sensing circuits 130, and these three sensing circuits 130 are connected to a processing circuit 140 to sum the neural network data output by the three sensing circuits 130 to obtain neural network data associated with the Kth neural network layer of the second neural network model.

[0110] and Figure 2A The two-dimensional memory array 111_1 to 111_p is similar. Figure 6A The sub-arrays 111_1A-111_1C in the embodiment receive the neural network data related to the first neural network model via word lines and transmit the neural network data related to the first neural network model via bit lines (e.g. Figure 6A In addition, the sub-arrays 111_1A to 111_1C receive the neural network data related to the second neural network model via the bit lines and transmit the neural network data related to the second neural network model via the word lines (as shown in the upper half of FIG. Figure 4A to store the second set of data.

[0111] Figure 6B Schematic diagram of subarrays 111_1A-111_1C storing neural network data according to some other embodiments of the present disclosure. In some embodiments, Figure 6B The sub-arrays 111_1A to 111_1C are used to realize Figure 2B The two-dimensional memory array 111_1 in.

[0112] In detail, Figure 4B Similarly, a portion of the sub-arrays 111_1A to 111_1C can receive neural network data related to the first neural network model via word lines and then transmit the neural network data related to the first neural network model via bit lines, while another portion of the sub-arrays 1111A to 1111C can receive neural network data related to the first neural network model via bit lines and then transmit the neural network data related to the first neural network model via word lines to jointly store the first set of data (e.g. Figure 6B The way in which the sub-arrays 1111A to 1111C store the second set of data is similar to that of Figure 4B , I will not go into details here.

[0113] Figure 6CSchematic diagram of subarrays 1111A-1111C storing neural network data according to some other embodiments of the present disclosure. In some embodiments, Figure 6C The sub-arrays 1111A to 1111C are used to realize Figure 2C The two-dimensional memory array 1111 in.

[0114] In detail, Figure 4C Similarly, sub-arrays 1111A-1111C are used to store neural network data associated with two adjacent neural network layers of a neural network model. First, sub-arrays 1111A-1111C utilize three encoding circuits 120 and three sensing circuits 130 to receive neural network data associated with the Kth neural network layer via word lines and then transmit the output data via bit lines. Next, processing circuit 140 sums the outputs of the three sensing circuits 130 to obtain neural network data associated with the (K+1)th neural network layer and transmits this data to another three encoding circuits 120 and another three sensing circuits 130. Therefore, sub-arrays 1111A-1111C can then receive neural network data associated with the (K+1)th neural network layer via bit lines and transmit the output data to another processing circuit 140 via word lines to sum neural network data associated with the (K+2)th neural network layer.

[0115] In addition, with Figure 4C Similarly, in some embodiments, a portion of sub-arrays 1111A to 1111C may first receive / transmit a first set of neural network data using word lines / bit lines, and then receive / transmit a second set of neural network data using bit lines / word lines; another portion may first receive / transmit a first set of neural network data using bit lines / word lines, and then receive / transmit a second set of neural network data using word lines / bit lines.

[0116] Figure 6D Schematic diagram of sub-arrays 1111A-1111C storing neural network data according to some further embodiments of the present disclosure. Figure 6D Similar to Figure 6C , the difference is that, Figure 6D The subarrays 1111A-1111C in can be used to store neural network data related to two parts of a neural network layer of a neural network model. In other words, Figure 6D The subarrays 111_1A to 111_1C use the parts [a, b, c] of the K-th neural network layer as the first set of neural network data, and use the parts [d, e, f] of the K-th neural network layer as the second set of neural network data to jointly store the neural network data related to the K-th neural network layer.

[0117] Through the configuration of the three-dimensional memory device 100 proposed in the present disclosure, the function of storing two sets of neural network data can be realized by inputting two sets of data through word lines / bit lines and outputting them through bit lines / word lines respectively, thereby improving the storage capacity of the three-dimensional memory device 100.

[0118] The above are only preferred embodiments of the present disclosure. Without departing from the scope or spirit of the present disclosure, the structure of the present disclosure can be modified and equivalently varied. In summary, all modifications and equivalent variations made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

Claims

1. A three-dimensional memory device, comprising: multiple word lines; a plurality of bit lines; A three-dimensional memory array includes a plurality of two-dimensional memory arrays for storing a first neural network data, a second neural network data, a third neural network data, and a fourth neural network data associated with at least one neural network model. Each of the two-dimensional memory arrays is coupled to the plurality of word lines and the plurality of bit lines, and is configured to receive a first input voltage and output a first output current, and to receive a second input voltage and output a second output current; a plurality of encoding circuits, respectively coupled to the plurality of two-dimensional memory arrays, for generating the first input voltage and the second input voltage according to the first neural network data and the second neural network data, respectively; as well as A plurality of sensing circuits are respectively coupled to the plurality of two-dimensional memory arrays, and are used to generate the third neural network data and the fourth neural network data according to the first output current and the second output current respectively.

2. The three-dimensional memory device of claim 1 , wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the third neural network data is associated with a (K+1)-th neural network layer in the first neural network model, and The second neural network data is associated with an M-th neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with an (M+1)-th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

3. The three-dimensional memory device of claim 2 , wherein a first two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two sensing circuits among the plurality of sensing circuits, a second two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to two encoding circuits among the plurality of encoding circuits, and The two sensing circuits of the plurality of sensing circuits are respectively coupled to the two encoding circuits of the plurality of encoding circuits, and are respectively used to: inputting the third neural network data of the first two-dimensional memory array into the second two-dimensional memory array to serve as the first neural network data of the second two-dimensional memory array; and The fourth neural network data of the first two-dimensional memory array is input into the second two-dimensional memory array to serve as the second neural network data of the second two-dimensional memory array.

4. The three-dimensional memory device according to claim 3, wherein the plurality of two-dimensional memory arrays all receive the first neural network data via the plurality of word lines and receive the second neural network data via the plurality of bit lines, and The multiple two-dimensional memory arrays all transmit the third neural network data through the multiple bit lines and transmit the fourth neural network data through the multiple word lines.

5. The three-dimensional memory device of claim 3 , wherein a portion of the plurality of two-dimensional memory arrays receives the first neural network data via the plurality of word lines, receives the second neural network data via the plurality of bit lines, transmits the third neural network data via the plurality of bit lines, and transmits the fourth neural network data via the plurality of word lines, and Another portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple bit lines, receives the second neural network data via the multiple word lines, transmits the third neural network data via the multiple word lines, and transmits the fourth neural network data via the multiple bit lines.

6. The three-dimensional memory device according to claim 1, wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is the same as the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model, wherein K is a positive integer.

7. The three-dimensional memory device of claim 6 , wherein a first two-dimensional memory array among the plurality of two-dimensional memory arrays is coupled to a first sensing circuit and a second sensing circuit among the plurality of sensing circuits, and is coupled to a first encoding circuit and a second encoding circuit among the plurality of encoding circuits. The first encoding circuit is used to receive the first neural network data. The first sensing circuit is coupled to the second encoding circuit for transmitting the third neural network data as the second neural network data to the first two-dimensional memory array, and The second sensing circuit is used to transmit the fourth neural network data to a second two-dimensional memory array among the multiple two-dimensional memory arrays to serve as the first neural network data of the second two-dimensional memory array.

8. The three-dimensional memory device according to claim 7, wherein the plurality of two-dimensional memory arrays all receive the first neural network data via the plurality of word lines and receive the second neural network data via the plurality of bit lines, and The multiple two-dimensional memory arrays all transmit the third neural network data through the multiple bit lines and transmit the fourth neural network data through the multiple word lines.

9. The three-dimensional memory device according to claim 7, wherein a portion of the plurality of two-dimensional memory arrays receives the first neural network data via the plurality of word lines, transmits the third neural network data and receives the second neural network data via the plurality of bit lines, and then transmits the fourth neural network data via the plurality of word lines, and Another portion of the multiple two-dimensional memory arrays receives the first neural network data via the multiple bit lines, transmits the third neural network data and receives the second neural network data via the multiple word lines, and then transmits the fourth neural network data via the multiple bit lines.

10. A three-dimensional memory device comprising: multiple word lines; a plurality of bit lines; A three-dimensional memory array includes a plurality of two-dimensional memory arrays, wherein each of the plurality of two-dimensional memory arrays includes a plurality of sub-arrays of the same size for storing a first neural network data, a second neural network data, a third neural network data, and a fourth neural network data associated with at least one neural network model. wherein the plurality of sub-arrays are coupled to the plurality of word lines and the plurality of bit lines, and are configured to receive a plurality of first input voltages and output a plurality of first output currents, and to receive a plurality of second input voltages and output a plurality of second output currents; a plurality of encoding circuits, respectively coupled to the plurality of sub-arrays, for generating the plurality of first input voltages and the plurality of second input voltages according to the first neural network data and the second neural network data; as well as A plurality of sensing circuits are respectively coupled to the plurality of sub-arrays, and are used to generate the third neural network data and the fourth neural network data according to the sum of the plurality of first output currents and the sum of the plurality of second output currents.

11. The three-dimensional memory device of claim 10 , wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, and the third neural network data is associated with a (K+1)-th neural network layer in the first neural network model; and The second neural network data is associated with an M-th neural network layer in a second neural network model of the at least one neural network model, and the fourth neural network data is associated with an (M+1)-th neural network layer in the second neural network model. The first neural network model is different from the second neural network model, and M and K are positive integers.

12. The three-dimensional memory device of claim 11 , wherein each of the plurality of first sub-arrays in the plurality of sub-arrays is coupled to two sensing circuits of the plurality of sensing circuits, each of the plurality of second sub-arrays in the plurality of sub-arrays is coupled to two encoding circuits of the plurality of encoding circuits, and The plurality of sensing circuits coupled to the plurality of first sub-arrays are coupled to the plurality of encoding circuits coupled to the plurality of second sub-arrays, for: inputting the third neural network data of the plurality of first sub-arrays into the plurality of second sub-arrays to serve as the first neural network data of the plurality of second sub-arrays; and The fourth neural network data of the plurality of first sub-arrays are input to the plurality of second sub-arrays to serve as the second neural network data of the plurality of second sub-arrays.

13. The three-dimensional memory device according to claim 12 , wherein the plurality of sub-arrays all receive the first neural network data via the plurality of word lines and receive the second neural network data via the plurality of bit lines, and The multiple sub-arrays all transmit the third neural network data via the multiple bit lines and transmit the fourth neural network data via the multiple word lines.

14. The three-dimensional memory device of claim 12 , wherein a portion of the plurality of sub-arrays receives the first neural network data via the plurality of word lines, receives the second neural network data via the plurality of bit lines, transmits the third neural network data via the plurality of bit lines, and transmits the fourth neural network data via the plurality of word lines, and Another portion of the multiple sub-arrays receives the first neural network data via the multiple bit lines, receives the second neural network data via the multiple word lines, transmits the third neural network data via the multiple word lines, and transmits the fourth neural network data via the multiple bit lines.

15. The three-dimensional memory device of claim 10 , wherein the first neural network data is associated with a K-th neural network layer in a first neural network model of the at least one neural network model, the second neural network data is identical to the third neural network data and is associated with a (K+1)-th neural network layer in the first neural network model, and the fourth neural network data is associated with a (K+2)-th neural network layer in the first neural network model, wherein K is a positive integer.

16. The three-dimensional memory device of claim 15 , wherein first sub-arrays among the plurality of sub-arrays are coupled to first sensing circuits and second sensing circuits among the plurality of sensing circuits, and coupled to first encoding circuits and second encoding circuits among the plurality of encoding circuits. wherein the plurality of first encoding circuits are used to receive the first neural network data, The plurality of first sensing circuits are coupled to the plurality of second encoding circuits for transmitting the third neural network data as the second neural network data to the plurality of first sub-arrays, and The plurality of second sensing circuits are used to transmit the fourth neural network data to a plurality of second sub-arrays among the plurality of sub-arrays to serve as the first neural network data of the plurality of second sub-arrays.

17. The three-dimensional memory device according to claim 16 , wherein the plurality of sub-arrays all receive the first neural network data via the plurality of word lines and receive the second neural network data via the plurality of bit lines, and The multiple sub-arrays all transmit the third neural network data via the multiple bit lines and transmit the fourth neural network data via the multiple word lines.

18. The three-dimensional memory device of claim 16 , wherein a portion of the plurality of sub-arrays receives the first neural network data via the plurality of word lines, transmits the third neural network data and receives the second neural network data via the plurality of bit lines, and then transmits the fourth neural network data via the plurality of word lines, and Another portion of the multiple sub-arrays receives the first neural network data via the multiple bit lines, transmits the third neural network data and receives the second neural network data via the multiple word lines, and then transmits the fourth neural network data via the multiple bit lines.

19. The three-dimensional memory device according to claim 10, wherein the first neural network data, the second neural network data, the third neural network data and the fourth neural network data are different from each other and are all related to a neural network layer in one of the neural network models in the at least one neural network model.

20. The three-dimensional memory device according to claim 19, wherein the plurality of sub-arrays all receive the first neural network data via the plurality of word lines and receive the second neural network data via the plurality of bit lines, and The multiple sub-arrays all transmit the third neural network data via the multiple bit lines and transmit the fourth neural network data via the multiple word lines.

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