Programming method of memory, memory and memory system

Abstract

The invention provides a programming method of a memory, the memory and a memory system, and is applied to the technical field of chip storage. The programming method of the memory comprises the following steps: receiving a write-in instruction, wherein the write-in instruction is used for indicating to write to-be-written data into a target storage unit in a plurality of storage units; the to-be-written data comprises N bits. According to the write-in instruction, in a first programming stage, performing first programming on part of bits of data to be written in; and in a second programming stage, performing second programming on all the bits of the data to be written. And after each second programming, performing verification reading on the target storage unit based on the verification voltage. The parameters of the verification voltage corresponding to the N bits with different values are different. On the basis of the operation, threshold voltage broadening caused by overprogramming in the programming operation process is effectively restrained.

Description

Technical Field

[0001] The present disclosure relates to the field of chip storage technology, and in particular to a memory programming method, a memory, and a storage system. Background Art

[0002] Memory operations on memory cells include programming and reading. Programming writes data to memory cells. Reading data from memory cells is done based on the threshold voltage. During programming, overprogramming can cause the threshold voltage to widen, leading to inaccurate read data. Summary of the Invention

[0003] The embodiments of the present disclosure provide a memory programming method, a memory, and a storage system, which effectively suppress the threshold voltage widening caused by over-programming during the programming operation.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, an embodiment of the present disclosure provides a programming method for a memory, wherein the memory includes a plurality of memory cells. The programming method includes: receiving a write instruction, the write instruction is used to instruct writing data to be written to a target memory cell among the plurality of memory cells. The data to be written includes N bits. According to the write instruction, in a first programming stage: a first programming is performed on some bits of the data to be written. In a second programming stage: a second programming is performed on all bits of the data to be written. After each second programming, a verification read is performed on the target memory cell based on a verification voltage. The parameters of the verification voltage corresponding to N bits with different values are different.

[0006] In some possible implementations, the parameters of the verification voltage include a voltage duration of the verification voltage; N bits with different values correspond to different voltage durations.

[0007] In some possible implementations, the voltage duration includes a pre-charge period, a development period, and a sensing and reading period. The verification voltages corresponding to N bits with different values have different durations in the development period.

[0008] In some possible implementations, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the shorter the development period.

[0009] In some possible implementations, the parameter of the verification voltage includes a voltage magnitude, and the verification voltage magnitudes corresponding to N bits with different values are different.

[0010] In some possible implementations, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the smaller the magnitude of the verification voltage.

[0011] In some possible implementations, the programming method further includes: obtaining a mapping table entry according to the write instruction, the mapping table entry being used to indicate a correspondence between N bits with different values and parameters of different verification voltages, and determining the verification voltage parameter according to the mapping table entry and the values of the N bits.

[0012] In a second aspect, an embodiment of the present disclosure further provides a memory comprising a peripheral circuit and a plurality of memory cells. The peripheral circuit is used to: receive a write instruction, the write instruction being used to instruct writing data to be written to a target memory cell among the plurality of memory cells. The data to be written comprises N bits. According to the write instruction, in a first programming stage: a first programming is performed on some bits of the data to be written. In a second programming stage: a second programming is performed on all bits of the data to be written. After each second programming, a verification reading is performed on the target memory cell based on a verification voltage; the parameters of the verification voltage corresponding to N bits with different values are different.

[0013] In some possible implementations, the verification voltage parameter includes a voltage duration of the verification voltage. N bits with different values correspond to different voltage durations.

[0014] In some possible implementations, the voltage duration includes a pre-charge period, a development period, and a sensing and reading period. The verification voltages corresponding to N bits with different values have different durations in the development period.

[0015] In some possible implementations, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the shorter the development period.

[0016] In some possible implementations, the parameter of the verification voltage includes a voltage magnitude, and the verification voltage magnitudes corresponding to N bits with different values are different.

[0017] In some possible implementations, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the smaller the magnitude of the verification voltage.

[0018] In some possible implementations, the peripheral circuit is further configured to: obtain a mapping table entry according to a write instruction, the mapping table entry being configured to indicate a correspondence between N bits with different values and different verification voltage parameters; and determine the verification voltage parameter according to the mapping table entry and the values of the N bits.

[0019] In a third aspect, an embodiment of the present disclosure further provides a storage system, the storage system comprising a controller and a memory as in any embodiment of the second aspect. The controller is coupled to the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] Figure 1 is a schematic diagram of a module of a memory according to some embodiments;

[0022] Figure 2 is a schematic diagram of a module of a storage array according to some embodiments;

[0023] Figure 3 A memory programming method according to some embodiments is shown. Figure 1 ;

[0024] Figure 4 Schematic diagram of another memory programming method according to some embodiments Figure 2 ;

[0025] Figure 5 Schematic diagram of another memory programming method according to some embodiments Figure 3 ;

[0026] Figure 6 Schematic diagram of another memory programming method according to some embodiments Figure 4 ;

[0027] Figure 7 Schematic diagram of another memory programming method according to some embodiments Figure 5 ;

[0028] Figure 8 A schematic diagram showing the relationship between the degree of threshold voltage convergence and the time corresponding to the development period according to some embodiments;

[0029] Figure 9 For Figure 8 After the data is processed, a processing result is obtained. Figure 1 ;

[0030] Figure 10 For Figure 8 Another processing result after data processing Figure 2 ;

[0031] Figure 11 Schematic diagram of another memory programming method according to some embodiments Figure 6 ;

[0032] Figure 12 Schematic diagram of another memory programming method according to some embodiments Figure 7 ;

[0033] Figure 13 Schematic diagram of another memory programming method according to some embodiments Figure 8 ;

[0034] Figure 14 A schematic diagram of a module of a storage system according to some embodiments Figure 1 ;

[0035] Figure 15 A schematic diagram of a module of another storage system according to some embodiments Figure 2 ;

[0036] Figure 16 A schematic diagram of a module of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0042] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is intended to be open and inclusive, as a process, step, calculation, or other action “based on” one or more conditions or values may, in practice, be based on additional conditions or beyond values.

[0046] The embodiment of the present disclosure provides a memory, such as Figure 1As shown, the memory 100 includes a peripheral circuit 10 and a memory array 20. The peripheral circuit 10 includes a control circuit 1, a register 2, a drive circuit 3, a page buffer circuit 4, a row decoding circuit 5, a column decoding circuit 6 and an interface circuit 7. The page buffer circuit 4 also includes a read verification circuit 41. Figure 1 As shown, memory array 20 includes multiple memory cells M. Control circuit 1 is coupled to register 2, driver circuit 3, page buffer circuit 4, row decoding circuit 5, column decoding circuit 6, memory array 20, and interface circuit 7. Driver circuit 3 is further coupled to page buffer circuit 4, row decoding circuit 5, and column decoding circuit 6. Column decoding circuit 6 is further coupled to interface circuit 7. Memory 100 is coupled to peripheral devices via interface circuit 7.

[0047] In some possible implementations, such as Figure 2 As shown, the memory array 20 of the memory 100 includes a plurality of memory cell strings, each of which includes a top select gatecut (TSG) transistor, a memory cell M, a bottom select gatecut (BSG) transistor, etc. The memory 100 can read data from a selected transistor by performing operations such as charging and discharging a selected bit line BL and a selected WL.

[0048] In some possible implementations, the read verification circuit 41 may be a sense latch or a low voltage test latch in the page buffer circuit 4. The low voltage test latch is used to determine the fail bit count (FBC) and indicate the 3BL (bit line) bias.

[0049] In some possible implementations, the memory 100 may be a NAND flash memory. In some examples, the memory cells M in the memory array 20 may be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quadruple-level cells (QLC), penta-level cells (PLC), etc. In memory cells M based on SLC, MLC, TLC, etc., as the number of levels increases, the number of data bits that can be stored in each memory cell M also increases. A mapping table entry is stored in register 2. The mapping table entry is used to record processing parameters for the memory 100 to perform data processing operations.

[0050] In some examples, the data processing operations of the memory 100 include programming operations, data reading operations, and erasing operations. The programming operations of the memory 100 can be divided into two types: single-pressure programming and incremental step pulse programming (ISPP). Single-pressure programming refers to programming the selected memory cell M with a larger threshold voltage. The programming speed of single-pressure programming is faster, but it is prone to over-programming problems, resulting in reduced reliability of the memory 100. Incremental step pulse programming refers to implementing programming operations through multiple loop programming. Each loop programming includes a programming phase and a read verification (Program Verify, PV) phase. Among them, multiple loop programming will apply multiple programming voltages with different voltage values at a certain step to the selected memory cell M to perform multiple loop programming phases and verification phase processing operations.

[0051] For example, taking a memory cell M as an SLC, the SLC has one data bit number, including data values 0 and 1, corresponding to one erased state and one programmed state. For an SLC, a programming operation for multiple memory cells M in a certain storage area (e.g., a storage block or a storage page) can be implemented through two programming cycles using a loop programming method. When programming multiple memory cells M: in the initial programming phase, the control circuit 1 selects multiple memory cells M in the storage area based on the drive circuit 3, the row decoding circuit 5, and the column decoding circuit 6. First, the selected multiple memory cells M need to be programmed using the program start voltage (Program Start Voltage) as the starting threshold voltage. In the read verification phase after the initial programming phase, the selected multiple memory cells M are verified and read based on the verify start voltage (Verify Start Loop), and multiple first indication signals are output to the control circuit 1 via the read verification circuit 41 in the page buffer circuit 4. The multiple first indication signals are used to indicate the verification and read results of the corresponding multiple memory cells M. When a memory cell M passes verification, it indicates that the memory cell M has been programmed to the target programming state, and subsequent programming phases cease programming. When a memory cell M fails verification, it indicates that the memory cell M has not been programmed to the target programming state, and subsequent programming phases continue programming. The control circuit 1 can determine the FBC based on multiple first indication signals. The FBC is used to indicate the number of memory cells M that failed verification. In the second programming phase, the programming start voltage is increased in steps by a certain programming offset voltage value to program the memory cells M that failed verification. Similarly, in MLC, TLC, and other application scenarios, there are more programming states than in SLC applications, and more programming cycles are required. In each programming cycle, the verification read voltage in the verification phase is increased in steps by a certain read offset voltage value compared to the previous programming cycle. For example, the read offset voltage values in two adjacent programming cycles can be the same or different. The programming offset voltage values in two adjacent programming cycles can be the same or different.

[0052] In some possible implementations, ISPP is currently generally used for the programming operation of the memory 100. When the memory 100 is performing a write operation, the programming voltage applied is not in one step, but is stepped step by step. First, a programming voltage V1 is added to the WL (word line) of the memory 100. Since the WL is coupled to the memory cell M, the voltage can be applied to the gate of the memory cell M through the WL, and the electrons enter the charge capture layer, and then verify whether its threshold voltage (Vt) reaches the predetermined value. If the predetermined value has been reached, the threshold voltage distribution of the memory cell M meets the requirements, and the programming is completed. If the predetermined value has not been reached, the next programming voltage V2 (Note: the voltage of V2 will have a certain increment based on V1) is used for programming. Figure 3 As shown, each programming loop includes a programming phase and a verification phase. Multiple programming loops apply multiple programming voltages with different voltage values in a certain step to perform multiple programming and verification phases on the selected memory cell M. The verification phase may include a first verification phase (also known as a coarse verification phase) and a second verification phase (also known as a fine verification phase). The duration of the coarse verification phase may include a coarse verification precharge period, a coarse verification development period (sodev_coarse), and a coarse verification sensing and reading period. The duration of the fine verification phase may include a fine verification precharge period, a fine verification development period (sodev_fine), and a fine verification sensing and reading period. The coarse verification development period represents the duration of the discharge of the memory cell during the coarse verification phase, and the fine verification development period represents the duration of the discharge of the memory cell during the fine verification phase. The coarse verification phase may include multiple verification voltage parameters, such as the coarse verification development period size and the coarse verification voltage size, and the fine verification phase may include multiple verification voltage parameters, such as the fine verification development period size and the fine verification voltage size.

[0053] In some examples, such as Figure 4 As shown, the parameters of different verification voltages in the coarse verification stage and the fine verification stage can divide the threshold voltage states of all memory cells M on the same WL into three intervals of A, B and C, and obtain 3BL intervals. Among them, the vertical line dividing the A and B intervals represents the threshold voltage of the memory cell corresponding to the coarse verification development period. The vertical line dividing the B and C intervals represents the threshold voltage of the memory cell corresponding to the fine verification development period. Moreover, the smaller the coarse verification development period, the smaller the threshold voltage of the sensed memory cell, which is equivalent to the smaller the coarse verification voltage. It can be inferred that the smaller the coarse verification development period, the smaller the coarse verification voltage. The same is true for the fine verification development period, that is, the smaller the fine verification development period, the smaller the threshold voltage of the sensed memory cell, which is equivalent to the smaller the fine verification voltage. It can also be inferred that the smaller the fine verification development period, the smaller the fine verification voltage. In this embodiment, the fine verification development period is larger than the coarse verification development period, so if Figure 4As shown in FIG, the threshold voltage of the memory cell corresponding to the fine verification development period is greater than the threshold voltage of the memory cell corresponding to the coarse verification development period. Figure 4 It can be seen that the threshold voltages of the memory cells in the three intervals A, B, and C differ. The threshold voltage of the memory cells in interval A is lower than that of the memory cells in interval B, and the threshold voltage of the memory cells in interval B is lower than that of the memory cells in interval C. To avoid overprogramming, the voltages applied to the memory cells BL in intervals A, B, and C need to be increased sequentially during the programming phase. For example, a 0V voltage is applied to the BL of memory cell M in region A. An intermediate voltage, such as 0.5V, is applied to the BL of memory cell M in region B. Programming is prohibited for memory cell M in region C, and a higher voltage, such as 2V, is applied to the BL. In summary, the number of memory cells in the three BL intervals A, B, and C can be adjusted by adjusting the length of the development period. If the coarse verification development period is shortened, the threshold voltages of the memory cells corresponding to the coarse verification development period will also be reduced. This will cause the threshold voltages of more memory cells to enter region B, and the voltages applied to the BL of these memory cells will also increase, thus preventing overprogramming.

[0054] In some examples, the verification phase may also include multiple coarse verification phases. Figure 5 As shown, the verification phase includes two coarse verification phases and one fine verification phase. The duration of the coarse verification phase 1 may include a coarse verification precharge period 1, a coarse verification development period 1 (sodev_coarse1), and a coarse verification sensing read period 1. The duration of the coarse verification phase 2 may include a coarse verification precharge period 2, a coarse verification development period 2 (sodev_coarse2), and a coarse verification sensing read period 2. The duration of the fine verification phase may include a fine verification precharge period, a fine verification development period, and a fine verification sensing read period. Among them, the coarse verification phase may also include multiple verification voltage parameters, such as the coarse verification development period size and the coarse verification voltage size. The fine verification phase may also include multiple verification voltage parameters, such as the fine verification development period size and the fine verification voltage size.

[0055] For example, Figure 4 The same is true for the 3BL interval shown, such as Figure 6As shown in the figure, the parameters of different verification voltages in two coarse verification phases and one fine verification phase can divide the threshold voltage states of all memory cells M coupled to the same WL into four intervals: A, B, C, and D, resulting in 4BL intervals. Then, in the programming phases, the voltage applied to the memory cells BL increases sequentially in the four intervals A, B, C, and D. For example, a 0V voltage is applied to the BL of the memory cells in region A. A 0.5V voltage is applied to the BL of the memory cells in region B. A 1V voltage is applied to the BL of the memory cells M in region C. Programming is prohibited for the memory cells in region D, and a higher voltage, such as 2V, is applied to the BL.

[0056] In some possible implementations, taking the memory cell M as a QLC NAND as an example, each memory cell M can store 4 bits of data, and the 4 bits of data are recorded as bit[3]bit[2]bit[1]bit[0]. The most common programming mode for QLC is 16-16 mode, that is, the 4 bits of data to be written to the memory cell M are first programmed (also called coarse programming) and then programmed to the corresponding first target state among 16 states (including 1 erased state and 15 programmed states). At this time, the threshold voltage of the first target state is relatively wide. Then, the first target state obtained in the first programming stage is subjected to a second programming (also called fine programming) to obtain a second target state with a narrower threshold voltage. However, the 16-16 mode programming mode programs the data to be written to the corresponding state among the 16 states in one step during the coarse programming stage, which takes a long time to program and the corresponding peripheral circuit hardware cost is relatively high. Therefore, in order to continuously improve programming time and reduce costs, an n-16 mode (n<16, n is an integer) programming mode has been developed in some implementations. Where n represents the n states corresponding to coarse programming, and 16 represents the 16 states corresponding to fine programming of the states obtained after coarse programming. That is, the n-16 mode programming mode indicates a two-step programming of the memory cell M. The first step is the first programming phase (also called the coarse programming phase), in which the threshold voltage of the memory cell is first divided into n states. The second step is the second programming phase (also called the fine programming phase), in which the n states obtained in the coarse programming phase are finely programmed to obtain the 16 states corresponding to the fine programming phase.

[0057] In some examples, the 4-16 mode programming mode is taken as an example. Figure 7As shown, the coarse programming stage first charges the target memory cell to one of the four voltage ranges (11, 01, 00, and 10) that match the two data bits [0] and [1] to be written. Then, the fine programming stage continues to charge and complete the write operation of the two data bits [2] and [3] to be written based on the two data bits [2] and [3] to be written and the current voltage state of the target memory cell. In this way, at least one state in the coarse programming stage will correspond to at least two states in the fine programming stage, such as the 15-16 mode programming mode or the 4-16 mode programming mode.

[0058] In some examples, such as Figure 7 As shown in the figure, taking QLC NAND memory cell M and the 4-16 mode programming mode as an example, each memory cell M can have 16 states for storing different data. These 16 states can be denoted as: P0 (erased state), P1 (programmed state), P2 (programmed state), P3 (programmed state), P4 (programmed state), P5 (programmed state), P6 (programmed state), P7 (programmed state), P8 (programmed state), P9 (programmed state), P10 (programmed state), P11 (programmed state), P12 (programmed state), P13 (programmed state), P14 (programmed state), and P15 (programmed state). These 16 states correspond to 16 threshold voltages, and the probability distribution of the threshold voltages follows a normal distribution. The possible values of each threshold voltage are likely to fall within the Vt ± 3sigma range. Each Vt ± 3sigma region can be divided into the Vt - 3sigma region and the Vt + 3sigma region. Since the threshold voltage in the Vt-3sigma range is reduced, it is not easy to cause overlap of different states, so the threshold voltage broadening of Vt+3sigma is generally considered. Figure 8 As shown, the corresponding relationship between the convergence degree of the threshold voltage of the programming state of P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 and P14 and the length of the rough verification development period is shown. Figure 8The horizontal axis represents time, and the vertical axis is dimensionless. The relative magnitude of the vertical axis values in the same figure indicates the degree of threshold voltage convergence. Larger relative values indicate greater convergence. The Vt-3sigma region and Vt+3sigma region of the threshold voltage corresponding to the P1 programming state are denoted as E1 and E2. The corresponding P2 programming state corresponds to E3 and E4, the P3 programming state corresponds to E5 and E6, the P4 programming state corresponds to E7 and E8, the P5 programming state corresponds to E9 and E10, the P6 programming state corresponds to E11 and E12, the P7 programming state corresponds to E13 and E14, the P8 programming state corresponds to E15 and E16, the P9 programming state corresponds to E17 and E18, the P10 programming state corresponds to E19 and E20, the P11 programming state corresponds to E21 and E22, the P12 programming state corresponds to E23 and E24, the P13 programming state corresponds to E25 and E26, and the P14 programming state corresponds to E27 and E28. Figure 8 There are 15 graphs in this chart: Avg(E2), Avg(E4), Avg(E6), Avg(E8), Avg(E10), Avg(E12), Avg(E14), Avg(E16), Avg(E18), Avg(E20), Avg(E22), Avg(E24), Avg(E26), Avg(E28) and Avg(Esum), where Avg(·) indicates the average value. Figure 8 The vertical dashed lines in the 15 figures in the paper represent the length of the rough verification development period. The vertical dashed lines are in the same position in each figure, indicating that Figure 8 The 15 figures in the figure share the rough verification development period during the verification stage.

[0059] For example, by Figure 8 It can be seen that under the condition of the shared coarse verification development period, the position of the vertical dotted line in Figure Avg (E4) and Avg (E8) is slightly different from the position of the threshold voltage convergence peak. The position of the vertical dotted line in Figure Avg (E24) coincides with the position of the threshold voltage convergence peak. This shows that the threshold voltage of the programming state corresponding to Figure Avg (E4), Figure Avg (E8) and Figure Avg (E24) is more obviously narrowed. In Figure Avg (E2), the position of the vertical dotted line is significantly different from the position of the threshold voltage convergence peak, causing the threshold voltage to widen, indicating that the threshold voltage of the programming state corresponding to Figure Avg (E2) is more obviously widened.

[0060] like Figure 9 As shown, Figure 9 For Figure 8 The data corresponding to the vertical axis is processed to indicate the convergence degree of the threshold voltage. Specifically, Figure 9 The vertical axis represents Figure 8The difference between the convergence degree corresponding to the convergence peak of the middle threshold voltage and the convergence degree of the threshold voltage corresponding to the shared coarse verification development period (vertical dotted line in the figure).

[0061] like Figure 10 As shown, Figure 10 For Figure 8 The data corresponding to the horizontal axis is processed to obtain the relative difference between the duration of the coarse verification development period corresponding to the convergence peak of the threshold voltage and the duration of the shared coarse verification development period (the vertical dashed line in the figure). Figure Avg(Esum) represents the sum of the threshold voltage spreads in Avg(E2), Avg(E4), Avg(E6), Avg(E8), Avg(E10), Avg(E12), Avg(E14), Avg(E16), Avg(E18), Avg(E20), Avg(E22), Avg(E24), Avg(E26), and Avg(E28).

[0062] according to Figure 8 、 Figure 9 、 Figure 10 Analysis shows that, under the shared coarse verification development period, different programming states correspond to different threshold voltage spreads. Some programming states exhibit better threshold voltage convergence, while others exhibit poorer threshold voltage convergence, i.e., a greater degree of threshold voltage spread. For example, in the 4-16 mode programming mode, programming state 11 during the coarse programming phase may correspond to one of the fine programming states: 1111, 0111, 0011, or 1011. Clearly, the distance between programming state 11 and programming states 1111, 0111, 0011, and 1011 is not the same. In other words, in actual programming, depending on the different values of the programmed data, a certain programming state in the coarse programming stage may obtain a different programming state after fine programming, and there will inevitably be a situation where the distance between the programming state in the same coarse programming stage and the programming state in different fine programming stages is different. That is, under the condition of sharing the coarse verification and development period, after the first programming state in the first programming stage is programmed in the second programming stage, the second programming state is obtained. If the distance between the first programming state and the second programming state is larger, the threshold voltage will be wider. However, in the current programming mode, all programming states in the fine programming stage share the same verification voltage parameters (verification voltage and development period). When the distance between the state in the fine programming stage and the state in the coarse programming stage is large, it is in the following state. Figure 4 Middle A area, or Figure 6 There are many memory cells M in the A and B regions. In order to program the threshold voltages of these memory cells to the target threshold, a smaller voltage or no voltage needs to be applied to the BLs of these memory cells. Therefore, over-programming is prone to occur, causing the threshold voltage to widen.

[0063] In order to suppress the threshold voltage widening caused by over-programming during the programming operation of the memory cell, the embodiment of the present disclosure provides a memory programming method based on the following steps: Figure 1 and Figure 2 The memory 100 of the structure shown in the figure executes the programming method. The memory 100 includes a plurality of memory cells M. Figure 11 As shown, the memory programming method includes the following steps S110 to S130:

[0064] S110 , the peripheral circuit 10 receives a write instruction.

[0065] In some possible implementations, the write instruction is used to instruct writing data to be written to a target storage unit among the plurality of storage units. The data to be written includes N bits, where N is an integer greater than or equal to 1.

[0066] In some examples, N represents the number of bits of data that the target storage unit can store. For example, when storage unit M is SLC, N = 1. When storage unit M is MLC, N = 2. When storage unit M is TLC, N = 3. When storage unit M is QLC, N = 4. When storage unit M is PLC, N = 5.

[0067] S120 , the peripheral circuit 10 obtains a mapping table entry according to the write instruction.

[0068] In some possible implementations, the mapping table entry is used to indicate a correspondence between N bits of different values and parameters of different verification voltages.

[0069] In some examples, the peripheral circuit 10 determines parameters of the verification voltage according to the mapping table entry and the values of the N bits.

[0070] In some examples, the verification voltage parameter includes a voltage duration of the verification voltage. N bits with different values correspond to different voltage durations.

[0071] For example, taking N=4, and N bits of different values being 1111, 1011, 0111, and 0011, the voltage duration corresponding to 1111 is less than (smaller than) the voltage duration corresponding to 1011. The voltage duration corresponding to 0111 is less than the voltage duration corresponding to 0011.

[0072] In some examples, the voltage duration includes a pre-charge period, a development period, and a sensing and reading period. The verification voltages corresponding to the N bits with different values have different durations in the development period.

[0073] Exemplarily, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the shorter the development period.

[0074] Specifically, take N=4, the memory cell M is QLC NAND, the 4-16 mode programming mode is adopted, some of the N bits are 11, and the values of all bits are 1111, 1011, 0111, and 0011 as an example. The development period corresponding to 1111 is < (less than) the development period corresponding to 1011 < the development period corresponding to 0111 < the development period corresponding to 0011.

[0075] Specifically, if Figure 8 As shown, if different coarse verification development periods are used for different states, for example, the programming state corresponding to E2 does not share the same coarse verification development period, but instead sets the coarse verification development period at the location of the threshold voltage convergence peak, the threshold voltage can be narrowed. Similarly, if all programming states do not share the same coarse verification development period, but instead set coarse verification development periods corresponding to the convergence peak of their threshold voltage for different programming states, and store this mapping relationship in register 2 for easy lookup. This solution effectively suppresses the threshold voltage broadening caused by overprogramming by allowing different programming states to independently control the coarse verification development period in the second programming phase, setting the coarse verification development period corresponding to the convergence peak of the threshold voltage for programming states with larger spacing.

[0076] Further, if Figure 12 As shown in , it means that all programming states share the same coarse verification development period. Figure 13 As shown in FIG, it represents the coarse verification development period corresponding to the convergence peak value of the threshold voltage of different programming states. Figure 12 and Figure 13 In FIG, Pn and Pn+k represent the P programming state obtained by the first programming and the two programming states obtained by the second programming. The distance between the Pn programming state and the P programming state is smaller, and the distance between the Pn+k programming state and the P programming state is larger. Figure 12 and Figure 13 It can be seen that Figure 13 The threshold voltage corresponding to the Pn+k programming state is compared with Figure 12 The threshold voltage corresponding to the Pn+k programming state is narrowed.

[0077] In some examples, the parameters of the verification voltage include voltage magnitude, and the verification voltage magnitudes corresponding to N bits with different values are different.

[0078] Exemplarily, for N bits with different values, the greater the difference between the values of some of the N bits and the values of all the bits, the smaller the voltage of the verification voltage.

[0079] Specifically, the smaller the verification voltage is, the Figure 4 Middle B area, or Figure 6 The more memory cells M in the middle C area, the easier it is to suppress the threshold voltage widening caused by over-programming. However, the smaller the voltage of the verification voltage is, the more programming cycles are required, resulting in a longer programming time (t PROG ) increases, so "the larger the difference between the value of some bits of the N bits and the value of all bits" and "the smaller the voltage of the verification voltage" are relative terms, and it does not mean that the smaller the verification voltage, the better. In this embodiment, compared with the effect of suppressing the threshold voltage widening by independently controlling different verification voltages for different programming states in the second programming stage, t PROG The increase in has little effect on the programming effect.

[0080] S130 , the peripheral circuit 10 performs a first programming and a second programming on the target memory cell according to the mapping table entry.

[0081] In some possible implementations, in a first programming phase, a portion of the bits of the data to be written are first programmed, and in a second programming phase, all the bits of the data to be written are second programmed, and after each second programming, a verification read is performed on the target memory cell based on a verification voltage.

[0082] In some examples, such as Figure 7 As shown, the memory cell M is QLC NAND, and the 4-16mode programming mode is used as an example. Each memory cell M can store 4 bits of data, and the 4 bits of data are recorded as bit[3]bit[2]bit[1]bit[0]. In the first programming stage, the target memory cell is charged to one of the four voltage intervals (11, 01, 00 and 10) that match the two bits of data bit[0] and bit[1] to be written. Then, in the second programming stage, according to the two bits of data bit[2] and bit[3] to be written and the current voltage state of the target memory cell, the charging is continued to complete the writing operation of the two bits of data bit[2] and bit[3] to be written. After each second programming, the target memory cell is verified and read based on the mapping table entry obtained in step S120.

[0083] It should be noted that verification is performed after programming in both the first and second programming stages, and verification can be performed once or multiple times during the verification stage. The programming method provided in this embodiment can also effectively suppress threshold voltage stretching in the first programming stage. However, considering that there are fewer programmed states in the first programming stage, even if threshold voltage stretching exists, it has little impact on data reading. Furthermore, considering programming efficiency, this embodiment is primarily used to suppress threshold voltage stretching in the second programming stage.

[0084] At the same time, after each second programming, a verification read is performed on the target memory cell based on the verification voltage. If multiple verifications are performed after the second programming, the last verification is a fine verification. Since the voltage applied to the BL of the memory cell M near the verification voltage in the fine verification stage is relatively large, over-programming is less likely to occur. Therefore, the fine verification development period has little impact on over-programming, and all programming states in the fine programming stage can share the same fine verification development period. Therefore, this embodiment can be mainly used for the coarse verification development period of the coarse verification stage after the second programming.

[0085] In some examples, this embodiment is not limited to application to two-step programming (including first programming and second programming), but can also be applied to three-step programming (including first programming, second programming and third programming). Taking the storage unit M as QLC NAND as an example, the three-step programming can be 2-4-16 mode, 4-8-16 mode, etc.

[0086] In some examples, a gray code encoding mode may also be used while implementing the programming method provided in this embodiment.

[0087] Embodiments of the present disclosure provide a memory programming method, memory, and storage system. The memory includes multiple memory cells. The memory obtains a mapping table entry stored in a register based on a received write instruction. The mapping table entry indicates the correspondence between N bits with different values and different verification voltage parameters. The memory determines verification voltage parameters based on the mapping table entry and the values of the N bits, and performs first programming and second programming on the target memory cell based on the verification voltage parameters. After each second programming step, a verification read is performed on the target memory cell based on the verification voltage. During the verification read phase, the verification voltage parameters corresponding to the N bits with different values are different. The verification voltage parameters include the voltage duration and the magnitude of the verification voltage. The magnitude of the verification voltage duration is primarily achieved by controlling the coarse verification development period included in the voltage duration. Therefore, in the second programming phase, this solution allows different programming states to independently control the coarse verification development period and different verification voltages. A coarse verification development period corresponding to the convergence peak of the threshold voltage is set for programming states with larger spacing, thereby effectively suppressing threshold voltage broadening caused by overprogramming.

[0088] The embodiment of the present disclosure also provides a storage system, such as Figure 14 、 Figure 15 As shown, Figure 14 is a block diagram of a storage system according to some embodiments. Figure 15 is a block diagram of a storage system according to some other embodiments.

[0089] See Figure 14 and Figure 15 Some embodiments of the present disclosure further provide a storage system 1000, which includes a controller 200 and the memory 100 of some embodiments above. The controller 200 is coupled to the memory 100 to control the memory 100 to store data.

[0090] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0091] In some embodiments, see Figure 14 The storage system 1000 includes a controller 200 and a memory 100 , and the storage system 1000 can be integrated into a memory card.

[0092] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0093] In other embodiments, see Figure 15 The storage system 1000 includes a controller 200 and a plurality of memories 100. The storage system 1000 is integrated into a solid state drive (SSD).

[0094] In the storage system 1000, in some embodiments, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0095] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0096] In some embodiments, the controller 200 may be configured to manage data stored in the memory 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 200 may also be configured to control operations of the memory 100, such as programming operations such as reading and erasing. In some embodiments, the controller 200 may also be configured to manage various functions related to data stored or to be stored in the memory 100, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In some embodiments, the controller 200 may also be configured to process error correction codes for data read from or written to the memory 100.

[0097] Of course, the controller 200 may also perform any other suitable functions, such as formatting the memory 100. For example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0098] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0099] Some embodiments of the present disclosure further provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0100] like Figure 16 As shown, the electronic device 10000 may include the storage system 1000 described above, and may also include at least one of a processor 2000 and a cache.

[0101] Exemplarily, the processor 2000 may be a chip, specifically a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), a microcontroller (MCU), a programmable logic device (PLD), or other integrated chips.

[0102] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A memory programming method, characterized in that: The memory includes a plurality of storage units; The programming method comprises: receiving a write instruction, wherein the write instruction is used to instruct writing data to be written into a target storage unit among the plurality of storage units; the data to be written includes N bits; According to the write instruction, in the first programming stage: the first programming is performed on some bits of the data to be written; in the second programming stage: the second programming is performed on all bits of the data to be written; after each second programming, the target storage unit is verified and read based on the verification voltage; the parameters of the verification voltage corresponding to the N bits with different values are different.

2. The programming method according to claim 1, wherein: The parameters of the verification voltage include a voltage duration of the verification voltage; the voltage durations corresponding to the N bits with different values are different.

3. The programming method according to claim 2, wherein: The voltage duration includes a pre-charge period, a development period, and a sensing and reading period; the verification voltages corresponding to the N bits with different values have different durations in the development period.

4. The programming method according to claim 3, wherein: For the N bits with different values, the greater the difference between the values of the part of the N bits and the values of all the bits, the shorter the development period.

5. The programming method according to claim 1, wherein: The parameters of the verification voltage include voltage magnitude, and the N bits with different values correspond to different voltage magnitudes of the verification voltage.

6. The programming method according to claim 5, characterized in that: For the N bits with different values, the greater the difference between the values of the part of the N bits and the values of all the bits, the smaller the voltage of the verification voltage.

7. The programming method according to any one of claims 1 to 6, characterized in that: The programming method further comprises: Obtaining a mapping table entry according to the write instruction, the mapping table entry being used to indicate a correspondence between the N bits with different values and parameters of different verification voltages; The parameters of the verification voltage are determined according to the mapping table entry and the values of the N bits.

8. A memory, characterized in that: The device comprises a peripheral circuit and a plurality of storage units; the peripheral circuit is used for: receiving a write instruction for instructing to write data to a target storage unit among the plurality of storage units; the data to be written includes N bits; and performing a first programming on a portion of the bits of the data to be written in a first programming phase according to the write instruction; In the second programming stage: performing second programming on all bits of the data to be written; After each second programming, the target memory cell is verified and read based on a verification voltage; the parameters of the verification voltage corresponding to the N bits with different values are different.

9. The memory according to claim 8, wherein: The parameters of the verification voltage include a voltage duration of the verification voltage; the voltage durations corresponding to the N bits with different values are different.

10. The memory according to claim 9, wherein: The voltage duration includes a pre-charge period, a development period, and a sensing and reading period; the verification voltages corresponding to the N bits with different values have different durations in the development period.

11. The memory according to claim 10, wherein: For the N bits with different values, the greater the difference between the values of the part of the N bits and the values of all the bits, the shorter the development period.

12. The memory according to claim 8, wherein: The parameters of the verification voltage include voltage magnitude, and the N bits with different values correspond to different voltage magnitudes of the verification voltage.

13. The memory according to claim 12, wherein: For the N bits with different values, the greater the difference between the values of the part of the N bits and the values of all the bits, the smaller the voltage of the verification voltage.

14. The memory according to any one of claims 8 to 13, characterized in that: The peripheral circuit is also used for: Obtaining a mapping table entry according to the write instruction, the mapping table entry being used to indicate a correspondence between the N bits with different values and parameters of different verification voltages; The parameters of the verification voltage are determined according to the mapping table entry and the values of the N bits.

15. A storage system, characterized in that: The storage system includes a controller and the memory according to any one of claims 8 to 14; the controller is coupled to the memory.

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