Row activation count updating method and memory

Abstract

The embodiment of the invention relates to the technical field of semiconductors, in particular to a row activation count updating method and a memory, and the row activation count updating method comprises the following steps: updating a row activation count value of a target word line corresponding to an external activation command; the updating process comprises a data reading operation, a sensing amplification stage, a data processing stage and a data write-back operation which are executed in sequence; after the data reading operation is executed and before the data write-back operation is executed, the data pre-writing operation is executed in parallel; the data pre-writing operation is configured to write first data into the counting storage unit connected with the target word line; the data write-back operation is configured to write second data into the corresponding counting storage unit connected with the target word line; the second data writing speed of the memory is faster than the first data writing speed of the memory; the row activation counting updating method provided by the embodiment of the invention aims to shorten the time occupied by the row-by-row activation counting function.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a row activation count update method and a memory. Background Art

[0002] In the technical specifications (specs) of new memory products, some memory products have introduced a Per-Row Activation Counting (PRAC) function. The purpose of this function is to record the number of activations for each row to more accurately record and monitor the performance impact of row hammer on adjacent rows.

[0003] Compared to memories that don't support row-by-row activation counting, memories that do support it have additional timing requirements. Implementing row-by-row activation counting in memories while meeting the required timing, power consumption, and area are key areas of research and technological breakthroughs currently underway. Summary of the Invention

[0004] The present disclosure provides a row activation count update method and a memory, so as to shorten the time occupied by the row-by-row activation count function and reduce the impact of adding the row-by-row activation count function on the memory timing.

[0005] In the first aspect, an embodiment of the present disclosure provides an activation count update method, comprising: in response to an external activation command, updating the row activation count value of the target word line corresponding to the external activation command; wherein the update process comprises: a data reading operation, a sensing amplification stage, a data processing stage and a data write-back operation performed successively; the data reading operation and the sensing amplification stage are configured to obtain the row activation count value stored in the counting storage unit connected to the target word line; the data processing stage is configured to process the row activation count value to obtain the value to be written back; after executing the data reading operation and before executing the data write-back operation, a data pre-write operation is performed in parallel; the data pre-write operation is configured to write the first data to the counting storage unit connected to the target word line; the data write-back operation is configured to write the second data to the corresponding counting storage unit connected to the target word line based on the position of each second data in the value to be written back; the speed at which the memory writes the second data is faster than the speed at which the memory writes the first data.

[0006] In some embodiments, the data processing stage includes: an error detection and correction stage, a data processing operation and a check code generation stage; the error detection and correction stage is configured to include: performing error detection and correction on the row activation count value based on the check value corresponding to the row activation count value to obtain the correct row activation count value; the data processing operation is configured to perform accumulation processing on the row activation count value to generate the value to be written back; the check code generation stage is configured to generate the check value corresponding to the value to be written back.

[0007] In some embodiments, the data pre-write operation generates the first data based on a global driver and writes the first data through a global input-output line, or the data pre-write operation generates the first data based on a pre-write circuit and writes the first data through a bit line or a local input-output line located between the bit line and the global input-output line.

[0008] In some embodiments, the pre-write circuit includes an internal power supply corresponding to the first data, and the internal power supply is configured to provide a power supply voltage corresponding to the first data.

[0009] In some embodiments, if the data pre-write operation is based on the global driver writing the first data, the data pre-write operation is started after the sensing and amplification stage ends.

[0010] In some embodiments, if the data pre-write operation is based on the pre-write circuit to write the first data, the data pre-write operation is started in parallel with the sensing and amplification stage.

[0011] In some embodiments, during the process of the memory updating the row activation count value, the column selection transistors corresponding to all the counting storage units remain in the on state.

[0012] In some embodiments, in an update process after the memory reads the row activation count value, the column selection transistor corresponding to the write transistor between the local input / output line and the global input / output line remains in a turned-on state.

[0013] In some embodiments, the data processing operation is performed based on a data processing circuit, and the data processing circuit includes a serial carry adder.

[0014] In some embodiments, before updating the row activation count value of the target word line corresponding to the external activation command, the row activation count update method further includes: acquiring the target word line corresponding to the external activation command.

[0015] In some embodiments, after acquiring the target word line, the row activation count update method further includes: acquiring a counting storage unit address corresponding to the target word line.

[0016] In some embodiments, the counting storage unit includes a row activation count value storage unit for storing a row activation count value, and the method for obtaining the counting storage unit address corresponding to the target word line includes: judging whether the column address corresponding to the row activation count value storage unit has undergone redundant replacement based on the failure address stored in the register; if part of the column address corresponding to the row activation count value storage unit has undergone redundant replacement, then accessing the remaining column addresses that have not undergone redundant replacement and the redundant column addresses that have undergone redundant replacement corresponding to the row activation count value storage unit; if none of the column addresses corresponding to the row activation count value storage unit have undergone redundant replacement, then directly accessing the column address corresponding to the row activation count value storage unit.

[0017] In a second aspect, an embodiment of the present disclosure provides a memory comprising: a controller and a memory array, wherein the controller is configured to update the row activation count value corresponding to the target word line in the memory array based on the row activation count update method described in the first aspect above.

[0018] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0019] The data write-back process is split into a data pre-write operation and a data write-back operation. The data pre-write operation is used to write the first data, which has a slower write speed. Because the data pre-write operation is performed in parallel with at least one of the sensing amplification phase and the data processing phase, the data pre-write operation does not affect the update of the row activation count value. After the data pre-write operation, the data write-back operation only needs to complete the writing of the second data, which has a faster write speed. This helps speed up the execution time of the data write-back operation, thereby shortening the overall update time of the row activation count value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart corresponding to each step in the row activation count update method provided in some embodiments of the present disclosure;

[0022] Figure 2A flowchart corresponding to each step in the data processing stage provided in some embodiments of the present disclosure;

[0023] Figure 3 A schematic diagram of a circuit structure involved in executing a row activation count update provided in some embodiments of the present disclosure;

[0024] Figure 4 A schematic diagram of the structure of a memory provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0026] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0028] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0029] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0030] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0031] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or a third component can be present between the two components. Conversely, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0032] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component can be present between them. In addition, when a component such as a layer, film, region, or plate is "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located between them.

[0033] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0034] As can be seen from the background technology, how to implement the row-by-row activation counting function of the memory and meet the timing, power consumption and area requirements of the memory is an important aspect that is currently being focused on and technological breakthroughs are being made.

[0035] An embodiment of the present disclosure provides a row activation count update method, comprising: in response to an external activation command, updating the row activation count value of a target word line corresponding to the external activation command; wherein the update process comprises: a data reading operation, a sensing amplification stage, a data processing stage and a data write-back operation performed in sequence; the data reading operation and the sensing amplification stage are configured to obtain the row activation count value stored in a counting storage unit connected to the target word line; the data processing stage is configured to process the row activation count value to obtain a value to be written back; after performing the data reading operation and before performing the data write-back operation, a data pre-write operation is performed in parallel; the data pre-write operation is configured to write first data to the counting storage unit connected to the target word line; the data write-back operation is configured to write second data to the corresponding counting storage unit connected to the target word line based on the position of each second data in the value to be written back; the speed at which the memory writes the second data is faster than the speed at which the memory writes the first data.

[0036] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0037] refer to Figure 1 , Figure 1 A flowchart illustrating the steps in a row activation count update method provided in some embodiments. The row activation count update method includes step 100: in response to an external activation command, updating the row activation count value of the target word line corresponding to the external activation command. The update process includes steps 101 to 104; step 101 is a data read operation; step 102 is a sensing and amplification phase; step 103 is a data processing phase; and step 104 is a data write-back operation.

[0038] In addition, step 100 in the row activation count update method also includes step 105, a data pre-write operation. In the row activation count update method, after performing the data read operation and before performing the data write-back operation, the data pre-write operation is performed in parallel. That is, the update process includes a first action and a second action performed in parallel, wherein the first action is a sensing amplification stage and a data processing stage after the data read operation and before the data write-back operation, that is, steps 102 and 103 after step 101 and before step 104. The second action is a data pre-write operation after the data read operation and before the data write-back operation, that is, step 105 after step 101 and before step 104.

[0039] In step 100 , in response to an external active command, a row active count value of a target word line corresponding to the external active command is updated.

[0040] The external activation command is used to activate the word line (WL) in the memory. The word line to be activated by the external activation command is selected based on the row address (Row Address), that is, the row address corresponding to the external activation command is used to select the target word line from multiple word lines in the memory.

[0041] It should be noted that the "memory" mentioned in the description of the embodiments of this disclosure is a memory that supports a row-by-row activation counting function. For a memory that supports a row-by-row activation counting function, the storage cells connected to the word lines are divided into at least two categories according to their functions. The first category is a counting storage cell, and the second category is a regular storage cell; the counting storage cell is used to store a row activation count value, which is used to represent the number of times the corresponding word line is activated, and the regular storage cell is used to store data received from the outside and verification data generated based on the received data.

[0042] In addition, as for the row activation count value, based on the foregoing, it can be known that the row activation count value can be used to record and monitor the performance impact of row hammer on adjacent rows. When the row activation count value of a certain word line meets the preset requirements, the word line becomes the attacking row. After refreshing the victim row (i.e., the row hammer row) corresponding to the attacking row, the row activation count value corresponding to the attacking row can be reset to 0, indicating that the row hammer impact of the attacking row has been eliminated. It should be noted that after refreshing the row hammer row, the row activation count value of the attacking row can also be reset according to other rules, such as resetting it to half of the original row activation count value or adjusting it to a preset fixed value, so as to eliminate the adverse effects that may be caused by directly resetting it to 0. In other words, after refreshing the victim row, if the attacking row is activated, the operation performed in the data processing stage is no longer an accumulation operation, but a reset operation.

[0043] The memory usually includes multiple storage banks, and the counting storage units of different storage banks are independent of each other. Under normal working conditions, the memory usually only turns on one word line of a certain storage bank at the same time. The same storage bank can be divided into multiple storage areas, and different storage areas have corresponding word lines. The row address addresses of the word lines in the same row in different storage areas are the same. The memory will activate the corresponding word lines of different storage areas based on the same row address. Therefore, the word lines with the same row address in different storage areas can be regarded as one word line. Assume that there are N storage cells connected to a word line of the memory, and m of the N storage cells are used to store the row activation count value, that is, m counting storage cells, and Nm storage cells are used to store data received from the outside and verification data generated based on the received data, etc., where m is less than N. It should be noted that in the subsequent description of the embodiments of the present disclosure, a word line refers to a set of word lines with the same row address in different storage areas of the memory.

[0044] In some embodiments, m is 32, that is, each word line of the memory includes 32 counting storage cells. The first part of the 32 counting storage cells serves as a row activation count value storage cell for storing the row activation count value, the second part serves as a redundant storage cell for redundant replacement, and the third part serves as a check value storage cell for storing the check value corresponding to the row activation count value, so as to perform error detection and correction on the row activation count value. For example, 16 of the 32 counting storage cells serve as preset counting storage cells in the first part to store the corresponding row activation count value, 8 counting storage cells serve as redundant counting storage cells in the second part, and 8 counting storage cells serve as check value storage cells in the third part.

[0045] For a memory, the memory selects a target word line based on a row address and activates the target word line in response to an external activation command. After the target word line is activated, the memory performs related operations on the memory cells connected to the target word line, such as reading data stored in regular memory cells, writing data to regular memory cells, etc., and updating the row activation count value stored in the counting memory cell. Among them, step 100 is used to describe the process of updating the row activation count value stored in the counting memory cell.

[0046] For step 101 , the data read operation is configured as follows: after the target word line is activated based on the external activation command, a row activation count value corresponding to the target word line is read from a count storage unit corresponding to the target word line.

[0047] It should be noted that the row activation count value stored in the counting storage unit may be erroneous. In the subsequent data processing stage, it is necessary to check whether the row activation count value is erroneous based on the check value of the row activation count value in the counting storage unit. If an error occurs, the operation processing is performed after the error is corrected to update the row activation count value. If no error occurs, the operation processing is directly performed to update the row activation count value.

[0048] Regarding step 102 , the sensing and amplification stage is configured to perform sensing and amplification on the row activation count value to read out the row activation count value stored in the counting storage unit.

[0049] Regarding step 103, the data processing stage is configured to process the row activation count value to obtain the value to be written back, wherein the processing of the row activation count value is the row activation count value + 1, thereby obtaining the value to be written back.

[0050] For step 105, the data pre-write operation is configured to write the first data to the counting memory cells connected to the target word line. It is understood that the counting memory cells written with the first data refer to the counting memory cells for storing the row activation count value, not all the counting memory cells.

[0051] In step 104, the data write-back operation is configured to write the second data to the corresponding counting storage cells connected to the target word line based on the position of each second data in the value to be written back, wherein the speed at which the memory writes the second data is faster than the speed at which the memory writes the first data. It is understood that the corresponding counting storage cells connected to the target word line refer to the portion of the counting storage cells whose values to be written back are the second data among the plurality of counting storage cells for storing the row activation count value.

[0052] In some embodiments, if the speed at which the memory writes “1” is faster than the speed at which the memory writes “0”, the first data is “0” and the second data is “1”.

[0053] In some embodiments, if the speed of writing “0” into the memory is faster than the speed of writing “1” into the memory, the first data is “1” and the second data is “0”.

[0054] For example, if the speed of writing "0" in the memory is faster than the speed of writing "1", it is assumed that the row activation count values stored in the four least significant memory cells (the first cell, the second cell, the third cell and the fourth cell) of the counting memory cell are "0101".

[0055] The row activation count value obtained in steps 101 and 102 is "0101." Step 103 increments the row activation count by 1, obtaining the value to be written back as "0110." Step 105 is executed in parallel with steps 102 and 103. Step 105 is used to pre-write "1" to the first, second, third, and fourth cells. At this point, step 104 writes "0" to the first and fourth cells based on the position of the data "0" in the value to be written back as "0110," thereby writing the value to be written back into the counting storage unit.

[0056] In summary, data write-back is divided into a data pre-write operation and a data write-back operation. The data pre-write operation is used to write the first data with a slower write speed, and the data write-back operation is used to write the second data with a faster write speed. Since the data pre-write operation is performed in parallel with at least one of the sensing amplification stage and the data processing stage, the devices involved in the data pre-write operation are completely different from the devices involved in the data processing stage. Therefore, the data pre-write operation will not affect the update of the row activation count value. After the data pre-write operation, the data write-back operation only needs to complete the writing of the second data with a faster write speed, which is conducive to shortening the execution time of the data write-back operation, thereby shortening the overall time of the row activation count value update.

[0057] Among them, the data pre-write operation is performed in parallel with at least one of the sensing amplification stage and the data processing stage, which means that: the data pre-write operation is performed in parallel with part of the time period of the sensing amplification stage, or the data pre-write operation is performed in parallel with part of the time period of the sensing amplification stage and at least part of the time period of the data processing stage (for example, in parallel with a continuous time period consisting of the latter b / c time period of the sensing amplification stage and the first s / k time period of the data processing stage, where b, c, s and k are all positive integers greater than 1, c is greater than b, and k is greater than s), or the data pre-write operation is performed in parallel with at least part of the time period of the data processing stage.

[0058] In some embodiments, the data processing stage further includes error detection and correction of the row activation count value. Figure 2 , Figure 2 Flowcharts corresponding to the steps in the data processing phase provided in some embodiments. In some embodiments, the data processing phase includes: an error detection and correction phase, a data processing operation, and a check code generation phase. That is, step 103 includes steps 201 to 203, wherein step 201 is the error detection and correction phase; step 202 is the data processing operation; and step 203 is the check code generation phase.

[0059] Based on the foregoing, it can be seen that when the row activation count value needs to be error detected and corrected, the counting storage unit is used to store the row activation count value and the check value corresponding to the row activation count value. At this time, step 101 will read the row activation count value and the check value at the same time. For step 201, the error detection and correction stage is configured to include: error detection and correction of the row activation count value based on the check value corresponding to the row activation count value to obtain the correct row activation count value. For step 202, the data processing operation is configured to perform accumulation processing on the row activation count value to generate a value to be written back. For step 203, the check code generation stage is configured to generate a check value corresponding to the value to be written back. By performing error detection and correction on the row activation count value in the data processing stage, the accuracy of the row activation count value corresponding to the target word line is guaranteed, that is, the accuracy of the row-by-row activation counting function of the memory is guaranteed. It can be understood that in a specific scenario, if the data processing operation is configured to reset the row activation count value, the error detection and correction stage can be skipped and the data processing operation can be performed directly.

[0060] In step 100, the word lines in the memory include regular word lines and redundant word lines, wherein a regular word line may fail due to damage or other reasons and be replaced by a redundant word line. In some embodiments, before updating the row activation count value of the target word line corresponding to the external activation command, the row activation count update method further includes: obtaining the target word line corresponding to the external activation command.

[0061] Specifically, based on the failed row address stored in the register in the memory, it is determined whether the regular word line corresponding to the target row address has been replaced by a redundant word line. If the regular word line corresponding to the target row address has been replaced and repaired by a redundant word line, the redundant word line corresponding to the target row address is accessed, and the "target word line" is the redundant word line. If the regular word line corresponding to the target row address has not failed, the regular word line is directly accessed, and the "target word line" is the regular word line.

[0062] In addition, in some embodiments of the present application, when updating the row activation count value of a word line, the row activation count value update target is the counting storage unit corresponding to the target word line. In some embodiments, after obtaining the target word line, the row activation count update method further includes: obtaining the address of the counting storage unit corresponding to the target word line.

[0063] As previously mentioned, the counting storage cells corresponding to the target wordline include a row activation count storage cell, a redundant count cell, and a check value storage cell. It should be noted that a wordline is a "row" in the memory, and the selection of a specific storage cell from the target wordline is based on a "column." A "column" is a bitline in the memory, and a bitline is selected based on the column address.

[0064] In some embodiments, the counting storage unit includes a row activation count value storage unit for storing a row activation count value, and the method for obtaining the counting storage unit address corresponding to the target word line includes: judging whether the column address corresponding to the row activation count value storage unit has undergone redundant replacement based on the failed column address stored in the register of the memory; if part of the column address corresponding to the row activation count value storage unit has undergone redundant replacement, then accessing the remaining column addresses that have not undergone redundant replacement and the redundant column addresses that have undergone redundant replacement corresponding to the row activation count value storage unit; if none of the column addresses corresponding to the row activation count value storage unit have undergone redundant replacement, then directly accessing the column address corresponding to the row activation count value storage unit.

[0065] It should be noted that since the execution target of the external activation command is the word line, it is necessary to determine whether redundant replacement has occurred on the regular word line corresponding to the row address before executing the external activation command. The actual storage column address of the row activation count value is obtained for updating the row activation count value, so it can be obtained before executing the update of the row activation count value. In other words, the actual storage column address of the row activation count value can be obtained before activating the corresponding word line in response to the external activation command, or it can be performed in the precharge stage after activating the word line in response to the external activation command.

[0066] refer to Figure 3 , Figure 3 Schematic diagram of the circuit structure involved in performing row activation count update provided in some embodiments. Figure 3 (a) is a schematic diagram of the related circuit of the bit line sense amplifier. Figure 3 (b) is a circuit diagram of a counting storage unit, which includes a transmission transistor and a storage capacitor C s , Figure 3 (c) is a schematic diagram of the memory read-write conversion circuit. Figure 3 (d) is the circuit diagram of the global driver GIO driver. Figure 3 Signals, components, circuits, etc. that are not directly related to the embodiments of the present disclosure, Figure 3 No relevant markings are made in the examples. Figure 3 The various types of circuit structures shown in are only examples and do not constitute a structural limitation on the embodiments of the present disclosure. The embodiments of the present disclosure may adopt other types of circuit structures as long as they can implement corresponding data reading and data writing.

[0067] It should be noted that the "sensing amplification stage" mentioned in the embodiments of the present disclosure includes a first amplification stage performed by a bit line sense amplifier (BLSA), a second amplification stage performed by a local sense amplifier (LSA), and a third sensing stage performed by a global sense amplifier (YSA). The "sensing amplifier" mentioned in the embodiments of the present disclosure refers to a bit line sense amplifier (BLSA). The bit line sense amplifier is used to amplify the voltage difference between the bit line and the complementary bit line, the local sense amplifier is used to amplify the voltage difference between the local data line and the local complementary data line, and the global sense amplifier is used to amplify the voltage difference between the global data line and the global complementary data line. The bit line / complementary bit line is connected to the local data line / local complementary data line through a column select transistor, and the local data line / local complementary data line is connected to the global data line / global complementary data line through a read-write conversion circuit.

[0068] refer to Figure 3 (b) When the target word line WL is activated, the row activation count value stored in the counting storage unit corresponding to the target word line WL is transmitted to the bit line BL.

[0069] refer to Figure 3 (a) The sense amplifier amplifies the row activation count value on the bit line BL. After the column select transistors corresponding to the bit line BL / complementary bit line are turned on by the corresponding column select signal CSL, the row activation count value is transmitted to the local data line Io / local complementary data line IoN. The bit line sense amplifier has a power connection point PCS and a ground connection point NCS. The power connection point PCS is used to receive a high-level voltage, and the ground connection point NCS is used to receive a low-level voltage.

[0070] refer to Figure 3 (c) The read-write conversion circuit is configured to transfer the data on the local data line Io to the global data line Yio and the data on the local complementary data line IoN to the global complementary data line YioN based on the read enable signal RdEn, or transfer the data on the global data line Yio to the local data line Io and the data on the global complementary data line YioN to the local complementary data line IoN based on the write enable signal WrEn. It can be understood that due to Figure 3 Due to the structural limitation of the read-write conversion circuit shown in c, during a read operation, the data on the local data line Io and the global data line Yio are actually opposite, and the data on the local complementary data line IoN and the global complementary data line YioN are actually opposite.

[0071] refer to Figure 3(d) The global driver GIO driver is configured to, based on a write enable signal WrEn, write data Data to the global data line Yio and write complementary data Data- to the global complementary data line YioN, where the data Data and complementary data Data- are complementary data. It should be noted that during a read operation on the memory, the data is ultimately transmitted to the next-level data line via the global data line and the global complementary data line. During a write operation (writing received external data), the data is written to the global data line and the global complementary data line via the global driver and ultimately written to the memory cell.

[0072] In the subsequent description of the embodiments of the present disclosure, the working principles and connection relationships are described based on the local data line Io and the global data line Yio. Those skilled in the art can obtain the corresponding working principles and connection relationships of the local complementary data line IoN and the global complementary data line YioN based on the corresponding complementary relationships, and the embodiments of the present disclosure will not be repeated.

[0073] Continue to refer Figure 3 In some embodiments, the data pre-write operation generates first data based on a global driver GIO driver and writes the first data through a global data line Yio.

[0074] The data pre-write operation is based on the global driver GIO driver writing the first data Data into the global data line Yio. The global data line Yio writes the first data into the local data line Io based on the write enable WrEn. After the column select transistor connected to the local data line Io is turned on based on the corresponding column select signal CSL, the first data is transferred to the bit line BL and thus written into the counting storage unit.

[0075] Because the data pre-write operation's write path is the same as the read path during the sensing and amplification phase, both passing through the bit lines, local data lines, and global data lines, if the data pre-write operation is performed through the global driver and the sensing and amplification phase are performed simultaneously, a conflict will occur between the two, resulting in data errors. Therefore, if the data pre-write operation is performed through the global driver, the data pre-write operation must be executed after the sensing and amplification phase ends. That is, after step 102 is executed, steps 103 and 105 are executed simultaneously.

[0076] Continue to refer Figure 3 In some embodiments, the data pre-write operation generates first data based on a pre-write circuit and writes the first data through the bit line BL or the local data line Io located between the bit line BL and the global data line Yio.

[0077] Specifically, the data pre-write operation is based on the first data generated by the pre-write circuit being directly transferred to the bit line BL, bypassing the local data line and the global data line, and thus directly written into the counting storage unit. Alternatively, the data pre-write operation is based on the first data generated by the pre-write circuit being directly transferred to the local data line Io, bypassing the global data line. After the column select transistor connected to the local data line Io is turned on based on the corresponding column selection signal CSL, the first data is transferred to the bit line BL, thereby being written into the counting storage unit. In this way, when the read row activation count value is transmitted to the global data line or the local data line via the read-write conversion circuit, the data pre-write operation can be performed, which helps to reserve more time for the data pre-write operation and ensure that the data pre-write operation is completed before the data processing stage is completed.

[0078] In some embodiments, the pre-write circuit includes an internal power supply corresponding to the first data, and the internal power supply is configured to provide a power supply voltage corresponding to the first data.

[0079] In some embodiments, if the first data written in the data pre-write operation is "0", the internal power supply is used to provide a low level; if the first data written in the data pre-write operation is "1", the internal power supply is used to provide a high level.

[0080] In addition, based on the above content, it can be known that the pre-write circuit can be connected to the bit line BL or the local data line Io. Based on the difference between the bit line BL and the local data line Io, the internal power supply of the pre-write circuit provides different power supply voltages for the first data.

[0081] In some embodiments, if the first data written by the first pre-write operation to the bit line BL or the local data line Io is "1", the first complementary data written by the first pre-write operation to the complementary bit line or the local complementary input / output line IoN is "0".

[0082] In some embodiments, the internal power supply may output the power supply voltage or the ground voltage through a relatively complex structure such as a driver, or may output the power supply voltage or the ground voltage through a relatively simple circuit such as a switch tube.

[0083] Based on the above description, it can be known that in the sensing and amplification stage, the memory needs to turn on the column selection transistor to transfer the stored read value on the bit line BL to the local data line Io; in the data pre-write operation, the memory may need to turn on the column selection transistor to transfer the first data from the local data line Io to the bit line BL to write the first data to the counting storage unit; in the data write-back stage, the column selection transistor also needs to be turned on when the value to be written back is transferred from the global data line Yio to the bit line BL. In some embodiments, in the process of updating the row activation count value in the memory, the column selection transistor corresponding to the counting storage unit remains in the on state to avoid the power consumption waste caused by the frequent turning on of the column selection transistor and reduce the power consumption of updating the row activation count value. It should be noted that the column selection transistors corresponding to all counting storage units can be maintained in the on state during the update process, or the column selection transistors corresponding to the storage unit that only stores the row activation count value can be maintained in the on state during the update process.

[0084] Furthermore, during the data write-back phase, the transfer of the value to be written back from the global data line Yio to the bit line BL also requires turning on the column select transistor corresponding to the write transistor between the local data line Io and the global data line Yio (driven by the write enable WrEn). In the data pre-write operation, in a scheme where the data is written based on a global driver, the column select transistor corresponding to the write transistor between the local data line Io and the global data line Yio also needs to be turned on. In some embodiments, during the update process after the memory reads the row activation count value, the column select transistor corresponding to the write transistor between the local data line Io and the global data line Yio remains in the on state to avoid power consumption caused by frequently turning on the write transistor and reduce power consumption for updating the row activation count value.

[0085] In some embodiments, the data processing operation is performed based on a data processing circuit, and the data processing circuit includes a serial carry adder. Based on the foregoing, it can be seen that the data processing stage and the sensing amplification stage are performed in parallel with the data pre-write operation, and the memory performs the data write-back operation only after the data processing stage and the data pre-write operation are completed. Among them, since the data pre-write operation needs to write the first data, the speed of the memory writing the first data is slow. In order to avoid the data processing stage being too much ahead of the completion of the data pre-write operation, the data processing circuit can release the reduced timing requirements. Therefore, the data processing circuit can use a small and slow adder, such as a serial carry adder, etc., to reduce the area of the memory.

[0086] In summary, for the row activation count update method provided by the embodiment of the present disclosure, the data write-back part is split into a data pre-write operation and a data write-back operation, and the data pre-write operation is used to write the first data with a slower writing speed. Since the data pre-write operation is performed in parallel with at least one of the sensing amplification stage and the data processing stage, the data pre-write operation does not affect the update of the row activation count value. After the data pre-write operation, the data write-back operation only needs to complete the writing of the second data with a faster writing speed, which is conducive to speeding up the execution time of the data write-back operation, thereby shortening the overall time of the row activation count value update.

[0087] It should be noted that, in the absence of conflict, the features disclosed in the row activation count update method provided in the above embodiments can be randomly combined to obtain a new row activation count update method embodiment.

[0088] Another embodiment of the present disclosure further provides a memory to shorten the time occupied by the row-by-row activation counting function, thereby reducing the impact of adding the row-by-row activation counting function on the memory timing.

[0089] refer to Figure 4 , Figure 4 Schematic diagram of a memory structure provided in some embodiments. In some embodiments, memory 300 includes a controller 301 and a memory array 302. Controller 301 is configured to update the row activation count value corresponding to the target word line in the memory array based on the row activation count update method provided in the above embodiments.

[0090] In some embodiments, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (25DDR4 SDRAM), a thyristor random access memory (TRAM), or the like; or may be a non-volatile memory, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), or the like.

[0091] In some embodiments, the memory provided in this application can be applied to a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0092] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0093] The basic concepts have been described above. It will be apparent to those skilled in the art that the detailed disclosure above is merely illustrative and does not limit the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application and remain within the spirit and scope of the exemplary embodiments of the present application.

[0094] The above is a detailed introduction to a row activation count update method and memory provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A row activation count update method, applied to a memory, characterized in that: include: In response to an external activation command, updating a row activation count value of a target word line corresponding to the external activation command; wherein the update process includes: a data read operation, a sensing amplification stage, a data processing stage, and a data write-back operation performed in sequence; The data reading operation and the sense amplification stage are configured to obtain a row activation count value stored in a count storage unit connected to the target word line; The data processing stage is configured to process the row activation count value to obtain a value to be written back; After executing the data read operation and before executing the data write-back operation, executing a data pre-write operation in parallel; The data pre-write operation is configured to write first data into the counting storage unit connected to the target word line; The data write-back operation is configured to write the second data into the corresponding counting storage unit connected to the target word line based on the position of each second data in the to-be-written-back value; The memory writes the second data faster than the memory writes the first data.

2. The row activation count update method according to claim 1, wherein: The data processing stage includes: an error detection and correction stage, a data processing operation and a check code generation stage; The error detection and correction stage is configured to include: performing error detection and correction on the row activation count value based on a check value corresponding to the row activation count value to obtain a correct row activation count value; The data processing operation is configured to perform accumulation processing on the row activation count value to generate the to-be-written-back value; The check code generation stage is configured to generate a check value corresponding to the value to be written back.

3. The row activation count update method according to claim 1, wherein: The data pre-write operation generates the first data based on a global driver and writes the first data through a global input-output line, or the data pre-write operation generates the first data based on a pre-write circuit and writes the first data through a bit line or a local input-output line located between the bit line and the global input-output line. 4 . The row activation count update method according to claim 3 , wherein the pre-write circuit comprises an internal power supply corresponding to the first data, and the internal power supply is configured to provide a power supply voltage corresponding to the first data.

5. The row activation count update method according to claim 3, characterized in that: If the data pre-write operation is based on writing the first data by the global driver, the data pre-write operation is started after the sensing and amplification stage ends.

6. The row activation count update method according to claim 3, wherein: If the data pre-write operation is based on writing the first data by the pre-write circuit, the data pre-write operation is started in parallel with the sensing and amplification stage.

7. The row activation count update method according to claim 1, wherein: In the process of updating the row activation count value in the memory, the column selection transistors corresponding to all the counting storage units are kept in the on state.

8. The row activation count update method according to claim 7, wherein: In an update process after the memory reads the row activation count value, the column selection transistor corresponding to the write transistor between the local input / output line and the global input / output line is kept in an on state.

9. The row activation count update method according to claim 2, wherein: The data processing operation is performed based on a data processing circuit, and the data processing circuit includes a serial carry adder.

10. The row activation count update method according to claim 1, wherein: Before updating the row activation count value of the target word line corresponding to the external activation command, the row activation count update method further includes: acquiring the target word line corresponding to the external activation command.

11. The row activation count update method according to claim 10, wherein: After acquiring the target word line, the row activation count update method further includes: acquiring a counting storage unit address corresponding to the target word line.

12. The row activation count update method according to claim 11, wherein: The counting storage unit includes a row activation count value storage unit for storing a row activation count value, and the method for obtaining the counting storage unit address corresponding to the target word line includes: determining whether a column address corresponding to the row activation count value storage unit has been redundantly replaced based on the failure address stored in the register; If a portion of the column addresses corresponding to the row activation count value storage unit undergoes redundant replacement, accessing the remaining portion of the column addresses corresponding to the row activation count value storage unit that have not undergone redundant replacement and the redundant column addresses that undergo redundant replacement; If no redundant replacement occurs in the column addresses corresponding to the row activation count value storage units, the column addresses corresponding to the row activation count value storage units are directly accessed.

13. A memory, characterized in that: include: A controller and a memory array, wherein the controller is configured to update a row activation count value corresponding to a target word line in the memory array based on the row activation count update method according to any one of claims 1 to 12.

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