Method of manufacturing semiconductor package

Abstract

A method of manufacturing a semiconductor package includes preparing a molded structure having connection bumps provided thereon, forming a mold release layer at least partially filling a space between the connection bumps, in which the mold release layer includes a silicon (Si)-based polymer, forming an adhesive layer covering the mold release layer and the connection bumps, and forming an adhesive layer covering the mold release layer and the connection bumps. A unit package on which the release layer and the adhesive layer are formed is separated by cutting the molded structure, the release layer, and the adhesive layer, the unit package is attached to a base film by the adhesive layer, the adhesive layer facing the base film, and the unit package is separated by cutting the release layer and the adhesive layer. Forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion of the adhesive layer, and separating the unit packages covered with the shielding material layer from the release layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2024-0019793 filed on February 8, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Example embodiments of the present disclosure relate to methods of manufacturing semiconductor packages. Background Art

[0004] In order to protect users of electronic devices or semiconductor chips from electromagnetic interference (EMI), EMI shielding of semiconductor packages is required. Therefore, manufacturing technologies for semiconductor packages including electromagnetic wave shielding layers are being developed.

[0005] The information disclosed in this background section is known or derived by the inventors before or during the process of implementing the embodiments of the present application, or is technical information obtained in the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0006] One or more example embodiments provide a method of manufacturing a semiconductor package having improved reliability.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to aspects of one or more embodiments, a method for manufacturing a semiconductor package may include: preparing (preparing) a molded (molded) structure on which connecting bumps (bumps) are provided, forming a release layer (release layer) that at least partially fills the space between the connecting bumps, wherein the release layer includes a silicon (Si)-based polymer, forming an adhesive layer covering the release layer and the connecting bumps, separating the unit (unit) packages on which the release layer and the adhesive layer are formed by cutting the molded structure, the release layer and the adhesive layer, attaching the unit packages to a base film through the adhesive layer, wherein the adhesive layer faces the base film, forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer and at least a portion of the adhesive layer, separating the unit packages covered with the shielding material layer from the release layer, and removing residues of the release layer on the unit packages using an etchant including at least one of fluoride ions, hydroxide ions and hydrogen ions.

[0009] According to aspects of one or more embodiments, a method for manufacturing a semiconductor package may include: preparing a molded structure on which connecting bumps are provided, forming a release layer that at least partially fills the space between the connecting bumps, forming an adhesive layer covering the release layer and the connecting bumps, separating unit packages on which the release layer and the adhesive layer are formed by cutting the molded structure, the release layer and the adhesive layer, attaching the unit packages to a base film, forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer and at least a portion of the adhesive layer, and separating the unit packages covered with the shielding material layer from the release layer, wherein the release layer may include a first portion that at least partially fills the space between adjacent connecting bumps and a second portion that at least partially covers the surface of each of the connecting bumps, and a first thickness of the first portion of the release layer is different from a second thickness of the second portion of the release layer.

[0010] According to aspects of one or more embodiments, a method for manufacturing a semiconductor package may include: preparing a molded structure on which connecting bumps are provided, forming a release layer that at least partially fills a space between the connecting bumps, forming an adhesive layer covering the release layer and the connecting bumps, separating a unit package on which the release layer and the adhesive layer are formed by cutting the molded structure, the release layer, and the adhesive layer, attaching the unit package to a base film, forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion of the adhesive layer, and separating the unit package covered with the shielding material layer from the release layer, wherein the release layer may include polydimethylsiloxane (PDMS) or a cross-linked silicone polymer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of some example embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a flow chart illustrating a method of manufacturing a semiconductor package according to one or more embodiments;

[0013] Figure 2 To illustrate the Figure 1 a cross-sectional view of operation S101;

[0014] Figure 3A and 3B To illustrate the Figure 1 a cross-sectional view of operation S102;

[0015] Figure 4 To illustrate the Figure 1 a cross-sectional view of operation S103;

[0016] Figure 5 To illustrate the Figure 1 a cross-sectional view of operation S104;

[0017] Figure 6 To illustrate the Figure 1 a cross-sectional view of operation S105;

[0018] Figure 7 To illustrate the Figure 1 a cross-sectional view of operation S106;

[0019] Figure 8 To illustrate the Figure 1 a cross-sectional view of operations S107 and S108; and

[0020] Figure 9A and 9B is a cross-sectional view illustrating a semiconductor package according to one or more embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof will be omitted. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0022] As used herein, phrases such as “at least one of” when preceding or following a list of elements modify the entire list of elements and do not modify the individual elements of that list. For example, the phrase “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0023] Unless otherwise specified, the terms “upper portion,” “upper surface,” “lower portion,” “lower surface,” “side surface,” etc. are based on the drawings and may vary in the direction in which components are actually arranged when used.

[0024] It will be understood that when an element or layer is referred to as being “on,” “over,” “up,” “below,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly on, over, over, below, under, directly connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly below,” “directly below,” “directly below,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0025] As used herein, the terms “covering” and “filling” may refer to partial covering / filling or complete covering / filling, as will be understood by one of ordinary skill in the art from the disclosure herein.

[0026] In addition, ordinal numbers such as "first," "second," and "third" can be used as labels for specific elements, steps, directions, etc. to distinguish multiple elements, steps, directions, etc. from each other. Terms that are not described using "first," "second," etc. in the specification can still be referred to as "first" or "second" in the claims. In addition, terms referenced by specific ordinal numbers can be described using different ordinal numbers elsewhere.

[0027] Figure 1 FIG. 1 is a flow chart illustrating a method S100 of manufacturing a semiconductor package according to one or more embodiments.

[0028] Reference Figure 1According to one or more embodiments, the method for manufacturing a semiconductor package (S100) may include: an operation (S101) of preparing a mold structure to which connection bumps are attached; an operation (S102) of forming a release layer on one surface of the mold structure to fill spaces between the connection bumps; an operation (S103) of forming an adhesive layer covering the release layer and the connection bumps on the mold structure; an operation (S104) of separating unit packages on which the release layer and the adhesive layer are formed by cutting the mold structure, the release layer, and the adhesive layer; an operation (S105) of attaching the unit packages to a base film; an operation (S106) of forming a shielding material layer covering each of the unit packages, the release layer, and at least a portion of the adhesive layer; and an operation (S107) of separating the unit packages covered with the shielding material layer from the release layer. According to one or more embodiments, the method for manufacturing a semiconductor package (S100) may further include an operation (S108) of removing residues of the release layer on the unit packages.

[0029] According to one or more embodiments, by using a release layer comprising a silicon (Si)-based polymer, the unit package can be mechanically separated from the release layer without requiring an additional process to remove the adhesive force between the release layer and the connection bump. That is, the unit package can be separated from the release layer while the release layer and the adhesive layer remain adhered to the base film. In addition, even if the size of the connection bump, such as the horizontal width and / or height, increases, the release layer comprising a silicon (Si)-based polymer can fully fill the space between adjacent connection bumps, thereby preventing the occurrence of voids and back-spill defects.

[0030] In the following, reference is made to Figures 2 to 8 A method S100 of manufacturing a semiconductor package according to one or more embodiments is described in detail.

[0031] Figure 2 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S101.

[0032] Reference Figure 1 and 2 , a molded structure MS including a plurality of unit packages 100U may be prepared. The molded structure MS may include a substrate bar 110 ′, a semiconductor chip 120 , a molding (mold) layer 130 , and connection bumps 150 .

[0033] The substrate strip 110' may include a plurality of package substrates (e.g., printed circuit boards (PCBs)) connected as one. The semiconductor chip 120 may be electrically connected to the first surface 110S1 of the substrate strip 110' using a flip-chip method or a wire bonding method. The semiconductor chips 120 may be provided in a larger number than shown in the figure. For example, each of the plurality of unit packages 100U may include a plurality of semiconductor chips arranged vertically and / or horizontally on the substrate strip 110' or the package substrate.

[0034] The semiconductor chip 120 may include logic chips, such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, and an application-specific integrated circuit (ASIC), and / or memory chips including: volatile memory, such as dynamic random access memory (RAM) (DRAM), static RAM (SRAM), etc., and non-volatile memory, such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, etc.

[0035] The molding layer 130 may include an insulating resin that seals the semiconductor chip 120, such as a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or a prepreg (prepreg), Ajinomoto build-up film (ABF), FR-4, bismaleimide-triazine (BT), epoxy molding compound (EMC), etc.

[0036] Connecting bumps 150 may be arranged on second surface 110S2 of substrate strip 110'. Connecting bumps 150 may be attached to lower terminals 110P of substrate strip 110'. Connecting bumps 150 may include a low-melting-point metal, such as tin (Sn) or an alloy including tin (Sn) (e.g., Sn-Ag-Cu, Sn-Ag, etc.). According to one or more embodiments, connecting bumps 150 may have a combination of a post and a ball.

[0037] The height H of the connecting bump 150 may be about 180 μm or greater. For example, the height H of the connecting bump 150 may be about 180 μm to about 400 μm, but is not limited thereto. The horizontal width W of the connecting bump 150 may be about 180 μm or greater. For example, the horizontal width W of the connecting bump 150 may be about 180 μm to about 400 μm, but is not limited thereto. The spacing d between adjacent connecting bumps 150 may be about 180 μm to about 400 μm, but is not limited thereto. Since the connecting bump 150 is completely impregnated with the release layer to be described below, in the method S100 of manufacturing a semiconductor package in one or more embodiments, the electromagnetic wave shielding layer for the semiconductor package can be formed without being restricted by the size of the connecting bump 150.

[0038] Figure 3A and 3B To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S102 .

[0039] Reference Figure 1 and 3A The release layer 210 may be formed on the mold structure MS. The release layer 210 may be directly coated on the second surface 110S2 of the substrate strip 110'. The release layer 210 may be formed using, for example, spin coating or slit coating. The release layer 210 may include a silicon (Si)-based polymer.

[0040] The release layer 210 may include, for example, polydimethylsiloxane (PDMS) or a cross-linked silicone polymer. In one or more embodiments, the release layer 210 may include a compound represented by the following chemical formula (1) or chemical formula (2). The following chemical formula (1) represents the structural formula of PDMS, and the following chemical formula (2) represents the polymer formula of a cross-linked silicone polymer using polymethylsiloxane (methicone) and vinyl polydimethylsiloxane (dimethicone).

[0041] [Chemical formula (1)]

[0042]

[0043] "n" represents the degree of polymerization, which varies depending on the chain length of the respective species.

[0044] In the chemical formula (1), n is 1 or greater.

[0045] [Chemical formula (2)]

[0046]

[0047] "x" and "y" represent the degree of polymerization, which varies depending on the chain length of each species.

[0048] In the chemical formula (2), x and y are 1 or greater.

[0049] The viscosity of the release layer 210 may range from about 0.5 mPa·s to about 30,000 mPa·s, or from about 10 mPa·s to about 1,000 mPa·s (@25° C.). If the viscosity of the release layer 210 exceeds about 30,000 mPa·s, the filling property of the release layer 210 between the connection bumps 150 may be reduced. If the viscosity of the release layer 210 is less than about 0.5 mPa·s, it may be difficult for the release layer 210 to cover the curved surface of the connection bump 150. In addition, in order to make the release layer 210 smooth during the sawing process (see FIG. 2 ), the release layer 210 may be smooth during the sawing process (see FIG. 2 ). Figure 5 ), the elastic modulus of the release layer 210 may range from about 0.1 MPa to about 5 MPa, or from about 0.5 MPa to about 3 MPa, but is not limited thereto.

[0050] The release layer 210 may be formed using a silicon (Si)-based polymer mixed with various additives to have the aforementioned physical properties. For example, the release layer 210 of the example embodiment may be formed using a silicon (Si)-based polymer, wherein a silicon (Si)-containing polymer (e.g., PDMS, polymethylsiloxane, vinyl polydimethylsiloxane, etc.) is mixed with a cross-linking agent at a ratio of about 5:1 to about 20:1.

[0051] Release layer 210 may include a first portion 211 that fills the space between adjacent connection bumps 150 and a second portion 212 that covers at least a portion of the curved surface of each connection bump 150. First portion 211 of release layer 210 may cover ½ or more of the height H of connection bump 150. That is, first portion 211 may extend from surface 110S2 to at least half of the height H of connection bump 150. Second portion 212 of release layer 210 may conformally extend along at least a portion of the curved surface of each connection bump 150. A first thickness t1 of first portion 211 of release layer 210 and a second thickness t2 of second portion 212 of release layer 210 may differ from each other. First thickness t1 of first portion 211 of release layer 210 may be ½ or more of the height H of connection bump 150. Second thickness t2 of second portion 212 of release layer 210 may be less than first thickness t1 of first portion 211. For example, the first thickness t1 of the first portion 211 of the release layer 210 may be about 90 μm to about 300 μm, but is not limited thereto. The first thickness t1 of the first portion 211 of the release layer 210 may be determined by considering the height H, horizontal width W, and spacing d of the connection bumps 150 .

[0052] Reference Figure 1 and 3BAccording to one or more embodiments, before forming the release layer 210, an operation of surface treating the mold structure MS and the connection bump 150 may be further included. A surface treatment layer 210p may be further formed between the release layer 210 and the mold structure MS and between the release layer 210 and the connection bump 150. The surface treatment layer 210p may modify the surfaces of the connection bump 150 and the mold structure MS to be hydrophobic, allowing the release layer 210 to be easily separated in subsequent processes. When the mold structure MS is separated from the release layer 210, the surface treatment layer 210p may suppress the occurrence of residues of the release layer 210 and prevent damage to the connection bump 150. Depending on the process, the boundary between the surface treatment layer 210p and the release layer 210 may not be obvious. For example, when the release layer 210 includes PDMS, the surface treatment layer 210p may include a compound represented by the following chemical formula (3). The following chemical formula (3) represents hexamethyldisilazane (HMDS).

[0053] [Chemical formula (3)]

[0054]

[0055] Figure 4 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S103 .

[0056] Reference Figure 1 and 4 , an adhesive layer 220 may be formed on the molded structure MS. The adhesive layer 220 may be formed to cover the entire release layer 210 and the connection bump 150 (e.g., the exposed surface of the connection bump 150). The adhesive layer 220 may include a thermosetting polymer or a photocurable polymer. In one or more embodiments, the adhesive layer 220 may include a thermosetting silicone polymer or a photocurable silicone acryl polymer.

[0057] Connecting bump 150 may include an upper region covered by first portion 211 of release layer 210 and a lower region covered by second portion 212 of release layer 210. A height h1 of the upper region of connecting bump 150 may be equal to or greater than a height h2 of the lower region. A third thickness t3 of adhesive layer 220 may be greater than height h2 of the lower region of connecting bump 150. For example, third thickness t3 of adhesive layer 220 may be approximately 100 μm to approximately 250 μm, but is not limited thereto. Third thickness t3 of adhesive layer 220 may be determined by taking into account, for example, height h2 of the lower region of connecting bump 150.

[0058] Figure 5 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S104 .

[0059] Reference Figure 1 and 5 , the unit package 100U in which the release layer 210 and the adhesive layer 220 are formed can be separated. The unit package 100U may include the package substrate 110 separated from the substrate strip 110', at least one semiconductor chip 120, the mold layer 130 disposed on the upper surface 110S1 of the package substrate 110, and the connection bump 150 disposed on the lower surface 110S2 of the package substrate 110. The unit package 100U can be formed by cutting the mold structure MS, the release layer 210, and the adhesive layer 220. The mold structure MS, the release layer 210, and the adhesive layer 220 can be cut by a sawing process.

[0060] Figure 6 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S105 .

[0061] Reference Figure 1 and 6 , the unit package 100U can be attached to the base film 310. The unit package 100U can be arranged so that the adhesive layer 220 faces the base film 310. The unit package 100U can be arranged on the base film 310 pickup device 330 to be spaced apart from each other in the horizontal direction. The frame 320 can be attached to the end of the base film 310. The frame 320 can be formed of metal, but is not limited thereto. The base film 310 can be a film coated with an adhesive on at least one side thereof. For example, the base film 310 may include a polyimide (PI) film, a polyethylene terephthalate (PET) film, or a polyethylene naphthalate (PEN) film.

[0062] Figure 7 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operation S106 .

[0063] Reference Figure 1 and 7 , a shielding material layer 160' may be formed to cover the unit package 100U. The shielding material layer 160' may cover each of the unit packages 100U, the release layer 210, and at least a portion of the adhesive layer 220. The shielding material layer 160' may be conformally formed by a coating device 340. The coating device 340 may form the shielding material layer 160' by performing a deposition process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). For example, the coating device 340 may be a sputtering device, but is not limited thereto.

[0064] The shielding material layer 160' may be a thin film formed on the surface of each of the unit packages 100U, the release layer 210, and the adhesive layer 220. The thickness of the shielding material layer 160' may be about 5 μm or less, but is not limited thereto. The shielding material layer 160' may include a conductive material for electromagnetic interference (EMI) shielding, such as iron (Fe), nickel (Ni), gold (Au), silver (Ag), copper (Cu), and alloys thereof. The shielding material layer 160' may include at least one conductive film. For example, the shielding material layer 160' may be a three-layer film in which a stainless steel (SUS) film, a copper (Cu) film, and a stainless steel (SUS) film are sequentially stacked.

[0065] Figure 8 To illustrate the Figure 1 FIG. 1 is a cross-sectional view of operations S107 and S108.

[0066] Reference Figure 1 and 8 , the unit package 100U on which the electromagnetic wave shielding layer 160 is formed (i.e., through the shielding material layer 160') can be separated from the release layer 210. The pickup device 330 can pick up the unit package 100U on which the shielding material layer 160' is formed. Since the release layer 210 has a relatively weak adhesive force compared to the adhesive layer 220, the unit package 100U can be separated from the release layer 210 by the pickup device 330, and the shielding material layer 160' can be cut to form the electromagnetic wave shielding layer 160 covering the unit package 100U. In this way, according to the method S100 of manufacturing a semiconductor package of one or more embodiments, the unit package 100U can be separated without the need for an additional process to remove the adhesive force between the release layer 210 and the connecting bump 150. That is, the unit package 100U can be separated while the release layer 210 and the adhesive layer 220 remain adhered to the base film 310.

[0067] According to one or more embodiments, an operation of removing the residue of the release layer 210 on the unit package 100U may be further performed. The residue of the release layer 210 may be removed by a wet etching process using an etchant. For example, the etchant may be sprayed toward the lower surface of the unit package 100U and / or the connection bump 150 using a nozzle 350. The etchant may include fluorine ions (F - ), hydroxide ions (OH - ) and hydrogen ions (H + ). For example, the etchant may remove the residue of the release layer 210 by a reaction of the following chemical formula (4). The following chemical formula (4) represents a decomposition reaction of a silicon-based compound by an etchant including tetra-n-butylammonium fluoride (TBMF).

[0068] [Chemical Formula 4]

[0069]

[0070] Figure 9A and 9B is a cross-sectional view of a semiconductor package according to one or more embodiments. Figure 9A and 9B Shown separately by Figure 1 A semiconductor package formed by a manufacturing method.

[0071] Reference Figure 9A The semiconductor package 100A according to one or more embodiments may include a package substrate 110 , a plurality of semiconductor chips 120 , a molding layer 130 , connection bumps 150 , and an electromagnetic wave shielding layer 160 .

[0072] The package substrate 110 may be a semiconductor package substrate, including a PCB, a ceramic substrate, a glass substrate, or a substrate with wiring. For example, the package substrate 110 may be a double-sided PCB or a multi-layer PCB. The package substrate 110 may include an insulating layer 111, an interconnection pattern 112, and interconnection vias 113.

[0073] The insulating layer 111 may include, for example, a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), a prepreg including an inorganic filler and / or glass fiber (glass cloth or glass fabric), ABF, FR-4, etc. The insulating layer 111 may include a plurality of insulating layers stacked in a vertical direction. For example, the insulating layer 111 may include a core layer and a build-up layer stacked on the upper surface and / or lower surface of the core layer. Depending on the process, the boundaries between the plurality of insulating layers may be unclear. According to one or more embodiments, the insulating layer 111 may include a photosensitive resin, such as a photoimageable dielectric (PID).

[0074] The interconnection patterns 112 may form electrical connection paths within the insulating layer 111. The interconnection patterns 112 may include, for example, at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), or an alloy comprising two or more of these metals. Each of the interconnection patterns 112 may be formed from, for example, electrolytically deposited (ED) copper foil, rolled annealed (RA) copper foil, ultra-thin copper foil, sputtered copper, a copper alloy, or the like. The interconnection patterns 112 may include multiple pattern layers spaced apart from each other in the vertical direction. The multiple pattern layers may extend horizontally on each vertical level. The interconnection patterns 112 may include fewer or more pattern layers than shown in the figure. The interconnection patterns 112 may include lower connection terminals 110P1 and upper connection terminals 110P2. The lower connection terminal 110P1 may be a pad portion of the lowermost interconnection pattern 112 , and the upper connection terminal 110P2 may be a pad portion of the uppermost interconnection pattern 112 .

[0075] The interconnection vias 113 may electrically connect the interconnection patterns 112 within the insulating layer 111. The interconnection vias 113 may include, for example, at least one of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C), or an alloy including two or more of these metals. The interconnection vias 113 may include a conductive material that completely fills a via hole that penetrates at least a portion of the insulating layer 111, or include a conductive material that is conformally formed along the wall of the via hole. According to one or more embodiments, at least some of the interconnection vias 113 may be formed such that the conductive material is applied along the wall of the via hole, and the inner space of the via hole surrounded by the conductive material is filled with an insulating material.

[0076] The package substrate 110 may further include a protective layer 114. The protective layer 114 may be formed on the upper and / or lower surface of the insulating layer 111. For example, the protective layer 114 may include a lower protective layer 114a and an upper protective layer 114b. The lower protective layer 114a may include an opening that exposes at least a portion of the lower connection terminal 110P1. The upper protective layer 114b may include an opening that exposes at least a portion of the upper connection terminal 110P2. The protective layer 114 may be formed using, for example, solder resist.

[0077] A plurality of semiconductor chips 120 may be mounted on the package substrate 110. The plurality of semiconductor chips 120 may be electrically connected to the package substrate 110 using a wire bonding method. The plurality of semiconductor chips 120 may be attached to the package substrate 110 and other vertically adjacent semiconductor chips 120 using an adhesive film 121. The adhesive film 121 may include an inorganic adhesive or a polymer adhesive. The polymer adhesive may include, for example, a thermosetting polymer, a thermoplastic polymer, or a hybrid resin (hybrid resin) that is a mixture of the thermosetting polymer and the thermoplastic polymer. The connection pads 120P of the plurality of semiconductor chips 120 may be electrically connected to the upper connection terminals 110P2 via bonding wires 122. The plurality of semiconductor chips 120 may be bare semiconductor chips without separate bumps or interconnect layers, but are not limited thereto, and the plurality of semiconductor chips 120 may be packaged semiconductor chips. The plurality of semiconductor chips 120 may include a semiconductor wafer and an integrated circuit (IC) formed on the semiconductor wafer, wherein the semiconductor wafer includes semiconductor elements (elementary substances) such as silicon and germanium or semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The plurality of semiconductor chips 120 may include semiconductor chips 120-1 and 120-2 of different types. For example, the plurality of semiconductor chips 120 may include a plurality of first semiconductor chips 120-1 and at least one second semiconductor chip 120-2. According to one or more embodiments, at least some of the plurality of semiconductor chips 120 may be mounted using a flip-chip method.

[0078] The plurality of first semiconductor chips 120-1 may be memory semiconductor chips. The plurality of first semiconductor chips 120-1 may include non-volatile memory devices such as flash memory, PRAM, MRAM, ferroelectric random access memory (FeRAM) and RRAM, as well as volatile memory devices such as DRAM and SRAM. The flash memory may be, for example, V-NAND flash memory. The plurality of first semiconductor chips 120-1 may be shifted in at least one direction so that the connection pads 120P are each exposed upward, but the stacking form of the plurality of first semiconductor chips 120-1 is not limited to that shown in the figure. The plurality of first semiconductor chips 120-1 may be electrically connected to each other via bonding wires 122.

[0079] At least one second semiconductor chip 120-2 may be a control semiconductor chip. At least one second semiconductor chip 120-2 may include various active and / or passive devices, such as field effect transistors (FETs) (including planar FETs and FinFETs), logic devices such as AND, OR, and NOT, system large-scale integration (LSI) circuits, complementary metal oxide semiconductor (CMOS) image sensors (CIS), and micro-electromechanical systems (MEMS).

[0080] At least one second semiconductor chip 120-2 may control access to data stored in the plurality of first semiconductor chips 120-1. The at least one second semiconductor chip 120-2 may control write / read operations of the plurality of first semiconductor chips 120-1 according to a control command from an external host. The at least one second semiconductor chip 120-2 may perform wear leveling, garbage collection, bad block management, and error correction code (ECC). The at least one second semiconductor chip 120-2 may be spaced apart from the plurality of first semiconductor chips 120-1, but embodiments are not limited thereto.

[0081] The mold layer 130 may seal the plurality of semiconductor chips 120 on the package substrate 100. The mold layer 130 may cover each of the plurality of first semiconductor chips 120-1 and the at least one second semiconductor chip 120-2. The mold layer 130 may include, for example, EMC.

[0082] The connection bumps 150 may be arranged on the lower surface of the package substrate 110. The semiconductor package 100A may be electrically connected to an external device, such as a module substrate or a main board, through the connection bumps 150. The connection bumps 150 may include, for example, tin (Sn) or an alloy including tin (Sn) (e.g., Sn-Ag-Cu, Sn-Ag, etc.). The connection bumps 150 may have the same material as described above. Figure 2 In the method of manufacturing a semiconductor package according to one or more embodiments, the electromagnetic wave shielding layer 160 may be formed without limitation depending on the size of the connection bump 150 .

[0083] The electromagnetic wave shielding layer 160 may cover the package substrate 110 and the mold layer 130. The electromagnetic wave shielding layer 160 may be formed using a conformal shielding method. For example, the electromagnetic wave shielding layer 160 may extend along the side surface of the package substrate 100 and the side surface and upper surface of the mold layer 130 to have a substantially constant thickness. According to one or more embodiments, the electromagnetic wave shielding layer 160 may be connected to the ground pattern in the interconnection pattern 112. The electromagnetic wave shielding layer 160 may be formed by, for example, a PVD method. According to one or more embodiments, the electromagnetic wave shielding layer 160 may be formed by a spraying (spraying) method. The electromagnetic wave shielding layer 160 may include a metal material, such as copper (Cu) or stainless steel, but is not limited thereto.

[0084] Reference Figure 9B The semiconductor package 100B of one or more embodiments may include a package substrate 110, at least one semiconductor chip 120, a molding layer 130, connection bumps 150, and an electromagnetic wave shielding layer 160. The semiconductor package 100B may include Figure 9A, except that at least one semiconductor chip 120 is mounted in a flip-chip manner. Therefore, corresponding components are denoted by the same or similar reference numerals, and redundant descriptions may be omitted below.

[0085] At least one semiconductor chip 120 may be arranged such that the active surface having connection pads 120P arranged thereon faces the package substrate 110. The at least one semiconductor chip 120 may be a bare semiconductor chip without separate bumps or interconnect layers, but is not limited thereto, and the at least one semiconductor chip 120 may be a packaged semiconductor chip. The at least one semiconductor chip 120 may be electrically connected to the upper connection terminals 110P2 via conductive bumps 128. The conductive bumps 128 may include pillar portions 124 and solder portions 126. The pillar portions 124 may include copper (Cu) or a copper (Cu) alloy, and the solder portions 126 may include a low-melting-point metal, such as tin (Sn) or an alloy including tin (Sn) (Sn-Ag-Cu). According to one or more embodiments, the conductive bumps 128 may include only the pillar portions 124 or only the solder portions 126. The at least one semiconductor chip 120 may be a logic chip, including a CPU, GPU, FPGA, AP, digital signal processor, cryptographic processor, microprocessor, microcontroller, analog-to-digital converter, ASIC, etc. According to one or more embodiments, the at least one semiconductor chip 120 may further include a memory chip including volatile memories such as DRAM and SRAM, and nonvolatile memories such as PRAM, MRAM, RRAM, and flash memory.

[0086] According to one or more embodiments, a method of manufacturing a semiconductor package having improved reliability may be provided by introducing a release layer filling spaces between connection bumps.

[0087] The embodiments provided in the above description are each not exclusive of association with one or more features of additional examples or additional embodiments that are also provided herein or not provided herein but are consistent with the present disclosure.

[0088] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: preparing a molded structure having connection bumps provided thereon; forming a release layer at least partially filling a space between the connection bumps, wherein the release layer comprises a silicon (Si)-based polymer; forming an adhesive layer covering the release layer and the connection bumps; separating a unit package having the release layer and the adhesive layer formed thereon by cutting the molded structure, the release layer, and the adhesive layer; attaching the unit package to a base film through the adhesive layer, wherein the adhesive layer faces the base film; forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion of the adhesive layer; separating the unit package covered with the shielding material layer from the release layer; as well as A residue of the release layer on the unit package is removed using an etchant including at least one of fluorine ions, hydroxide ions, and hydrogen ions. 2 . The method of claim 1 , wherein the unit package is separated from the release layer while the release layer and the adhesive layer remain adhered to the base film. 3 . The method of claim 1 , wherein the release layer comprises polydimethylsiloxane (PDMS) or a cross-linked silicone polymer.

4. The method of claim 3, wherein the release layer comprises polydimethylsiloxane (PDMS); and The method further includes performing surface treatment on the molded structure and the connection bump before forming the release layer. 5 . The method according to claim 4 , wherein the surface treatment layer between the release layer and the mold structure and between the release layer and the connection bump comprises hexamethyldisilazane (HMDS). The method according to claim 1 , wherein the release layer is formed by a spin coating process. 7 . The method according to claim 1 , wherein the release layer includes a first portion at least partially filling a space between adjacent connection bumps and a second portion extending along a surface of at least a portion of each of the connection bumps. 8 . The method according to claim 7 , wherein a first thickness of the first portion of the release layer is at least half of a height of the connecting bump. 9 . The method of claim 8 , wherein the connection bumps have a height ranging from about 180 μm to about 350 μm.

10. The method of claim 1, wherein the adhesive layer comprises a thermosetting polymer or a photocurable polymer. The method of claim 10 , wherein the adhesive layer comprises a silicone polymer or a silicone acryl polymer.

12. The method of claim 1, wherein the etchant comprises tetra-n-butylammonium fluoride (TBMF).

13. The method of claim 1, wherein the molded structure comprises: base slats; providing a semiconductor chip on a first surface of the substrate strip; and a mold layer that seals the semiconductor chip, and The connecting bumps are provided on the second surface of the substrate strip.

14. The method according to claim 1, wherein each of the unit packages comprises: a package substrate separated from the substrate strip; semiconductor chips; and sealing the semiconductor chip and providing a molding layer on the upper surface of the package substrate, and The connection bumps are provided on the lower surface of the package substrate.

15. A method for manufacturing a semiconductor package, the method comprising: preparing a molded structure having connection bumps provided thereon; forming a release layer that at least partially fills the spaces between the connection bumps; forming an adhesive layer covering the release layer and the connection bumps; separating a unit package having the release layer and the adhesive layer formed thereon by cutting the molded structure, the release layer, and the adhesive layer; attaching the unit package to a base film; forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion of the adhesive layer; as well as separating the unit package covered with the shielding material layer from the release layer, wherein the release layer includes a first portion that at least partially fills a space between adjacent connection bumps and a second portion that at least partially covers a surface of each of the connection bumps; and The first portion of the release layer has a first thickness that is different from the second portion of the release layer.

16. The method of claim 15, wherein the connecting bumps each include an upper region at least partially covered by the first portion of the release layer and a lower region at least partially covered by the second portion of the release layer, wherein the height of the upper region is equal to or greater than the height of the lower region, and The third thickness of the adhesive layer is greater than a height of the lower region of the connecting bump. 17 . The method of claim 15 , wherein the second portion of the release layer conformally extends along at least a portion of the surface of each of the connecting bumps.

18. A method for manufacturing a semiconductor package, the method comprising: preparing a molded structure having connection bumps provided thereon; forming a release layer that at least partially fills the spaces between the connection bumps; forming an adhesive layer covering the release layer and the connection bumps; separating a unit package having the release layer and the adhesive layer formed thereon by cutting the molded structure, the release layer, and the adhesive layer; attaching the unit package to a base film; forming a shielding material layer covering at least a portion of each of the unit packages, at least a portion of the release layer, and at least a portion of the adhesive layer; as well as separating the unit package covered with the shielding material layer from the release layer, The release layer comprises polydimethylsiloxane (PDMS) or a cross-linked silicone polymer.

19. The method of claim 18, wherein the adhesive layer comprises a silicone acryl polymer.

20. The method of claim 18, wherein the base film comprises polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN).

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