Test layout and detection method for shared contact hole detection
By designing a test layout for shared contact hole detection for PMOS and NMOS areas, using channel resistance measurement methods, the problem of unable to effectively detect shared contact holes in the prior art is solved, and fast and efficient detection is achieved, and detection efficiency and yield are improved.
Patent Information
- Application Number
- CN202510499200.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2025-08-08
AI Technical Summary
The existing detection methods cannot effectively detect the process quality of the shared contact hole, especially the shared contact holes that are incomplete contact but are in a high resistance state, resulting in electron beam scanning passing but yield loss.
A test layout is designed, including first and second test layouts for shared contact hole detection in PMOS and NMOS regions, the process quality of the shared contact hole is judged by measuring channel resistance, the active region and the gate pattern are connected by using the first and second pad patterns, and the current measurement is performed in combination with the metal layer pattern.
It realizes fast and effective shared contact hole detection, saves area, and can quickly judge the process quality of shared contact holes in acceptable wafer tests, improving detection efficiency and yield.
Smart Images
Figure CN120453264A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a test layout and a detection method for shared contact hole detection, which is applicable to all processes that require detection of shared contact holes of N / PMOS. Background Art
[0002] With the continuous development of integrated circuits, transistor size is constantly shrinking, and process development is becoming increasingly difficult. The function of contact holes (CT) is to connect the three electrodes (source, drain, and gate) of the transistor, and then realize the device functions through the metal layer.
[0003] Conventional contact holes are typically square in top view and columnar in shape. However, some processes utilize rectangular CTs to simultaneously connect the metal gate and source / drain regions. These are called shared CTs. While shared CTs facilitate the connection between the gate and source / drain regions, they present additional challenges in terms of process window. Because shared CTs differ from conventional contact holes in morphology and the film composition they contact, they can fail to connect to the metal gate or source / drain regions during etching, even though conventional contact holes normally connect to them.
[0004] Currently, the only way to determine whether the shared contact hole process is healthy is through electron beam scanning. However, in actual cases, if the shared contact hole is not completely disconnected from the contact area and is in a high-resistance state that seems to be connected but not connected, the electron beam cannot ensure that this situation will be regarded as a process failure. As a result, the electron beam scan passes but the yield is greatly lost. Summary of the Invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide a test layout and detection method for shared contact hole detection, so as to solve the problem that the existing detection method cannot effectively detect the process quality of shared contact holes.
[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a test layout for shared contact hole detection, including: a first test layout for shared contact hole detection in a PMOS region, a second test layout for shared contact hole detection in an NMOS region, and a first pad pattern and a second pad pattern for measuring the channel resistance in the first test layout and the second test layout, and a third pad pattern for controlling the gate pattern in the first test layout and the second test layout to be turned on or off, wherein the first test layout and the second test layout both include a first active area pattern, a second active area pattern, a shared contact hole pattern, and a gate pattern. The first active area pattern is chain-shaped and consists of two rows of active area patterns arranged alternately, each row of active area patterns consists of a plurality of active area patterns arranged at intervals, the second active area pattern consists of one active area pattern, the first test layout and the second test layout are connected in parallel, the parallel node of the first active area pattern in the first test layout and the second test layout is connected to the first pad pattern via the metal layer pattern, the parallel node of the second active area pattern in the first test layout and the second test layout is connected to the second pad pattern via the metal layer pattern, and the third pad pattern is connected to the gate pattern in the first test layout and the second test layout via the metal layer pattern.
[0007] Preferably, in the first active area pattern, the number of active area patterns in each row is the same, and the number of active area patterns in each row is N, where N≧3.
[0008] Preferably, the length of the second active area pattern is equal to the sum of N times the length of each active area pattern in the first active area pattern and (N-1) times the spacing between active area patterns in the same row.
[0009] Preferably, in the first active area pattern, each active area pattern has the same characteristic size, the spacing between active area patterns in the same row is the same, and the vertical spacing between active area patterns in adjacent rows is the same.
[0010] Preferably, in the first active area pattern, each active area pattern is spanned by three gate patterns arranged at equal intervals.
[0011] Preferably, in the first active area pattern, except for the active area patterns located at the leftmost and rightmost ends of the first active area pattern, the gate patterns spanning the left and right ends of the remaining active area patterns are shared by the staggered adjacent active area patterns and do not span the second active area pattern, and the gate pattern spanning the center position of the remaining active area patterns spans the second active area pattern and the center position of the interval between adjacent active area patterns in adjacent rows of the first active area pattern.
[0012] Preferably, in the first active area pattern, the other two gate patterns that span the leftmost active area pattern and are not shared by other active area patterns do not span the second active area pattern, and the other two gate patterns that span the rightmost active area pattern and are not shared by other active area patterns span the second active area pattern.
[0013] Preferably, the gate pattern crossing the second active area pattern also includes a gate pattern that is evenly spaced on both sides of the central gate pattern and does not cross the first active area pattern. The projection of the contact hole pattern shared between adjacent active area patterns in the same row in the first active area pattern is within the projection of the active area pattern in the first active area pattern or within the projection of the second active area pattern.
[0014] Preferably, a projection of the shared contact hole pattern is within a projection of the active area pattern in the first active area pattern or within a projection of the second active area pattern.
[0015] Preferably, the shared contact hole patterns projected within the projection of the active area pattern in the first active area pattern are arranged in two rows, the number of shared contact hole patterns in each row is the same, one end of each shared contact hole pattern is located within the projection of the gate pattern spanning both ends of the active area pattern, and the other end is located within the projection of the active area pattern between the two gate patterns respectively spanning the end and central positions of the active area pattern.
[0016] Preferably, the shared contact hole patterns projected within the projection of the second active area pattern are arranged into two rows, the number of shared contact hole patterns in each row is the same, one end of each shared contact hole pattern is located within the projection of the gate pattern, and the other end is located within the projection of the second active area pattern between two adjacent gate patterns, and the length extension directions of the shared contact hole patterns located at both ends are the same, and in the shared contact hole pattern located in the middle part, the length extension direction of the shared contact hole pattern adjacent to the shared contact hole pattern located at both ends is the same as the length extension direction of the shared contact hole pattern located at both ends in the first row, and is opposite to the length extension direction of the shared contact hole pattern located at both ends in the second row, the length extension directions of adjacent shared contact hole patterns located in the same row are opposite, and the length extension directions of adjacent shared contact hole patterns with one end located within the projection of the same gate pattern are opposite.
[0017] The present application also provides a detection method for shared contact hole detection, comprising:
[0018] Step 1: preparing a test circuit according to the above test layout, wherein the test circuit includes a first test circuit for detecting shared contact holes in the PMOS area and a second test circuit for detecting shared contact holes in the NMOS area;
[0019] Step 2: Apply a negative voltage to the third pad in the test circuit to turn on the gate in the first test circuit, measure the current between the first pad and the second pad in the test circuit, obtain the channel resistance of the PMOS region, and judge the process quality of the shared contact hole in the PMOS region based on the channel resistance;
[0020] Step three, apply a positive voltage to the third pad in the test circuit to turn on the gate in the second test circuit, measure the current between the first pad and the second pad in the test circuit, obtain the channel resistance of the NMOS region, and judge the process quality of the shared contact hole in the NMOS region based on the channel resistance.
[0021] As described above, the test layout and detection method for shared contact hole detection provided by the present application have the following beneficial effects: the shared contact holes in the N / PMOS area can be tested quickly, efficiently and in an area-saving manner. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0023] Figure 1 A schematic diagram showing a test layout for shared contact hole detection provided by an embodiment of the present application is shown. DETAILED DESCRIPTION
[0024] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0025] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or location relationships, are used solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0029] See also Figure 1 , which shows a schematic diagram of a test layout for shared contact hole detection provided by an embodiment of the present application.
[0030] like Figure 1As shown, the test layout for shared contact hole detection includes a first test layout, a second test layout, a first pad pattern (PAD1) 111 and a second pad pattern (PAD2) 112 for measuring the channel resistance in the first test layout and the second test layout, and a third pad pattern (PAD3) 113 for controlling the gate pattern 103 in the first test layout and the second test layout to be turned on or off. The first test layout (the area marked by the dotted box in the figure) is used for detecting shared contact holes in the PMOS area, and the second test layout is used for detecting shared contact holes in the NMOS area. The first test layout and the second test layout both include a first active area pattern, a second active area pattern 102, a shared contact hole pattern 105 and a gate pattern 103. The gate pattern 103, the first active area pattern is chain-shaped, consisting of two rows of active area patterns arranged alternately, each row of active area patterns consisting of a plurality of active area patterns 101 arranged at intervals, the second active area pattern 102 consisting of one active area pattern, the first test layout and the second test layout are connected in parallel, the parallel node of the first active area pattern in the first test layout and the second test layout is connected to the first pad pattern 111 via the metal layer pattern 106, the parallel node of the second active area pattern 102 in the first test layout and the second test layout is connected to the second pad pattern 112 via the metal layer pattern 106, and the third pad pattern 113 is connected to the gate pattern 103 in the first test layout and the second test layout via the metal layer pattern 106.
[0031] As an example, in the first active area pattern, the number of active area patterns in each row is the same, the feature size of each active area pattern 101 is the same, the spacing between active area patterns 101 in the same row is the same, and the vertical spacing between active area patterns 101 in adjacent rows is the same.
[0032] As an example, the number of active area patterns 101 in each row of the first active area pattern is N (N≧3), and the length of the second active area pattern 102 is equal to the sum of N times the length of each active area pattern 101 in the first active area pattern and (N-1) times the spacing between active area patterns 101 in the same row.
[0033] The two ends of the second active area pattern 102 are aligned with the two distal ends of one row of active area patterns in the first active area pattern. As an example, another row of active area patterns in the first active area pattern is located between the row of active area patterns aligned with the two ends of the second active area pattern 102 and the second active area pattern 102.
[0034] In the first active area pattern, each active area pattern 101 is spanned by three gate patterns 103 arranged at equal intervals (ie, the length direction of the gate pattern 103 is perpendicular to the length direction of the active area pattern 101 ).
[0035] Except for the active area patterns 101 located at the leftmost and rightmost ends of the first active area pattern, among the gate patterns 103 spanning the remaining active area patterns 101, the gate patterns 103 spanning the left and right ends of the active area pattern 101 are shared by the staggered adjacent active area patterns 101 and do not span the second active area pattern 102; the gate pattern 103 spanning the center of the active area pattern 101 spans the second active area pattern 102 and the center position of the interval between adjacent active area patterns 101 in adjacent rows of the first active area pattern; the other two gate patterns 103 spanning the leftmost active area pattern 101 that are not shared by the other active area patterns 101 do not span the second active area pattern 102; and the other two gate patterns 103 spanning the rightmost active area pattern 101 that are not shared by the other active area patterns 101 span the second active area pattern 102.
[0036] The gate pattern 103 spanning the second active area pattern 102 also includes gate patterns 103 arranged at equal intervals on both sides of the gate pattern 103 spanning the central position between adjacent active area patterns 101 in the same row in the first active area pattern (and spanning the central position of another row of active area patterns 101 in the first active area pattern). The gate pattern 103 does not span the first active area pattern.
[0037] The gate patterns 103 crossing the second active area patterns 102 in the first test layout are all shared by the second active area patterns 102 in the second test layout.
[0038] The first pad pattern 111 is connected to the gate pattern 103 that spans the left end of the leftmost active area pattern 101 in the first active area pattern in the first test layout through the metal layer pattern 106. The gate pattern 103 is not shared by other active area patterns 101 in the first active area pattern and spans the left end of the leftmost active area pattern 101 in the first active area pattern in the second test layout.
[0039] The second pad pattern 112 is connected to the gate pattern 103 across the leftmost end of the second active area pattern 102 via the metal layer pattern 106 . The projection of the metal layer pattern 106 does not overlap with the projection of the second active area pattern 102 and the projection of the metal layer pattern 106 connected to the third pad pattern 113 .
[0040] The third pad pattern 113 is connected to the gate pattern 103 across the center of the active area pattern 101 in the first active area pattern via the metal layer pattern 106 . The projection of the metal layer pattern 106 is located between the projection of the first test pattern and the projection of the second test pattern.
[0041] The metal layer pattern 106 is connected to the gate pattern 103 via the contact hole pattern 107 .
[0042] A projection of the shared contact hole pattern 105 is within a projection of the active area pattern 101 or a projection of the second active area pattern 102 among the first active area patterns.
[0043] The shared contact hole patterns 105 projected within the projection of the active area pattern 101 in the first active area pattern are arranged in two rows, and the number of shared contact hole patterns 105 in each row is the same. One end of each shared contact hole pattern 105 is located within the projection of the gate pattern 103 spanning across both ends of the active area pattern 101, and the other end is located within the projection of the active area pattern 101 between the two gate patterns 103 spanning the end and the center of the active area pattern 101.
[0044] The shared contact hole patterns 105 projected within the projection of the second active area pattern 102 are arranged into two rows, and the number of shared contact hole patterns 105 in each row is the same. One end of each shared contact hole pattern 105 is located within the projection of the gate pattern 103, and the other end is located within the projection of the second active area pattern 102 between two adjacent gate patterns 103, and the length extension directions of the shared contact hole patterns 105 located at both ends are the same. Among the shared contact hole patterns 105 located in the middle part, the length extension direction of the shared contact hole patterns 105 adjacent to the shared contact hole patterns 105 located at both ends is the same as the length extension direction of the shared contact hole patterns 105 located at both ends in the first row, and is opposite to the length extension direction of the shared contact hole patterns 105 located at both ends in the second row. The length extension directions of adjacent shared contact hole patterns 105 in the same row are opposite, and the length extension directions of adjacent shared contact hole patterns 105 with one end located within the projection of the same gate pattern 103 are opposite.
[0045] Another embodiment of the present application further provides a detection method for shared contact hole detection, comprising:
[0046] Step 1: preparing a test circuit according to the test layout for shared contact hole detection, the test circuit including a first test circuit for shared contact hole detection in a PMOS region and a second test circuit for shared contact hole detection in an NMOS region;
[0047] Step 2: Apply a negative voltage to the third pad in the test circuit to turn on the gate in the first test circuit, measure the current between the first pad and the second pad in the test circuit, obtain the channel resistance of the PMOS region, and judge the process quality of the shared contact hole in the PMOS region based on the channel resistance;
[0048] Step three, apply a positive voltage to the third pad in the test circuit to turn on the gate in the second test circuit, measure the current between the first pad and the second pad in the test circuit, obtain the channel resistance of the NMOS region, and judge the process quality of the shared contact hole in the NMOS region based on the channel resistance.
[0049] As an example, the order of implementing steps 2 and 3 can be swapped. As long as any shared contact hole in the test circuit has an incomplete contact problem (usually there is an abnormality in the contact surface between the shared contact hole and the active area, such as incomplete contact), the channel resistance will be too large.
[0050] This test circuit allows for rapid testing of shared contact holes in N / PMOS regions, efficiently and efficiently saving area. Implementing this test during wafer acceptance testing (WAT) allows for testing of the entire or half-area of the test layout, enabling rapid assessment of the process quality of the shared contact holes. Therefore, this application effectively overcomes the shortcomings of the prior art and possesses high industrial value.
[0051] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present application. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0052] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this application.
Claims
1. A test layout for shared contact hole detection, characterized in that: The test layout includes: a first test layout for shared contact hole detection in the PMOS area, a second test layout for shared contact hole detection in the NMOS area, a first pad pattern and a second pad pattern for measuring the channel resistance in the first test layout and the second test layout, and a third pad pattern for controlling the gate pattern in the first test layout and the second test layout to be turned on or off, wherein the first test layout and the second test layout both include a first active area pattern, a second active area pattern, a shared contact hole pattern and a gate pattern, and the first active area pattern is in a chain shape and is arranged in a staggered manner. The present invention is composed of two rows of active area patterns, each row of active area patterns is composed of a plurality of active area patterns arranged at intervals, the second active area pattern is composed of one active area pattern, the first test layout and the second test layout are connected in parallel, the parallel nodes of the first active area patterns in the first test layout and the second test layout are connected to the first pad pattern via a metal layer pattern, the parallel nodes of the second active area patterns in the first test layout and the second test layout are connected to the second pad pattern via a metal layer pattern, and the third pad pattern is connected to the gate patterns in the first test layout and the second test layout via a metal layer pattern.
2. The method according to claim 1, characterized in that In the first active area pattern, the number of active area patterns in each row is the same, and the number of active area patterns in each row is N, where N≧3.
3. The method according to claim 2, characterized in that The length of the second active area pattern is equal to the sum of N times the length of each active area pattern in the first active area pattern and (N-1) times the spacing between active area patterns in the same row.
4. The method according to claim 1, wherein In the first active area patterns, each active area pattern has the same characteristic size, the spacing between active area patterns in the same row is the same, and the vertical spacing between active area patterns in adjacent rows is the same.
5. The method according to claim 1, wherein In the first active area patterns, each active area pattern is spanned by three gate patterns arranged at equal intervals.
6. The method according to claim 1, characterized in that In the first active area pattern, except for the active area patterns located at the leftmost and rightmost ends of the first active area pattern, the gate patterns spanning the left and right ends of the remaining active area patterns are shared by the staggered adjacent active area patterns and do not span the second active area pattern. The gate pattern spanning the center position of the remaining active area patterns spans the second active area pattern and the center position of the interval between adjacent active area patterns in adjacent rows of the first active area pattern.
7. The method according to claim 5, characterized in that In the first active area pattern, the other two gate patterns that cross the leftmost active area pattern and are not shared by other active area patterns do not cross the second active area pattern, and the other two gate patterns that cross the rightmost active area pattern and are not shared by other active area patterns cross the second active area pattern.
8. The method according to claim 1, characterized in that The gate patterns crossing the second active area pattern further include gate patterns arranged at equal intervals on both sides of the gate pattern crossing the center position between adjacent active area patterns in the same row in the first active area pattern and not crossing the first active area pattern.
9. The method according to claim 1, characterized in that A projection of the shared contact hole pattern is within a projection of an active area pattern in the first active area pattern or within a projection of the second active area pattern.
10. The method according to claim 9, characterized in that The shared contact hole patterns projected within the projection of the active area pattern in the first active area pattern are arranged in two rows, the number of shared contact hole patterns in each row is the same, one end of each shared contact hole pattern is located within the projection of the gate pattern spanning both ends of the active area pattern, and the other end is located within the projection of the active area pattern between two gate patterns respectively spanning the end and central positions of the active area pattern.
11. The method according to claim 9, characterized in that The shared contact hole patterns projected within the projection of the second active area pattern are arranged into two rows, and the number of shared contact hole patterns in each row is the same. One end of each shared contact hole pattern is located within the projection of the gate pattern, and the other end is located within the projection of the second active area pattern between two adjacent gate patterns. The length extension directions of the shared contact hole patterns located at both ends are the same. Among the shared contact hole patterns located in the middle part, the length extension direction of the shared contact hole patterns adjacent to the shared contact hole patterns located at both ends is the same as the length extension direction of the shared contact hole patterns located at both ends in the first row, and is opposite to the length extension direction of the shared contact hole patterns located at both ends in the second row. The length extension directions of adjacent shared contact hole patterns in the same row are opposite, and the length extension directions of adjacent shared contact hole patterns with one end located within the projection of the same gate pattern are opposite.
12. A detection method for shared contact hole detection, characterized in that: The method comprises: Step 1: preparing a test circuit according to the test layout of any one of claims 1 to 11, wherein the test circuit includes a first test circuit for detecting shared contact holes in a PMOS area and a second test circuit for detecting shared contact holes in an NMOS area; Step 2: applying a negative voltage to the third pad in the test circuit to turn on the gate in the first test circuit, measuring the current between the first pad and the second pad in the test circuit to obtain the channel resistance of the PMOS region, and judging the process quality of the shared contact hole in the PMOS region based on the channel resistance; Step three, apply a positive voltage to the third pad in the test circuit to turn on the gate in the second test circuit, measure the current between the first pad and the second pad in the test circuit, obtain the channel resistance of the NMOS region, and judge the process quality of the shared contact hole in the NMOS region based on the channel resistance.