Interface circuit and network equipment

Abstract

The interface circuit comprises an Ethernet physical layer chip and an RJ45 interface, the interface circuit further comprises a protection circuit, the protection circuit is electrically connected between the Ethernet physical layer chip and the RJ45 interface, the protection circuit comprises a network transformer, the network transformer is electrically connected between the Ethernet physical layer chip and the RJ45 interface, and the network transformer is electrically connected between the Ethernet physical layer chip and the RJ45 interface. The isolation module is used for isolating the Ethernet physical layer chip from the RJ45 interface so as to reduce receiving interference of the Ethernet physical layer chip; the first protection circuit is electrically connected to the primary side of the network transformer and is used for releasing electromagnetic interference current; the second protection circuit is electrically connected to the primary side of the network transformer and is used for releasing the electromagnetic interference current; and the third protection circuit is electrically connected between the secondary side of the network transformer and the Ethernet physical layer chip, and is used for clamping the surge voltage at the first preset voltage, so that the anti-electromagnetic interference capability is enhanced, and the stability and reliability of data transmission are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection, in particular to an interface circuit. Background Art

[0002] Existing physical layer network equipment connectors are typically used for gigabit (1000Mbps) connections and can meet basic electromagnetic protection requirements, such as the basic electrostatic protection requirements of the CISPR 35 regulation (8kV for air discharge and 4kV for contact discharge). However, with the development of the network, the demand for network speed is also increasing. The higher the network speed, the higher the requirements for network equipment. Therefore, the requirements for the electromagnetic interference resistance of the high-speed connectors of physical layer network equipment are also higher. When the existing high-speed connectors of physical layer network equipment are used for high speeds of 10Gbps and above, the electromagnetic protection requirements are more stringent, such as the electrostatic protection requirements (NEBS electrostatic interference, 15kV for air discharge and 8kV for contact discharge). However, the existing physical layer network equipment connectors cannot meet the electromagnetic protection requirements for high-speed transmission, resulting in port link disconnection and reducing the stability and reliability of data transmission. Summary of the Invention

[0003] In view of this, it is necessary to provide an interface circuit to enhance the anti-electromagnetic interference capability and ensure the stability and reliability of data transmission.

[0004] One embodiment of the present invention provides an interface circuit, comprising: an Ethernet physical layer chip and an RJ45 interface, the interface circuit also comprising a protection circuit, the protection circuit being electrically connected between the Ethernet physical layer chip and the RJ45 interface, the protection circuit comprising: a network transformer electrically connected between the Ethernet physical layer chip and the RJ45 interface, for isolating the Ethernet physical layer chip from the RJ45 interface to reduce reception interference of the Ethernet physical layer chip; a first protection circuit electrically connected to the primary side of the network transformer, for releasing electromagnetic interference current; a second protection circuit electrically connected to the primary side of the network transformer, for releasing the electromagnetic interference current; and a third protection circuit electrically connected between the secondary side of the network transformer and the Ethernet physical layer chip, for clamping a surge voltage at a first preset voltage.

[0005] Preferably, the network transformer includes four network transformer sub-circuits with identical structures, each network transformer sub-circuit including: a transformer including an input end, an output end, a primary center tap, and a secondary center tap, wherein the input end of the transformer is electrically connected to the RJ45 interface through a first differential pair, and the primary center tap is electrically connected to the first protection circuit and the second protection circuit; a common-mode inductor is arranged on the secondary side of the transformer for suppressing common-mode noise, the output end of the transformer is electrically connected to the common-mode inductor, the common-mode inductor is electrically connected to the Ethernet physical layer chip through a second differential pair, and the secondary center tap is electrically connected to the third protection circuit through the common-mode inductor.

[0006] Preferably, the first protection circuit includes four first protection sub-circuits with the same structure, which are connected one-to-one to the primary center taps of the transformers in the four network transformer sub-circuits; the second protection circuit includes four second protection sub-circuits with the same structure, which are connected one-to-one to the primary center taps of the transformers in the four network transformer sub-circuits.

[0007] Preferably, each first protection subcircuit comprises: a first capacitor, one end of which is electrically connected to the primary center tap of the corresponding transformer; and a first resistor, one end of which is electrically connected to the other end of the first capacitor and the other end of which is grounded.

[0008] Preferably, each second protection subcircuit comprises: a capacitor unit comprising at least one second capacitor, wherein the at least one second capacitor is connected in parallel with each other, one end of the capacitor is electrically connected to the primary center tap of the corresponding transformer, and the other end is grounded.

[0009] Preferably, the electromagnetic interference current is released to the ground through the first capacitor and the first resistor; and the electromagnetic interference current is released to the ground through the second capacitor.

[0010] Preferably, the third protection circuit includes four third protection sub-circuits with identical structures, which are connected to the secondary center taps of the transformers in the four network transformer sub-circuits in a one-to-one correspondence.

[0011] Preferably, each third protection sub-circuit comprises: a transient voltage suppressor diode, a cathode of the transient voltage suppressor diode being electrically connected to the secondary center tap of the corresponding transformer, and an anode of the transient voltage suppressor diode being grounded.

[0012] Preferably, the interface circuit is integrated on a printed circuit board; and an inner layer of the printed circuit board in the layout area of the first protection circuit and the second protection circuit is a hollow layer.

[0013] Compared to existing technologies, the interface circuit provided by the present invention incorporates a first protection circuit and a second protection circuit on the primary side of the network transformer. These circuits simultaneously release electromagnetic interference current from the RJ45 interface, enhancing immunity to electromagnetic interference and ensuring the stability and reliability of data transmission. Furthermore, a third protection circuit is incorporated on the secondary side of the network transformer. When the interface circuit 1 experiences an abnormal overvoltage, the abnormally high voltage is clamped within a safe voltage range, further protecting the Ethernet physical layer chip and improving the performance and stability of network equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of a module of an interface circuit according to an embodiment of the present invention.

[0015] Figure 2 2 is a circuit diagram of an embodiment of an interface circuit of the present invention.

[0016] Description of main component symbols

[0017] 1.1a-Interface circuit

[0018] J1, J1a - RJ45 interface

[0019] 10.10a-Protection circuit

[0020] 101, 101a-Network transformer

[0021] 102, 102a-first protection circuit

[0022] 103, 103a-Second protection circuit

[0023] 104, 104a-third protection circuit

[0024] 1011, 1012, 1013, 1014-Network transformer subcircuit

[0025] T1, T2, T3, T4-transformer

[0026] L1, L2, L3, L4 - common mode inductors

[0027] 1021, 1022, 1023, 1024 - first protection sub-circuit

[0028] C1-first capacitor

[0029] R1 - first resistor

[0030] C2 - second capacitor

[0031] D1 - TVS diode

[0032] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0034] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] See also Figure 1 As shown, Figure 1 FIG. 1 is a block diagram of an embodiment of an interface circuit 1 of the present invention. In this embodiment, the interface circuit 1 can be applied to a network device, such as a switch. Figure 1 As shown, the interface circuit 1 includes an Ethernet physical layer chip PHY, an RJ45 interface J1, and a protection circuit 10. In this embodiment, the protection circuit 10 is electrically connected between the Ethernet physical layer chip PHY and the RJ45 interface J1 to isolate the Ethernet physical layer chip PHY from the RJ45 interface J1, enhance immunity to electromagnetic interference, particularly electrostatic interference, and protect the Ethernet physical layer chip PHY.

[0036] In this embodiment, the protection circuit 10 includes a network transformer 101, a first protection circuit 102, a second protection circuit 103, and a third protection circuit 104. The network transformer 101 is electrically connected between the Ethernet physical layer chip PHY and the RJ45 interface J1, and is used to isolate the Ethernet physical layer chip PHY from the RJ45 interface J1 to reduce reception interference of the Ethernet physical layer chip PHY. The first protection circuit 102 is electrically connected to the primary side of the network transformer 101 and is used to release electromagnetic interference current. The second protection circuit 103 is electrically connected to the primary side of the network transformer 101 and is used to release the electromagnetic interference current. The RJ45 interface J1 is connected to external network devices via a network cable. The nearly 100-meter network cable is equivalent to a very long antenna. External electromagnetic interference (including thousands of volts of lightning interference, thousands of volts of static interference, etc.) can enter the Ethernet physical layer chip PHY through the network cable, which may cause errors in the transmitted data signal. In severe cases, it may even break down the Ethernet physical layer chip PHY, seriously affecting the stability and reliability of data transmission. In this embodiment, the electromagnetic interference current is released simultaneously by the first protection circuit 102 and the second protection circuit 103 , thereby enhancing the anti-electromagnetic interference capability and ensuring the stability and reliability of data transmission.

[0037] The third protection circuit 104 is electrically connected between the secondary side of the network transformer 101 and the Ethernet physical layer chip PHY, and is used to clamp the surge voltage to a first preset voltage. The third protection circuit 104 contains a TVS (Transient Voltage Suppressor) diode. When the interface circuit 1 is operating normally, the TVS diode in the third protection circuit 104 is in the off state (high impedance state), which does not affect the normal operation of the interface circuit 1. When the interface circuit 1 is under abnormal overvoltage and reaches its breakdown voltage, the TVS diode quickly changes from a high impedance state to a low impedance state, providing a low-impedance conduction path for the transient current and clamping the abnormal high voltage to a safe level, thereby protecting the Ethernet physical layer chip PHY. When the abnormal overvoltage disappears, the TVS diode returns to a high impedance state, and the interface circuit 1 operates normally, ensuring the stability of the network equipment.

[0038] See also Figure 2 As shown, Figure 2 FIG. 1 is a circuit diagram of an embodiment of the interface circuit 1a of the present invention. In this embodiment, the interface circuit 1a can be applied to network equipment, such as a switch. Figure 2As shown, the interface circuit 1a includes an Ethernet physical layer chip PHY1, an RJ45 interface J1a, and a protection circuit 10a. In this embodiment, the protection circuit 10a is electrically connected between the Ethernet physical layer chip PHY1 and the RJ45 interface J1a. It is primarily used to isolate the Ethernet physical layer chip PHY1 from the RJ45 interface J1a, enhancing immunity to electromagnetic interference, particularly electrostatic interference, and protecting the Ethernet physical layer chip PHY1. The protection circuit 10a includes a network transformer 101a, a first protection circuit 102a, a second protection circuit 103a, and a third protection circuit 104a. In this embodiment, the operating principles and connection relationships of the Ethernet physical layer chip PHY1, the RJ45 interface J1a, and the protection circuit 10a are similar to those of the above embodiment and will not be further described here.

[0039] In this embodiment, the network transformer 101a includes four network transformer sub-circuits 1011, 1012, 1013, and 1014. These sub-circuits have identical structures. The network transformer sub-circuit 1011 is used as an example for illustration. It includes a transformer T1 and a common-mode inductor L1. Transformer T1 includes an input, an output, a primary center tap, and a secondary center tap. The input of transformer T1 is electrically connected to the RJ45 connector J1a via a first differential pair TRP1+ and TRP1-. The primary center tap is electrically connected to the first protection circuit 102a and the second protection circuit 103a. Common-mode inductor L1 is provided on the secondary side of transformer T1 to suppress common-mode noise. The output end of the transformer T1 is electrically connected to the common mode inductor L1, which is electrically connected to the Ethernet physical layer chip PHY1 through the second differential pair TRD1+ and TRD1-. The secondary center tap is electrically connected to the third protection circuit 104a through the common mode inductor L1.

[0040] In this embodiment, the first protection circuit 102a includes four first protection sub-circuits 1021, 1022, 1023, and 1024. The first protection sub-circuits 1021, 1022, 1023, and 1024 have identical structures. The first protection sub-circuits 1021, 1022, 1023, and 1024 are connected to the primary center taps of transformers T1, T2, T3, and T4 in the network transformer sub-circuits 1011, 1012, 1013, and 1014, respectively. Taking the first protection sub-circuit 1021 as an example, the first protection sub-circuit 1011 includes a first capacitor C1 and a first resistor R1. One end of the first capacitor C1 is electrically connected to the corresponding transformer T1, i.e., the primary center tap of transformer T1, and the other end is electrically connected to one end of the first resistor R1. The other end of the first resistor R1 is grounded.

[0041] The second protection circuit 103a includes four second protection sub-circuits 1031, 1032, 1033, and 1034. The second protection sub-circuits 1031, 1032, 1033, and 1034 have identical structures. Each of the second protection sub-circuits 1031, 1032, 1033, and 1034 is connected to the primary center taps of transformers T1, T2, T3, and T4 in the network transformer sub-circuits 1011, 1012, 1013, and 1014, respectively. Taking the second protection sub-circuit 1031 as an example, the second protection circuit 1031 includes at least one second capacitor C2, which is connected in parallel with each other. As shown in the figure, one second capacitor C2 is used as an example in this embodiment, but the present invention is not limited thereto. One end of the second capacitor C2 is electrically connected to the primary center tap of the corresponding transformer T1, and the other end is grounded.

[0042] In this embodiment, the first protection circuit 102a and the second protection circuit 103a are independent protection circuits. The electromagnetic interference current can be released to the ground through the first capacitor C1 and the first resistor R1, and can also be released to the ground through the second capacitor C2. The electromagnetic interference current is released simultaneously by the first protection circuit 102 and the second protection circuit 103, thereby enhancing the anti-electromagnetic interference capability and ensuring the stability and reliability of data transmission.

[0043] In this embodiment, the third protection circuit 104a includes four third protection sub-circuits 1041, 1042, 1043, and 1044. The third protection sub-circuits 1041, 1042, 1043, and 1044 have identical structures. They are connected to the secondary center taps of transformers T1, T2, T3, and T4, respectively, via common-mode inductors L1, L2, L3, and L4. Taking third protection sub-circuit 1041 as an example, third protection circuit 1041 includes a TVS diode D1, the cathode of which is electrically connected to the secondary center tap of the corresponding transformer.

[0044] In this embodiment, the interface circuit 1 is integrated on a printed circuit board, and the inner layer of the printed circuit board in the layout area of the first protection circuit 102a and the third protection circuit 104a is a middle control layer, that is, the vertical layer area corresponding to the layout area of the first protection circuit 102a and the third protection circuit 104a is hollowed out.

[0045] Compared to existing technologies, the interface circuit provided by the present invention incorporates a first and second protection circuit on the primary side of the network transformer. These circuits simultaneously release electromagnetic interference current from the RJ45 interface, enhancing immunity to electromagnetic interference and ensuring the stability and reliability of data transmission. Furthermore, a third protection circuit is incorporated on the secondary side of the network transformer. When the interface circuit experiences an abnormal overvoltage, the circuit clamps the abnormally high voltage within a safe voltage range, further protecting the Ethernet physical layer chip and improving the performance and stability of network equipment.

[0046] Those skilled in the art should recognize that the above embodiments are merely intended to illustrate the present invention and are not intended to limit the present invention. Any appropriate changes and modifications to the above embodiments fall within the scope of the present invention as long as they are within the spirit of the present invention.

Claims

1. An interface circuit, comprising an Ethernet physical layer chip and an RJ45 interface, characterized in that: The interface circuit further includes a protection circuit, which is electrically connected between the Ethernet physical layer chip and the RJ45 interface, and includes: a network transformer, electrically connected between the Ethernet physical layer chip and the RJ45 interface, for isolating the Ethernet physical layer chip from the RJ45 interface to reduce reception interference of the Ethernet physical layer chip; a first protection circuit, electrically connected to the primary side of the network transformer, for releasing electromagnetic interference current; a second protection circuit, electrically connected to the primary side of the network transformer, for releasing the electromagnetic interference current; A third protection circuit is electrically connected between the secondary side of the network transformer and the Ethernet physical layer chip, and is used for clamping the surge voltage to a first preset voltage.

2. The interface circuit according to claim 1, wherein: The network transformer includes four network transformer sub-circuits with the same structure, each network transformer sub-circuit including: a transformer, comprising an input end, an output end, a primary center tap, and a secondary center tap, wherein the input end of the transformer is electrically connected to the RJ45 interface via a first differential pair, and the primary center tap is electrically connected to the first protection circuit and the second protection circuit; A common-mode inductor is provided on the secondary side of the transformer for suppressing common-mode noise. The output end of the transformer is electrically connected to the common-mode inductor. The common-mode inductor is electrically connected to the Ethernet physical layer chip through a second differential pair. The secondary center tap is electrically connected to the third protection circuit through the common-mode inductor.

3. The interface circuit according to claim 2, wherein: The first protection circuit includes four first protection sub-circuits with the same structure, which are connected to the primary center taps of the transformers in the four network transformer sub-circuits in a one-to-one correspondence; The second protection circuit includes four second protection sub-circuits with the same structure, which are connected to the primary center taps of the transformers in the four network transformer sub-circuits in a one-to-one correspondence.

4. The interface circuit according to claim 3, wherein: Each first protection sub-circuit comprises: a first capacitor having one end electrically connected to the primary center tap of the corresponding transformer; The first resistor has one end electrically connected to the other end of the first capacitor and the other end grounded.

5. The interface circuit according to claim 4, wherein: Each second protection sub-circuit comprises: The capacitor unit includes at least one second capacitor, which is connected in parallel with each other, one end of which is electrically connected to the primary center tap of the corresponding transformer, and the other end of which is grounded.

6. The interface circuit according to claim 5, wherein: The electromagnetic interference current is discharged to the ground through the first capacitor and the first resistor; The electromagnetic interference current is discharged to the ground through the second capacitor.

7. The interface circuit according to claim 2, wherein: The third protection circuit includes four third protection sub-circuits with the same structure, which are connected to the secondary center taps of the transformers in the four network transformer sub-circuits in a one-to-one correspondence.

8. The interface circuit according to claim 7, wherein: Each third protection sub-circuit comprises: A transient voltage suppressor diode (TVS) has a cathode electrically connected to a secondary center tap of a corresponding transformer, and an anode of the TVS is grounded.

9. The interface circuit according to claim 1, wherein: The interface circuit is integrated on a printed circuit board; An inner layer of the printed circuit board in the layout area of the first protection circuit and the second protection circuit is a hollow layer.

10. A network device, characterized in that: The interface circuit comprises the interface circuit according to any one of claims 1 to 9.

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