Frequency-modulated continuous wave modulation source with double-ring architecture

Abstract

The invention provides a frequency-modulated continuous wave modulation source of a double-loop architecture, which comprises a first phase locking module and a second frequency modulation module, and is characterized in that the frequency of an input first reference signal is improved through the first phase locking module to obtain a second reference signal with a preset frequency; an integer frequency division sequence value and a decimal frequency division sequence value are generated by inputting a starting point frequency division ratio signal, an end point frequency division ratio signal, a frequency hopping frequency stepping signal and a frequency hopping time stepping signal of the second frequency modulation module; and adjusting the response time of generating the target frequency division sequence value by the two frequency division sequence values to be consistent in a manner of delaying the integer frequency division sequence value, so as to perform frequency modulation processing on the second reference signal through the target frequency division sequence value to obtain a target frequency signal. According to the invention, the first phase locking module provides the second reference signal of the preset frequency band and delays integer frequency division sequence value processing, so that the linearity of the output frequency-modulated continuous wave is improved from two aspects, the better frequency modulation linearity is realized, and the application range is wider.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication electronic circuits, and in particular to a frequency modulated continuous wave modulation source with a dual-loop architecture. Background Art

[0002] FMCW (Freauency Modulated Continuous Wave) frequency modulated continuous waves are widely used in applications such as automotive radar and industrial ranging. FMCW technology is based on the frequency modulation of continuous wave signals. It transmits electromagnetic waves whose frequency changes linearly with time and receives echo signals reflected by the target test object. The transmitted signal and the echo signal are mixed to generate a difference frequency signal. Its frequency is linearly related to the target distance, and the phase change reflects the target speed. By extracting the frequency and phase information of the difference frequency signal through Fourier transform, the distance, speed, and direction of the target test object can be calculated synchronously to achieve high-precision detection. In related technologies, the FMCW frequency modulated continuous waves currently generated are nonlinear, resulting in nonlinear errors in the frequency modulated continuous waves. The nonlinear errors will cause the frequency of the difference frequency signal to shift, which in turn will cause errors in the calculated distance and other information, ultimately directly affecting performance indicators such as measurement accuracy and resolution.

[0003] Therefore, how to provide a frequency modulated continuous wave modulation source with high linearity is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a technical solution of a frequency modulated continuous wave modulation source with a dual-ring architecture to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.

[0006] According to a first aspect of an embodiment of the present application, a frequency modulated continuous wave modulation source with a dual-ring architecture is provided, comprising:

[0007] a first phase-locking module, receiving a first reference signal, performing frequency multiplication, phase locking, and frequency division processing on the first reference signal to obtain a second reference signal, so as to provide the second reference signal of a preset frequency;

[0008] The second frequency modulation module receives the second reference signal, the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, generates an integer frequency division sequence value and a fractional frequency division sequence value according to the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, delays the integer frequency division sequence value so that the response time for generating the target frequency division sequence value based on the integer frequency division sequence value and the fractional frequency division sequence value is the same, and frequency modulates the second reference signal based on the target frequency division sequence value to obtain a target frequency signal.

[0009] In one embodiment of the present invention, the first phase-locked module includes a buffer, a first frequency multiplier, a selector, a first phase frequency detector, a first charge pump, a loop filter, a first voltage-controlled oscillator, a first feedback frequency divider, and a first frequency divider. The output of the buffer is connected to the input of the first frequency multiplier and the first input of the selector, the output of the first frequency multiplier is connected to the second input of the selector, the output of the selector is connected to the first input of the first phase frequency detector, the output of the first phase frequency detector is connected to the input of the first charge pump, the output of the first charge pump is connected to the input of the loop filter, the output of the loop filter is connected to the input of the first voltage-controlled oscillator, the output of the first voltage-controlled oscillator is connected to the input of the first feedback frequency divider and the input of the first frequency divider, and the output of the first feedback frequency divider is connected to the second input of the first phase frequency detector. The input of the buffer is connected to the first reference signal, and the output of the first frequency divider outputs the second reference signal.

[0010] In one embodiment of the present invention, the second frequency modulation module includes a frequency division sequence determination unit and a frequency adjustment unit. The frequency division sequence determination unit receives the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal. The frequency division sequence determination unit generates the integer frequency division sequence value and the fractional frequency division sequence value based on the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal. By delaying the integer frequency division sequence value, the response time of the integer frequency division sequence value and the fractional frequency division sequence value in the frequency division sequence determination module to generate the target frequency division sequence value is adjusted to be consistent. The frequency adjustment unit receives the second reference signal and the target frequency division sequence value, generates a feedback signal based on the target frequency division sequence value, performs phase-locking processing on the second reference signal based on the feedback signal, and adjusts the frequency waveform after phase locking to obtain the target frequency signal.

[0011] In one embodiment of the present invention, the frequency division sequence determination unit includes a frequency modulation generation subunit, a delay control subunit, and a Sigma-delta modulator. A first output terminal of the frequency modulation generation subunit is connected to an input terminal of the delay control subunit, a second output terminal of the frequency modulation generation subunit is connected to a first input terminal of the Sigma-delta modulator, and an output terminal of the delay control subunit is connected to a second input terminal of the Sigma-delta modulator. The input terminal of the frequency modulation generation subunit is connected to the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, and the output terminal of the Sigma-delta modulator outputs the target frequency division sequence value.

[0012] In one embodiment of the present invention, the frequency adjustment unit includes a second phase frequency detector, a second charge pump, a second-order tunable loop filter, a second voltage-controlled oscillator, a second feedback frequency divider, a second frequency multiplier, an amplifier, and a third frequency multiplier. The output of the second phase frequency detector is connected to the input of the second charge pump, the output of the second charge pump is connected to the first input of the second-order tunable loop filter, the output of the second-order tunable loop filter is connected to the input of the second voltage-controlled oscillator, the output of the second voltage-controlled oscillator is connected to the first input of the second feedback frequency divider and the input of the second frequency multiplier, the output of the second frequency multiplier is connected to the input of the amplifier, and the output of the amplifier is connected to the input of the third frequency multiplier. The first input of the second phase frequency detector is connected to the second reference signal, the output of the second feedback frequency divider is connected to the second input of the second phase frequency detector and the third input of the sigma-delta modulator, the second input of the second feedback frequency divider is connected to the target frequency division sequence value, and the output of the third frequency multiplier outputs the target frequency signal.

[0013] In one embodiment of the present invention, the FM generation subunit further generates a bandwidth expansion control signal based on the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, so as to adjust the operating current of the second charge pump and the resistance value of the second-order adjustable loop filter through the bandwidth expansion control signal. The second output terminal of the FM generation subunit is connected to the control terminal of the second charge pump and the control terminal of the second-order adjustable loop filter.

[0014] In one embodiment of the present invention, the second-order adjustable loop filter includes a signal transmission subunit and a resistance adjustment subunit. The input end of the signal transmission subunit is connected to the output end of the second frequency and phase detector, and the output end of the signal transmission subunit is connected to the input end of the second voltage-controlled oscillator. The signal transmission subunit transmits the signal output by the second charge pump. The resistance adjustment subunit is connected to the signal transmission subunit and adjusts the resistance of the second-order resistor according to the bandwidth broadening control signal.

[0015] In one embodiment of the present invention, the signal transmission subunit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, and a second resistor. The first end of the first capacitor is connected to the first end of the second capacitor, the first end of the first capacitor is also connected to the first end of the first resistor, the second end of the first capacitor is grounded, the second end of the first resistor is grounded after passing through the third capacitor, the second end of the first resistor is also connected to the first end of the second resistor, and the second end of the second resistor is grounded after passing through the fourth capacitor. The first end of the first capacitor is the input end of the signal transmission subunit, the second end of the second resistor is the output end of the signal transmission subunit, and the second end of the second capacitor is connected to the resistance adjustment subunit.

[0016] In one embodiment of the present invention, the resistance adjustment subunit includes an NMOS transistor, M third resistors, M fourth resistors, M first switches, and M second switches. The first end of the i-th third resistor is grounded after passing through the i-th first switch, the i-th second switch, and the i-th fourth resistor. The drain of the NMOS transistor is connected to a common end of the i-th first switch and the i-th second switch, and the source of the NMOS transistor is grounded. The gate of the NMOS transistor is connected to the bandwidth broadening control signal, and the second end of the i-th third resistor is connected to the signal transmission subunit. M and i are positive integers, and 1≤i≤M.

[0017] The present application provides a frequency-modulated continuous wave modulation source with a dual-loop architecture, which includes a first phase-locked module and a second frequency modulation module. The first phase-locked module increases the frequency of an input first reference signal to obtain a second reference signal with a preset frequency. An integer frequency-division sequence value and a fractional frequency-division sequence value are generated by inputting a starting frequency-division ratio signal, an end frequency-division ratio signal, a frequency-hopping frequency step signal, and a frequency-hopping time step signal into the second frequency modulation module. The response times of the two frequency-division sequence values are adjusted to be consistent through a delay method to generate a target frequency-division sequence value, so as to perform frequency modulation processing on the second reference signal through the target frequency-division sequence value to obtain a target frequency signal. The present application provides a frequency modulation continuous wave modulation source with a dual-loop architecture, which provides a second reference signal of a preset frequency band through a first phase-locked module, provides a higher phase-locked frequency for the second frequency modulation module, and improves the linearity of the frequency modulation continuous wave. Through delay processing, the response time of the integer frequency division sequence value and the fractional frequency division sequence value to generate the target frequency division sequence value is made the same, thereby improving matching and achieving better frequency modulation linearity. The linearity of the frequency modulation continuous modulated source is improved from two aspects, making the application range of the modulation source wider.

[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that a person skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0020] Figure 1 is a block diagram of a frequency modulated continuous wave modulation source of a dual-ring architecture shown in an exemplary embodiment of the present invention;

[0021] Figure 2 is a specific structural diagram of a first phase-locked module shown in an exemplary embodiment of the present invention;

[0022] Figure 3 is a specific structural diagram of a second frequency modulation module shown in an exemplary embodiment of the present invention;

[0023] Figure 4 is a specific structural circuit diagram of a second-order adjustable loop filter shown in an exemplary embodiment of the present invention;

[0024] Figure 5 1 is a schematic diagram of a frequency characteristic curve of a triangle wave modulation with a sweep time of 30 μs, shown in an exemplary embodiment of the present invention;

[0025] Figure 6 1 is a schematic diagram of a frequency characteristic curve of a triangle wave modulation with a sweep time of 300 μs according to an exemplary embodiment of the present invention;

[0026] Figure 7 1 is a schematic diagram of a sawtooth wave modulation frequency characteristic curve with a sweep time of 30 us, shown in an exemplary embodiment of the present invention;

[0027] Figure 8 1 is a schematic diagram of a sawtooth wave modulation frequency characteristic curve with a sweep time of 300 us according to an exemplary embodiment of the present invention;

[0028] Figure 9 1 is a schematic diagram of a nonlinear frequency deviation characteristic curve with a sweep time of 30 μs according to an exemplary embodiment of the present invention;

[0029] Figure 10 1 is a schematic diagram of a nonlinear frequency deviation characteristic curve with a sweep time of 300 μs, shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0031] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0032] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0033] Frequency Modulated Continuous Wave (FMCW) is widely used in applications such as automotive radar and industrial ranging. FMCW technology is based on the frequency modulation of continuous wave signals. It transmits electromagnetic waves whose frequency changes linearly with time and receives the echo signal reflected by the target test object. The transmitted signal and the echo signal are mixed to generate a difference frequency signal. Its frequency is linearly related to the target distance, and the phase change reflects the target speed. By extracting the frequency and phase information of the difference frequency signal through Fourier transform, the distance, speed, and direction of the target test object can be calculated synchronously to achieve high-precision detection. In related technologies, the FMCW frequency modulated continuous wave currently generated is nonlinear, resulting in nonlinear errors in the frequency modulated continuous wave. The nonlinear error will cause the frequency offset of the difference frequency signal, which in turn causes errors in the calculated distance and other information, ultimately directly affecting performance indicators such as measurement accuracy and resolution.

[0034] To provide a higher linearity FM continuous wave modulation source, such as Figure 1 As shown, the present application provides a frequency modulated continuous wave modulation source with a dual-ring architecture, comprising:

[0035] The first phase-locked module receives the first reference signal F ref1 , for the first reference signal F ref1 Perform frequency multiplication, phase locking and frequency division to obtain the second reference signal F ref2 , to provide a second reference signal F of a preset frequency ref2 ;

[0036] The second frequency modulation module receives the second reference signal F ref1 , starting frequency division ratio signal N min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step , according to the starting frequency division ratio signal N min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step Generate an integer frequency division sequence value and a fractional frequency division sequence value, delay the integer frequency division sequence value so that the response time of generating the target frequency division sequence value based on the integer frequency division sequence value and the fractional frequency division sequence value is the same, and perform a delay process on the second reference signal F based on the target frequency division sequence value. ref2 Perform frequency modulation processing to obtain the target frequency signal F out .

[0037] It should be noted that the starting frequency division ratio signal N min Indicates the starting frequency of frequency modulation and the end frequency division ratio signal Nmax Indicates the end frequency of frequency modulation, the frequency hopping frequency step signal F step Indicates the frequency size of each frequency jump, the frequency hopping time step signal T step Indicates the time interval between each frequency hop.

[0038] In detail, such as Figure 2 As shown, the first phase-locked module includes a buffer, a first frequency multiplier, a selector, a first frequency detector, a first charge pump, a loop filter, a first voltage-controlled oscillator, a first feedback frequency divider and a first frequency divider. The output of the buffer is connected to the input of the first frequency multiplier and the first input of the selector, the output of the first frequency multiplier is connected to the second input of the selector, the output of the selector is connected to the first input of the first frequency detector, the output of the first frequency detector is connected to the input of the first charge pump, the output of the first charge pump is connected to the input of the loop filter, the output of the loop filter is connected to the input of the first voltage-controlled oscillator, the output of the first voltage-controlled oscillator is connected to the input of the first feedback frequency divider and the input of the first frequency divider, and the output of the first feedback frequency divider is connected to the second input of the first frequency detector. The input of the buffer is connected to the first reference signal F ref1 The output end of the first frequency divider outputs the second reference signal F ref2 .

[0039] It can be understood that the first reference signal F ref1 After the input buffer is buffered, the first reference signal F can be input through the first frequency multiplier ref1 Perform multiple processing, or directly input it into the selector, determined according to the actual situation; select the frequency size of the input first phase-locked loop (first phase frequency detector, first charge pump, loop filter, first voltage-controlled oscillator, first feedback divider) through the selector, such as Figure 2 As shown, if the first reference signal F ref1 is 40MHz, and the first reference signal F is ref1 Phase-locked processing is performed, and the first voltage-controlled oscillator stably outputs a frequency signal of 4.8 GHz. After the first frequency divider divides the 4.8 GHz signal by six, a second reference signal F with a frequency of 800 MHz is obtained. ref2 .

[0040] In detail, the second frequency modulation module includes a frequency division sequence determination unit and a frequency adjustment unit. The frequency division sequence determination unit receives the starting frequency division ratio signal N min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step The frequency division sequence determination unit determines the frequency division ratio signal N according to the starting frequency division ratio signal N. min , End frequency division ratio signal Nmax , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step Generate integer frequency division sequence value N int and fractional frequency sequence value N frac , by dividing the integer frequency sequence value N int Perform delay processing and determine the integer frequency division sequence value N in the frequency division sequence determination module int and fractional frequency sequence value N frac The response time of generating the target frequency division sequence value N is adjusted to be consistent; the frequency adjustment unit receives the second reference signal F ref2 and the target frequency division sequence value N, and generates a feedback signal F based on the target frequency division sequence value N V , based on the feedback signal F V For the second reference signal F ref2 Perform phase-locking processing and adjust the frequency waveform after phase locking to obtain the target frequency signal F out .

[0041] In more detail, Figure 3 As shown, the frequency division sequence determination unit includes a frequency modulation generation subunit, a delay control subunit, and a Sigma-delta modulator. The first output terminal of the frequency modulation generation subunit is connected to the input terminal of the delay control subunit, the second output terminal of the frequency modulation generation subunit is connected to the first input terminal of the Sigma-delta modulator, and the output terminal of the delay control subunit is connected to the second input terminal of the Sigma-delta modulator. The input terminal of the frequency modulation generation subunit is connected to the starting frequency division ratio signal N min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step , the output end of the Sigma-delta modulator outputs the target frequency division sequence value N.

[0042] In detail, such as Figure 3 As shown, the frequency adjustment unit includes a second phase frequency detector, a second charge pump, a second-order adjustable loop filter, a second voltage controlled oscillator, a second feedback frequency divider, a second frequency multiplier, an amplifier, and a third frequency multiplier. The output of the second phase frequency detector is connected to the input of the second charge pump, the output of the second charge pump is connected to the first input of the second-order adjustable loop filter, the output of the second-order adjustable loop filter is connected to the input of the second voltage controlled oscillator, the output of the second voltage controlled oscillator is connected to the first input of the second feedback frequency divider and the input of the second frequency multiplier, the output of the second frequency multiplier is connected to the input of the amplifier, and the output of the amplifier is connected to the input of the third frequency multiplier. The first input of the second phase frequency detector is connected to the second reference signal F ref2The output terminal of the second feedback divider is connected to the second input terminal of the second frequency detector and the third input terminal of the Sigma-delta modulator. The second input terminal of the second feedback divider is connected to the target frequency division sequence value N. The output terminal of the third frequency multiplier outputs the target frequency signal F to the outside. out .

[0043] It can be understood that when the second reference signal F is input ref2 When the frequency is 800MHz, set the starting frequency division ratio signal N according to the actual situation. min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step The frequency modulation generation subunit generates a frequency division ratio signal N according to the starting frequency division ratio signal N. min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step Generate integer frequency division sequence value N int and fractional frequency sequence value N frac , in order to make the Sigma-delta modulator process the integer frequency division sequence value N int and fractional frequency sequence value N frac The response time is the same, for integer frequency division sequence value N int The Sigma-delta modulator uses the clock signal of the second feedback divider output signal as the clock reference signal to perform delay processing and adjust the integer frequency division sequence value N int and fractional frequency sequence value N frac Perform combined calculation to obtain the target frequency division sequence value N. The second feedback frequency divider performs frequency division processing on the signal output by the second voltage-controlled oscillator according to the target frequency division sequence value N to obtain the feedback signal F v The second phase-locked loop (second phase frequency detector, second charge pump, second-order adjustable loop filter, second voltage-controlled oscillator) is based on the feedback signal F v For the second reference signal F ref2 Phase-locked processing is performed, and frequency pulling is performed quickly to make the second voltage-controlled oscillator stably output a frequency signal of 19 to 20.25 GHz. The signal output by the second voltage-controlled oscillator is doubled by the second frequency multiplier. The signal output by the second frequency multiplier is amplified by the amplifier to obtain a frequency signal of 38 to 40.5 GHz. The frequency signal of 38 to 40.5 GHz is then doubled by the third frequency multiplier to obtain a target frequency signal F with a frequency of 76 to 81 GHz. out .

[0044] In detail, such as Figure 3 As shown, the FM generation subunit also generates a frequency division ratio signal N according to the starting frequency division ratio signal N.min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step A bandwidth widening control signal BW_SP is generated to adjust the operating current of the second charge pump and the resistance value in the second-order adjustable loop filter through the bandwidth widening control signal BW_SP. The second output terminal of the frequency modulation generation subunit is connected to the control terminal of the second charge pump and the control terminal of the second-order adjustable loop filter.

[0045] In more detail, the second-order adjustable loop filter includes a signal transmission subunit and a resistance adjustment subunit. The input end of the signal transmission subunit is connected to the output end of the second frequency and phase detector, the output end of the signal transmission subunit is connected to the input end of the second voltage-controlled oscillator, the signal transmission subunit transmits the signal output by the second charge pump, and the resistance adjustment subunit is connected to the signal transmission subunit to adjust the resistance of the second-order resistor according to the bandwidth widening control signal BW_SP.

[0046] Specifically, if Figure 4 As shown, the signal transmission subunit includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, and a second resistor R1. The first end of the first capacitor C1 is connected to the first end of the second capacitor C2, the first end of the first capacitor C1 is also connected to the first end of the first resistor R1, the second end of the first capacitor C1 is grounded, the second end of the first resistor R1 is grounded via the third capacitor C3, the second end of the first resistor R1 is also connected to the first end of the second resistor R1, and the second end of the second resistor R1 is grounded via the fourth capacitor C4. The first end of the first capacitor C1 is the input end of the signal transmission subunit, the input end of the signal transmission subunit is connected to the output end of the second charge pump, the second end of the second resistor R1 is the output end of the signal transmission subunit, the output end of the signal transmission subunit is connected to the input end of the second voltage-controlled oscillator, and the second end of the second capacitor C2 is connected to the resistance adjustment subunit.

[0047] Specifically, if Figure 4 As shown, the resistance adjustment subunit includes an NMOS transistor NM1, M third resistors R31-R3M, M fourth resistors R41-R4M, M first switches SW1a-SWMa, and M second switches SW1b-SWMb. The first end of the i-th third resistor R3i is connected to ground via the i-th first switch SWia, the i-th second switch SWib, and the i-th fourth resistor R4i. The drain of the NMOS transistor NM1 is connected to the common end of the i-th first switch SWia and the i-th second switch SWib, and the source of the NMOS transistor NM1 is grounded. The gate of the NMOS transistor NM1 is connected to the bandwidth stretching control signal BW_SP. The second end of the i-th third resistor R3i is connected to the signal transmission subunit. M and i are positive integers, and 1≤i≤M.

[0048] Please refer to Figures 1 to 10 As shown, the working principle of the frequency modulated continuous wave modulation source of the dual-ring architecture provided by this application is as follows:

[0049] like Figure 1 As shown, the first phase-locked module includes a first phase-locked loop, and the input first reference signal F ref1 The frequency is 40MHz, such as Figure 2 As shown, after the first phase-locked loop phase-locked processing, the first voltage-controlled oscillator outputs a 4.8 GHz signal, and the 4.8 GHz signal is divided and output by the first frequency divider to obtain a second reference signal F with a frequency of 800 MHz. ref2 ; The function of the first phase-locked loop is to provide a higher phase frequency for the second frequency modulation module, thereby improving the linearity of the FMCW phase-locked loop frequency modulation.

[0050] like Figure 3 As shown, the second frequency modulation module is used to realize the modulation frequency output, and the core unit for controlling the frequency modulation is the frequency modulation generation subunit. The frequency modulation generation subunit generates the frequency modulation subunit according to the starting frequency division ratio signal N min , End frequency division ratio signal N max , frequency hopping frequency step signal F step , frequency hopping time stepping signal T step Determines the characteristics of frequency modulation; the FM generation subunit generates the frequency modulation signal according to the input N min 、N max 、F step and T step Output the corresponding integer frequency division sequence value N int and fractional frequency sequence value N frac .

[0051] Because the target frequency division sequence value N of the Sigma-delta modulator is determined by the integer frequency division sequence value N int and fractional frequency sequence value N frac The target frequency division sequence value N is calculated by combining the integer frequency division sequence value N. int The response is real-time, and the fractional frequency sequence value N frac The response of the Sigma-delta modulator needs to be delayed for several cycles of the Sigma-delta modulator input clock before it is reflected. Therefore, a delay control subunit is added between the FM generation subunit and the Sigma-delta modulator to control the integer frequency division sequence value N. int Delay, increase the integer frequency division sequence value N int and the fractional frequency sequence value N frac The matching of the input Sigma-Delta modulator achieves better frequency modulation linearity.

[0052] In the process of generating a sawtooth wave from a continuous wave modulation source, the second frequency modulation module is required to quickly respond to frequency mutations. When the frequency mutation occurs, the frequency modulation generation subunit will also output a bandwidth expansion control signal BW_SP. By increasing the charging and discharging current of the second charge pump and reducing the resistance of the second-order resistor in the second-order adjustable loop filter, it ensures that the loop bandwidth is increased while maintaining loop stability, speeds up the frequency establishment process, and achieves the effect of fast frequency response.

[0053] like Figure 4 As shown, when the bandwidth stretch control signal BW_SP is at a logic "1" level, NMOS transistor NM1 is turned on, and the second-order resistor connected to the second-order adjustable loop filter is reduced to R31||…||R3N. When the bandwidth stretch control signal BW_SP is at a logic "0" level, NMOS transistor NM1 is turned off, and the second-order resistor connected to the second-order adjustable loop filter is (R31||…||R3N) + (R41||…||R4N). The number of parallel resistors R31 and R41 can be selected based on the required loop bandwidth characteristics. When the modulation frequency needs to change rapidly (such as the frequency mutation stage in sawtooth frequency modulation), the bandwidth stretch control signal BW_SP automatically outputs a logic "1" level through the frequency modulation generation subunit, which can simultaneously increase the charge and discharge current of the second charge pump and reduce the second-order resistor value of the second-order adjustable loop filter, thereby widening the loop bandwidth and accelerating transient response.

[0054] like Figure 5 As shown, Figure 5 The frequency characteristic curve of triangle wave modulation with a sweep time of 30us is shown. The single-side sweep time is 30us and the sweep range is 76GHz-81GHz. The linear frequency modulation speed in the frequency range of 76GHz-81GHz reaches about 166.67MHz / μs.

[0055] like Figure 6 As shown, Figure 6 The frequency characteristic curve of the triangle wave modulation with a sweep time of 300us is shown. The single-side sweep time is 300us and the sweep range is 76GHz-81GHz. The linear frequency modulation speed in the frequency range of 76GHz-81GHz reaches about 16.67MHz / μs.

[0056] like Figure 7 As shown, Figure 7 The sawtooth wave modulation frequency characteristic curve with a sweep time of 30us is shown, which has a linear and fast frequency modulation effect. The sweep range is 76GHz-81GHz, and the linear frequency modulation speed in the 76GHz-81GHz frequency range reaches about 166.67MHz / μs.

[0057] like Figure 8 As shown, Figure 8The sawtooth wave modulation frequency characteristic curve with a sweep time of 300us is shown, which has a linear and fast frequency modulation effect. The sweep range is 76GHz-81GHz, and the linear frequency modulation speed in the 76GHz-81GHz frequency range reaches about 16.67MHz / μs.

[0058] The method for calculating the nonlinearity of the frequency characteristic curve output by the continuous wave modulation source is: intercept a curve in a certain rising or falling area of the measured modulation frequency curve, interconnect the two ends of the curve to form an ideal curve, calculate the frequency difference between the measured curve and the ideal curve, and divide it by the intercepted frequency bandwidth to obtain the nonlinearity of the frequency characteristic curve.

[0059] like Figure 9 As shown, Figure 9 The nonlinear frequency deviation characteristic curve with a sweep time of 30 us is shown. Under a modulation bandwidth of 5 GHz, the maximum frequency deviation is about 2.35 MHz, and the corresponding frequency modulation nonlinearity is about -0.047%.

[0060] like Figure 10 As shown, Figure 10 The nonlinear frequency deviation characteristic curve with a sweep time of 300 us is shown. Under a modulation bandwidth of 5 GHz, the maximum frequency deviation is about 0.31 MHz, and the corresponding frequency modulation nonlinearity is about -0.0062%.

[0061] Depend on Figures 5 to 10 It can be seen that the frequency modulated continuous wave modulation source provided in this application has relatively high linearity and very low nonlinearity under different sweep times, whether it is a triangle wave or a sawtooth wave, so that the measurement accuracy is high and the resolution is accurate when measuring the target test object through the signal generated by the frequency modulated continuous wave modulation source.

[0062] The present application provides a frequency-modulated continuous wave modulation source with a dual-loop architecture, which includes a first phase-locked module and a second frequency modulation module. The first phase-locked module increases the frequency of an input first reference signal to obtain a second reference signal with a preset frequency. An integer frequency division sequence value, a fractional frequency division sequence value, and a bandwidth expansion control signal are generated by inputting a starting frequency division ratio signal, an end frequency division ratio signal, a frequency hopping frequency step signal, and a frequency hopping time step signal into the second frequency modulation module. The response time of the two frequency division sequence values to generate a target frequency division sequence value is adjusted to be consistent by delaying the integer frequency division sequence value. The loop bandwidth of the second frequency modulation module is also widened according to the bandwidth expansion control signal, so that the second reference signal is frequency modulated by the target frequency division sequence value to obtain a target frequency signal. The present application provides a frequency modulation continuous wave modulation source with a dual-loop architecture, which provides a second reference signal of a preset frequency band through a first phase-locked module, provides a higher phase-locked frequency for the second frequency modulation module, improves the linearity of the frequency modulation continuous wave, and delays the integer frequency division sequence value so that the response time of the two frequency division sequence values to generate the target frequency division sequence value is the same, thereby improving the matching and achieving better frequency modulation linearity, thereby improving the linearity of the output signal of the frequency modulation continuous wave modulation source from two different aspects; it also increases the loop bandwidth of the second frequency modulation module through a bandwidth widening control signal, improves the transient response speed, and broadens the application range of the output signal of the frequency modulation continuous wave modulation source.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A frequency modulated continuous wave modulation source with a dual-ring architecture, characterized in that: include: a first phase-locking module, receiving a first reference signal, performing frequency multiplication, phase locking, and frequency division processing on the first reference signal to obtain a second reference signal, so as to provide the second reference signal of a preset frequency; The second frequency modulation module receives the second reference signal, the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, generates an integer frequency division sequence value and a fractional frequency division sequence value according to the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, delays the integer frequency division sequence value so that the response time for generating the target frequency division sequence value based on the integer frequency division sequence value and the fractional frequency division sequence value is the same, and frequency modulates the second reference signal based on the target frequency division sequence value to obtain a target frequency signal.

2. The dual-ring architecture FMCW modulation source according to claim 1, wherein: The first phase-locked module includes a buffer, a first frequency multiplier, a selector, a first phase frequency detector, a first charge pump, a loop filter, a first voltage-controlled oscillator, a first feedback frequency divider, and a first frequency divider. The output of the buffer is connected to the input of the first frequency multiplier and the first input of the selector, the output of the first frequency multiplier is connected to the second input of the selector, the output of the selector is connected to the first input of the first phase frequency detector, the output of the first phase frequency detector is connected to the input of the first charge pump, the output of the first charge pump is connected to the input of the loop filter, the output of the loop filter is connected to the input of the first voltage-controlled oscillator, the output of the first voltage-controlled oscillator is connected to the input of the first feedback frequency divider and the input of the first frequency divider, and the output of the first feedback frequency divider is connected to the second input of the first phase frequency detector. The input of the buffer is connected to the first reference signal, and the output of the first frequency divider outputs the second reference signal.

3. The dual-ring architecture FMCW modulation source according to claim 1, wherein: The second frequency modulation module includes a frequency division sequence determination unit and a frequency adjustment unit. The frequency division sequence determination unit receives the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal. The frequency division sequence determination unit generates the integer frequency division sequence value and the fractional frequency division sequence value according to the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal. By delaying the integer frequency division sequence value, the response time of the integer frequency division sequence value and the fractional frequency division sequence value in the frequency division sequence determination module to generate the target frequency division sequence value is adjusted to be consistent. The frequency adjustment unit receives the second reference signal and the target frequency division sequence value, generates a feedback signal based on the target frequency division sequence value, performs phase-locking processing on the second reference signal based on the feedback signal, and adjusts the frequency waveform after phase locking to obtain the target frequency signal.

4. The dual-ring architecture FMCW modulation source according to claim 3, wherein: The frequency division sequence determination unit includes a frequency modulation generation subunit, a delay control subunit, and a Sigma-delta modulator. The first output end of the frequency modulation generation subunit is connected to the input end of the delay control subunit, the second output end of the frequency modulation generation subunit is connected to the first input end of the Sigma-delta modulator, and the output end of the delay control subunit is connected to the second input end of the Sigma-delta modulator. The input end of the frequency modulation generation subunit is connected to the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, and the output end of the Sigma-delta modulator outputs the target frequency division sequence value.

5. The dual-ring architecture FMCW modulation source according to claim 4, characterized in that: The frequency adjustment unit includes a second phase frequency detector, a second charge pump, a second-order adjustable loop filter, a second voltage-controlled oscillator, a second feedback frequency divider, a second frequency multiplier, an amplifier, and a third frequency multiplier. The output of the second phase frequency detector is connected to the input of the second charge pump, the output of the second charge pump is connected to the first input of the second-order adjustable loop filter, the output of the second-order adjustable loop filter is connected to the input of the second voltage-controlled oscillator, the output of the second voltage-controlled oscillator is connected to the first input of the second feedback frequency divider and the input of the second frequency multiplier, the output of the second frequency multiplier is connected to the input of the amplifier, and the output of the amplifier is connected to the input of the third frequency multiplier. The first input of the second phase frequency detector is connected to the second reference signal, the output of the second feedback frequency divider is connected to the second input of the second phase frequency detector and the third input of the sigma-delta modulator, the second input of the second feedback frequency divider is connected to the target frequency division sequence value, and the output of the third frequency multiplier outputs the target frequency signal.

6. The dual-ring architecture FMCW modulation source according to claim 5, characterized in that: The frequency modulation generation subunit further generates a bandwidth expansion control signal based on the starting frequency division ratio signal, the ending frequency division ratio signal, the frequency hopping frequency step signal, and the frequency hopping time step signal, so as to adjust the operating current of the second charge pump and the resistance value in the second-order adjustable loop filter through the bandwidth expansion control signal. The second output terminal of the frequency modulation generation subunit is connected to the control terminal of the second charge pump and the control terminal of the second-order adjustable loop filter.

7. The dual-ring architecture FMCW modulation source according to claim 6, wherein: The second-order adjustable loop filter includes a signal transmission subunit and a resistance adjustment subunit. The input end of the signal transmission subunit is connected to the output end of the second charge pump, and the output end of the signal transmission subunit is connected to the input end of the second voltage-controlled oscillator. The signal transmission subunit transmits the signal output by the second charge pump. The resistance adjustment subunit is connected to the signal transmission subunit and adjusts the resistance of the second-order resistor according to the bandwidth broadening control signal.

8. The dual-ring architecture FMCW modulation source according to claim 7, wherein: The signal transmission subunit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, and a second resistor. The first end of the first capacitor is connected to the first end of the second capacitor, the first end of the first capacitor is also connected to the first end of the first resistor, the second end of the first capacitor is grounded, the second end of the first resistor is grounded after passing through the third capacitor, the second end of the first resistor is also connected to the first end of the second resistor, and the second end of the second resistor is grounded after passing through the fourth capacitor. The first end of the first capacitor is the input end of the signal transmission subunit, the second end of the second resistor is the output end of the signal transmission subunit, and the second end of the second capacitor is connected to the resistance adjustment subunit.

9. The dual-ring architecture FMCW modulation source according to claim 7, wherein: The resistance adjustment subunit includes an NMOS transistor, M third resistors, M fourth resistors, M first switches, and M second switches. The first end of the i-th third resistor is grounded after passing through the i-th first switch, the i-th second switch, and the i-th fourth resistor. The drain of the NMOS transistor is connected to the common end of the i-th first switch and the i-th second switch, and the source of the NMOS transistor is grounded. The gate of the NMOS transistor is connected to the bandwidth broadening control signal, and the second end of the i-th third resistor is connected to the signal transmission subunit. M and i are positive integers, and 1≤i≤M.

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