Frame header detection method and frame header detection device

Abstract

The embodiment of the invention provides a frame header detection method and a frame header detection device, and relates to the technical field of communication. The frame header detection device comprises a counter synchronous detection module, a specific code pattern detection circuit and a phase-locked loop. And the counter synchronous detection module comprises a counter. The frame header detection method comprises the following steps: under the condition that a phase-locked loop is unlocked, a counter synchronous detection module performs frame header detection on a received frame signal through a counter, and generates a first reference clock of the phase-locked loop; the phase-locked loop is locked according to the first reference clock; and under the condition that the phase-locked loop is locked, the specific code pattern detection circuit performs frame header detection on the received frame signal. The design of a high-precision clock is not needed, so that the cost and complexity of the design are effectively reduced. And after the phase-locked loop is locked, a counter is not used any more, so that the EMC capability is improved, and the influence caused by electromagnetic interference is avoided.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a frame header detection method and a frame header detection device. Background Art

[0002] In a burst mode communication system, the beginning of a frame is called a preamble. The preamble is used to detect the frame header and receive and recover valid data based on the detected frame header. Specifically, when the preamble is detected, it indicates the beginning of a frame of valid data.

[0003] Compared to continuous-mode communication systems, burst-mode communication systems require a frame header to identify the beginning of a frame. However, an excessively long frame header can negatively impact bandwidth utilization. Therefore, the preamble length is typically limited.

[0004] On the other hand, when a short preamble is used as a frame header, detection of the frame header may be affected by electromagnetic interference (EMC), leading to misjudgment and resulting in bit errors and frame loss. In this case, it is necessary to fully utilize the fixed pattern of the preamble to detect the frame header. This places certain demands on the accuracy of the reference clock at the receiver, increasing design cost and practical complexity.

[0005] How to reduce the cost and accuracy requirements in frame header detection is the technical problem to be solved in this application. Summary of the Invention

[0006] The purpose of this application is to provide a frame header detection method and a frame header detection device to reduce the cost and accuracy requirements in the detection of frame headers.

[0007] To achieve the above objectives, one or more embodiments of the present application adopt the following technical solutions.

[0008] In a first aspect, an embodiment of the present application provides a frame header detection method, which is applied to a frame header detection device, wherein the frame header detection device includes a counter synchronization detection module, a specific code pattern detection circuit, and a phase-locked loop; the counter synchronization detection module includes a counter;

[0009] The frame header detection method comprises:

[0010] When the phase-locked loop is not locked, the counter synchronization detection module performs frame header detection on the received frame signal through the counter and generates a first reference clock of the phase-locked loop;

[0011] Before the phase-locked loop is locked, the phase-locked loop is locked according to the first reference clock;

[0012] When the phase-locked loop is locked, the specific code pattern detection circuit performs frame header detection on the received frame signal and generates a second reference clock for the phase-locked loop.

[0013] Optionally, the counter synchronization detection module performs frame header detection on the received frame signal through the counter, and generates the first reference clock of the phase-locked loop, including:

[0014] Whenever the counter detects a frame header, it generates a pulse signal as the first reference clock, and the frequency of the first reference clock is the frequency of the frame.

[0015] Optionally, the step of the counter synchronization detection module performing frame header detection on the received frame signal through the counter includes:

[0016] Count the rising edges of the received frame signal, and determine that the frame header is detected when the count reaches a set value;

[0017] Or count the falling edges of the received frame signal, and determine that the frame header is detected when the count reaches a set value;

[0018] Or the rising and falling edges of the received frame signal are counted, and when the count reaches a set value, it is determined that the frame header is detected.

[0019] Optionally, the frame header detection device further includes an EMC protection window module;

[0020] The frame header detection method further includes: the EMC protection window module generating an EMC protection window;

[0021] When the phase-locked loop is not locked, the counter synchronization detection module performs frame header detection on the received signal through the counter within the time period of the EMC protection window;

[0022] When the phase-locked loop is locked, the specific code pattern detection circuit performs frame header detection on the received signal within the time period of the EMC protection window.

[0023] Optionally, a width of the EMC protection window when the phase-locked loop is unlocked is greater than a width of the EMC protection window when the phase-locked loop is locked.

[0024] Optionally, the step of performing frame header detection on the received frame signal by the specific code pattern detection circuit includes:

[0025] generating a plurality of clocks with the same frequency but different phases according to the phase-locked loop, and sampling the received frame signal according to the plurality of clocks with the same frequency but different phases;

[0026] The data obtained by sampling each clock is compared with a specific code pattern, and whether the frame header is detected is determined based on the comparison result.

[0027] Optionally, the step of determining whether a frame header is detected according to the comparison result includes:

[0028] When the number of clocks in which data is consistent with a specific pattern reaches a set number, it is determined that the frame header is detected; the set number is greater than or equal to 1.

[0029] In a second aspect, an embodiment of the present application provides a frame header detection device, comprising a counter synchronization detection module, a specific code pattern detection circuit, a data selector, and a phase-locked loop; the counter synchronization detection module comprises a counter;

[0030] The input end of the counter synchronization detection module and the input end of the specific code pattern detection circuit are used to receive the frame signal;

[0031] The output end of the counter synchronization detection module is connected to the first input end of the data selector;

[0032] The output end of the specific code pattern detection circuit is connected to the second input end of the data selector;

[0033] The output end of the data selector is connected to the input end of the phase-locked loop;

[0034] The clock output end of the phase-locked loop is connected to the clock input end of the specific code pattern detection circuit;

[0035] The locking state output terminal of the phase-locked loop is connected to the control terminal of the data selector;

[0036] The counter synchronization detection module is used to perform frame header detection on the received frame signal through the counter, and generate a first reference clock of the phase-locked loop and transmit it to the first input end of the data selector;

[0037] The specific code pattern detection circuit is used to perform frame header detection on the received frame signal and generate a second reference clock to transmit to the second input end of the data selector;

[0038] The phase-locked loop is used to lock according to the first reference clock; when unlocked, the locked state output terminal is a first signal; when locked, the locked state output terminal is a second signal, and a third reference clock is provided to the specific code pattern detection circuit at the phase-locked loop clock output terminal;

[0039] The specific code pattern detection circuit is used to perform frame header detection on the received frame signal and generate a second reference clock to transmit to the second input end of the data selector;

[0040] The data selector is used to output the signal of the first input terminal of the data selector when the control terminal is the first signal; and to output the signal of the second input terminal of the data selector when the control terminal is the second signal.

[0041] Optionally, the frame header detection device further includes an EMC protection window module and a low-precision clock module, and the accuracy of the low-precision clock module is lower than the accuracy of the phase-locked loop locked clock;

[0042] The first input end of the EMC protection window module is connected to the output end of the data selector;

[0043] The second input end of the EMC protection window module is connected to the clock output end of the phase-locked loop;

[0044] The third input terminal of the EMC protection window module is connected to the low-precision clock module;

[0045] The output end of the EMC protection window module is connected to the enable end of the counter synchronization detection module and the enable end of the specific code pattern detection circuit;

[0046] The EMC protection window module is used for:

[0047] When the phase-locked loop is not locked, the EMC protection window is determined according to the low-precision clock module; when the phase-locked loop is locked, the EMC protection window is determined according to the clock output terminal signal of the phase-locked loop;

[0048] During the EMC protection window period, an enable signal is sent at the output end of the EMC protection window module.

[0049] Optionally, the frame header detection device further includes an EMC protection window module;

[0050] The first input end of the EMC protection window module is connected to the output end of the data selector;

[0051] The second input end of the EMC protection window module is connected to the clock output end of the phase-locked loop;

[0052] The output end of the EMC protection window module is connected to the enable end of the specific code pattern detection circuit; the EMC protection window module is used to send an enable signal at the output end of the EMC protection window module within the EMC protection window time period.

[0053] Compared with the prior art, this application has the following beneficial effects:

[0054] Since a high-precision clock design is not required, the design cost and complexity are effectively reduced. After the phase-locked loop is locked, the counter is no longer used, which improves EMC performance and avoids the impact of electromagnetic interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 This is a schematic diagram of a frame of data in a burst mode communication system;

[0057] Figure 2 Schematic diagram of a preamble code;

[0058] Figure 3 A schematic diagram of a frame header detection device provided in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of a specific code pattern detection circuit provided in an embodiment of the present application;

[0060] Figure 5 A schematic diagram of a frame header detection device with a Hamming distance detection function provided in an embodiment of the present application;

[0061] Figure 6 A schematic diagram of an EMC protection window provided in an embodiment of the present application;

[0062] Figure 7 A schematic diagram of a frame header detection device with an EMC protection window module provided in an embodiment of the present application;

[0063] Figure 8 A schematic diagram showing that the size of an EMC protection window provided in an embodiment of the present application can be adjusted according to the current state of a frame header detection circuit;

[0064] Figure 9 A schematic diagram of abandoning the EMC protection window when using counting for frame header detection is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, but not all of the embodiments. Generally, the components of the embodiments of the present application described in the drawings herein can be arranged and designed in various different configurations.

[0066] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is claimed, but rather merely represents selected embodiments of the present application. All other embodiments derived by persons of ordinary skill in the art based on the embodiments in this application without creative effort are intended to fall within the scope of protection of this application. The following embodiments and features therein may be combined with each other unless there is a conflict.

[0067] In the description of this application, it is necessary to explain:

[0068] Relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply any actual relationship or order between these entities or operations;

[0069] “Connection” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0070] Figure 1 The figure shows an example of a data frame in a burst mode communication system. The preamble precedes the data segment, and the data code follows the preamble. Figure 2 The figure below is a specific example of a preamble. It consists of a specific 24-bit pattern. The preamble is checked to see if it meets expectations. For example, if the number of error bits detected is less than or equal to 2, it indicates that a frame of data has been detected, and data recovery and reception begins.

[0071] When the receiver's clock deviates from the transmitter's, direct preamble sampling and detection may produce errors. This requires a clock deviation of no more than 5%. Furthermore, considering the sampling phase, intersymbol interference, and noise, the accuracy requirement is even higher, reaching <1% to ensure adequate robustness and reliability. This accuracy requirement can significantly increase the difficulty and complexity of the receiver's reference clock design, even requiring the use of a crystal oscillator to ensure adequate robustness. This further increases design costs.

[0072] Another possible implementation is to detect frame headers by counting the number of rising and falling edges of the data. In the absence of electromagnetic interference, the frame header pattern is fixed, and counting fixed rising and falling edges can accurately complete frame header detection. However, in the presence of electromagnetic interference, this detection method may incorrectly output frame header detection information prematurely, resulting in bit errors or frame loss.

[0073] This embodiment of the present application provides a frame header detection method, including:

[0074] When the phase-locked loop is not locked, a counter is used to detect a frame header of a received frame signal and generate a first reference clock of the phase-locked loop;

[0075] Before the phase-locked loop is locked, the phase-locked loop is locked according to the first reference clock;

[0076] When the phase-locked loop is locked, a specific code detection circuit is used to perform frame header detection on the received frame signal and generate a second reference clock of the phase-locked loop. After the phase-locked loop is locked, the phase-locked loop can continue to receive the second reference clock.

[0077] In this frame header detection method, the design of a high-precision clock is not required, which effectively reduces the cost and complexity of the design. After the phase-locked loop is locked, the counter is no longer used, the EMC capability is improved, and the influence of electromagnetic interference is avoided.

[0078] The process of using a counter to detect the frame header of the received frame signal can be to count the rising edges of the received frame signal and determine that the frame header is detected when the count reaches a set value; it can also be to count the falling edges of the received frame signal and determine that the frame header is detected when the count reaches a set value; it can also be to count the rising and falling edges of the received frame signal and determine that the frame header is detected when the count reaches a set value.

[0079] The process of using a counter to detect the frame header of the received frame signal and generate the first reference clock of the phase-locked loop can be to generate a pulse signal every time the counter detects a frame header. These pulse signals serve as the first reference clock, and the frequency of the first reference clock is the frequency of the frame.

[0080] The frame header detection method can be achieved by Figure 3 The frame header detection device shown is implemented as follows: Figure 3 The frame header detection device includes a counter synchronization detection module, a specific code pattern detection circuit and a phase-locked loop. The counter synchronization detection module includes a counter.

[0081] like Figure 3 , the various parts of the frame header detection device have the following connection relationship:

[0082] The input end of the counter synchronization detection module and the input end of the specific code pattern detection circuit are used to receive the frame signal, which can be a burst mode signal, namely, burst mode data in the figure;

[0083] The output end of the counter synchronization detection module is connected to the first input end of the data selector;

[0084] The output end of the specific code pattern detection circuit is connected to the second input end of the data selector;

[0085] The output end of the data selector is connected to the input end of the phase-locked loop;

[0086] The clock output terminal of the phase-locked loop is connected to the clock input terminal of the specific pattern detection circuit;

[0087] The locking state output terminal of the phase-locked loop is connected to the control terminal of the data selector.

[0088] The functions of each part of the frame header detection device are as follows:

[0089] The counter synchronization detection module is used to perform frame header detection on the received frame signal through the counter, and generate a first reference clock of the phase-locked loop and transmit it to the first input end of the data selector;

[0090] The specific code pattern detection circuit is used to perform frame header detection on the received frame signal and generate a second reference clock to transmit to the second input end of the data selector;

[0091] The phase-locked loop is configured to lock according to a first reference clock; when the phase-locked loop is unlocked, the locked state output terminal is a first signal; when the phase-locked loop is locked, the locked state output terminal is a second signal PLL LOCK, and a third reference clock is provided at the phase-locked loop clock output terminal for a specific pattern detection circuit;

[0092] The data selector is used to output the signal at the first input end of the data selector as the synchronization header signal sync header when the control end is the first signal; and to output the signal at the second input end of the data selector as the synchronization header signal sync header when the control end is the second signal PLL LOCK.

[0093] The signal PLL CLOCK at the phase-locked loop clock output terminal can be used as the clock signal of the clock data recovery circuit. The clock data recovery circuit recovers the clock data of the frame signal according to the signal PLL CLOCK and outputs the recovered clock recoveredclock and recovered data recovereddata.

[0094] A specific principle of the specific code type detection circuit can be as follows: there are multiple sampling units on the input data data in line, and each sampling unit receives a clock signal from the multi-phase clock output of the phase-locked loop. These clock signals are multiple clocks with the same frequency but different phases. Each sampling unit performs open-loop oversampling on the received frame signal according to the multiple clocks with the same frequency but different phases, thereby avoiding the use of a complex clock data recovery circuit, and has higher accuracy, avoiding missing the frame header, and then the data obtained by each clock sampling can be compared with the specific code type, and whether the frame header is detected can be determined based on the comparison result. For example, when the number of clocks whose data is consistent with the specific code type reaches a set number, it is determined that the frame header is detected; the set number can be 1 or greater than 1.

[0095] like Figure 4 A structure of a specific pattern detection circuit is as follows: there are multiple sampling units on the input data data in line, and each sampling unit is connected to the multi-phase clock outputs of the phase-locked loop (PLL). The data obtained by the sampling unit is shifted, stored, and XORed with the known specific pattern. The data can be input into the OR gate (OR) through the shift register (shiftregs) and the exclusive-OR gate (XNOR). Detecting a signal that meets the Hamming distance requirement at any phase means that the preamble code is detected. The OR gate outputs the result to the retimer (Retimer). The retimer retimes according to the input data data in, obtains the frequency and phase information of the input data data in, and generates a synchronization header signal sync header to provide a reference clock for the phase-locked loop.

[0096] This specific pattern detection circuit can directly perform frame header detection without the need for a clock data recovery circuit, and has low power consumption and hardware overhead. Figure 4 The figure shows 4-phase oversampling, but the actual phase can be increased or decreased.

[0097] against Figure 2 In the case of a 24-bit preamble, if detection is performed directly without a PLL to provide a precise clock, under the worst-case sampling phase, ignoring intersymbol interference (ISI) and noise, four-phase oversampling will result in an initial phase error of 1 / 4 phase, resulting in only a 3% probability of correctly detecting the frame header. To account for noise and ISI and ensure robustness, this value must be less than 1%, significantly increasing the cost and complexity of on-chip clock design. However, when using a PLL clock locked to the frame header as the reference clock, there is no clock error. Oversampling multiple clocks with the same frequency but different phases only needs to tolerate the effects of noise, ISI, and initial sampling phase deviation, significantly reducing implementation cost and complexity.

[0098] As an alternative embodiment, the above-mentioned specific code pattern detection method can be Hamming distance detection, such as Figure 5 The specific code pattern detection method is not unique, and other specific code patterns and detection circuits and methods thereof are also possible.

[0099] As an optional embodiment, the frame header detection apparatus may further include an EMC protection window module. The frame header detection method further includes: the EMC protection window module generating an EMC protection window, wherein the frame header detection process may be performed only within the EMC protection window period. When interference is present in the system idle state, if the interference occurs outside the EMC protection window, the frame header detection circuit does not operate. Therefore, the interference does not affect frame header detection, thereby improving EMC performance.

[0100] It is possible to limit only the frame header detection mode of the counter to within the EMC protection window time period, or only the frame header detection mode of the specific code type detection circuit to within the EMC protection window time period, or to limit both the frame header detection mode of the counter and the frame header detection mode of the specific code type detection circuit to within the EMC protection window time period.

[0101] Regarding the calculation method for generating the EMC protection window, when the phase-locked loop is not locked, the system can know the approximate position of the frame header by counting. The calculated frame header start time can be moved forward to the time of the set time period, and the frame header detection is enabled at this time, such as Figure 6 , enabling it during the EMC window period helps improve the anti-interference capability against EMC.

[0102] The structure of the frame header detection device can be as follows Figure 7 The frame header detection device further includes a low-precision clock module, the accuracy of which is lower than the accuracy of the phase-locked loop locked clock; and has the following connection relationship:

[0103] The first input terminal of the EMC protection window module is connected to the output terminal of the data selector;

[0104] The second input terminal of the EMC protection window module is connected to the clock output terminal of the phase-locked loop;

[0105] The third input terminal of the EMC protection window module is connected to the low-precision clock module;

[0106] The output end of the EMC protection window module is connected to the enable end of the counter synchronization detection module and the enable end of the specific code pattern detection circuit.

[0107] The EMC protection window module is used to: determine the EMC protection window based on the low-precision clock module when the phase-locked loop is not locked; determine the EMC protection window based on the clock output signal of the phase-locked loop when the phase-locked loop is locked; and send an enable signal at the output of the EMC protection window module during the EMC protection window period.

[0108] As a special case, the size of the EMC protection window can be adjusted according to the current state of the frame header detection circuit: when a counter is used for frame header detection, since only a low-precision clock can be used in the EMC protection window, the window size can be appropriately relaxed; when a specific pattern detection circuit is used, the phase-locked loop has been locked and the clock frequency is accurate enough, a more stringent window size can be used, such as Figure 8 During the phase-locked loop locking process, the signal PLL CLOCK accuracy becomes higher and higher, and the EMC protection window can become narrower and narrower, which is conducive to enhancing the EMC capability and can adapt even to short preamble codes as frame headers.

[0109] A further special case is that when using counting for frame header detection, the use of EMC protection window can be directly abandoned, such as Figure 9 , compared to Figure 7 The output terminal of the EMC protection window module is removed and connected to the enable terminal of the counter synchronization detection module. The beneficial effect of this embodiment is that compared with Figure 7 , which avoids missing the frame header detection due to the EMC protection window being too small.

[0110] In summary, this application proposes a frame header detection method and device. At the beginning of link establishment, frame header detection is performed by counting rising and falling edges of data. This detection information is then used as a reference clock to provide to a local phase-locked loop (PLL). Once the PLL is locked, it provides a precise high-frequency clock for preamble detection, fully utilizing the fixed pattern information of the preamble to improve EMC capabilities.

[0111] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art may understand and implement the present invention without inventive effort.

[0112] The above are merely preferred embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A frame header detection method, characterized in that: Applicable to a frame header detection device, the frame header detection device includes a counter synchronization detection module, a specific code pattern detection circuit and a phase-locked loop; The counter synchronization detection module includes a counter; The frame header detection method comprises: When the phase-locked loop is not locked, the counter synchronization detection module performs frame header detection on the received frame signal through the counter and generates a first reference clock of the phase-locked loop; Before the phase-locked loop is locked, the phase-locked loop is locked according to the first reference clock; When the phase-locked loop is locked, the specific code pattern detection circuit performs frame header detection on the received frame signal and generates a second reference clock for the phase-locked loop.

2. The frame header detection method according to claim 1, wherein: The counter synchronization detection module performs frame header detection on the received frame signal through the counter and generates the first reference clock of the phase-locked loop, including: Whenever the counter detects a frame header, it generates a pulse signal as the first reference clock, and the frequency of the first reference clock is the frequency of the frame.

3. The frame header detection method according to claim 1, wherein: The step of the counter synchronization detection module performing frame header detection on the received frame signal through the counter includes: Count the rising edges of the received frame signal, and determine that the frame header is detected when the count reaches a set value; Or count the falling edges of the received frame signal, and determine that the frame header is detected when the count reaches a set value; Or the rising and falling edges of the received frame signal are counted, and when the count reaches a set value, it is determined that the frame header is detected.

4. The frame header detection method according to claim 1, wherein: The frame header detection device also includes an EMC protection window module; The frame header detection method further includes: the EMC protection window module generating an EMC protection window; When the phase-locked loop is not locked, the counter synchronization detection module performs frame header detection on the received signal through the counter within the time period of the EMC protection window; When the phase-locked loop is locked, the specific code pattern detection circuit performs frame header detection on the received signal within the time period of the EMC protection window.

5. The frame header detection method according to claim 4, wherein: The width of the EMC protection window when the phase-locked loop is unlocked is greater than the width of the EMC protection window when the phase-locked loop is locked.

6. The frame header detection method according to claim 1, wherein: The step of the specific code pattern detection circuit performing frame header detection on the received frame signal includes: generating a plurality of clocks with the same frequency but different phases according to the phase-locked loop, and sampling the received frame signal according to the plurality of clocks with the same frequency but different phases; The data obtained by sampling each clock is compared with a specific code pattern, and whether the frame header is detected is determined based on the comparison result.

7. The frame header detection method according to claim 6, wherein: The steps of determining whether a frame header is detected according to the comparison result include: When the number of clocks in which data is consistent with a specific pattern reaches a set number, it is determined that the frame header is detected; the set number is greater than or equal to 1.

8. A frame header detection device, characterized in that: It includes a counter synchronization detection module, a specific code detection circuit, a data selector and a phase-locked loop; the counter synchronization detection module includes a counter; The input end of the counter synchronization detection module and the input end of the specific code pattern detection circuit are used to receive the frame signal; The output end of the counter synchronization detection module is connected to the first input end of the data selector; The output end of the specific code pattern detection circuit is connected to the second input end of the data selector; The output end of the data selector is connected to the input end of the phase-locked loop; The clock output end of the phase-locked loop is connected to the clock input end of the specific code pattern detection circuit; The locking state output terminal of the phase-locked loop is connected to the control terminal of the data selector; The counter synchronization detection module is used to perform frame header detection on the received frame signal through the counter, and generate a first reference clock of the phase-locked loop and transmit it to the first input end of the data selector; The specific code pattern detection circuit is used to perform frame header detection on the received frame signal and generate a second reference clock to transmit to the second input end of the data selector; The phase-locked loop is configured to be locked according to the first reference clock; In the case of unlocked state, the lock state output terminal is a first signal; in the case of locked state, the lock state output terminal is a second signal, and a third reference clock is provided to the specific code pattern detection circuit at the clock output terminal of the phase-locked loop; The data selector is used to output the signal of the first input terminal of the data selector when the control terminal is the first signal; When the control terminal is a second signal, the signal of the second input terminal of the data selector is output.

9. The frame header detection device according to claim 8, wherein: The frame header detection device further includes an EMC protection window module and a low-precision clock module, wherein the accuracy of the low-precision clock module is lower than the accuracy of the phase-locked loop locked clock; The first input end of the EMC protection window module is connected to the output end of the data selector; The second input end of the EMC protection window module is connected to the clock output end of the phase-locked loop; The third input terminal of the EMC protection window module is connected to the low-precision clock module; The output end of the EMC protection window module is connected to the enable end of the counter synchronization detection module and the enable end of the specific code pattern detection circuit; The EMC protection window module is used for: When the phase-locked loop is not locked, the EMC protection window is determined according to the low-precision clock module; when the phase-locked loop is locked, the EMC protection window is determined according to the clock output terminal signal of the phase-locked loop; During the EMC protection window period, an enable signal is sent at the output end of the EMC protection window module.

10. The frame header detection device according to claim 8, wherein: The frame header detection device also includes an EMC protection window module; The first input end of the EMC protection window module is connected to the output end of the data selector; The second input end of the EMC protection window module is connected to the clock output end of the phase-locked loop; The output end of the EMC protection window module is connected to the enable end of the specific code pattern detection circuit; The EMC protection window module is used to send an enable signal at the output end of the EMC protection window module within the EMC protection window time period.

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