Interrupt control method and device based on PCIe and computer equipment

Abstract

The invention relates to the technical field of network communication, and discloses a PCIe-based interrupt control method and device and computer equipment, which are applied to an on-chip system with a PCIe controller in an EP mode, and a target address corresponding to a corresponding RC component is allocated to an address space corresponding to the on-chip system with the PCIe controller in the EP mode. The target address is configured to represent generation of an interrupt request when data is written in. The method comprises the steps of responding to monitoring of a data writing event of the target address; and when the data writing event of the target address is monitored, determining that an interrupt request issued by the RC component is received and triggering an interrupt processing flow. Compared with an EP equipment polling mode, the receiving timeliness of the interrupt instruction is improved, and the occupation of processor resources of the EP equipment and the complexity of software implementation are reduced.

Description

Technical Field

[0001] The present invention relates to the field of network communication technology, and in particular to a PCIe-based interrupt control method, device, computer equipment, storage medium, and computer program product. Background Art

[0002] In the PCIe communication standard, an EP (End Point) can send interrupts to an RC component (Root Complex). However, the standard PCIe protocol does not support a mechanism for the RC component to send interrupts to an EP device. However, if the EP device is a SoC (System on a chip) with a PCIe controller and the SoC with a PCIe controller is set to EP mode, it may need to receive interrupts from the RC component.

[0003] In the related art, this type of receiving interrupt instructions from the RC component usually relies on the polling mechanism of the EP device, that is, the EP device sets the software to periodically check whether the RC component has information or events that need to be processed by it. However, this method requires the EP device to perform frequent checking operations. The entire process is inefficient, occupies the processor resources of the EP device, and also increases the complexity of software implementation. Summary of the Invention

[0004] In view of this, an embodiment of the present invention provides a PCIe-based interrupt control method, apparatus and computer device to solve the technical problems that the existing method of receiving interrupt instructions from RC is inefficient, occupies processor resources of EP devices and has a complex implementation process.

[0005] According to the first aspect, an embodiment of the present invention provides a PCIe-based interrupt control method, which is applied to a system on chip with a PCIe controller in EP mode, wherein the address space corresponding to the system on chip with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component, and the target address is configured to represent an interrupt request when data is written to it; the method includes: responding to monitoring of a data write event to the target address; when monitoring a data write event to the target address, determining that an interrupt request issued by the RC component is received and triggering an interrupt processing process.

[0006] Optionally, the method further includes: upon determining that an interrupt request sent by the RC component is received, activating a preset shared peripheral interrupt; and sending the interrupt request to an interrupt controller of the system on chip via the preset shared peripheral interrupt to respond to an interrupt processing operation.

[0007] Optionally, the method further comprises: mapping the selected target address to a corresponding RC component through a base address register mechanism.

[0008] Optionally, the target address is a predetermined address on the AXI bus.

[0009] According to the second aspect, an embodiment of the present invention provides a PCIe-based interrupt control device applied to a system on chip with a PCIe controller in EP mode, wherein the address space corresponding to the system on chip with a PCIe controller in EP mode is allocated with a target address corresponding to the corresponding RC component, and the target address is configured to represent an interrupt request when data is written to it; the device includes: a monitoring module for responding to monitoring of data write events at the target address; a triggering module for determining that an interrupt request issued by the RC component is received and triggering an interrupt processing process when monitoring data write events at the target address.

[0010] Optionally, the device also includes: an activation module, which is used to activate the preset shared peripheral interrupt when it is determined that an interrupt request sent by the RC component is received; and a sending module, which is used to send the interrupt request to the interrupt controller of the on-chip system through the preset shared peripheral interrupt to respond to the interrupt processing operation.

[0011] Optionally, the apparatus further comprises: a mapping module, configured to map the selected target address to a corresponding RC component through a base address register mechanism.

[0012] According to a third aspect, an embodiment of the present invention provides a computer device comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the PCIe-based interrupt control method described in the first aspect or any optional embodiment of the first aspect by executing the computer instructions.

[0013] According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the PCIe-based interrupt control method described in the first aspect or any optional embodiment of the first aspect.

[0014] According to a fifth aspect, an embodiment of the present invention provides a computer program product, comprising computer instructions, where the computer instructions are used to enable a computer to execute the PCIe-based interrupt control method described in the first aspect or any optional implementation manner of the first aspect.

[0015] The PCIe-based interrupt control method provided by an embodiment of the present invention is applied to a system-on-chip (SoC) with a PCIe controller in EP mode. The address space corresponding to the SoC with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component. The target address is configured to indicate the generation of an interrupt request when data is written to the target address. The method responds to monitoring of data write events at the target address. When monitoring data write events at the target address, the method determines whether an interrupt request issued by the RC component has been received and triggers an interrupt processing flow. By monitoring whether there is a data write event at the target address, the method determines whether an interrupt request issued by the RC component has been received to trigger the corresponding interrupt processing flow. Compared with the polling method through the EP device in the related art, the method improves the timeliness of receiving interrupt instructions and reduces the occupation of processor resources of the EP device and the complexity of software implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a flow chart of a PCIe-based interrupt control method according to an embodiment of the present invention;

[0018] Figure 2 1 is a block diagram of a PCIe-based interrupt control device according to an embodiment of the present invention;

[0019] Figure 3 It is a schematic diagram of the hardware structure of the computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0021] According to an embodiment of the present invention, an embodiment of a PCIe-based interrupt control method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0022] In the PCIe (PCI Express) communications standard, an endpoint device (EP) can send interrupts to the root complex (RC), including legacy interrupts, message-signaled interrupts (MSI), and extended message-signaled interrupts (MSI-X). An interrupt is a request from the processor to interrupt the currently executing code (where permitted) to handle the event promptly. If the request is accepted, the processor suspends its current activity, saves its state, and executes a function called an interrupt handler or interrupt service routine (ISR) to handle the event. This interruption is usually temporary, allowing the software to resume normal activities after the interrupt handler is completed; in the PCIe system, RC connects the CPU and memory subsystem to the PCI Express switching network composed of one or more PCIe or PCI devices. In the embodiment of the present application, the RC also refers to the software system and hardware system on the entire RC side; EP is a device other than RC and switch, which is the requester or completer of PCIe transactions and is a peripheral device such as Ethernet, USB or graphics device. EP initiates transactions as a requester or responds to transactions as a completer. In the embodiment of the present application, EP also refers to the software system and hardware system on the entire EP side.

[0023] The standard PCIe protocol does not support a mechanism for RC components to send interrupts to EP devices. However, if the EP device is a SoC (System on a Chip) with a PCIe controller and is set to EP mode, it may need to receive interrupts from the RC component. An SoC is an integrated circuit that integrates most or all components of a computer or other electronic system. These components generally include an integrated central processing unit (CPU), memory interfaces, input / output devices and interfaces, auxiliary storage interfaces, and other components such as a radio frequency modem and graphics processing unit (GPU), all on a single substrate or microchip. SoCs can include digital circuits, analog circuits, and mixed-signal circuits. Heterogeneous SoCs are system chips that integrate multiple different types of processing units, including CPUs, GPUs, NPUs (Neural Processing Units), DSPs (Digital Signal Processors), and ISPs (Image Signal Processors). Heterogeneous SoCs can handle different types of tasks simultaneously, for example, performing general computing tasks while efficiently processing images, signals, or artificial intelligence inference tasks within a single chip. This architecture optimizes performance and energy efficiency by combining different types of specialized processing units, making it suitable for complex application scenarios that require multi-tasking, such as artificial intelligence, autonomous driving, and high-performance computing.

[0024] In the related art, receiving interrupt instructions from the RC typically relies on a polling mechanism on the EP device. This involves the EP device configuring software to periodically check whether the RC has any information or events requiring its processing. However, this approach requires the EP device to frequently perform these checks, resulting in low efficiency, consuming the EP device's processor resources, and increasing the complexity of software implementation. Polling, in which a client program synchronously samples the status of an external device, is commonly used for input / output (I / O) and is also known as polled I / O or software-driven I / O.

[0025] For scenarios where RC needs to send interrupt requests to EP, such as in the field of AI reasoning and training, the system-on-chip with a PCIe controller in EP mode in the corresponding field usually needs to process a large amount of data and frequently interact with the main controller (RC). When the system-on-chip with a PCIe controller in EP mode completes the processing of a batch of data, it quickly transmits the data processing results back to RC through an interrupt to obtain the next batch of data. However, RC cannot immediately send an interrupt to the system-on-chip with a PCIe controller in EP mode to inform it to start processing new tasks or data, thereby affecting the overall training efficiency and response speed; or in a high-performance computing environment, multiple computing tasks need to be efficiently allocated and coordinated among different processing units. RC also needs to issue tasks by interrupting the system-on-chip with a PCIe controller in EP mode in the corresponding scenario when necessary. Distribution or state synchronization signals to minimize latency and ensure tighter task coordination and faster execution speed; or for real-time image processing applications, such as video surveillance analysis or autonomous driving systems, fast data processing and decision feedback are also crucial, so RC needs to be able to immediately notify the on-chip system with a PCIe controller in EP mode through an interrupt when a key event or data change is detected, so that it can immediately process the new image data or adjust the processing strategy to improve the overall real-time responsiveness of the system; or in a distributed storage system, data consistency and access efficiency are the key to system design. After the data is updated, if RC can immediately notify the on-chip system with a PCIe controller in EP mode in the corresponding scenario to synchronize data or update the cache, the data processing process can be optimized, which can reduce data access latency and improve the overall performance of the system.

[0026] In this embodiment, a PCIe-based interrupt control method is provided, which is applied to a system-on-chip with a PCIe controller in EP mode, wherein the address space corresponding to the system-on-chip with a PCIe controller in EP mode is allocated with a target address corresponding to the corresponding RC component, and the target address is configured to represent the generation of an interrupt request when data is written. In the embodiment of the present application, the system-on-chip with a PCIe controller and its corresponding RC component can be connected for communication via an AXI (Advanced eXtensible Interface) bus, and the target address is a predetermined address on the AXI bus; the address space corresponding to the system-on-chip with a PCIe controller in EP mode is allocated to its corresponding RC component, and the target address information is mapped to the corresponding RC component, so that the corresponding RC component performs a data write operation to the target address when an interrupt request needs to be sent. Specifically, a write instruction can be sent to perform a specific data write operation; such as Figure 1 As shown, the process includes the following steps:

[0027] Step S101, responding to monitoring of a data write event to a target address; illustratively, a method of monitoring a data write event to a target address may be to compare the address information corresponding to a write command received from an AXI bus with the address information of the target address, and when the received address information is the same as the address information of the target address, it indicates that a data write event to the target address has been monitored.

[0028] Step S102 : When monitoring a data write event at a target address, it is determined that an interrupt request sent by the RC component is received and an interrupt processing flow is triggered.

[0029] For example, by mapping the target address to the corresponding RC component, the corresponding RC component can perform a data write operation at the target address. When a data write event to the target address is monitored, it can be determined that the corresponding RC component has issued an interrupt request. After confirming that the RC component has issued an interrupt request, the corresponding interrupt processing flow is triggered, such as pausing the current processing process to switch to the interrupt processing process or sending the interrupt request instruction to the interrupt controller to perform interrupt processing operations such as priority determination.

[0030] The PCIe-based interrupt control method provided by an embodiment of the present invention is applied to a system-on-chip (SoC) with a PCIe controller in EP mode. The address space corresponding to the SoC with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component. The target address is configured to indicate the generation of an interrupt request when data is written to the target address. The method responds to monitoring of data write events at the target address. When monitoring data write events at the target address, the method determines whether an interrupt request issued by the RC component has been received and triggers an interrupt processing flow. By monitoring whether there is a data write event at the target address, the method determines whether an interrupt request issued by the RC component has been received to trigger the corresponding interrupt processing flow. Compared with the polling method through the EP device in the related art, the method improves the timeliness of receiving interrupt instructions and reduces the occupation of processor resources of the EP device and the complexity of software implementation.

[0031] As an optional implementation of an embodiment of the present invention, the method further includes: when it is determined that an interrupt request sent by the RC component is received, activating a preset shared peripheral interrupt; and sending the interrupt request to the interrupt controller of the on-chip system through the preset shared peripheral interrupt to respond to the interrupt processing operation.

[0032] For example, a shared peripheral interrupt (SPI) can be pre-configured for the interrupt controller during the system initialization phase through software configuration or other means, so that the interrupt controller can obtain interrupt responses first, avoid interference with the interrupt request from other devices or tasks, and enable the interrupt controller to handle SPI-related events in a timely manner. In the embodiment of the present application, the interrupt controller can be a general interrupt controller (GIC), which receives interrupt request signals from various peripherals and external devices inside the chip through a hardware module integrated in the ARM chip. Then, according to pre-set priority and configuration information, the interrupt request can be reasonably distributed to the processor for processing, ensuring that the system can respond to and handle various interrupt events in a timely manner.

[0033] As an optional implementation of the embodiment of the present invention, the method further includes: mapping the selected target address to the corresponding RC component through a base address register mechanism.

[0034] For example, a base address register (BAR) is a register in a computer system used to store specific address information. The BAR is an important mechanism for configuring and managing device address space and is part of the device configuration space. It can be used to specify the base address of the memory or I / O space of a PCIe device. The base address register mechanism can be used to associate the target address with the RC, establishing a corresponding relationship between the target address and the RC. When the RC needs to send an interrupt to the EP, it directly writes to the BAR address, enabling correct data transmission and interaction between the two. Specifically, when an interrupt needs to be sent to a system-on-chip (SoC) with a PCIe controller in EP mode, the RC can write specific interrupt-related information (such as the interrupt type and interrupt vector) to the BAR address. The SoC with a PCIe controller in EP mode can receive this information and trigger the corresponding interrupt handler. Because the mapping relationship between the listening address and the RC has been established, writing to the BAR address indicates that an interrupt event has occurred to the SoC with a PCIe controller in EP mode. The SoC with a PCIe controller in EP mode can then perform the corresponding interrupt processing based on the received interrupt event information, thereby implementing an interrupt-based communication mechanism between the RC and EP.

[0035] As a specific embodiment of this application, any SoC is configured with a PCIe controller operating in EP mode. It is configured to listen to address 0x1000 connected to the AXI bus, or exposed as a register for software configuration. This address is mapped to the RC via the BAR. When the RC's application needs to notify the SoC of a situation, the RC triggers an interrupt by writing to address 0x1000. This action triggers the hardware logic, activating the preset SPI, and the resulting interrupt is captured and processed by the SoC's interrupt controller.

[0036] The PCIe-based interrupt control method provided in the embodiments of the present application can realize an efficient two-way interrupt communication mechanism, significantly improving the response speed and processing efficiency of SoC-based systems in complex data processing and real-time tasks, while reducing the waste of CPU resources caused by the polling mechanism and simplifying the implementation complexity at the software level. Specifically, in an autonomous driving vehicle system, the processing unit needs to receive and process a large amount of data collected from various sensors (such as cameras and radars) in real time. And it is likely to use multiple SoCs to process. These SoCs are cascaded via PCIe, which is equivalent to some SoCs acting as RCs and some SoCs acting as EPs. The SoC in EP mode is used for data processing and then transmits the data to the SoC in RC mode. The data processed by the SoC in EP mode is crucial for achieving environmental perception, decision making, and behavior control. The interrupt control method from the RC side to the EP side in the embodiments of the present application is integrated into the SoC in EP mode of autonomous driving. When the SoC system in RC mode receives emergency information (such as sudden road conditions or control instruction updates), it can immediately notify the SoC in EP mode through a PCIe interrupt. The SoC in RC mode does not need to wait for the polling cycle, which can ensure that the autonomous driving system can respond to external changes as quickly as possible and improve driving safety. This immediate response mechanism significantly improves the reaction time and reliability of the autonomous driving system and reduces the safety risks that may be caused by delayed responses. Similarly, in the processing scenario where the AI chip server is dedicated to accelerating the training and reasoning of machine learning models and requires a large amount of computing resources and fast data processing, the PCIe controller of the AI chip is configured in EP mode and integrates the interrupt control method from the RC side to the EP side in the embodiment of the present application, so that the main controller (i.e., RC) of the data center can directly send an interrupt signal to the AI chip through PCIe to trigger data processing or model update tasks, so that the AI chip can respond to interrupts immediately, significantly reducing the delay and waste of CPU resources caused by polling requirements. The interrupt mechanism from the RC side to the EP side can ensure the immediate processing of critical tasks and improve system stability and reliability. This configuration makes the AI chip server more efficient in AI task processing and is particularly suitable for scenarios that require rapid decision-making and instant analysis.

[0037] This embodiment also provides a PCIe-based interrupt control device for implementing the above-mentioned embodiments and preferred implementations. Details already described will not be repeated. The term "module" used below may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0038] This embodiment provides a PCIe-based interrupt control device, which is applied to a system on chip with a PCIe controller in EP mode. The address space corresponding to the system on chip with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component. The target address is configured to indicate the generation of an interrupt request when data is written to it; Figure 2 Shown, including:

[0039] A monitoring module 201 is configured to monitor a data write event to a target address;

[0040] The trigger module 202 is used to monitor the data writing event of the target address, determine that an interrupt request sent by the RC component is received and trigger the interrupt processing process. Detailed descriptions can be found in the corresponding descriptions of the above method embodiments, which will not be repeated here.

[0041] The PCIe-based interrupt control device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0042] The PCIe-based interrupt control device provided in this embodiment is applied to a system-on-chip (SoC) with a PCIe controller in EP mode. The address space corresponding to the SoC with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component. The target address is configured to indicate the generation of an interrupt request when data is written to the target address. The device monitors data write events at the target address. When monitoring data write events at the target address, the device determines that an interrupt request issued by the RC component has been received and triggers an interrupt processing flow. By monitoring whether there are data write events at the target address, the device determines whether an interrupt request issued by the RC component has been received to trigger the corresponding interrupt processing flow. Compared to the polling method used by the EP device in the related art, this device improves the timeliness of receiving interrupt instructions and reduces the occupancy of the EP device's processor resources and the complexity of software implementation.

[0043] As an optional implementation of an embodiment of the present invention, the device also includes: an activation module, which is used to activate the preset shared peripheral interrupt when it is determined that an interrupt request sent by the RC component is received; and a sending module, which is used to send the interrupt request to the interrupt controller of the on-chip system through the preset shared peripheral interrupt to respond to the interrupt processing operation.

[0044] As an optional implementation of the embodiment of the present invention, the apparatus further includes: a mapping module, configured to map the selected target address to the corresponding RC component through a base address register mechanism.

[0045] As an optional implementation of the embodiment of the present invention, the target address is a predetermined address on the AXI bus.

[0046] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0047] The PCIe-based interrupt control device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0048] The embodiment of the present invention also provides a computer device having the above Figure 2 The PCIe-based interrupt control device is shown.

[0049] See also Figure 3 , Figure 3 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 3 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 3 A processor 10 is taken as an example.

[0050] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0051] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0052] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0053] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0054] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 3 The bus connection is taken as an example.

[0055] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0056] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0057] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0058] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A PCIe-based interrupt control method, characterized in that: Applied to a system on chip with a PCIe controller in EP mode, a target address corresponding to a corresponding RC component is allocated in an address space corresponding to the system on chip with a PCIe controller in EP mode, and the target address is configured to indicate the generation of an interrupt request when data is written to the target address; the method includes: Respond to the monitoring of data write events at the target address; When monitoring the data write event of the target address, it is determined that the interrupt request sent by the RC component is received and the interrupt processing flow is triggered.

2. The method according to claim 1, characterized in that The method further comprises: When it is confirmed that an interrupt request sent by the RC component is received, the preset shared peripheral interrupt is activated; The interrupt request is sent to the interrupt controller of the system on chip through the preset shared peripheral interrupt to respond to the interrupt processing operation.

3. The method according to claim 1, characterized in that The method further includes mapping the selected target address to a corresponding RC component through a base address register mechanism.

4. The method according to claim 1, wherein The target address is a predetermined address on the AXI bus.

5. A PCIe-based interrupt control device, characterized in that: Applicable to a system on chip with a PCIe controller in EP mode, wherein the address space corresponding to the system on chip with a PCIe controller in EP mode is allocated with a target address corresponding to a corresponding RC component, and the target address is configured to indicate the generation of an interrupt request when data is written to the target address; the device comprises: A monitoring module, used for responding to the monitoring of data writing events at the target address; The trigger module is used to monitor the data write event of the target address, determine whether the interrupt request sent by the RC component is received and trigger the interrupt processing process.

6. The device according to claim 5, characterized in that The device further comprises: The activation module is used to activate the preset shared peripheral interrupt when it is determined that an interrupt request sent by the RC component is received; The sending module is used to send the interrupt request to the interrupt controller of the system on chip through the preset shared peripheral interrupt to respond to the interrupt processing operation.

7. The device according to claim 5, characterized in that The device further comprises: The mapping module is used to map the selected target address to the corresponding RC component through the base address register mechanism.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the PCIe-based interrupt control method according to any one of claims 1 to 4 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the PCIe-based interrupt control method according to any one of claims 1 to 4.

10. A computer program product, characterized in that The computer program product comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the PCIe-based interrupt control method according to any one of claims 1 to 4.

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