Imaging device and electronic apparatus

Abstract

The invention relates to an imaging device and an electronic apparatus. The invention provides an imaging device which can easily perform pooling processing. In the camera device, a pixel area comprises a plurality of pooling modules and an output circuit, each pooling module comprises a pooling circuit and a comparison module, each pooling circuit comprises a plurality of pixels and an operational circuit, and each comparison module comprises a plurality of comparison circuits and a decision circuit. Pixels can obtain a first signal through photoelectric conversion, and multiply the first signal at any multiplying power to generate a second signal. The pooling circuit generates third signals by adding the plurality of second signals via the arithmetic circuit, the comparison module outputs the maximum third signal to the decision circuit by comparing the plurality of third signals, and the decision circuit generates a fourth signal by binarizing the maximum third signal by determining the maximum third signal. And the pooling module performs pooling processing according to the number of the pixels and outputs data subjected to pooling processing.

Description

[0001] This application is a divisional application of application number 202210606282.4, filed on June 5, 2018, entitled “Camera Device and Electronic Equipment.” This prior application is a divisional application of application number PCT / IB2018 / 053999, filed on June 5, 2018, which entered the Chinese national phase on December 12, 2019, and has the national application number 201880039316.8 and the title “Camera Device and Electronic Equipment.” Technical Field

[0002] One embodiment of the present invention relates to an imaging device and an electronic device.

[0003] Note that one embodiment of the present invention is not limited to the aforementioned technical field. The technical field of one embodiment of the invention disclosed in this specification and other aspects relates to an object, method, or manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0004] In this specification and other documents, a semiconductor device refers to an element, circuit, or device that operates by utilizing semiconductor properties. For example, semiconductor elements such as transistors and diodes are semiconductor devices. For another example, a circuit containing a semiconductor element is a semiconductor device. For another example, a device including a circuit containing a semiconductor element is a semiconductor device. Background Art

[0005] With the development of information technologies such as IoT (Internet of Things) and AI (Artificial Intelligence), the amount of data being processed is increasing. In order to utilize information technologies such as IoT and AI in electronic devices, it is necessary to manage large amounts of data in a distributed manner.

[0006] Improving the image recognition processing speed using AI is gaining attention in image processing systems for in-vehicle electronic devices and image processing systems for monitoring moving objects. For example, Patent Document 1 discloses a technique for adding a computing function to an imaging device.

[0007] [Prior technical literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2016-123087 Summary of the Invention

[0010] Technical problem to be solved by the invention

[0011] As technology advances, it has become easier to capture high-quality images in imaging devices that include solid-state imaging elements such as CMOS image sensors. However, there is a demand for next-generation imaging devices to incorporate even more intelligent functions.

[0012] Advanced image processing is required to identify objects from image data. This advanced image processing utilizes various image analysis processes, such as filtering and comparison operations. The more pixels processed, the more computational effort required, and this computational effort increases processing time. For example, in automotive image processing systems, increased processing time can impact safety. Furthermore, image processing systems also experience increased power consumption as computational effort increases.

[0013] In view of the above-mentioned problems, one object of one embodiment of the present invention is to provide an imaging device having a novel structure. Another object of one embodiment of the present invention is to provide an imaging device having a pooling processing function of a neural network. Another object of one embodiment of the present invention is to provide an imaging device having a novel structure that can reduce the amount of computation and shorten processing time. Another object of one embodiment of the present invention is to provide an imaging device having a novel structure that can reduce power consumption.

[0014] Note that the inclusion of these objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the present invention does not necessarily achieve all of the aforementioned objectives. Objectives other than the aforementioned objectives may be apparent from, and may be extracted from, the description of the specification, drawings, claims, and the like.

[0015] Note that the purpose of one embodiment of the present invention is not limited to the purpose described above. The purpose described above does not preclude the existence of other purposes. In addition, other purposes may be purposes not mentioned above but will be described below. A person skilled in the art can derive and appropriately extract such purposes from the description, drawings, etc. of the specification. In addition, one embodiment of the present invention achieves at least one of the above-mentioned and / or other purposes.

[0016] Means of solving technical problems

[0017] One embodiment of the present invention is a camera device including a pixel area and a first circuit, wherein the pixel area includes a pooling module and an output circuit, the pooling module includes multiple pooling circuits and a comparison module, the pooling circuit includes multiple pixels and an operation circuit, the comparison module includes multiple comparison circuits and a determination circuit, the pixel has a function of obtaining a first signal through photoelectric conversion, the pixel has a function of multiplying the first signal at an arbitrary magnification to generate a second signal, the pooling circuit has a function of adding multiple second signals through an operation circuit to generate a third signal, the comparison module has a function of selecting the largest third signal by comparing multiple third signals and outputting it to the determination circuit, the determination circuit has a function of determining the largest third signal and binarizing it to generate a fourth signal, the first circuit controls the timing of outputting the fourth signal to the output circuit, the pooling module performs pooling processing according to the number of pixels, and the pooling module outputs the fourth signal generated by the pooling processing.

[0018] In the imaging device of the above structure, it is preferred that the imaging device further includes a second circuit, a third circuit, a first wiring, a second wiring, and a third wiring, wherein the pixel includes a first output terminal, the arithmetic circuit includes a first transistor, a second transistor, and a third transistor, the second circuit is electrically connected to a plurality of pixels extending in a row direction via the first wiring, the third circuit is electrically connected to a plurality of pixels extending in a column direction via the second wiring, the third wiring is electrically connected to one of the source and the drain of the first transistor, one of the source and the drain of the second transistor, and one of the source and the drain of the third transistor, and the gate of the first transistor is electrically connected to the other of the source and the drain of the first transistor and the gate of the second transistor. , the gate of the third transistor and the first output terminal of the pixel included in the pooling circuit, the third circuit has a function of outputting a selection signal to the second wiring, the second circuit has a function of setting the pixel to an arbitrary magnification through the first wiring, the first transistor has the same channel length as the second transistor and the third transistor, the second transistor has a function of outputting a third signal that adds multiple second signals by having the same width as the channel width of the first transistor, and the third transistor has a length obtained by dividing the channel width of the first transistor by the number of pixels included in the pooling circuit, thereby having a function of outputting a fifth signal of a size obtained by dividing the size of the third signal by the number of pixels.

[0019] In the camera device of the above structure, preferably, the comparison module includes a first comparison circuit, a second comparison circuit and a current mirror circuit, the first comparison circuit includes fourth to ninth transistors, a first input terminal, a second input terminal, a second output terminal and a fourth wiring, the second output terminal of the first comparison circuit is electrically connected to the first input terminal of the second comparison circuit through the current mirror circuit, the first input terminal is electrically connected to one of the source and drain of the fifth transistor, one of the source and drain of the seventh transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor, the second input terminal is electrically connected to one of the source and drain of the eighth transistor, one of the source and drain of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor and the gate of the ninth transistor, the second output terminal is electrically connected to one of the source and drain of the fourth transistor and one of the source and drain of the ninth transistor, the fourth to ninth transistors have the same channel length, and the channel width of the fourth transistor is preferably the same as the channel width of the fifth transistor. The channel width of the sixth transistor is preferably twice that of the fifth transistor. The fourth to sixth transistors form a first current mirror circuit. The channel width of the ninth transistor is preferably the same as that of the eighth transistor. The channel width of the seventh transistor is preferably twice that of the eighth transistor. The seventh to ninth transistors form a second current mirror circuit. The sixth signal is supplied to a first input terminal of the first comparator circuit, the seventh signal is supplied to a second input terminal of the first comparator circuit, and the larger of the sixth and seventh signals is output as an eighth signal at a second output terminal of the first comparator circuit. The eighth signal is supplied to a first input terminal of the second comparator circuit, the ninth signal is supplied to a second input terminal of the second comparator circuit, and the ninth signal is supplied to a second output terminal of the second comparator circuit. The larger of the eighth and ninth signals is output to the determination circuit as a tenth signal. The determination circuit has a function of determining the tenth signal, binarizing it, and generating a fourth signal. The first circuit has a function of controlling the timing of outputting the fourth signal to the output circuit.

[0020] In the imaging device having the above configuration, it is preferable that the plurality of pixels are arranged in a matrix with light-shielded areas between adjacent pixels.

[0021] In the imaging device of the above structure, preferably, the pixel further includes a photoelectric conversion element, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a first capacitor, one electrode of the photoelectric conversion element is electrically connected to one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor, one of the source and the drain of the eleventh transistor is electrically connected to the gate of the twelfth transistor, the gate of the twelfth transistor is electrically connected to one electrode of the first capacitor, one of the source and the drain of the twelfth transistor is electrically connected to the first output terminal, the other electrode of the first capacitor is electrically connected to one of the source and the drain of the thirteenth transistor, the other of the source and the drain of the thirteenth transistor is electrically connected to the first wiring, the gate of the thirteenth transistor is electrically connected to the second wiring, and the tenth transistor and the twelfth transistor contain metal oxide in the channel formation region.

[0022] In the imaging device having the above structure, the metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0023] In the imaging device having the above configuration, it is preferable that the photoelectric conversion element contains selenium or a compound containing selenium.

[0024] Effects of the Invention

[0025] In view of the above-mentioned problems, one embodiment of the present invention can provide an imaging device with a novel structure. Furthermore, one embodiment of the present invention can provide an imaging device with a pooling processing function of a neural network. Furthermore, one embodiment of the present invention can provide an imaging device with a novel structure that can reduce the amount of computation and shorten processing time. Furthermore, one object of one embodiment of the present invention is to provide an imaging device with a novel structure that can reduce power consumption.

[0026] Note that the effects of one embodiment of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. In addition, other effects are effects not mentioned above but will be described in the following description. A person skilled in the art can derive and appropriately extract the effects not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the effects described above and / or other effects. Therefore, depending on the circumstances, one embodiment of the present invention may not include the effects listed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] [ Figure 1 ]A block diagram illustrating a camera device.

[0028] [ Figure 2 ]A block diagram illustrating a camera device.

[0029] [ Figure 3 (A) A block diagram illustrating an imaging device. (B) A circuit diagram illustrating an imaging device.

[0030] [ Figure 4 ]A circuit diagram illustrating a pixel.

[0031] [ Figure 5 (A) A block diagram illustrating an imaging device. (B) A timing diagram illustrating the operation of the imaging device.

[0032] [ Figure 6 ]A block diagram illustrating a camera device.

[0033] [ Figure 7 ]A circuit diagram illustrating a pixel.

[0034] [ Figure 8 ]A diagram illustrating the structure of pixels in an imaging device.

[0035] [ Figure 9 ]A diagram illustrating the structure of pixels in an imaging device.

[0036] [ Figure 10 ]A diagram illustrating the structure of pixels in an imaging device.

[0037] [ Figure 11 (A) A diagram illustrating the structure of a pixel of an imaging device. (B) A cross-sectional view showing the structure of the imaging device.

[0038] [ Figure 12 ]A diagram illustrating the structure of pixels in an imaging device.

[0039] [ Figure 13 ]A diagram illustrating the structure of pixels in an imaging device.

[0040] [ Figure 14 ] A three-dimensional diagram of the package and module that accommodate the camera device.

[0041] [ Figure 15 ]A diagram showing a structural example of an electronic device. DETAILED DESCRIPTION

[0042] (Implementation Method 1)

[0043] In this embodiment, referring to Figures 1 to 7 An imaging device that efficiently performs pooling processing using a neural network will be described.

[0044] First, refer to Figure 1A block diagram illustrating the imaging device 10 is provided. The imaging device 10 includes a pixel region, a driver 11, a driver 12, a driver 13, multiple wirings 111, multiple wirings 112 (not shown), and multiple wirings 113a (not shown). The pixel region includes multiple pooling modules 200, multiple analog-to-digital conversion circuits 250, and an output circuit 251. The pooling module 200 includes multiple pooling circuits 210 and a comparison module 220. The pooling circuit 210 includes multiple pixels 100 and an arithmetic circuit 212 (not shown). The comparison module 220 includes multiple comparison circuits 230 (not shown) and a determination circuit 221 (not shown).

[0045] Pixel 100 can convert light into an electrical signal to obtain a first signal, and can also multiply the first signal by an arbitrary magnification to generate a second signal. The first and second signals are output as currents. The arbitrary magnification refers to the value of the weight data used in the pooling process of the neural network.

[0046] The pooling circuit 210 may generate a third signal by adding the plurality of second signals via the operation circuit 212. Alternatively, the operation circuit 212 may generate a fifth signal by averaging the plurality of second signals.

[0047] The comparison module 220 may select the largest third signal by comparing the plurality of third signals, and output the largest third signal to the determination circuit 221. The determination circuit 221 may determine the largest third signal, binarize the largest third signal, and generate a fourth signal.

[0048] The pooling module 200 may perform pooling processing according to the number of pixels included in the pooling module 200. That is, the pooling module 200 may obtain a first signal from a plurality of pixels included in the pooling module 200, perform pooling processing on the first signal to generate a fourth signal, and output the fourth signal.

[0049] The driver 11 can control the timing of outputting the fourth signal to the output circuit 251 based on the selection signal supplied to the wiring 111. Although not shown in the figure, the output circuit 251 can output the fourth signal to the neural network that controls the camera device 10. When the camera device 10 performs pooling processing on the first data, data with features of the data is input to the neural network. Therefore, the neural network only needs to process the features of the extracted data, thereby reducing the amount of data to be processed. Therefore, the data transfer time from the camera element to the neural network is shortened, and the amount of computation required by the neural network can be reduced. By reducing the amount of computation required by the neural network, power consumption can be reduced.

[0050] The pooling module 200 preferably includes a plurality of pooling circuits 210 . Figure 1The example in which the pooling module 200 includes four pooling circuits 210 is shown. The number of pooling circuits 210 included in the pooling module 200 can be greater than 1 and less than n (n is a natural number greater than 2). When multiple pooling circuits are included, it is easier to extract features of the data. In addition, when the number of pixels included in the pooling circuit 210 increases, the compression rate of the data becomes higher, thereby reducing the amount of computation required by the neural network. Therefore, the power consumption of the neural network is further reduced.

[0051] exist Figure 2 , an example of a pooling circuit 210 is described with reference to a block diagram. The pooling circuit 210 includes a plurality of pixels 100, an operation circuit 212, a switch 203, a switch 204, a plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210a. The pixel 100 includes a first output terminal, and the operation circuit 212 includes a transistor 212a, a transistor 212b, and a transistor 212c. Note that the description Figure 2 The pooling circuit 210 is shown as an example including four pixels.

[0052] The driver 12 is electrically connected to a plurality of pixels 100 extending in the row direction via a wiring 112 , and the driver 13 is electrically connected to a plurality of pixels 100 extending in the column direction via a wiring 113 a .

[0053] Wiring 114 is electrically connected to one of the source and drain of transistor 212a, one of the source and drain of transistor 212b, and one of the source and drain of transistor 212c. The gate of transistor 212a is electrically connected to the other of the source and drain of transistor 212a, the gate of transistor 212b, and the gate of transistor 212c. The gate of transistor 212a is also electrically connected to output terminals 100a of the plurality of pixels 100 included in the pooling circuit 210.

[0054] The other of the source and drain of transistor 212b is electrically connected to one electrode of switch 203, and the other of the source and drain of transistor 212c is electrically connected to one electrode of switch 204. The other electrode of switch 203 is electrically connected to the other electrode of switch 204 and comparison module 220 via wiring 210a.

[0055] The driver 13 can output a selection signal to the wiring 113a. The driver 12 can set the pixel 100 to an arbitrary magnification as weight data through the wiring 112. The transistor 212a has the same channel length as the transistor 212b and the transistor 212c, and the transistor 212b has the same channel width as the transistor 212a, thereby outputting a third signal that adds the multiple second signals. The transistor 212c has a channel width obtained by dividing the channel width of the transistor 212a by the number of pixels 100 included in the pooling circuit 210, thereby outputting a fifth signal of a size obtained by dividing the size of the third signal by the number of pixels 100. The third signal and the fifth signal are controlled by current. The switch 203 and the switch 204 are preferably in a complementary relationship.

[0056] The switch 203 and the switch 204 are controlled by a first switching signal supplied to the wiring 115 . Figure 2 An example is shown in which a p-channel transistor is used for the switch 203 and an n-channel transistor is used for the switch 204 .

[0057] When the first switching signal is “L”, the pooling circuit 210 may output the third signal to the comparison module 220 through the wiring 210 a .

[0058] When the first switching signal is “H”, the pooling circuit 210 may output the fifth signal to the comparison module 220 through the wiring 210 a .

[0059] For example, in an in-vehicle image processing system, it is necessary to instantly determine the surrounding conditions of a high-speed moving vehicle. Therefore, by using the imaging device 10 with the pooling module 200 exclusively for detecting features from the image data, the amount of computation can be reduced and processing time can be shortened.

[0060] Notice, Figure 2 This illustrates an example of supplying different weight data to each pixel 100 included in the pooling circuit 210. Furthermore, weight data can be supplied to each pooling circuit 210 or pooling module 200 as a single unit. Therefore, the wiring 112 and the wiring 113a can be electrically connected to each pooling circuit 210 or pooling module 200 as a single unit. By reducing the number of wirings 112 and 113a, the integration density of the imaging device 10 can be increased.

[0061] exist Figure 3FIG. 2A (A) illustrates an example of a comparison module 220 with reference to a block diagram. Comparison module 220 includes multiple comparison circuits 230, multiple current mirror circuits 222, and a determination circuit 221. Each comparison circuit 230 includes an input terminal 231a, an input terminal 231b, and an output terminal 231c. Determination circuit 221 includes input terminals 221a, an input terminal 221b, and an output terminal 221c. Current mirror circuit 222 includes an input terminal 224a and an output terminal 224b.

[0062] exist Figure 3 FIG. 2 (A) shows an example of supplying output signals from four pooling circuits 210 to the comparison module 220. In addition, the comparison module 220 is electrically connected to four different pooling circuits 210 via wiring 210a(i, j) to wiring 210a(i+1, j+1). It is preferable to provide a comparison circuit 230 according to the number of input signals. Figure 3 In the example shown in FIG. 2A , the comparison module 220 includes a comparison circuit 230 a , a comparison circuit 230 b , a comparison circuit 230 c , a current mirror circuit 222 a , a current mirror circuit 222 b , and a determination circuit 221 .

[0063] Next, a connection example of the comparison circuits 230a, 230b, and 230c, the current mirror circuits 222a and 222b, and the determination circuit 221 will be described. The input terminal 231a of the comparison circuit 230a is electrically connected to the wiring 210a(i, j), the input terminal 231b is electrically connected to the wiring 210a(i+1, j), the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222a, and the output terminal 224b of the current mirror circuit 222a is electrically connected to the input terminal 231a of the comparison circuit 230b.

[0064] The input terminal 231b of the comparison circuit 230b is electrically connected to the wiring 210a(i, j+1), and the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222b. The output terminal 224b of the current mirror circuit 222b is electrically connected to the input terminal 231a of the comparison circuit 230c. The input terminal 231b of the comparison circuit 230c is electrically connected to the wiring 210a(i+1, j+1), and the output terminal 231c is electrically connected to the input terminal 221a of the determination circuit 221.

[0065] Current mirror circuit 222 includes transistor 223a and transistor 223b. Transistor 223a and transistor 223b are preferably p-channel transistors. One of the source and drain of transistor 223a is electrically connected to one of the source and drain of transistor 223b and wiring 114. The gate of transistor 223a is electrically connected to the other of the source and drain of transistor 223a and the gate of transistor 223b.

[0066] Input terminal 231a of comparator circuit 230a is supplied with signal a1 via wiring 210a(i, j). Input terminal 231b is supplied with signal a2 via wiring 210a(i+1, j). Output terminal 231c outputs the larger of signal a1 and signal a2 as signal a3, which is supplied to input terminal 224a of current mirror circuit 222a. Signal a3 passes through current mirror circuit 222a, becoming signal b1 of the same magnitude as signal a3. Signal b1 is then supplied to output terminal 224b of the current mirror circuit. Therefore, input terminal 231a of comparator circuit 230b is supplied with signal b1 of the same magnitude as signal a3. Note that signals a3 and b1 have different directions.

[0067] Comparator circuit 230b receives signal b2 via wiring 210a(i, j+1) from input terminal 231b and outputs the larger of signal b1 and signal b2 as signal b3 from output terminal 231c. Comparator circuit 230c receives signal c1 via current mirror circuit 222b from input terminal 231a and signal c2 via wiring 210a(i+1, j+1) from input terminal 231b. Comparator circuit 230c outputs the larger of signal c1 and signal c2 as signal c3 from output terminal 231c to determination circuit 221. Each of signals a1, a2, a3, b1, b2, b3, c1, c2, and c3 is preferably an analog signal.

[0068] Therefore, the determination circuit 221 determines the signal c3 input to the input terminal 221a, binarizes it, and generates a fourth signal, which can be output to the output terminal 221c. The driver 11 can control the timing of outputting the fourth signal to the output circuit 251 via the wiring 211 based on the selection signal supplied to the wiring 111.

[0069] exist Figure 3 FIG. 2B shows a circuit diagram of the comparison circuit 230 . The comparison circuit 230 includes transistors 241 to 246 , an input terminal 231 a , an input terminal 231 b , an output terminal 231 c , and a wiring 232 .

[0070] The input terminal 231a is electrically connected to one of the source and drain of the transistor 242, one of the source and drain of the transistor 244, the gate of the transistor 241, the gate of the transistor 242, and the gate of the transistor 243. The input terminal 231b is electrically connected to one of the source and drain of the transistor 245, one of the source and drain of the transistor 243, the gate of the transistor 244, the gate of the transistor 245, and the gate of the transistor 246. The output terminal 231c is electrically connected to one of the source and drain of the transistor 241 and one of the source and drain of the transistor 246. The wiring 232 is electrically connected to the other of the source and drain of the transistors 241 to 246.

[0071] Furthermore, the transistors 241 to 246 have the same channel length.

[0072] In addition, the channel width of the transistor 241 is preferably the same as the channel width of the transistor 242, and the channel width of the transistor 243 is preferably twice the channel width of the transistor 242. The transistors 241 to 243 form a first current mirror circuit.

[0073] In addition, the channel width of the transistor 246 is preferably the same as the channel width of the transistor 245, and the channel width of the transistor 244 is preferably twice the channel width of the transistor 245. The transistors 244 to 246 form a second current mirror circuit.

[0074] Next, the operation of comparator circuit 230 will be described. Note that input terminals 231a and 231b are supplied with current as analog signals, while output terminal 231c is a sink for analog current. For example, when the signal input to input terminal 231a is greater than the signal input to input terminal 231b, the signal supplied to input terminal 231b is sunk into transistor 243. As a different example, when the signal input to input terminal 231b is greater than the signal input to input terminal 231a, the signal input to input terminal 231a is sunk into transistor 244. Therefore, output terminal 231c can sink a signal of the same magnitude as the larger signal input to input terminal 231a or input terminal 231b via either the first current mirror circuit or the second current mirror circuit.

[0075] Note that when the input signals at input terminals 231a and 231b are equal in magnitude, the magnitude of the signals absorbed by transistors 242 and 245 is approximately half that magnitude. Therefore, output terminal 231c absorbs a signal of the magnitude resulting from the combined signals from transistors 241 and 246. Thus, output terminal 231c can absorb signals of the same magnitude as input terminals 231a and 231b. Wiring 232 preferably has a low potential capable of absorbing signals.

[0076] Therefore, in Figure 3 In FIG. 1A , the largest signal among the signals a1, a2, b2, and c2 supplied to the comparison module 220 is supplied to the determination circuit 221 as signal c3. The determination circuit 221 can determine and binarize the signal c3, generating a fourth signal. The driver 11 can supply a selection signal to the determination circuit 221 via the wiring 111, and the output circuit 251 can output the determination result.

[0077] exist Figure 4 100, an example of a pixel 100 is described with reference to a circuit diagram. Pixel 100 includes a photoelectric conversion element 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and an output terminal 100a. Pixel 100 is also electrically connected to wiring 112, wiring 113a, wiring 113b, wiring 117, wiring 118, and wiring 119.

[0078] One electrode of the photoelectric conversion element 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one of the source and drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104. One of the source and drain of the transistor 105 is electrically connected to the output terminal 100a, and the other electrode of the capacitor 104 is electrically connected to one of the source and drain of the transistor 106. The other of the source and drain of the transistor 106 is electrically connected to the wiring 112, and the gate of the transistor 106 is electrically connected to the wiring 113a. The gate of the transistor 102 is electrically connected to the wiring 113b. The gate of the transistor 103 is electrically connected to the wiring 113c. The other of the source and drain of the transistor 103 is electrically connected to the wiring 118. The other electrode of the photoelectric conversion element 101 is electrically connected to the wiring 117. The other of the source and drain of the transistor 105 is electrically connected to the wiring 119.

[0079] The node FN is formed by connecting the other of the source and drain of the transistor 102, one of the source and drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104. Note that a structure without providing the capacitor 104 is also possible.

[0080] Transistor 103 can be turned on by a signal supplied to wiring 113c. Thus, node FN can be initialized by a reset potential supplied to wiring 118. Transistor 102 can be turned on by a signal supplied to wiring 113b. Therefore, photoelectric conversion element 101 can be updated using imaging data obtained by photoelectrically converting data at node FN by transistor 102. Furthermore, transistor 102 can be turned off by a signal supplied to wiring 113b. By turning off transistor 102, node FN can retain imaging data. In other words, the first signal refers to the current flowing when imaging data is supplied to the gate of transistor 105.

[0081] Figure 4 Although an n-channel transistor is used as the transistor 105 as an example, a p-channel transistor can also be used. Note that when the transistor 105 is an n-channel transistor, the potential supplied to the wiring 119 is preferably low, and when the transistor 105 is a p-channel transistor, the potential supplied to the wiring 119 is also preferably low.

[0082] In addition, transistor 106 can be turned on according to a signal supplied to wiring 113a. Weight data can be supplied to capacitor 104 from wiring 112 through transistor 106. Preferably, node FN is a floating node when transistors 102 and 103 are in the off state. Therefore, transistors 102 and 103 preferably use transistors with small off-state current. Transistors with small off-state current preferably use transistors (OS transistors) containing metal oxide in the channel formation region. OS transistors will be described in detail in Embodiment 2.

[0083] Capacitor 104 adds weight data to the image data held at node FN. Specifically, a data voltage obtained by adding weight data to the image data is supplied to the gate of transistor 105. Therefore, transistor 105 can multiply the weight data at any factor using the resistance of transistor 105. In other words, the second signal refers to the current that flows when the data voltage obtained by adding weight data to the image data is supplied to the gate of transistor 105.

[0084] exist Figure 5 In FIG, an example of the working method of the pooling module 200 is described. Figure 5 In FIG. 1A , for simplicity, the pooling module 200 is shown as including four pooling circuits 210 and a comparison module 220. Furthermore, the pooling circuit 210 is shown as including four pixels. However, there is no limitation on the number of pooling modules 200 included in the imaging device 10.

[0085] Figure 5 Figure (B) shows Figure 5 (A) is a timing diagram of an example of the working method of the pooling module 200. Although not shown in the figure, Figure 5 The timing chart shown in FIG. 1(B) shows an example in which an L signal is supplied to the wiring 115 and the pooling circuit 210 performs an addition process on the first signals of the plurality of pixels 100 .

[0086] In T1, an H signal is supplied to wiring 113c, turning on transistor 103 in each pixel 100. Therefore, node FN is reset using the potential supplied to wiring 118. Furthermore, a selection signal is supplied to wiring 113a, and an initial value Res of weight data is supplied via wiring 112.

[0087] In T2, an H signal is supplied to the wiring 113b, and each pixel 100 performs photoelectric conversion (sensing) by the photoelectric conversion element 101, and the node FN is updated using the image data.

[0088] In T3, an L signal is supplied to wiring 113b to determine the image data of node FN. In addition, a selection signal is supplied to wiring 113a(1), and weight data of pixels 100(1), 100(2), 100(5), and 100(6) are set via wirings 112(1) to 112(4).

[0089] In T4, a selection signal is supplied to wiring 113a(2), and weight data of pixel 100(3), pixel 100(4), pixel 100(7), and pixel 100(8) are set through wiring 112(1) to wiring 112(4).

[0090] At T5, a selection signal is supplied to wiring 113a(3), and weight data for pixels 100(9), 100(10), 100(13), and 100(14) is set via wiring 112(1) to wiring 112(4). Furthermore, pooling circuit 210(1,1) outputs data signal a1, which adds weight data to the image data, to wiring 210a(1,1). Furthermore, pooling circuit 210(2,1) outputs signal a2, which adds weight data to the image data, to wiring 210a(2,1).

[0091] In T6, a selection signal is supplied to wiring 113a(4), and weight data of pixel 100(11), pixel 100(12), pixel 100(15), and pixel 100(16) are set through wiring 112(1) to wiring 112(4).

[0092] At T7, the pooling circuit 210 (1, 1) outputs a data signal b2 obtained by adding weight data to the image data to the wiring 210a (1, 2). In addition, the pooling circuit 210 (2, 2) outputs a signal c2 obtained by adding weight data to the image data to the wiring 210a (2, 2).

[0093] At T8, the comparison module 220 detects the largest signal among a1, a2, b2, and c2. The determination circuit 221 included in the comparison module 220 determines the detected largest signal, binarizes it, and outputs the digital signal out to the wiring 211. The digital signal out is supplied to the output circuit 251. To facilitate processing in the neural network, the output circuit 251 combines the digital signals out and outputs them as digital data of arbitrary data width.

[0094] exist Figure 6 In the block diagram, refer to the Figure 2 Examples of pooling circuit 210 with different configurations. Figure 6 of and Figure 2 The differences are that the pooling circuit 210 includes a plurality of wirings 113d, a wiring 211a, and a wiring 211b; and the pixel 100 includes an output terminal 100b.

[0095] Wiring 113d is electrically connected to a plurality of pixels extending in the column direction. Wiring 211a is electrically connected to output terminal 100b of pixel 100 extending in the row direction. Image data is output to wiring 211a or wiring 211b. The image data is output to analog-to-digital conversion circuit 250 via wiring 211a and wiring 211b.

[0096] Figure 7 Description Figure 4 Examples of pixel 100 with different structures. Figure 7 of and Figure 4 The difference lies in the inclusion of transistors 107 and 108 .

[0097] The gate of transistor 107 is electrically connected to node FN. One of the source and drain of transistor 107 is electrically connected to one of the source and drain of transistor 108. The other of the source and drain of transistor 108 is electrically connected to output terminal 100b. The gate of transistor 108 is electrically connected to wiring 113d. The other of the source and drain of transistor 107 is electrically connected to wiring 119.

[0098] Transistor 107 allows current to flow in accordance with the potential of the image data held at node FN. Transistor 108 outputs the image data to output terminal 100b in accordance with a selection signal supplied to wiring 113d. Note that when weight data is set in capacitor 104, a multiplication result obtained by adding the weight data to the image data and in accordance with the resistance of transistor 105 is output.

[0099] The camera device 10 can easily perform pooling processing by including the pooling module 200. Therefore, by reducing the amount of data transmitted to the neural network and the amount of calculation, power consumption can be reduced.

[0100] As described above, the structure and method described in this embodiment can be used in combination with the structure and method described in other embodiments as appropriate.

[0101] (Implementation Method 2)

[0102] In this embodiment, referring to Figures 8 to 14 The photoelectric conversion element 101 used in the imaging device 10 will be described.

[0103] <Structural Example of Pixel Circuit>

[0104] Figure 8 FIG. 1 (A) shows an example of the structure of a pixel having the above-mentioned pixel circuit. Figure 8 FIG. 1 (A) shows an example in which a pixel has a stacked-layer structure including a layer 61 and a layer 62 .

[0105] Layer 61 includes the photoelectric conversion element 101. Figure 8 As shown in FIG. 5(C) , the photoelectric conversion element 101 may be a stack of layers 65 a , 65 b , and 65 c .

[0106] Figure 8 The photoelectric conversion element 101 shown in FIG. 1 (C) is a pn junction type photodiode, and for example, p + type semiconductor, an n-type semiconductor is used as layer 65b, and an n-type semiconductor is used as layer 65c. + Alternatively, n may be used as layer 65a. + type semiconductor, a p-type semiconductor is used as layer 65b, and a p-type semiconductor is used as layer 65c. + Alternatively, the photoelectric conversion element 101 may use a pin junction photodiode using an i-type semiconductor as the layer 65b.

[0107] The pn junction photodiode or pin junction photodiode can be formed using single crystal silicon. Alternatively, the pin junction photodiode can be formed using a thin film of amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

[0108] In addition, if Figure 8 As shown in FIG. 1(D), the photoelectric conversion element 101 included in the layer 61 may be a stack of layers 66a, 66b, 66c, and 66d. Figure 8 The photoelectric conversion element 101 shown in FIG. 1 (D) is an example of an avalanche photodiode. The layers 66a and 66d correspond to electrodes, and the layers 66b and 66c correspond to photoelectric conversion units.

[0109] The layer 66a is preferably made of a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

[0110] Layer 66d is preferably a conductive layer having high transmittance to visible light. For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, or graphene can be used. Layer 66d may be omitted.

[0111] The photoelectric conversion layers 66b and 66c may have a pn junction photodiode structure using a selenium-based material as the photoelectric conversion layer. Preferably, a p-type semiconductor selenium-based material is used as layer 66b, and an n-type semiconductor such as gallium oxide is used as layer 66c.

[0112] Photoelectric conversion elements using selenium-based materials have high external quantum efficiencies for visible light. These elements can utilize avalanche multiplication to increase the electron amplification relative to the incident light. Furthermore, selenium-based materials have high light absorption coefficients, allowing for the production of photoelectric conversion layers in thin films, which is advantageous from a production perspective. Thin films of selenium-based materials can be formed using methods such as vacuum evaporation and sputtering.

[0113] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a copper, indium, and selenium compound (CIS), or a copper, indium, gallium, and selenium compound (CIGS) can be used.

[0114] The n-type semiconductor is preferably made of a material with a wide bandgap and transparency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as hole injection barriers, reducing dark current.

[0115] As Figure 8 The layer 62 shown in FIG. (A) can be, for example, a silicon substrate. Si transistors and the like are provided on the silicon substrate. In addition to the above-mentioned pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, and the like can also be provided.

[0116] In addition, if Figure 8 As shown in FIG. 6B , the pixel may also have a stacked structure of layer 61 , layer 63 and layer 62 .

[0117] Layer 63 may include OS transistors (e.g., transistors 102 and 103 of the pixel circuit). At this time, layer 62 preferably includes Si transistors (e.g., transistors 107 and 108 of the pixel circuit).

[0118] By adopting this structure, the elements constituting the pixel circuit can be dispersed into multiple layers and the elements can be arranged in an overlapping manner, so that the area of the imaging device can be reduced. In addition, in Figure 8 the structure of (B) in the figure, layer 62 can also be used as a support substrate and pixels 100 and peripheral circuits can be provided on layer 61 and layer 63.

[0119] <OS transistor>

[0120] As the semiconductor material for the OS transistor, a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium can be used, etc., for example, CAC-OS described later can be used.

[0121] As the semiconductor layer, for example, a film represented by "In-M-Zn type oxide" containing indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be adopted.

[0122] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, it is preferable that the atomic number ratio of the metal elements of the sputtering target used to deposit and form the In-M-Zn oxide film satisfies In ≥ M and Zn ≥ M. The atomic number ratio of the metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic number ratio of the semiconductor layer deposited and formed can vary within the range of ±40% of the atomic number ratio of the metal elements in the above sputtering target.

[0123] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, as the semiconductor layer, a semiconductor with a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, and further preferably 1×10 11 / cm 3Below, more preferably less than 1×10 10 / cm 3 And 1×10 -9 / cm 3 Oxide semiconductors with carrier densities above 100 nm are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Due to their low impurity concentration and defect level density, they can be said to have stable properties.

[0124] Note that the present invention is not limited to the above description, and materials having an appropriate composition can be used depending on the desired semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0125] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the elements in Group 14, oxygen vacancies increase, and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0126] In addition, when alkali metals and alkaline earth metals are bonded to oxide semiconductors, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0127] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, the carrier density increases, and the n-type is easily converted. As a result, the transistor using the oxide semiconductor containing nitrogen is likely to have a normally-on characteristic. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 the following.

[0128] In addition, the semiconductor layer may also have a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) with c-axis orientation, or C-Axis Aligned and AB-plane Anchored Crystalline Oxide Semiconductor, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest defect energy level density, while CAAC-OS has the lowest defect energy level density.

[0129] An oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystalline component. Alternatively, an oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and no crystalline portion.

[0130] Furthermore, the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above regions.

[0131] Next, the structure of CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, will be described.

[0132] CAC-OS refers to, for example, a configuration in which elements contained in an oxide semiconductor are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing these metal elements are mixed at a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size, is hereinafter referred to as a mosaic or patch-like state.

[0133] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0134] For example, CAC-OS (among CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO) in In-Ga-Zn oxide refers to a material that is divided into indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0.) or indium zinc oxide (hereinafter referred to as InX2 Zn Y2 O Z2 (X2, Y2 and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4 and Z4 are real numbers greater than 0). ) etc. and become a mosaic, and the mosaic-shaped InO X1 or In X2 Zn Y2 O Z2 A structure uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0135] In other words, CAC-OS is a GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0136] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0137] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0138] CAC-OS, on the other hand, is related to the material composition of the oxide semiconductor. CAC-OS refers to a structure in which, within a material composition containing In, Ga, Zn, and O, nanoparticle-like regions primarily composed of Ga are observed in some areas, while nanoparticle-like regions primarily composed of In are observed in others. These regions are then randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0139] CAC-OS does not include a stacked-layer structure of two or more films having different compositions, for example, a structure consisting of two layers: a film containing In as a main component and a film containing Ga as a main component.

[0140] Note that sometimes no GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 There are clear boundaries between the regions of the main components.

[0141] In the case where CAC-OS includes one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, CAC-OS refers to the following structure: nanoparticle-like regions with the element as the main component are observed in a part and nanoparticle-like regions with In as the main component are observed in a part, which are irregularly dispersed in a mosaic shape.

[0142] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen, and nitrogen can be used as the film-forming gas. Furthermore, the lower the flow rate ratio of oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow rate ratio of oxygen gas is set to be between 0% and less than 30%, preferably between 0% and less than 10%.

[0143] CAC-OS is characterized by the absence of clear peaks when measured using the out-of-plane θ / 2θ scanning method, one of the X-ray diffraction (XRD) measurement techniques. This means that X-ray diffraction indicates no orientation in the ab-plane or c-axis directions within the measurement region.

[0144] Furthermore, an electron diffraction pattern of CAC-OS obtained by irradiating the material with an electron beam (also known as a nanobeam) with a beam diameter of 1 nm reveals a ring-shaped region of high brightness and multiple bright spots within this ring-shaped region. This electron diffraction pattern indicates that the crystalline structure of CAC-OS has an nc (nano-crystal) structure with no orientation in either the planar or cross-sectional directions.

[0145] In addition, for example, in CAC-OS of In-Ga-Zn oxide, it can be confirmed from EDX surface analysis images (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) that there is GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 A mixed structure in which the main components are unevenly distributed.

[0146] The structure of CAC-OS is different from that of IGZO compound in which metal elements are evenly distributed, and it has different properties from IGZO compound. X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 The regions containing the elements as main components are separated from each other, and the regions containing the elements as main components are in a mosaic-like structure.

[0147] Here, In X2 Zn Y2 O Z2 or InO X1 The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component. X3 In other words, when the carrier flows through the region with In as the main component X2 Zn Y2 O Z2 or InO X1 When the region is composed mainly of In, it exhibits the conductivity of an oxide semiconductor. X2 Zn Y2 O Z2 or InO X1 When the region as the main component is distributed in a cloud-like manner in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0148] On the other hand, GaO X3 The insulation of the area with In as the main component is higher than that of the area with In as the main component. X2 Zn Y2 O Z2 or InO X1 In other words, when GaO X3 When regions whose main components are ions such as ions are distributed in an oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0149] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the reason for In X2 Zn Y2 O Z2 or InO X1 The complementary effect of the conductivity can achieve high on-state current (I on ) and high field-effect mobility (μ).

[0150] Furthermore, semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0151] Figure 9 Figure (A) shows Figure 8 FIG. 1A shows an example of a cross section of a pixel. As the photoelectric conversion element 101, layer 61 includes a pn junction photodiode using silicon as a photoelectric conversion layer. Layer 62 includes Si transistors and the like that constitute the pixel circuit.

[0152] In the photoelectric conversion element 101, the layer 65a may be p + type region, layer 65b is an n-type region and layer 65c is an n-type region. + In addition, layer 65b is provided with a region 36 for connecting the power line to layer 65c. For example, region 36 may be p + Type area.

[0153] exist Figure 9 FIG. 1(A) shows a Si transistor having a planar structure with a channel formation region on a silicon substrate 40. However, as shown in FIG. Figure 12 Figure (A), Figure 12 As shown in FIG. 1B , a structure including a fin-shaped semiconductor layer on a silicon substrate 40 may also be employed. Figure 12 Figure (A) is equivalent to the cross section in the channel length direction. Figure 12 Figure (B) corresponds to a cross section in the channel width direction.

[0154] In addition, if Figure 12 As shown in FIG. 3(C) , a transistor including a semiconductor layer 45 of a silicon thin film may be used. For example, the semiconductor layer 45 may be formed of single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 46 on a silicon substrate 40 .

[0155] Here, Figure 9 FIG. 1A shows an example in which the components of layer 61 and the components of layer 62 are electrically connected by lamination technology.

[0156] Insulating layer 42, conductive layer 33, and conductive layer 34 are provided on layer 61. Conductive layer 33 and conductive layer 34 have regions that bury insulating layer 42. Conductive layer 33 is electrically connected to layer 65a. Conductive layer 34 is electrically connected to region 36. Furthermore, the surfaces of insulating layer 42, conductive layer 33, and conductive layer 34 are flattened so that their heights are uniform.

[0157] Insulating layer 41, conductive layer 31, and conductive layer 32 are provided on layer 62. Conductive layer 31 and conductive layer 32 have regions buried in insulating layer 41. Conductive layer 32 is electrically connected to a power supply line. Conductive layer 31 is electrically connected to one of the source and drain of transistor 102. Furthermore, the surfaces of insulating layer 41, conductive layer 31, and conductive layer 32 are flattened so that their heights are uniform.

[0158] Here, the main components of conductive layer 31 and conductive layer 33 are preferably the same metal element. The main components of conductive layer 32 and conductive layer 34 are preferably the same metal element. Insulating layer 41 and insulating layer 42 are preferably composed of the same component.

[0159] For example, Cu, Al, Sn, Zn, W, Mo, Ag, Pt, or Au can be used as the conductive layers 31, 32, 33, and 34. From the perspective of ease of bonding, Cu, Al, W, or Au is preferably used. Furthermore, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used as the insulating layers 41 and 42.

[0160] In other words, it is preferable to use the same metal material as the above-mentioned metal material for the combination of conductive layer 31 and conductive layer 33, and for the combination of conductive layer 32 and conductive layer 34. Furthermore, it is preferable to use the same insulating material as the above-mentioned insulating material for insulating layer 41 and insulating layer 42. With this structure, lamination can be performed with the boundary between layer 61 and layer 62 as the lamination position.

[0161] The above lamination process provides electrical connections between the combination of conductive layer 31 and conductive layer 33 and the combination of conductive layer 32 and conductive layer 34. In addition, a mechanically strong connection between insulating layer 41 and insulating layer 42 can be achieved.

[0162] When joining metal layers, surface activation bonding can be used. In this method, surface oxide films and impurity adsorption layers are removed through sputtering, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, diffusion bonding, which combines temperature and pressure to achieve surface bonding, can be used. All of these methods produce atomic-level bonding, resulting in electrically and mechanically excellent bonds.

[0163] Furthermore, when bonding insulating layers, hydrophilic bonding methods can be used. After achieving high flatness through polishing, surfaces treated with oxygen plasma or other methods for hydrophilicity are brought into contact for temporary bonding. Heat treatment is then used to dehydrate the surfaces, allowing for final bonding. Hydrophilic bonding also creates atomic-level bonding, resulting in mechanically superior bonding.

[0164] In the case of the bonding layer 61 and the layer 62, since the insulating layer and the metal layer are mixed at each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

[0165] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, a difficult-to-oxidize metal such as Au can be used as the surface of the metal layer and a hydrophilic treatment can be performed. In addition, bonding methods other than the above methods can also be used.

[0166] Figure 9 Figure (B) is as Figure 8 FIG. (A) shows a cross-sectional view of a pixel layer 61 using a pn junction photodiode with a selenium-based material as a photoelectric conversion layer. The layer 61 includes a layer 66a as one electrode, layers 66b and 66c as photoelectric conversion layers, and a layer 66d as another electrode.

[0167] In this case, the layer 61 can be provided directly on the layer 62. The layer 66a is electrically connected to the source or drain of the transistor 102. The layer 66d is electrically connected to the power supply line through the conductive layer 37.

[0168] Figure 10 Figure (A) shows Figure 8 FIG. (B) shows an example of a cross section of a pixel. As the photoelectric conversion element 101, layer 61 includes a pn junction photodiode using silicon as a photoelectric conversion layer. Layer 62 includes Si transistors, etc. Layer 63 includes OS transistors, etc. Figure 10 FIG. 1(A) shows an example of a structure in which a bonding layer 61 and a layer 63 are electrically connected.

[0169] Figure 10 FIG. (A) shows that the OS transistor is a self-aligned structure, but as Figure 12 As shown in FIG. 1 (D), a transistor having a non-self-aligned structure can also be used.

[0170] Although the transistor 102 is shown to include a back gate 35, a structure including a back gate may also be employed. Figure 12 As shown in FIG. 3(E) , the back gate 35 may be electrically connected to the front gate of the transistor facing it. Alternatively, a structure may be adopted in which a fixed potential different from that of the front gate can be supplied to the back gate 35.

[0171] An insulating layer 43 is provided between the region where the OS transistor is formed and the region where the Si transistor is formed, to prevent hydrogen diffusion. Hydrogen in the insulating layer provided near the channel formation region of the transistors 107 and 108 terminates dangling bonds in silicon. On the other hand, hydrogen in the insulating layer provided near the channel formation region of the transistor 102 may contribute to the generation of carriers in the oxide semiconductor layer.

[0172] By providing the insulating layer 43 and confining hydrogen in one layer, the reliability of the transistors 107 and 108 can be improved. At the same time, since diffusion of hydrogen from one layer to another can be suppressed, the reliability of the transistor 102 can be improved.

[0173] The insulating layer 43 can be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0174] Figure 10 Figure (B) shows that Figure 8 FIG. 6B shows a cross-sectional view of a pixel in which layer 61 is a pn junction photodiode using a selenium-based material as a photoelectric conversion layer. Layer 61 can be directly provided on layer 63. Details of layers 61, 62, and 63 can be found in the above description.

[0175] Figure 11 Figure (A) shows Figure 10 Figure 1 shows a structure of a CMOS chip. The sensor region is composed of layer 61 having photoelectric conversion elements 101 and layer 63 having OS transistors. The operation region is composed of layer 63 having Si transistors and the like. The operation region includes transistors 107 and 108 in the pixel, as well as circuits such as the pooling circuit and drivers 11, 12, and 13 of Embodiment 1. The stacked structure of the sensor region and the operation region can reduce the circuit area.

[0176] Figure 11 Figure (B) shows cross-sectional photographs of the sensor area and the computation area. The sensor area consists of a pn-junction photodiode and an OS transistor (OSFET) using a selenium-based material as the photoelectric conversion layer, while the computation area comprises various circuits composed of Si transistors (SiFET).

[0177] <Other pixel components>

[0178] Figure 13Figure (A) is a perspective view showing an example of adding a color filter or the like to a pixel of an imaging device according to one embodiment of the present invention. The perspective view also shows a cross section of a plurality of pixels. An insulating layer 80 is formed on the layer 61 forming the photoelectric conversion element 101. The insulating layer 80 can be made of a silicon oxide film having high light transmittance to visible light. Alternatively, a structure in which a stacked silicon nitride film is used as a passivation film. Alternatively, a structure in which a dielectric film such as hafnium oxide is stacked can be used as an antireflection film.

[0179] A light shielding layer 81 may also be formed on the insulating layer 80. The light shielding layer 81 has the function of preventing the mixing of light passing through the color filter above. A metal layer such as aluminum or tungsten can be used as the light shielding layer 81. Alternatively, the metal layer may be laminated with a dielectric film that functions as an antireflection film.

[0180] An organic resin layer 82 serving as a planarization film may be provided on the insulating layer 80 and the light-shielding layer 81. Furthermore, a color filter 83 (color filters 83a, 83b, and 83c) is formed in each pixel. For example, color filters 83a, 83b, and 83c may have colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta), thereby producing a color image.

[0181] An insulating layer 86 or the like having a light-transmitting property for visible light may be provided on the color filter 83 .

[0182] In addition, if Figure 13 As shown in FIG. 8B , an optical conversion layer 85 may be used instead of the color filter 83. By adopting such a structure, an imaging device capable of acquiring images in various wavelength regions can be formed.

[0183] For example, using a color filter that blocks light with wavelengths shorter than or equal to visible light as the optical conversion layer 85 can produce an infrared imaging device. Using a color filter that blocks light with wavelengths shorter than or equal to near-infrared light as the optical conversion layer 85 can produce a far-infrared imaging device. Furthermore, using a color filter that blocks light with wavelengths longer than or equal to visible light as the optical conversion layer 85 can produce an ultraviolet imaging device. Visible light filters can be combined with infrared or ultraviolet filters.

[0184] Furthermore, by using a scintillator in the optical conversion layer 85, an imaging device for use in X-ray imaging devices, etc., can be formed that obtains images that visualize radiation intensity. When radiation, such as X-rays, that has passed through a subject enters the scintillator, photoluminescence causes it to be converted into light (fluorescence) such as visible light or ultraviolet light. This light is detected by the photoelectric conversion element 101, thereby obtaining image data. Furthermore, an imaging device with this structure can also be used in radiation detectors, etc.

[0185] Scintillators contain materials that, when irradiated with radiation such as X-rays or gamma rays, absorb the radiation energy and emit visible light or ultraviolet light. Examples of materials that can be used include Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO dispersed in resin or ceramics.

[0186] In addition, in the photoelectric conversion element 101 using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, a scintillator does not need to be used.

[0187] In addition, if Figure 13 As shown in FIG. 8 (C), a micro lens array 84 may be provided on the color filter 83. Light passing through each lens of the micro lens array 84 is irradiated to the photoelectric conversion element 101 via the color filter 83 provided thereunder. Figure 13 A microlens array 84 is provided on the optical conversion layer 85 shown in FIG.

[0188] <Example of package and module structure>

[0189] An example of a package and a camera module that house an image sensor chip will be described below. The image sensor chip may be the same as the image pickup device described above.

[0190] Figure 14 Figure (A1) is a perspective view of the top surface of a package housing an image sensor chip. The package includes a package substrate 410 for securing an image sensor chip 450, a glass cover 420, and adhesive 430 for bonding them together.

[0191] Figure 14 Figure (A2) is a perspective view of the bottom side of the package. The bottom side of the package includes a BGA (ball grid array) with solder balls as bumps 440. Note that this is not limited to BGAs and can also include LGAs (land grid arrays) and PGAs (pin grid arrays).

[0192] Figure 14 FIG (A3) is a perspective view of the package, omitting a portion of the glass cover 420 and adhesive 430. Electrode pads 460 are formed on the package substrate 410 and are electrically connected to the bumps 440 via through-holes. Electrode pads 460 are electrically connected to the image sensor chip 450 via wires 470.

[0193] in addition, Figure 14Figure (B1) is a perspective view of the top surface of a camera module that houses an image sensor chip in a lens-integrated package. This camera module includes a package substrate 411 that secures image sensor chip 451, a lens cover 421, and a lens 435. Furthermore, an IC chip 490, which includes functions such as an imaging device driver circuit and signal conversion circuit, is located between package substrate 411 and image sensor chip 451, resulting in a system-in-package (SiP) structure.

[0194] Figure 14 (B2) is a perspective view of the bottom side of the camera module. The bottom and side surfaces of the package substrate 411 have a QFN (Quad Flat No-Lead Package) structure with housing pads 441. Note that this structure is only an example; a QFP (Quad Flat Package) or the aforementioned BGA can also be used.

[0195] Figure 14 FIG (B3) is a perspective view of the module omitting a portion of the lens cover 421 and the lens 435. The connection pads 441 are electrically connected to the electrode pads 461, and the electrode pads 461 are electrically connected to the image sensor chip 451 or the IC chip 490 via the wires 471.

[0196] By housing the image sensor chip in a package of the above type, it can be easily mounted on a printed circuit board or the like, thereby enabling the image sensor chip to be incorporated into various semiconductor devices and electronic devices.

[0197] As described above, the structure and method described in this embodiment can be used in combination with the structure and method described in other embodiments as appropriate.

[0198] (Implementation 3)

[0199] Examples of electronic devices that can use an imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices and image reproduction devices having recording media, mobile phones, portable game consoles, portable data terminals, e-book readers, imaging devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. Figure 15 Specific examples of these electronic devices are shown.

[0200] Figure 15Figure (A) shows a surveillance camera, which includes a bracket 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is provided with a rotating mechanism, etc., and can capture the surroundings by being installed on the ceiling. As one of the components for obtaining images in the camera unit, a camera device according to one embodiment of the present invention can be provided. Note that "surveillance camera" is a general name and is not limited to its use. For example, a device having the function of a surveillance camera is called a video camera or a video camera.

[0201] Figure 15 FIG. 2B shows a video camera including a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connector 976, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring images in this video camera, an imaging device according to one embodiment of the present invention may be provided.

[0202] Figure 15 FIG. 9C shows a digital camera including a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, etc. As one of the components for acquiring an image in this digital camera, an imaging device according to one embodiment of the present invention may be provided.

[0203] Figure 15 Figure (D) shows a watch-type information terminal, which includes a display unit 932, a housing and wristband 933, and a camera 939. Display unit 932 may also include a touch panel for operating the information terminal. Display unit 932 and housing and wristband 933 are flexible and suitable for wear. As one of the components for capturing images in this information terminal, a camera device according to one embodiment of the present invention may be included.

[0204] Figure 15 Figure (E) shows an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection interface 984, a speaker 985, a microphone 986, a camera 987, and the like. This mobile phone has a touch sensor on the display portion 982. By touching the display portion 982 with a finger or a stylus, various operations such as making a call and inputting text can be performed. As one of the components for capturing images in this mobile phone, a camera device according to one embodiment of the present invention can be included.

[0205] Figure 15FIG. (F) shows a portable data terminal including a housing 911, a display unit 912, and a camera 919. Information can be input and output using the touch panel function of the display unit 912. This portable data terminal may include an imaging device according to one embodiment of the present invention as one of the components for capturing images.

[0206] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0207] In this specification, etc., a display element, a display device including a display element, a light-emitting element, and a light-emitting device including a light-emitting element may be implemented in various ways or include various elements. For example, the display element, display device, light-emitting element, or light-emitting device may include at least one of an EL (electroluminescent) element (including organic and inorganic EL elements, organic EL elements, and inorganic EL elements), an LED chip (a white LED chip, a red LED chip, a green LED chip, a blue LED chip, etc.), a transistor (a transistor that emits light in response to an electric current), a plasma display panel (PDP), an electron emission element, a display element using carbon nanotubes, a liquid crystal element, electronic ink, an electrowetting element, an electrophoretic element, a display element using a MEMS (microelectromechanical system) (for example, a grating light valve (GLV), a digital micromirror device (DMD), a DMS (digital micromirror device), MIRASOL (registered trademark in Japan), an IMOD (interferometric modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, a piezoelectric ceramic display, etc.), and a quantum dot. In addition, display elements, display devices, light-emitting elements, or light-emitting devices may also include display media whose contrast, brightness, reflectivity, transmittance, and other characteristics vary due to electrical or magnetic effects. Examples of display devices using EL elements include EL displays. Examples of display devices using electron-emitting elements include field emission displays (FEDs) or SED flat-panel displays (SEDs). Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive, semi-transmissive, reflective, direct-view, and projection liquid crystal displays). Examples of display devices using electronic ink, electronic powder (a registered trademark in Japan), or electrophoretic elements include electronic paper. Examples of display devices using quantum dots in each pixel include quantum dot displays. Quantum dots can be used as part of a backlight, rather than as display elements. The use of quantum dots enables displays with high color purity. Note that when implementing a semi-transmissive or reflective liquid crystal display, some or all of the pixel electrodes can function as reflective electrodes. For example, part or all of the pixel electrode can be made of aluminum, silver, or the like. Furthermore, a memory circuit such as an SRAM can be placed beneath the reflective electrode. This can further reduce power consumption. Note that when using an LED chip, graphene or graphite can also be placed beneath the LED chip's electrodes or nitride semiconductors. Graphene or graphite can also be a multilayer film with multiple layers stacked on top of each other. By placing graphene or graphite, it is easier to form a nitride semiconductor, such as a crystalline n-type GaN semiconductor layer, thereon.Furthermore, a p-type GaN semiconductor layer having crystallization is provided thereon, thereby being able to constitute an LED chip. In addition, an AlN layer may be provided between graphene or graphite and the n-type GaN semiconductor layer having crystallization. In addition, the GaN semiconductor layer included in the LED chip may also be formed by MOCVD. Note that the GaN semiconductor layer included in the LED chip may also be formed by sputtering by providing graphene. In addition, in a display element using MEMS, by disposing a desiccant in a space where the display element is sealed (for example, between an element substrate on which the display element is provided and an opposing substrate opposite to the element substrate), it is possible to prevent the MEMS etc. from malfunctioning or deteriorating due to moisture.

[0208] Note that this embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0209] (Supplementary Notes Regarding the Descriptions in This Manual, etc.)

[0210] Below, comments are added to each structure and description in the above-mentioned embodiment.

[0211] <Supplementary Notes on One Mode of the Invention Shown in the Embodiment>

[0212] The structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one embodiment of the present invention. In addition, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0213] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in that embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0214] Note that the contents described in the embodiments refer to the contents described in the various drawings in each embodiment or the contents described in the text described in the specification.

[0215] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one figure (or part thereof) shown in one or more other embodiments.

[0216] <Note on Ordinal Numbers>

[0217] In this specification, etc., ordinal numbers such as "first," "second," and "third" are added to avoid confusion between constituent elements. Therefore, they are not added to limit the number of constituent elements. In addition, they are not added to limit the order of constituent elements. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments of this specification, etc. may have the ordinal number "second" attached in another embodiment or claim. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments of this specification, etc. may have the ordinal number "first" omitted in another embodiment or claim.

[0218] <Supplementary Notes Regarding Description of the Drawings>

[0219] The embodiments are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different forms, and their methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same figure marks are used in different drawings to show the same parts or parts with the same functions, and repeated descriptions are omitted.

[0220] For convenience, in this specification and other descriptions, terms such as "upper" and "lower" are used to describe the positional relationships of components with reference to the accompanying drawings. The positional relationships of the components may vary depending on the orientation in which they are described. Therefore, terms and expressions describing the positional relationships are not limited to those shown in this specification and may be appropriately changed depending on the circumstances.

[0221] Furthermore, the terms "above" and "below" do not limit components to being positioned "directly above" or "directly below" and in direct contact. For example, a description such as "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with the insulating layer. The description also includes situations where other components are located between insulating layer A and electrode B.

[0222] In the drawings, dimensions, layer thicknesses, and regions may be exaggerated for clarity. Therefore, the present invention is not necessarily limited to the dimensions shown above. The drawings show arbitrary dimensions for clarity and are not limited to the shapes or numerical values shown. For example, variations in signals, voltages, or currents caused by noise or timing variations may be included.

[0223] In drawings such as perspective views, some components may be omitted for clarity.

[0224] In the drawings, the same reference numerals may be used to indicate the same components, components having the same function, components made of the same material, components formed simultaneously, and the like, and repeated descriptions may be omitted.

[0225] <Supplementary Notes on Records That May Be Renamed>

[0226] In this specification, etc., when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and the drain" (first electrode or first terminal), and the other of the source and the drain is referred to as "the other of the source and the drain" (second electrode or second terminal). This is because the source and drain of the transistor are interchangeable depending on the structure or operating conditions of the transistor. The source and drain of the transistor can be appropriately renamed as the source (drain) terminal, the source (drain) electrode, etc., depending on the situation. In addition, in this specification, etc., the two terminals other than the gate are sometimes referred to as the first terminal and the second terminal or the third terminal and the fourth terminal. In addition, when a transistor described in this specification, etc. has more than two gates (this structure is sometimes referred to as a dual-gate structure), the gate is sometimes referred to as the first gate, the second gate, the front gate, or the back gate. In particular, the "front gate" can be simply replaced by the "gate". In addition, the "back gate" can be simply replaced by the "gate". In addition, a “bottom gate” refers to a terminal formed before a channel formation region is formed when forming a transistor, and a “top gate” refers to a terminal formed after a channel formation region is formed when forming a transistor.

[0227] A transistor consists of three terminals: a gate, a source, and a drain. The gate serves as a control terminal that controls the transistor's conduction state. Of the two input / output terminals that function as a source or drain, one terminal functions as a source and the other as a drain, depending on the type of transistor or the potential level supplied to each terminal. Therefore, in this specification and other text, "source" and "drain" may be interchanged.

[0228] Note that in this specification and other contexts, the terms "electrode" and "wiring" do not functionally limit the components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also encompass situations where multiple "electrodes" or "wirings" are integrated.

[0229] In this specification and other publications, the terms "voltage" and "potential" may be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, when the reference potential is ground potential, voltage can be referred to as "potential." Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., may vary depending on the reference potential.

[0230] In this specification, etc., the terms "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be replaced with "conductive film." Also, "insulating film" may be replaced with "insulating layer." Furthermore, depending on the situation or state, other terms may be used in place of the terms "film" and "layer." For example, "conductive layer" or "conductive film" may be replaced with "conductive body." Also, for example, "insulating layer" or "insulating film" may be replaced with "insulator."

[0231] In this specification, etc., the terms "wiring," "signal line," and "power line" can be interchanged depending on the situation or status. For example, "wiring" can sometimes be replaced with "signal line." Also, for example, "wiring" can sometimes be replaced with "power line." Vice versa, "signal line" or "power line" can sometimes be replaced with "wiring." Sometimes "power line" can be replaced with "signal line." Vice versa, "signal line" can sometimes be replaced with "power line." Furthermore, depending on the situation or status, the "potential" applied to the wiring can be replaced with "signal." Vice versa, "signal" can sometimes be replaced with "potential."

[0232] <Notes on Definitions of Terms and Phrases>

[0233] The following describes the definitions of the words and phrases involved in the above-mentioned embodiments.

[0234] On Impurities in Semiconductors

[0235] Impurities of a semiconductor are, for example, substances other than the main components that constitute the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. Sometimes, due to the inclusion of impurities, DOS (Density of States) is formed in the semiconductor, carrier mobility is reduced, or crystallinity is reduced. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group I elements, Group II elements, Group XIII elements, Group XIV elements, Group XV elements, or transition metals other than the main components, in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, for example, the mixing of impurities such as hydrogen sometimes leads to the generation of oxygen defects. In addition, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group I elements other than hydrogen, Group II elements, Group XIII elements, Group XV elements, etc.

[0236] "transistor"

[0237] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). By applying a voltage exceeding the threshold voltage between the gate and source, a channel is formed in the channel formation region, allowing current to flow between the source and drain.

[0238] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0239] "switch"

[0240] In this specification, etc., a switch refers to an element that controls whether current flows by switching to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element that selects and switches a current path.

[0241] For example, an electric switch or a mechanical switch can be used. In other words, the switch is not limited to a specific switch as long as it can control the current.

[0242] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits combining these elements.

[0243] When a transistor is used as a switch, the transistor's "on state" refers to a state in which the source and drain electrodes of the transistor are electrically short-circuited. On the other hand, the transistor's "off state" refers to a state in which the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conductivity type).

[0244] An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology such as a digital micromirror device (DMD). This switch has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0245] "connect"

[0246] Note that in this specification, "X and Y are connected" encompasses the following: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or the text, and include connections other than those shown in the drawings or the text.

[0247] X and Y used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0248] As an example of electrically connecting X and Y, one or more elements capable of electrically connecting X and Y (e.g., switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) may be connected between X and Y. Furthermore, a switch has the function of controlling on and off. In other words, whether or not current flows is controlled by placing the switch in a conducting state (on) or a non-conducting state (off).

[0249] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generating circuits, storage circuits, control circuits, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0250] Furthermore, when it is explicitly stated that "X is electrically connected to Y," this includes the following: X is electrically connected to Y (in other words, X and Y are connected with another element or other circuit interposed therebetween); X and Y are functionally connected (in other words, X and Y are functionally connected with another circuit interposed therebetween); and X and Y are directly connected (in other words, X and Y are connected without any other element or other circuit interposed therebetween). In other words, when "electrically connected" is explicitly stated, the same thing applies as when "connected" is simply explicitly stated.

[0251] Note that, for example, in the case where the source (or first terminal, etc.) of the transistor is electrically connected to X via Z1 (or not via Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 (or not via Z2), and in the case where the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be displayed as follows.

[0252] For example, it can be expressed as “X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y.” Alternatively, it can be expressed as “the source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y.” Alternatively, it can be expressed as “X is electrically connected to Y via the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are arranged to be connected to each other in this order.” By specifying the connection order in the circuit structure using the same expression method as this example, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor can be distinguished from each other, thereby determining the technical scope. Note that these expressions are merely examples and are not limited to the above expressions. Here, X, Y, Z1, and Z2 are objects (eg, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0253] Furthermore, even when independent components are electrically connected on a circuit diagram, a single component may sometimes perform the functions of multiple components. For example, when a portion of a wiring serves as an electrode, a single conductive film may perform the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also encompasses situations where a single conductive film performs the functions of multiple components.

[0254] "Parallel, Perpendicular"

[0255] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0256] [Explanation of symbols]

[0257] 10: Camera, 11: Driver, 12: Driver, 13: Driver, 31: Conductive layer, 32: Conductive layer, 33: Conductive layer, 34: Conductive layer, 35: Back gate, 36: Region, 37: Conductive layer, 40: Silicon substrate, 41: Insulating layer, 42: Insulating layer, 43: Insulating layer, 45: Semiconductor layer, 46: Insulating layer, 80: Insulating layer, 81: Light shielding layer, 82: Organic resin layer, 83: Color filter, 83a: Color filter, 83b: Color filter, 83c: Color filter, 84: Microlens array, 85: Optical conversion layer, 86: Insulating layer, 100: Pixel, 100a: Output terminal, 100b: Output terminal, 101: Photoelectric conversion element, 102: Transistor, 103: Crystal Transistor, 104: Capacitor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Transistor, 111: Wiring, 112: Wiring, 113a: Wiring, 113b: Wiring, 113c: Wiring, 113d: Wiring, 114: Wiring, 115: Wiring, 117: Wiring, 118: Wiring, 119: Wiring, 200: Pooling module, 203: Switch, 204: Switch, 210: Pooling circuit, 210a: Wiring, 211: Wiring, 211a: Wiring, 211b: Wiring, 212: Arithmetic circuit, 212a: Transistor, 212b: Transistor, 212c: Transistor, 220: Comparison module, 221: Determination circuit, 221a: Input terminal , 221b: input terminal, 221c: output terminal, 223a: transistor, 223b: transistor, 224a: input terminal, 224b: output terminal, 230: comparison circuit, 230a: comparison circuit, 230b: comparison circuit, 230c: comparison circuit, 231a: input terminal, 231b: input terminal, 231c: output terminal, 232: wiring, 236: transistor, 241: transistor, 242: transistor, 243: transistor, 244: transistor, 245: transistor, 246: transistor, 250: analog-to-digital conversion circuit, 251: output circuit, 410: packaging substrate, 411: packaging substrate, 420: glass cover, 421: lens cover, 43 0: Adhesive, 435: Lens, 440: Bump, 441: Connector, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode pad, 470: Lead, 471: Lead, 490: IC chip, 911: Housing, 912: Display, 919: Camera, 932: Display, 933: Housing and wristband, 939: Camera, 951: Bracket, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light-emitting unit, 971: Housing, 972: Housing, 973: Display, 974: Operation key, 975: Lens, 976: Connector,981: Housing, 982: Display, 983: Operation buttons, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

1. A photographing device, comprising: Multiple pixels in the capture area; as well as A current mirror circuit includes a first transistor and a second transistor, wherein the plurality of pixels and the current mirror circuit are stacked, the plurality of pixels comprising a first plurality of pixels and a second plurality of pixels, One of a source and a drain of the first transistor is electrically connected to a first wiring to which a current based on an analog signal obtained from the first plurality of pixels is input, The one of the source and the drain of the first transistor is electrically connected to the gate of the first transistor, The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, The other of the source and the drain of the second transistor is electrically connected to a second wiring to which a current based on an analog signal obtained from the second plurality of pixels is input, and A gate of the second transistor is electrically connected to the gate of the first transistor.

2. The photographing device according to claim 1, wherein the transistors included in the plurality of pixels are n-channel transistors, and The first transistor and the second transistor are p-channel transistors.

3. A photographing device comprising: Shooting area; as well as A current mirror circuit includes a first input terminal and a second input terminal, Wherein, the shooting area and the current mirror circuit are stacked, A first analog signal obtained from a pixel portion in the photographing area is input to the first input terminal, A second analog signal obtained from the pixel portion in the photographing area is input to the second input terminal, and At least one of the first analog signal or the second analog signal is a current obtained by averaging currents based on analog signals obtained by a plurality of pixels included in the pixel portion.

4. The photographing device according to claim 3, wherein the transistors included in the plurality of pixels are n-channel transistors, and The transistors included in the current mirror circuit are p-channel transistors.

5. A camera device comprising pixels, wherein the pixels include: Photoelectric conversion element; first to third transistors; as well as capacitors, wherein one of the source and the drain of the first transistor is electrically connected to the photoelectric conversion element, The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the capacitor, and The other electrode of the capacitor is electrically connected to one of a source and a drain of the third transistor.

6. A camera device comprising pixels, wherein the pixels include: Photoelectric conversion element; first to fourth transistors; as well as capacitors, wherein one of the source and the drain of the first transistor is electrically connected to the photoelectric conversion element, The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and the drain of the fourth transistor, and one electrode of the capacitor, and The other electrode of the capacitor is electrically connected to one of a source and a drain of the third transistor.

7. The photographing device according to claim 5 or 6, wherein weight data is supplied to the other of the source and the drain of the third transistor.

8. A photographing device comprising: First to fourth pixels in the photographing area; first and second operational circuits; as well as Comparator circuit, wherein the output terminal of the first pixel and the output terminal of the second pixel are electrically connected to the input terminal of the first operation circuit, The output terminal of the third pixel and the output terminal of the fourth pixel are electrically connected to the input terminal of the second operation circuit, An output terminal of the first operation circuit is electrically connected to a first input terminal of the comparison circuit, and An output terminal of the second operation circuit is electrically connected to a second input terminal of the comparison circuit.

9. A photographing device comprising: First to fourth pixels each including a photoelectric conversion element; first and second operational circuits; as well as Comparator circuit, wherein the output terminal of the first pixel and the output terminal of the second pixel are electrically connected to the input terminal of the first operation circuit, The output terminal of the third pixel and the output terminal of the fourth pixel are electrically connected to the input terminal of the second operation circuit, An output terminal of the first operation circuit is electrically connected to a first input terminal of the comparison circuit, and An output terminal of the second operation circuit is electrically connected to a second input terminal of the comparison circuit.

10. The photographing device according to claim 8 or 9, wherein the comparison circuit is configured to output a higher signal of a first signal supplied to the first input terminal of the comparison circuit and a second signal supplied to the second input terminal of the comparison circuit.

Images