Memory, stack structure thereof and logic chip stack

Abstract

The invention discloses a memory and a stack structure and a logic chip stack thereof, the logic chip stack comprises a logic chip, and the logic chip comprises a physical layer; the logic chip is arranged on the physical layer, the box magazine capacitor array chip and the logic chip are arranged in a stacked mode, the box magazine capacitor array chip comprises a box magazine capacitor unit, the box magazine capacitor unit comprises a box magazine capacitor, and the box magazine capacitor is connected with the physical layer. The physical layer of the logic chip is connected with the magazine capacitor, so that the arrangement of the capacitor in the logic chip can be reduced or even omitted, and the area overhead required for arranging the capacitor in the logic chip can be effectively saved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a memory and a stacking structure thereof and a logic chip stack. Background Art

[0002] High-bandwidth memory (HBM) is an evolution of traditional dynamic random access memory (DRAM) technology. It utilizes 3D stacking technology, vertically stacking multiple DRAM chips and interconnecting them via through-silicon vias (TSVs). HBM offers advantages such as high bandwidth, low latency, and low power consumption, making it widely used in high-performance computing, graphics processing, and artificial intelligence.

[0003] Compared with traditional memory, HBM's bandwidth has been significantly improved. However, in order to match the high-bandwidth characteristics, the logic chip in HBM requires a considerable area to set up capacitors, and the area overhead required to set up capacitors in the logic chip is relatively large. Summary of the Invention

[0004] The problem solved by the present invention is how to save the area overhead required for capacitors in a memory logic chip.

[0005] To solve the above problems, the present invention provides a memory logic chip stack, comprising:

[0006] Logic chip, the logic chip includes: a physical layer; a magazine capacitor array chip, the magazine capacitor array chip and the logic chip are stacked, the magazine capacitor array chip includes: a magazine capacitor unit, the magazine capacitor unit includes: a magazine capacitor, and the magazine capacitor is connected to the physical layer.

[0007] Optionally, the magazine capacitor unit also includes: a capacitor switch, the capacitor switch is located in the well area of the magazine capacitor unit, the capacitor switch includes: a control end and two connection ends, the control end is suitable for controlling conduction and cutoff between the two connection ends; the magazine capacitor is connected to one connection end of the capacitor switch.

[0008] Optionally, the magazine capacitor array chip includes: a magazine capacitor array, the magazine capacitor array includes: first magazine capacitor units arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are parallel to the surface of the magazine capacitor array chip and intersect; second magazine capacitor units, the second magazine capacitor units are distributed at positions outside the magazine capacitor array.

[0009] Optionally, the second magazine capacitor units are distributed on both sides of the magazine capacitor array.

[0010] Optionally, the second magazine capacitor units are distributed between adjacent magazine capacitor arrays.

[0011] Optionally, the first magazine capacitor unit and the second magazine capacitor unit are the same magazine capacitor unit; or, the first magazine capacitor unit and the second magazine capacitor unit only have different doping types of the magazine capacitor unit well regions; or, at least one of the first magazine capacitor unit and the second magazine capacitor unit does not have a capacitor switch.

[0012] Optionally, the magazine capacitor array chip further includes: a magazine capacitor array bit line, the magazine capacitor array bit line is connected to the magazine capacitor; and the physical layer is connected to the magazine capacitor through the magazine capacitor array bit line.

[0013] Optionally, the logic chip includes: a capacitor turn-on circuit, and the capacitor turn-on circuit is connected to the control end of the capacitor switch.

[0014] Optionally, the magazine capacitor array chip also includes: a magazine capacitor array word line, which is connected to the control end of the capacitor switch in the magazine capacitor unit; the magazine capacitor array chip also includes: a magazine capacitor array main word line, which is connected to all magazine capacitor array word lines; and the capacitor turn-on circuit is connected to the magazine capacitor array main word line.

[0015] Accordingly, the present invention further provides a memory stack structure, comprising:

[0016] Logic chip stacking, the logic chip stacking is the logic chip stacking of the present invention; storage array chip, the storage array chip and the logic chip are stacked.

[0017] Optionally, the storage array chip and the magazine capacitor array chip are the same chip.

[0018] Optionally, it also includes: memory chip stacking, the memory chip stacking includes: memory array chip; the memory chip stacking also includes: peripheral chip, the peripheral chip and memory chip are stacked.

[0019] Optionally, the storage array chip includes: a storage array, the storage array includes: storage cells arranged in an array, the storage cells include: storage cell capacitors; the magazine capacitor and the storage cell capacitor are the same capacitor.

[0020] Optionally, the storage unit also includes: a storage switch, the storage switch is located in the storage cell well area, the storage switch includes: a control end and two connection ends, the control end is suitable for controlling conduction and cutoff between the two connection ends, the storage cell capacitor is connected to one connection end of the storage switch; the capacitor switch of the magazine capacitor unit and the storage switch of the storage cell are the same switch.

[0021] Optionally, the first magazine capacitor unit and the storage unit of the magazine capacitor array chip are the same unit.

[0022] Optionally, the first magazine capacitor units are distributed in the same manner as the storage units.

[0023] Optionally, the memory array chip further includes: a peripheral dummy memory unit, the peripheral dummy memory unit includes: a dummy memory unit capacitor; the second magazine capacitor unit of the magazine capacitor array chip and the peripheral dummy memory unit are the same unit.

[0024] Optionally, the second magazine capacitor units are distributed in the same manner as the peripheral pseudo storage units.

[0025] Optionally, the storage array chip is connected to the physical layer of the logic chip.

[0026] In addition, the present invention further provides a memory, comprising:

[0027] The stacking structure is the stacking structure of the present invention; the processing chip is connected to the physical layer of the logic chip in the logic chip stack in the stacking structure.

[0028] Optionally, the logic chip includes: a first physical layer and a second physical layer; the first physical layer is connected to the storage array chip; and the second physical layer is connected to the processing chip.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the technical solution of the present invention, a logic chip stack includes a magazine capacitor array chip disposed therewith. The magazine capacitor units arranged in an array within the magazine capacitor array chip include magazine capacitors connected to the physical layer of the logic chip. The connection between the physical layer of the logic chip and the magazine capacitors can reduce or even eliminate the need for capacitors within the logic chip, effectively saving the area overhead required for capacitors within the logic chip.

[0031] In an optional solution of the present invention, the magazine capacitor array chip has the same structure as the storage array chip. By setting the magazine capacitor array chip to have the same structure as the storage array chip, the magazine capacitor array chip can be realized by utilizing the storage array chip without having to redesign and manufacture the magazine capacitor array chip, effectively controlling process and manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the cross-sectional structure of some memories;

[0033] Figure 2 It is a schematic diagram of the structure of storage array chips and logic chips in some memories;

[0034] Figure 31 is a schematic cross-sectional view of a first embodiment of a logic chip stack of a memory device according to the present invention;

[0035] Figure 4 1 is a schematic top view of the structure of the magazine capacitor array chip and the logic chip in the second embodiment of the logic chip stack of the memory of the present invention;

[0036] Figure 5 1 is a schematic cross-sectional structural diagram of a magazine capacitor unit in a third embodiment of a logic chip stack of a memory device according to the present invention;

[0037] Figure 6 1 is a schematic top view of the structure of a magazine capacitor array chip and a logic chip in a fourth embodiment of a logic chip stack of a memory device according to the present invention;

[0038] Figure 7 1 is a schematic top view of the structure of a magazine capacitor array chip and a logic chip in a fifth embodiment of a logic chip stack of a memory device according to the present invention;

[0039] Figure 8 1 is a schematic cross-sectional structural diagram of a first magazine capacitor unit in a sixth embodiment of a logic chip stack of a memory according to the present invention;

[0040] Figure 9 FIG1 is a schematic cross-sectional structural diagram of a second magazine capacitor unit in a seventh embodiment of a logic chip stack of a memory device according to the present invention;

[0041] Figure 10 1 is a schematic top view of the structure of the stack of the magazine capacitor array chip and the logic chip in the eighth embodiment of the memory of the present invention;

[0042] Figure 11 1 is a schematic cross-sectional structural diagram of a magazine capacitor unit in a ninth embodiment of a logic chip stack of a memory device according to the present invention;

[0043] Figure 12 1 is a schematic cross-sectional structural diagram of a magazine capacitor unit in a tenth embodiment of a logic chip stack of a memory according to the present invention;

[0044] Figure 13 1 is a schematic cross-sectional view of a first embodiment of a stacked structure of a memory device according to the present invention;

[0045] Figure 14 1 is a schematic top view of a memory array chip in a second embodiment of a stacked structure of a memory according to the present invention;

[0046] Figure 15 is a schematic cross-sectional view of a third embodiment of a stacked structure of a memory device according to the present invention;

[0047] Figure 16 FIG. 1 is a schematic top view of the memory chip stacking structure in the fourth embodiment of the memory stacking structure of the present invention. DETAILED DESCRIPTION

[0048] As can be seen from the background art, the logic chip in the prior art has the problem of large area overhead required for setting capacitors.

[0049] refer to Figure 1 , showing a schematic diagram of the cross-sectional structure of some memories.

[0050] The memory is a high-bandwidth memory and includes a stacked package substrate pkg, an interposer inter, a logic chip logic, a processing chip sys, and a memory array chip stack 11.

[0051] The interposer inter is located on the surface of the packaging substrate pkg and is electrically connected to the packaging substrate pkg; the logic chip logic and the processing chip sys are respectively located on the surface of the interposer inter, and the logic chip logic and the processing chip sys are electrically connected through the interposer inter; the storage array chip stack 11 is located on the surface of the logic chip logic and is electrically connected to the logic chip logic.

[0052] The memory chip stack 11 includes: a plurality of memory array chips 12 stacked together, the memory array chip 12 includes: an array area ar and a peripheral area per, the array area ar includes a memory array array (such as Figure 2 As shown), the peripheral area per includes peripheral circuit periphery (such as Figure 2 As shown in FIG, the array region ar and the peripheral region per are arranged in a direction parallel to the surface of the memory array chip. Different memory array chips 12 are bonded together through silicon vias (not shown) in the peripheral region per to achieve electrical connection.

[0053] The logic chip logic includes: a first physical layer phy1 and a second physical layer phy2. The first physical layer phy1 is bonded to the silicon through-via in the peripheral area pher in the nearest storage array chip 12 to achieve electrical connection. The second physical layer phy2 is bonded to the intermediate layer inter and electrically connected to the third physical layer phy in the system chip sys through the intermediate layer inter.

[0054] Combined with reference Figure 2 , showing a schematic structural diagram of storage array chips and logic chips in some memories.

[0055] like Figure 2As shown, the memory array chip 12 further includes: a first capacitor area cp1 and a second capacitor area cp2. The capacitor of the first capacitor area cp1 is a local power supply capacitor of the memory array chip and is electrically connected to the peripheral circuit periphery in the memory array chip. The capacitor of the second capacitor area cp2 is a capacitor of the logic chip logic and is electrically connected to the logic chip logic.

[0056] In the memory array chip 12, the first capacitor region cp1, the second capacitor region cp2, and the peripheral region per are all located on the same side of the memory array array. In the logic chip logic, the first physical layer phy1 and the second physical layer phy2 are arranged parallel to the surface of the logic chip logic; the capacitor of the second capacitor region cp2 is electrically connected to the first physical layer phy1, which is closer.

[0057] The distance between the second capacitor region cp2 and the second capacitor region cp2 is relatively far. If the second capacitor region cp2 and the second capacitor region cp2 are connected to each other (eg Figure 2 If the ESR is too low, the memory performance will be degraded. Figure 2 As shown, the logic chip logic further includes: a third capacitor area cp3, and the third capacitor area cp3 is electrically connected to the second physical layer phy2, that is, the third capacitor area cp3 needs to occupy the area of the logic chip logic.

[0058] In addition, the capacitors in the third capacitor region cp3 are generally metal-oxide-metal capacitors (MOMcap) and metal-oxide-semiconductor capacitors (MOScap) on the chip. The capacitance density of each layer of MOM capacitor is usually less than 10fF / μm. 2 The capacitance density of each metal-oxide-semiconductor capacitor is about 10~20 fF / μm 2 .

[0059] To meet the functional requirements of the second physical layer phy2, the total capacitance of the capacitors in the third capacitor region cp3 is approximately in the nF range. This requires a larger area to meet technical requirements. Therefore, the area overhead of the third capacitor region cp3 in the logic chip is significant.

[0060] To address this technical problem, the present invention provides a memory stack structure. The logic chip stack includes a magazine capacitor array chip disposed within the logic chip stack. The magazine capacitor units arranged in an array within the magazine capacitor array chip include magazine capacitors connected to the physical layer of the logic chip. The connection between the physical layer of the logic chip and the magazine capacitors can reduce or even eliminate the need for capacitors within the logic chip, effectively saving the area overhead required for capacitor configuration within the logic chip.

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0062] refer to Figure 3 , showing a schematic cross-sectional structure diagram of some embodiments of the logic chip stack of the memory of the present invention.

[0063] The memory-logic chip stack includes:

[0064] Logic chip 110, logic chip 110 includes: a physical layer 111; a magazine capacitor array chip 120, the magazine capacitor array chip 120 is stacked with the logic chip 110, the magazine capacitor array chip 120 includes: magazine capacitor units 121 arranged in an array, the magazine capacitor unit 121 includes: magazine capacitors 122, and the magazine capacitors 122 are connected to the physical layer 111.

[0065] By adding a magazine capacitor array chip 120, the physical layer 111 of the logic chip 110 is connected to the magazine capacitor 122 in the magazine capacitor unit 121 arranged in an array in the magazine capacitor array chip 120, and the magazine capacitor 122 is used for data transmission. There is no need to set up additional capacitors in the logic chip 110, which can effectively save the area overhead of the logic chip 110.

[0066] The technical solution of an embodiment of memory logic chip stacking will be described in detail below with reference to the accompanying drawings.

[0067] In a logic chip stack, the logic chip includes logic circuits to perform basic logic operations and perform signal processing and conversion. The physical layer in the logic chip is used to achieve electrical connections with other chips.

[0068] Specifically, the physical layer may include one or more of a low dropout regulator (LDO), a bandgap reference (BG), a voltage reference (Vref), and an input / output (I / O) structure.

[0069] Specific as Figure 3In some of the illustrated embodiments, the logic chip 110 includes a physical layer 111 .

[0070] Combined with reference Figure 4 , showing a schematic diagram of the top view of the structure of the magazine capacitor array chip and the logic chip in some embodiments of the logic chip stack of the memory of the present invention.

[0071] In some embodiments of the present invention, the physical layer of a logic chip includes a first physical layer and a second physical layer. Specifically, the first physical layer is used to connect to a memory array chip of a memory to read data stored in the memory array chip; the second physical layer is used to connect to a system chip to receive signals generated by the system chip.

[0072] In some exemplary embodiments, the first physical layer may include: a first low-dropout linear regulator, a first bandgap reference source, a first reference voltage source, and a first input-output structure; the second physical layer may include: a second low-dropout linear regulator, a second reference voltage source, and a second input-output structure.

[0073] Specific as Figure 4 In some illustrated embodiments, logic chip 110 includes a first physical layer 111a and a second physical layer 111b, which are arranged parallel to the surface of logic chip 110. The first physical layer 111a includes a through-silicon-valve (TSV) physical layer (PHY) for connecting to a memory array chip; the second physical layer 111b is electrically connected to a memory interposer for connecting to the system chip.

[0074] Continue to refer Figure 3 and Figure 4 In the logic chip, the magazine capacitor array chip is electrically connected to the physical layer of the logic chip to provide capacitance for the physical layer.

[0075] Specifically, the magazine capacitor array chip and the logic chip are stacked together. In some embodiments, the magazine capacitor array chip and the logic chip can be electrically connected using at least one of through-silicon-vias (TSVs), microbumps, or hybrid bonding.

[0076] For example, Figure 3 In some embodiments shown, the magazine capacitor array chip 120 is located on a side surface of the logic chip 110. The magazine capacitor array chip 120 and the logic chip 110 are electrically connected via through-silicon vias 120a, microbumps 120b, and hybrid bonding 120c.

[0077] The magazine capacitor array chip includes a magazine capacitor unit, which includes a magazine capacitor, and the magazine capacitor is electrically connected to the physical layer.

[0078] Magazine capacitor units are widely distributed in magazine capacitor array chips. Using virtual unit capacitors in the magazine capacitor units to form the physical layer capacitors of the logic chip can effectively shorten the interconnection distance and is less likely to cause problems related to equivalent series resistance. Moreover, there is no need to set on-chip capacitors in the logic chip, which can effectively save the area used by the capacitors in the logic chip and effectively reduce the area overhead of the logic chip.

[0079] Combined with reference Figure 5 , showing a schematic cross-sectional structure diagram of a magazine capacitor unit in some embodiments of the logic chip stack of the memory of the present invention.

[0080] In some embodiments of the present invention, the magazine capacitor unit also includes: a capacitor switch, the capacitor switch is located in the well area of the magazine capacitor unit, the capacitor switch includes: a control end and two connection ends, the control end is suitable for controlling the conduction and cutoff between the two connection ends; the magazine capacitor is connected to one connection end of the capacitor switch.

[0081] In some embodiments of the present invention, the memory employs a 1T1C structure, meaning that a single storage cell in the memory includes a storage switch and a storage cell capacitor. By configuring the magazine capacitor unit to include a magazine capacitor and a capacitor switch, the magazine capacitor unit's structure more closely resembles that of a storage cell in the memory, eliminating the need for a separate magazine capacitor array chip and effectively reducing process and manufacturing costs.

[0082] Moreover, the capacitance density of the memory cell capacitor in the memory cell is about pF / μm 2 The area efficiency of the storage unit capacitor is orders of magnitude higher than that of the on-chip capacitor, making the structure of the magazine capacitor unit close to the structure of the storage unit in the memory. The virtual unit capacitor has the same structure as the storage unit capacitor and has a higher capacitance density. The area efficiency of the capacitor provided by the magazine capacitor array chip is high, and the magazine capacitor array chip can meet the needs of the logic chip without additional process, which is conducive to reducing process cost and manufacturing cost.

[0083] like Figure 5 In some embodiments shown, the capacitor switch 123 is a transistor, and the capacitor switch 123 includes: a gate located on the magazine capacitor unit well region 123w and source and drain doped regions located in the magazine capacitor unit well region 123w on both sides of the gate.

[0084] Specifically, the gate is the control terminal of the capacitor switch 123 , and the two source and drain doping regions are two connection terminals, wherein one source and drain doping region is connected to the magazine capacitor 122 .

[0085] Continue to refer Figure 4 In some embodiments of the present invention, a magazine capacitor array chip includes: a magazine capacitor array, the magazine capacitor array includes: first magazine capacitor units arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are parallel to and intersect with the surface of the magazine capacitor array chip; second magazine capacitor units, the second magazine capacitor units are distributed at positions outside the magazine capacitor array.

[0086] The first magazine capacitor units correspond to the storage cells within the memory array chip used to store data, and the distribution of the first magazine capacitor units is consistent with the distribution of the storage cells. Specifically, in a plane parallel to the surface of the magazine capacitor array chip, the first magazine capacitor units are arranged in an array to form a magazine capacitor array.

[0087] like Figure 4 In some of the embodiments shown, the first magazine capacitor units 121a are arranged in an array along a first direction x and a second direction y that are perpendicular to each other to form a magazine capacitor array 124, wherein the first direction x and the second direction y are the row direction and the column direction of the magazine capacitor array 124, respectively.

[0088] like Figure 4 As shown, the first magazine capacitor unit 121a is widely distributed in the magazine capacitor array chip 120; in the logic chip 110, the first physical layer 111a and the second physical layer 111b can be connected to the first magazine capacitor unit 121a at different positions, and the interconnection distance between different physical layers and the connected first magazine capacitor unit 121a is limited, which can effectively reduce the probability of equivalent series resistance-related problems.

[0089] Moreover, the first magazine capacitor unit 121a corresponds to a storage unit for storing data in a storage array chip in a memory, the magazine capacitor 122 has the same capacitance as the storage unit capacitor in the storage unit, and the virtual unit capacitor 122 has a higher capacitance density. A smaller number of virtual unit capacitors 122 can meet the requirements of the physical layer, which can reduce process costs and manufacturing costs while ensuring the function of the logic circuit.

[0090] Continue to refer Figure 4 In some embodiments of the present invention, the magazine capacitor array chip further includes: a magazine capacitor array bit line, the magazine capacitor array bit line is connected to the magazine capacitor; and the physical layer is connected to the magazine capacitor through the magazine capacitor array bit line.

[0091] The magazine capacitor array bit line is used to realize the electrical connection between the magazine capacitor and the physical layer. One end of the magazine capacitor array bit line is electrically connected to the magazine capacitor and the other end is electrically connected to the physical layer.

[0092] The electrical connection between magazine capacitors in the magazine capacitor unit is achieved through the magazine capacitor array bit line, so that the structure of the magazine capacitor array chip is similar to that of the storage array chip in the memory. There is no need to design an additional magazine capacitor array chip, which can effectively reduce process costs and manufacturing costs.

[0093] In some embodiments, the magazine capacitor unit includes a capacitor switch and a virtual unit capacitor connected to one connection terminal of the capacitor switch; the magazine capacitor array bit line is connected to the other connection terminal of the capacitor switch.

[0094] For example, Figure 5 In some embodiments shown, the magazine capacitor array bit lines 125 (e.g. Figure 5 The blue solid line in the middle is connected to the source-drain doped region of the capacitor switch 123 that is not connected to the magazine capacitor 122 .

[0095] In some embodiments of the present invention, the magazine capacitor array bit lines include: a first magazine capacitor array bit line, the first magazine capacitor array bit line corresponding to a bit line in a memory array chip of a memory. The distribution of the first magazine capacitor array bit line is consistent with the distribution of the bit lines in the memory array chip. The first magazine capacitor array bit line is connected to a first magazine capacitor unit in the magazine capacitor array.

[0096] like Figure 4 In some embodiments shown, the magazine capacitor array bit lines 125 (e.g. Figure 4 The plurality of magazine capacitor array bit lines 125 are arranged in parallel along the first direction x (as shown by the blue solid line in the middle direction); the plurality of first magazine capacitor units 121a arranged in sequence along the second direction y are all connected to the same magazine capacitor array bit line 125.

[0097] It should be noted that in some embodiments, the magazine capacitor array chip further includes: magazine capacitor array word lines. The magazine capacitor array word lines correspond to word lines within the memory array chip. The distribution of the magazine capacitor array word lines is consistent with the distribution of word lines within the memory array chip. The magazine capacitor array word lines are connected to the first magazine capacitor unit in the magazine capacitor array.

[0098] For example, Figure 4 In some of the embodiments shown, the magazine capacitor array word line 126 extends along a first direction x, and multiple magazine capacitor array word lines 126 are arranged in parallel along a second direction y; multiple first magazine capacitor units 121a arranged in sequence along the first direction x are all connected to the same magazine capacitor array word line 126.

[0099] It should be noted that, in some embodiments, the magazine capacitor array word line is connected to the control end of the capacitor switch in the magazine capacitor unit. Figure 5 As shown, in the capacitor switch 123, the magazine capacitor array word line 126 (such as Figure 5 The gate of the capacitor switch 123 is connected to the gate of the capacitor switch 123.

[0100] The magazine capacitor array chip also includes a second magazine capacitor unit. The second magazine capacitor unit corresponds to a peripheral pseudo storage unit within the memory array chip. The distribution of the second magazine capacitor unit is consistent with the distribution of the peripheral pseudo storage unit. Specifically, in a plane parallel to the surface of the magazine capacitor array chip, the second magazine capacitor unit is distributed outside the magazine capacitor array.

[0101] like Figure 4 As shown, in a plane parallel to the surface of the magazine capacitor array chip 120, the second magazine capacitor units 121b are distributed on one side of the magazine capacitor array 124. In some embodiments, the second magazine capacitor units 121b are also arranged in an array outside the magazine capacitor array.

[0102] In some embodiments of the present invention, the magazine capacitor array bit lines further include a second magazine capacitor array bit line (not shown in the figure). The second magazine capacitor array bit line corresponds to a connection line connected to a connection terminal of a peripheral dummy memory cell in a memory array chip of the memory.

[0103] In some embodiments of the present invention, the magazine capacitor array chip and the memory array chip of the memory are the same chip. The magazine capacitor array chip includes an array area (not labeled in the figure) and a peripheral area (not labeled in the figure). The array area includes the magazine capacitor array, and the peripheral area includes virtual peripheral circuits.

[0104] Specific as Figure 4 In some of the embodiments shown, the array region includes a magazine capacitor array 124, the peripheral region includes a dummy peripheral circuit 127, and the array region and the peripheral region are arranged in a direction parallel to the surface of the magazine capacitor array chip.

[0105] In some embodiments, the magazine capacitor array chip further includes: a first capacitor region and a second capacitor region. The first capacitor region includes dummy cells, each of which includes a dummy capacitor, and the dummy cells are connected to the peripheral circuit of the peripheral region. The second capacitor region includes a second magazine capacitor cell.

[0106] Specific as Figure 4 In some embodiments shown, in the magazine capacitor array chip 120, the peripheral area, the first capacitor area cp1 and the second capacitor area cp2 are arranged in sequence along the second direction y, and the peripheral area, the first capacitor area cp1 and the second capacitor area cp2 are all located on the same side of the array area along the first direction x.

[0107] like Figure 4As shown, even if the second magazine capacitor units 121b are all distributed on the same side of the magazine capacitor array 124, since the first magazine capacitor units 121a constituting the magazine capacitor array 124 are widely distributed, different physical layers in the logic chip 110 can also be connected to magazine capacitor units at different positions, which can effectively shorten the interconnection distance and effectively improve the problems related to equivalent series resistance.

[0108] It should be noted that in the above embodiment, the peripheral region, the first capacitor region cp1, and the second capacitor region cp2 of the magazine capacitor array chip 120 are all distributed on the same side of the magazine capacitor array 124. However, this layout of the magazine capacitor array chip is only an example. In other embodiments of the present invention, the magazine capacitor array chip can also be arranged in other ways.

[0109] Combined with reference Figure 6 , showing a schematic diagram of the top view of the structure of the magazine capacitor array chip and the logic chip in other embodiments of the logic chip stack of the memory of the present invention.

[0110] The difference from the aforementioned embodiment is that, in some embodiments, in the magazine capacitor array chip, the second magazine capacitor units are evenly distributed at positions outside the magazine capacitor array.

[0111] In some embodiments of the present invention, the second magazine capacitor units are distributed on both sides of the magazine capacitor array. Specifically, the magazine capacitor array chip includes: at least one magazine capacitor array; along at least one of a first direction and a second direction intersecting each other, the second magazine capacitor units are distributed on both sides of the at least one magazine capacitor array.

[0112] like Figure 6 In some embodiments shown, the magazine capacitor array chip 220 includes two magazine capacitor arrays 224 ; along the first direction x, the second magazine capacitor units 221 b are distributed on both sides of the two magazine capacitor arrays 224 .

[0113] In some embodiments of the present invention, the second magazine capacitor units are distributed between adjacent magazine capacitor arrays. Specifically, the magazine capacitor array chip includes: at least two magazine capacitor arrays; the second magazine capacitor units are distributed between adjacent magazine capacitor arrays along at least one of a first direction and a second direction that intersect.

[0114] like Figure 6 In some of the embodiments shown, the magazine capacitor array chip 220 includes two magazine capacitor arrays 224, namely a first magazine capacitor array and a second magazine capacitor array; the first magazine capacitor array and the second magazine capacitor array are arranged along the first direction x; the second magazine capacitor unit 221b is distributed between the first magazine capacitor array and the second magazine capacitor array.

[0115] refer to Figure 7 , showing a schematic diagram of the top view of the structure of the magazine capacitor array chip and the logic chip in other embodiments of the logic chip stack of the memory of the present invention.

[0116] The present invention will not elaborate on the similarities with the above embodiments. The difference from the above embodiments is that, in some embodiments, the first magazine capacitor unit and the second magazine capacitor unit are different magazine capacitor units.

[0117] like Figure 7 As shown, in some embodiments, in the magazine capacitor array chip 320, the magazine capacitor array 324 includes: first magazine capacitor units 321a arranged in an array; and second magazine capacitor units 321b distributed on one side of the magazine capacitor array 324 along the first direction x.

[0118] The first magazine capacitor unit 321a corresponds to a memory cell constituting a memory array in a memory array chip in the memory; the second magazine capacitor unit 321b corresponds to a peripheral dummy memory cell in a memory array chip in the memory.

[0119] The first magazine capacitor unit 321a and the second magazine capacitor unit 321b correspond to the storage unit in the storage array chip and the peripheral pseudo storage unit respectively. The magazine capacitor array chip and the storage array chip in the memory are the same chip. There is no need to additionally design and manufacture the magazine capacitor array chip. The magazine capacitor array chip can be realized by using the storage array chip in the memory, which can effectively reduce manufacturing costs.

[0120] Combined with reference Figure 8 and Figure 9 ,in Figure 8 A schematic structural diagram of a first magazine capacitor unit in some embodiments of a logic chip stack of a memory according to the present invention is shown; Figure 9 A schematic structural diagram of the second magazine capacitor unit in some embodiments of the logic chip stack of the memory of the present invention is shown.

[0121] In some embodiments of the present invention, at least one of the first magazine capacitor unit and the second magazine capacitor unit includes: a magazine capacitor and a capacitor switch connected to the magazine capacitor.

[0122] like Figure 8 In some of the embodiments shown, in the first magazine capacitor unit 321a, the capacitor switch 323 is a transistor, and the capacitor switch 323 includes: a gate located on the magazine capacitor unit well region 323aw and source and drain doped regions located in the magazine capacitor unit well region 323aw on both sides of the gate, one of the source and drain doped regions is connected to the magazine capacitor 322.

[0123] like Figure 9In some of the embodiments shown, in the second magazine capacitor unit 321b, the capacitor switch 323 is a transistor, and the capacitor switch 323 includes: a gate located on the magazine capacitor unit well region 323bw and source and drain doped regions located in the magazine capacitor unit well region 323bw on both sides of the gate, one of the source and drain doped regions is connected to the magazine capacitor 322.

[0124] In some embodiments of the present invention, the first magazine capacitor unit and the second magazine capacitor unit differ only in the doping type of the magazine capacitor unit well region. Specifically, the first magazine capacitor unit and the second magazine capacitor unit differ only in the doping type of the magazine capacitor unit well region, and the other structures and materials are the same.

[0125] Moreover, the first magazine capacitor unit and the second magazine capacitor unit correspond to the storage unit and the peripheral pseudo storage unit in the storage array chip respectively; in the first magazine capacitor unit, the doping type of the magazine capacitor unit well region is different from the doping type of the source and drain doping region of the capacitor switch; in the second magazine capacitor unit, the doping type of the magazine capacitor unit well region is the same as the doping type of the source and drain doping region of the capacitor switch.

[0126] Specifically, such as Figure 8 and Figure 9 In some of the embodiments shown, the structures and materials of the capacitor switch 323 and the magazine capacitor 322 in the first magazine capacitor unit 321a and the capacitor switch 323 and the magazine capacitor 322 in the second magazine capacitor unit 321b are the same; the doping type of the magazine capacitor unit well region 323aw in the first magazine capacitor unit 321a is different from the doping type of the magazine capacitor unit well region 323bw in the second magazine capacitor unit 321b.

[0127] Moreover, in the first magazine capacitor unit 321a, the doping type of the magazine capacitor unit well region 323aw is different from the doping type of the source and drain doping regions of the capacitor switch 323; in the second magazine capacitor unit 321b, the doping type of the magazine capacitor unit well region 323bw is the same as the doping type of the source and drain doping regions of the capacitor switch 323.

[0128] In some embodiments, the first magazine capacitor unit corresponds to a memory cell in a memory array chip for storing data, and the second magazine capacitor unit corresponds to a peripheral dummy memory cell in the memory array chip. A magazine capacitor unit well region in the first magazine capacitor unit and a memory cell well region in the memory cell have the same doping type, and a magazine capacitor unit well region in the second magazine capacitor unit and a peripheral dummy memory cell well region in the peripheral dummy memory cell have the same doping type.

[0129] For example, in the storage array chip of the memory, the source and drain doping regions of the storage switch are both N-type doping regions, the storage unit well region is a P-type well region, the source and drain doping regions of the switch in the peripheral pseudo storage unit are both N-type doping regions, and the peripheral pseudo storage unit well region is an N-type well region; in the first magazine capacitor unit 321a, the source and drain doping regions of the capacitor switch are both N-type doping regions, and the magazine capacitor unit well region 323aw is a P-type well region; in the second magazine capacitor unit 321b, the source and drain doping regions of the capacitor switch are both N-type doping regions, and the magazine capacitor unit well region 323bw is an N-type well region.

[0130] In some embodiments of the present invention, the logic chip includes a capacitor activation circuit connected to a control terminal of a capacitor switch. Specifically, the capacitor activation circuit is adapted to activate the capacitor switch in the magazine capacitor unit to ensure electrical connection between the physical layer and the magazine capacitor.

[0131] Specific as Figure 7 As shown, in the logic chip 310, the capacitor turn-on circuit 312 can generate a turn-on signal; in the magazine capacitor unit of the magazine capacitor array chip 320, the control end of the capacitor switch 323 receives the turn-on signal to turn on the two connection ends of the capacitor switch 323, thereby realizing the electrical connection between the physical layer of the logic chip 310 and the magazine capacitor 322.

[0132] In some embodiments, the magazine capacitor array chip further includes: a magazine capacitor array word line, the magazine capacitor array word line is connected to the control end of the capacitor switch in the magazine capacitor unit; the magazine capacitor array chip further includes: a magazine capacitor array main word line, the magazine capacitor array main word line is connected to all magazine capacitor array word lines; the capacitor turn-on circuit is connected to the magazine capacitor array main word line.

[0133] Specifically, the magazine capacitor array word line and the magazine capacitor array main word line cooperate to achieve electrical connection between the capacitor opening circuit and the control end of the capacitor switch in the magazine capacitor unit to realize the opening of the capacitor switch.

[0134] In some embodiments, the magazine capacitor array word lines include: a first magazine capacitor array word line, the first magazine capacitor array word line corresponding to a word line in a memory array chip of the memory; a distribution of the first magazine capacitor array word line is consistent with the distribution of the word lines in the memory array chip; and the first magazine capacitor array word line is connected to a first magazine capacitor unit in the magazine capacitor array.

[0135] Specific as Figure 7 In some embodiments shown, the first magazine capacitor array word line 326a (eg, Figure 7(shown by the red solid line in the middle) extends along the first direction x, and a plurality of first magazine capacitor array word lines 326a are arranged in parallel along the second direction y; a plurality of first magazine capacitor units 321a arranged in sequence along the first direction x are all connected to the same first magazine capacitor array word line 326a; Figure 8 In some embodiments shown, the first magazine capacitor array word line 326 a is connected to the gate of the capacitor switch 323 in the first magazine capacitor unit 321 a .

[0136] Continue to refer Figure 7 The magazine capacitor array total word line 327 extends along the second direction y and is connected to multiple first magazine capacitor array word lines 326a arranged along the second direction y; the other end of the magazine capacitor array total word line 327 is connected to the capacitor start-up circuit 312 of the logic chip 310.

[0137] The magazine capacitor array word lines correspond to the word lines connected to the memory cells within the memory array chip. The distribution of the magazine capacitor array word lines is consistent with the distribution of the word lines within the memory array chip. The magazine capacitor array chip and the memory array chip are the same chip, eliminating the need for additional design and manufacturing of the magazine capacitor array chip. The magazine capacitor array chip can be implemented using the memory array chip within the memory, effectively reducing manufacturing costs.

[0138] It should be noted that, in some embodiments of the present invention, the magazine capacitor array chip further includes: a dummy connection line, which is connected to the control end of the capacitor switch in the second magazine capacitor unit.

[0139] like Figure 9 In some embodiments shown, in the magazine capacitor array chip 320 , the dummy connection line 326 b is connected to the gate of the capacitor switch 323 ; the dummy connection line 326 b is in a floating state.

[0140] refer to Figure 10 and Figure 11 ,in Figure 10 Schematic diagrams of the top view of the structure of the magazine capacitor array chip and the logic chip in other embodiments of the logic chip stack of the memory of the present invention are shown; Figure 11 A schematic structural diagram of a first magazine capacitor unit and a second magazine capacitor unit in some embodiments of a logic chip stack of a memory of the present invention is shown.

[0141] The present invention will not repeat the same points as the above embodiments. The difference from the above embodiments is that in some embodiments of the present invention, the first magazine capacitor unit and the second magazine capacitor unit are the same magazine capacitor unit.

[0142] Specifically, the first magazine capacitor unit and the second magazine capacitor unit are the same magazine capacitor unit, which means that the first magazine capacitor unit and the second magazine capacitor unit have the same structure, material, and doping type.

[0143] Specific as Figure 10 and Figure 11 In some of the embodiments shown, any one of the first magazine capacitor unit 421a and the second magazine capacitor unit 421b includes: a capacitor switch 423 and a magazine capacitor 422, the two connection ends of the capacitor switch 423 are respectively connected to the magazine capacitor 422 and the magazine capacitor array bit line 425, and the control end of the capacitor switch 423 is connected to the magazine capacitor array word line 426 or a virtual connection line (not shown in the figure).

[0144] like Figure 11 As shown, the capacitor switch 423 includes: a gate located on the magazine capacitor unit well region 423nw and a source-drain doped region located in the magazine capacitor unit well region 423nw on both sides of the gate; the source-drain doped region is a connection end, which is respectively connected to the magazine capacitor 422 and the magazine capacitor array bit line 425; the gate is the control end of the capacitor switch 423, which is connected to the magazine capacitor array word line 426 or a virtual connection line (not shown in the figure).

[0145] The first magazine capacitor unit 421a and the second magazine capacitor unit 421b are the same magazine capacitor unit, and the magazine capacitor unit well region 423nw of the first magazine capacitor unit 421a and the magazine capacitor unit well region 423nw of the second magazine capacitor unit 421b are well regions of the same doping type.

[0146] Specifically, the magazine capacitor unit well region 423nw of the first magazine capacitor unit 421a and the magazine capacitor unit well region 423nw of the second magazine capacitor unit 421b are both doped with the same type as the source and drain doping regions of their respective capacitor switches. For example, in the first magazine capacitor unit 421a and the second magazine capacitor unit 421b, the source and drain doping regions of the capacitor switches are both N-type doping regions, and the magazine capacitor unit well region 423nw are also both N-type well regions.

[0147] It should be noted that in the aforementioned embodiments, the magazine capacitor unit includes a capacitor switch, and the physical layer of the logic chip is connected to the magazine capacitor via the capacitor switch. However, this magazine capacitor unit is only an example. In other embodiments of the present invention, the magazine capacitor unit may not include a capacitor switch.

[0148] In some embodiments of the present invention, at least one of the first and second magazine capacitor units does not have a capacitor switch. Specifically, at least one of the first and second magazine capacitor units does not have a capacitor switch, and the magazine capacitors are directly connected to the magazine capacitor array bit lines.

[0149] Specific as Figure 12 As shown, the magazine capacitor unit does not include a capacitor switch, and the magazine capacitor 522 is directly connected to the magazine capacitor array bit line 525.

[0150] Correspondingly, the present invention also provides a memory stacking structure.

[0151] refer to Figure 13 , showing a schematic cross-sectional structure diagram of some embodiments of the stacking structure of the memory of the present invention.

[0152] The stacking structure of the memory includes: a logic chip stack, which is the logic chip stack of the present invention; and a memory array chip, which is stacked with the logic chip.

[0153] The logic chip stack includes logic chips with logic circuits to perform basic logical operations and signal processing and conversion. The logic chip stack is the logic chip stack of the present invention. The specific technical solution of the logic chip stack is referred to the embodiment of the logic chip stack described above.

[0154] Specific as Figure 13 In some embodiments shown, the stack structure includes: a logic chip stack 701. The specific technical solution of the logic chip stack 701 can refer to the aforementioned Figures 3 to 12 An embodiment of logic chip stacking is shown.

[0155] The memory array chip is used to store data.

[0156] Specifically, the memory array chip and the logic chip stack are stacked together. In some embodiments, the memory array chip and the logic chip stack are electrically connected by at least one of through silicon vias, microbumps, or hybrid bonding.

[0157] In some embodiments of the present invention, the memory array chip is stacked on the magazine capacitor array chip stacked with the logic chip. Specifically, the magazine capacitor array chip is located between the logic chip and the plurality of memory array chips, and the memory array chip is located on the side of the magazine capacitor array chip away from the logic chip to facilitate heat dissipation. For example, Figure 13 In some of the illustrated embodiments, the stacking structure includes: a plurality of memory array chips 730 , which are stacked on a side of the magazine capacitor array chip 720 of the logic chip stack 701 away from the logic chip 710 .

[0158] It should be noted that Figure 13In some of the illustrated embodiments, the memory array chip 730 is stacked on the magazine capacitor array chip 720 of the logic chip stack 701. This configuration is merely an example. In other embodiments of the present invention, the memory array chip may also be stacked on the magazine capacitor array chip of the logic chip stack. In other words, the logic chip is located between the magazine capacitor array chip and the plurality of memory array chips, with the magazine capacitor array chip located on the side of the memory array chip away from the logic chip.

[0159] In some embodiments of the present invention, a memory array chip is connected to the physical layer of a logic chip. The memory array chip is electrically connected to other chips via the physical layer of the logic chip to implement functions such as data transmission and signal reception. In some exemplary embodiments, the physical layer of the logic chip includes a first physical layer and a second physical layer; the memory array chip is electrically connected to the first physical layer of the logic chip.

[0160] For example, Figure 13 As shown, the memory array chip 730 is stacked on the side of the magazine capacitor array chip 720 away from the logic chip 710; the memory array chip 730 is electrically connected to the physical layer 711 in the logic chip 710 through the magazine capacitor array chip. In some embodiments of the present invention, the memory array chip and the magazine capacitor array chip are the same chip. By configuring the memory array chip and the magazine capacitor array chip as the same chip, the magazine capacitor array chip can be implemented through the memory array chip, eliminating the need for additional design and manufacturing of the magazine capacitor array chip, thereby effectively reducing costs.

[0161] Combined with reference Figure 14 , showing a schematic diagram of a top view of a memory array chip in some embodiments of the stacked structure of the memory of the present invention.

[0162] In some embodiments of the present invention, a memory array chip includes a memory array, the memory array includes memory cells arranged in an array, the memory cells include memory cell capacitors, and the magazine capacitors and the memory cell capacitors are the same capacitors.

[0163] The magazine capacitor and the storage unit capacitor are the same capacitor, that is, the structure and material of the magazine capacitor and the storage unit capacitor are the same. The capacitance density of the storage unit capacitor is about pF / μm 2 The area efficiency of the storage unit capacitor is orders of magnitude higher than that of the on-chip capacitor. The magazine capacitor is set to the same capacitance as the storage unit capacitor. The virtual unit capacitor has a higher capacitance density. The area efficiency of the capacitor provided by the magazine capacitor array chip is high. No additional process is required to make the magazine capacitor array chip meet the needs of the logic chip, which is conducive to reducing process cost and manufacturing cost.

[0164] Specific as Figure 14In some embodiments shown, in the memory array chip 730, the memory array 731 includes: memory cells 731a arranged in an array, the memory cells 731a include: memory cell capacitors 732; magazine capacitors (such as Figure 4 The magazine capacitor 122 shown in FIG. 1 is the same capacitor as the storage unit capacitor 732 .

[0165] In some embodiments of the present invention, the storage unit also includes: a storage switch, the storage switch is located in the storage cell well area, the storage switch includes: a control end and two connection ends, the control end is suitable for controlling conduction and cutoff between the two connection ends, the storage cell capacitor is connected to one connection end of the storage switch; the capacitor switch of the magazine capacitor unit and the storage switch of the storage cell are the same switch.

[0166] Specifically, the memory uses a 1T1C structure, meaning a single memory cell in the memory consists of a memory switch and a memory cell capacitor. The capacitor switch and the memory switch are identical, sharing the same structure, materials, and doping. The magazine capacitor cell structure more closely resembles that of the memory cell, eliminating the need for a separate magazine capacitor array chip and effectively reducing process and manufacturing costs.

[0167] Specific as Figure 14 In some embodiments shown, in the memory array chip 730, the memory unit 731a further includes: a memory switch 733; a memory switch 733 and a capacitor switch (such as Figure 4 The capacitive switch 123 in FIG. 1 is the same switch.

[0168] In some exemplary embodiments, the memory switch is a transistor, comprising a gate located on a memory cell well region and source / drain doped regions located on either side of the gate in the memory cell well region. The gate serves as a control terminal for the memory switch, and the two source / drain doped regions serve as connection terminals, one of which is connected to a memory cell capacitor.

[0169] In some embodiments of the present invention, the first magazine capacitor unit and the storage unit of the magazine capacitor array chip are identical units. Specifically, in the magazine capacitor array chip, the magazine capacitor array includes a first magazine capacitor unit; the first magazine capacitor unit and the storage unit have the same structure, material, and doping.

[0170] Specific as Figure 4 As shown, in the magazine capacitor array chip 120, the magazine capacitor array 124 includes a first magazine capacitor unit 121a; Figure 14 As shown, in the memory array chip 730 , the memory array 734 includes a memory unit 731 a ; and the first magazine capacitor unit 121 a and the memory unit 731 a are the same unit.

[0171] In some embodiments, the first magazine capacitor units are arranged in the same arrangement as the storage units. Specifically, in the magazine capacitor array, the first magazine capacitor units are arranged in an array; in the storage array, the storage units are also arranged in an array; and the magazine capacitor array is positioned in the same position in the magazine capacitor array chip as the storage array is positioned in the storage array chip.

[0172] Specific as Figure 4 As shown, in the magazine capacitor array 124, the first magazine capacitor units 121a are arranged in an array along the first direction x and the second direction y; Figure 14 As shown, in the memory array 734, the memory cells are arranged in an array along the first direction x and the second direction y.

[0173] It should be noted that in some embodiments of the present invention, the memory array chip further includes: a bit line, the bit line being connected to the memory cell capacitor; and the magazine capacitor array bit line and the bit line in the magazine capacitor array chip are identical bit lines. Specifically, the magazine capacitor array chip includes the magazine capacitor array bit line, and the magazine capacitor array bit line and the bit line have the same structure and material.

[0174] Specific as Figure 4 As shown, the magazine capacitor array chip 120 includes: magazine capacitor array bit lines 125 extending along the second direction y and arranged in parallel along the first direction x (as shown in FIG. Figure 4 As shown by the blue solid line); Figure 14 As shown, in the memory array chip, the bit line 735 (such as Figure 14 The plurality of memory cells 731 a arranged in sequence along the second direction y are all connected to the same bit line 735 .

[0175] It should also be noted that in some embodiments, a memory cell includes a memory switch and a memory unit capacitor connected to one terminal of the memory switch; a bit line is connected to the other terminal of the memory switch. For example, the bit line is connected to a source / drain doped region of the memory switch that is not connected to the memory unit capacitor.

[0176] In some embodiments of the present invention, the memory array chip further includes a word line connected to the memory switch; the magazine capacitor array word line and the word line in the magazine capacitor array chip are identical. Specifically, the magazine capacitor array chip includes the magazine capacitor array word line, and the magazine capacitor array word line and the word line have the same structure and material.

[0177] Specific as Figure 4 As shown, the magazine capacitor array chip 120 includes: magazine capacitor array word lines 126 extending along a first direction x and arranged in parallel along a second direction y (such as Figure 4 As shown by the red solid line in the middle); Figure 14 As shown, in the memory array chip, the word line 736 extends along the first direction x, and multiple word lines 736 are arranged in parallel along the second direction y; multiple memory cells 731a arranged in sequence along the first direction x are all connected to the same word line 736.

[0178] It should be noted that in some embodiments, the word line is connected to the control terminal of the storage switch in the memory cell. Specifically, in the storage switch 733 , the word line 736 is connected to the gate of the storage switch 733 .

[0179] Continue to refer Figure 14 In some embodiments of the present invention, the memory array chip further includes a peripheral dummy memory cell, each of which includes a dummy memory cell capacitor. The second magazine capacitor unit of the magazine capacitor array chip is the same as the peripheral dummy memory cell. The dummy memory cell capacitor of the peripheral dummy memory cell is connected to the logic chip to provide capacitance for the logic chip. Specifically, in the magazine capacitor array chip, the magazine capacitor array includes a second magazine capacitor unit; the second magazine capacitor unit and the peripheral dummy memory cell have the same structure, material, and doping.

[0180] Specific as Figure 4 As shown, the magazine capacitor array chip 120 includes a second magazine capacitor unit 121b; Figure 14 As shown, the memory array chip 730 includes a peripheral dummy memory unit 731b, which is located outside the memory array 734; the second magazine capacitor unit 121b and the peripheral dummy memory unit 731b are the same unit.

[0181] In some embodiments, the second magazine capacitor units are distributed identically to the peripheral dummy memory cells. Specifically, in a magazine capacitor array chip, the second magazine capacitor units are located outside the magazine capacitor array; in a memory array chip, the peripheral dummy memory cells are located outside the memory array; and the positions of the second magazine capacitor units in the magazine capacitor array chip and the positions of the peripheral dummy memory cells in the memory array chip correspond identically.

[0182] like Figure 4 As shown, the second magazine capacitor unit 121b is distributed in the second capacitor area cp2 on one side of the magazine capacitor array 124; Figure 14 As shown, the storage array chip 730 includes: a first capacitor area cp1 and a second capacitor area cp2, the second capacitor area cp2 includes a peripheral pseudo storage unit 731b; the second magazine capacitor unit 121b and the peripheral pseudo storage unit 731b of the second capacitor area cp2 are the same unit; the position of the second capacitor area cp2 in the magazine capacitor array chip 120 corresponds to the same position as the second capacitor area cp2 in the storage array chip 730.

[0183] It should be noted that in some embodiments of the present invention, the memory array chip and the magazine capacitor array chip are the same chip. Similar to the magazine capacitor array chip, the memory array chip also includes an array area (not labeled in the figure) and a peripheral area (not labeled in the figure). The array area includes the memory array, and the peripheral area includes peripheral circuits.

[0184] Specific as Figure 14 In some embodiments shown, the array region includes a memory array 734 , the peripheral region includes a peripheral circuit 737 , and the array region and the peripheral region are arranged in a direction parallel to the surface of the memory array chip 730 .

[0185] In addition, in the memory array chip, the first capacitor area also includes peripheral dummy memory cells (not shown in the figure), which include dummy memory cell capacitors. The peripheral dummy memory cells in the first capacitor area are connected to the peripheral circuits in the peripheral area to provide capacitance for the peripheral circuits.

[0186] The dummy cells of the first capacitor region in the magazine capacitor array chip and the peripheral dummy memory cells of the first capacitor region in the memory array chip are identical cells, and have the same structure, material, and doping as the peripheral dummy memory cells of the first capacitor region.

[0187] Specific as Figure 14 In some embodiments shown, in the memory array chip 730, the peripheral area, the first capacitor area cp1 and the second capacitor area cp2 are arranged in sequence along the second direction y, and the peripheral area, the first capacitor area cp1 and the second capacitor area cp2 are all located on the same side of the array area along the first direction x.

[0188] It should be noted that in the above embodiment, the memory array chip 730 is provided with peripheral circuits, so that the peripheral area, the first capacitor area cp1, and the second capacitor area cp2 are all distributed on the same side of the memory array 734. However, this layout of the memory array chip is only an example. In other embodiments of the present invention, the memory array chip can also be arranged in other ways, and the peripheral circuits can be provided in other chips.

[0189] Correspondingly, the present invention also provides a memory stacking structure.

[0190] refer to Figure 15 , shows a schematic cross-sectional view of some embodiments of the stacked structure of the memory of the present invention. Figure 16 , showing a schematic diagram of the top view structure of the memory chip stack in some embodiments of the memory of the present invention.

[0191] The difference from the above embodiments is that, in some embodiments, no peripheral circuits are provided in the memory array chip, and peripheral dummy memory cells are evenly distributed outside the memory array.

[0192] In some embodiments of the present invention, peripheral dummy memory cells are distributed on both sides of a memory array. Specifically, the memory array chip includes: at least one memory array; and the peripheral dummy memory cells are distributed on both sides of the at least one memory array along at least one of a first direction and a second direction intersecting each other.

[0193] like Figure 16 In some embodiments shown, the memory array chip 630 includes two memory arrays 634 ; along a first direction x, the peripheral dummy memory cells 631 b are distributed on both sides of the two memory arrays 634 .

[0194] In some embodiments of the present invention, peripheral dummy memory cells are distributed between adjacent memory arrays. Specifically, the memory array chip includes at least two memory arrays; the peripheral dummy memory cells are distributed between adjacent memory arrays along at least one of a first direction and a second direction that intersect.

[0195] like Figure 16 In some of the embodiments shown, the memory array chip 630 includes two memory arrays 634, namely a first memory array and a second memory array; the first memory array and the memory array are arranged along a first direction x; and the peripheral pseudo memory cells 631b are distributed between the first memory array and the memory array.

[0196] It should be noted that in some embodiments of the present invention, no peripheral circuit is set in the memory array chip; therefore, the stacking structure also includes: memory chip stacking, the memory chip stacking includes: memory array chip; the memory chip stacking also includes: peripheral chip, the peripheral chip and memory chip stacking arrangement.

[0197] The peripheral chip includes a peripheral circuit. The peripheral chip is connected to a dummy memory cell capacitor of a peripheral dummy memory cell in the memory array chip. The dummy memory cell capacitor is used to provide capacitance for the peripheral circuit.

[0198] Specifically, the peripheral chip includes one or more of a word line driver (WLD), a sense amplifier (SA), and an input / output (I / O) structure.

[0199] It should be noted that the configuration in which the peripheral chip includes one or more of a word line driver circuit, a sensitive amplifier, and an input / output structure is only an example. In other embodiments of the present invention, the peripheral chip may also include a control logic circuit, a power supply simulation module, and other types of circuits.

[0200] It should also be noted that in some embodiments of the present invention, the memory array chip includes: at least two memory arrays; the peripheral chip includes: at least two peripheral circuits, and the at least two peripheral circuits are connected to the at least two memory arrays in a one-to-one correspondence.

[0201] Specific as Figure 16 In some of the embodiments shown, the memory array chip 630 includes two memory arrays 634, namely a first memory array and a second memory array; the peripheral chip 640 includes: two peripheral circuits 641, namely a first peripheral circuit and a second peripheral circuit; the first peripheral circuit and the second peripheral circuit are respectively connected to the first memory array and the second memory array.

[0202] Continue to refer Figure 16 The peripheral chip and the memory array chip are stacked. In some embodiments, the peripheral chip and the memory array chip can be electrically connected by at least one of through-silicon-vias (TSVs), microbumps, or hybrid bonding.

[0203] For example, Figure 15 As shown, the memory chip stack 602 is stacked on the side of the magazine capacitor array chip 620 in the logic chip stack 601 away from the logic chip 610; the memory chip stack 602 includes: a stacked peripheral chip 640 and a memory array chip 630, wherein the peripheral chip 640 is located between the memory array chip 630 and the magazine capacitor array chip 620.

[0204] In some embodiments of the present invention, the stack structure includes: at least two memory stacks, the two memory stacks are stacked in sequence on the same side of the logic chip stack. Figure 15 In some of the illustrated embodiments, four memory chip stacks 602 are sequentially stacked on a side of the magazine capacitor array chip 620 away from the logic chip 610 .

[0205] It should be noted that Figure 15 In some of the illustrated embodiments, in the memory chip stack 602, the peripheral chip 640 is located between the memory array chip 630 and the magazine capacitor array chip 620. This arrangement is merely an example. In other embodiments of the present invention, the peripheral chip may be located on the side of the memory array chip away from the logic chip stack, that is, the memory array chip is located between the peripheral chip and the magazine capacitor array chip. Furthermore, the present invention provides a memory.

[0206] The memory comprises: a stacking structure, which is the stacking structure of the present invention; a processing chip, which is connected to a physical layer of a logic chip in a logic chip stack in the stacking structure.

[0207] The stacking structure is the stacking structure of the present invention. The specific technical solution of the stacking structure can refer to the embodiment of the aforementioned stacking structure, and can be specifically referred to Figures 13 to 16 An embodiment of a stacked structure is shown.

[0208] In some embodiments of the present invention, the processing chip may be at least one of a central processing unit (CPU), a graphics processing unit (GPU), or a system on a chip (SOC).

[0209] In some embodiments of the present invention, the logic chip includes: a first physical layer and a second physical layer; the first physical layer is connected to the storage array chip; and the second physical layer is connected to the processing chip.

[0210] In some embodiments, the memory includes: a packaging substrate; an interposer, which is stacked on the packaging substrate; the stacking structure and the processing chip are both stacked on the interposer and electrically connected to the interposer; the second physical layer of the logic chip is electrically connected to the processing chip through the interposer.

[0211] The magazine capacitor unit in the magazine capacitor array chip is connected to the physical layer of the logic chip, and the magazine capacitor provides capacitance for the physical layer, which can reduce or even eliminate the setting of capacitors in the logic chip and effectively eliminate the area overhead required for setting capacitors in the logic chip.

[0212] In summary, the logic chip stack includes a magazine capacitor array chip disposed within the logic chip stack. The magazine capacitor units arranged in an array within the magazine capacitor array chip include magazine capacitors connected to the physical layer of the logic chip. The connection between the physical layer of the logic chip and the magazine capacitors can reduce or even eliminate the need for capacitors within the logic chip, effectively reducing the area overhead required for capacitors within the logic chip.

[0213] Furthermore, the magazine capacitor array chip has the same structure as the memory array chip. By setting the magazine capacitor array chip to have the same structure as the memory array chip, there is no need to redesign and manufacture the magazine capacitor array chip. Instead, the magazine capacitor array chip can be realized by using the memory array chip, which can effectively control process and manufacturing costs.

[0214] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory logic chip stack, characterized in that: include: A logic chip, the logic chip comprising: a physical layer; A magazine capacitor array chip is stacked with the logic chip, the magazine capacitor array chip includes: a magazine capacitor unit, the magazine capacitor unit includes: a magazine capacitor, and the magazine capacitor is connected to the physical layer.

2. The logic chip stack according to claim 1, wherein: The magazine capacitor unit also includes: A capacitive switch, the capacitive switch being located in the magazine capacitor unit well region, the capacitive switch comprising: a control end and two connecting ends, the control end being adapted to control conduction and disconnection between the two connecting ends; The magazine capacitor is connected to one connection end of the capacitive switch.

3. The logic chip stack according to claim 1 or 2, wherein: The magazine capacitor array chip includes: A magazine capacitor array, the magazine capacitor array comprising: first magazine capacitor units arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are both parallel to and intersect a surface of the magazine capacitor array chip; A second magazine capacitor unit is distributed outside the magazine capacitor array.

4. The logic chip stack according to claim 3, wherein: The second magazine capacitor units are distributed on both sides of the magazine capacitor array.

5. The logic chip stack according to claim 3, wherein: The second magazine capacitor units are distributed between adjacent magazine capacitor arrays.

6. The logic chip stack according to claim 3, wherein: The first magazine capacitor unit and the second magazine capacitor unit are the same magazine capacitor unit; Alternatively, the first magazine capacitor unit and the second magazine capacitor unit differ only in doping type of the magazine capacitor unit well region; Alternatively, at least one of the first magazine capacitor unit and the second magazine capacitor unit does not have a capacitor switch.

7. The logic chip stack according to claim 2, wherein: The magazine capacitor array chip further includes: a magazine capacitor array bit line, wherein the magazine capacitor array bit line is connected to the magazine capacitor; The physical layer is connected to the magazine capacitor through the magazine capacitor array bit line.

8. The logic chip stack according to claim 2, wherein: The logic chip includes: a capacitor turn-on circuit, and the capacitor turn-on circuit is connected to the control end of the capacitor switch.

9. The logic chip stack according to claim 8, wherein: The magazine capacitor array chip further includes: a magazine capacitor array word line, the magazine capacitor array word line being connected to a control end of a capacitor switch in the magazine capacitor unit; The magazine capacitor array chip further includes: a magazine capacitor array master word line, wherein the magazine capacitor array master word line is connected to all magazine capacitor array word lines; The capacitor start-up circuit is connected to the magazine capacitor array main word line.

10. A memory stack structure, characterized in that: include: A logic chip stack, wherein the logic chip stack is as described in any one of claims 1 to 9; A memory array chip is stacked with the logic chip.

11. The stacking structure according to claim 10, wherein: The storage array chip and the magazine capacitor array chip are the same chip.

12. The stacking structure according to claim 10 or 11, wherein: Also included: a memory chip stack, the memory chip stack including: the memory array chip; The memory chip stack further includes: a peripheral chip, and the peripheral chip and the memory chip are stacked.

13. The stacking structure according to claim 10, wherein: The memory array chip includes: a memory array, the memory array includes: memory cells arranged in an array, the memory cells include: memory cell capacitors; The magazine capacitor and the storage unit capacitor are the same capacitor.

14. The stacking structure according to claim 13, wherein: The storage unit further includes: A storage switch, the storage switch being located in a memory cell well region, the storage switch comprising: a control terminal and two connection terminals, the control terminal being adapted to control conduction and disconnection between the two connection terminals, the memory cell capacitor being connected to one connection terminal of the storage switch; The capacitance switch of the magazine capacitance unit and the storage switch of the storage unit are the same switch.

15. The stacking structure according to claim 13, wherein: The first magazine capacitor unit of the magazine capacitor array chip and the storage unit are the same unit.

16. The stacking structure according to claim 15, wherein: The first magazine capacitor unit and the storage unit are distributed in the same manner.

17. The stacking structure according to claim 15, wherein: The memory array chip further includes: a peripheral dummy memory unit, wherein the peripheral dummy memory unit includes: a dummy memory unit capacitor; The second magazine capacitor unit of the magazine capacitor array chip and the peripheral pseudo storage unit are the same unit.

18. The stacking structure according to claim 17, wherein: The second magazine capacitor units are distributed in the same manner as the peripheral dummy storage units.

19. The stacking structure according to claim 10, wherein: The storage array chip is connected to the physical layer of the logic chip.

20. A memory, characterized in that: include: A stacking structure, the stacking structure being as described in any one of claims 1 to 19; A processing chip is connected to a physical layer of a logic chip in a logic chip stack in the stack structure.

21. The memory according to claim 20, wherein: The logic chip includes: a first physical layer and a second physical layer; The first physical layer is connected to the storage array chip; The second physical layer is connected to the processing chip.

Images