Semiconductor device and method of use

Abstract

The invention discloses a semiconductor device and a use method, the semiconductor device comprises a substrate, a storage function area and a control function area, and the substrate comprises a substrate, a buffer layer, a channel layer and a barrier layer which are stacked in sequence; the storage function region is arranged on one side, away from the substrate, of the barrier layer, the storage function region comprises a source electrode, a grid control electrode and a drain electrode which are arranged at intervals in the first direction, and the grid control electrode comprises a first cap layer, a first ohmic electrode and a grid electrode which are stacked in the thickness direction of the substrate; the first cap layer and the barrier layer are arranged in a contact mode, the first cap layer is acceptor type doping, and the first ohmic electrode and the grid electrode are arranged in an insulated mode; the control function area is arranged on the side, away from the substrate, of the barrier layer and comprises a first electrode and a second electrode which are arranged at intervals in the first direction, the first electrode is electrically connected with the source electrode, and the second electrode is electrically connected with the first ohmic electrode.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method of using the same. Background Art

[0002] A high electron mobility transistor (HEMT) is a semiconductor device based on gallium nitride that uses polarization effects to form a high-concentration two-dimensional electron gas between the barrier layer and the channel layer, enabling very low on-resistance and very high operating frequency.

[0003] At present, the application of HEMT devices is mainly normally-off devices. Generally, a layer of acceptor-doped gallium nitride material is added between the barrier layer and the gate to achieve the depletion of the two-dimensional electron gas under the gate, thereby improving the safety and reliability of the device in the power-off state.

[0004] However, when a non-ohmic contact, such as a Schottky contact or a metal-insulator-semiconductor (MIS) contact, is used between the acceptor-doped GaN material and the gate, the floating acceptor-doped GaN material may store net charge during the device switching process, easily causing the threshold voltage of the HEMT device to drift, negatively affecting the device's stability and service life. Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device and a method of use, which can utilize the threshold voltage drift of a HEMT device to achieve a storage function.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, which includes a substrate, a storage functional area, and a control functional area. The substrate includes a substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence, and the interface between the channel layer and the barrier layer is configured to generate a two-dimensional electron gas; the storage functional area is arranged on a side of the barrier layer away from the substrate, the storage functional area includes a source, a gate control electrode, and a drain spaced apart along a first direction, the gate control electrode includes a first cap layer, a first ohmic electrode, and a gate stacked along the thickness direction of the substrate, the first cap layer is arranged in contact with the barrier layer and The first cap layer is acceptor-type doped, and the first ohmic electrode is insulated from the gate; the control functional area is arranged on the side of the barrier layer away from the substrate, and the control functional area includes a first electrode and a second electrode spaced apart along a first direction, the first electrode is electrically connected to the source, and the second electrode is electrically connected to the first ohmic electrode, and the control functional area can be switched on or off according to the potential of the first electrode and the potential of the second electrode; wherein the orthographic projection of the storage functional area on the substrate and the orthographic projection of the control functional area on the substrate do not overlap with each other and are spaced apart along the second direction, and the second direction intersects with the first direction.

[0007] In some optional embodiments, the orthographic projection of the first ohmic electrode on the substrate falls within the orthographic projection range of the first cap layer on the substrate.

[0008] In some optional embodiments, the control functional region further includes a second cap layer, the second cap layer is sandwiched between the first electrode and the barrier layer, and the second cap layer is acceptor-type doped.

[0009] In some optional embodiments, the first electrode and the barrier layer are in Schottky contact, and the work function of the first electrode is greater than the work function of the barrier layer.

[0010] In some optional embodiments, the control function area also includes a third cap layer and a second ohmic electrode, the third cap layer is arranged between the first electrode and the second electrode along the first direction, the second ohmic electrode is arranged on the side of the third cap layer away from the barrier layer, and the second ohmic electrode is electrically connected to the first electrode.

[0011] In some optional embodiments, the control functional area also includes a channel formation layer and a third electrode, the channel formation layer is arranged on the side of the barrier layer away from the substrate, the channel formation layer is acceptor-type doped, the third electrode is arranged on the side of the channel formation layer away from the substrate and a second gate dielectric layer is arranged between the third electrode and the channel formation layer, and the third electrode is arranged between the first electrode and the second electrode along the first direction.

[0012] In some optional embodiments, the channel formation layer includes a first region, a channel formation region and a second region arranged in sequence along a first direction, the thickness of the channel formation region is less than the thickness of the first region, the thickness of the channel formation region is less than the thickness of the second region, and the orthographic projection of the channel formation region on the substrate falls within the orthographic projection range of the gate on the substrate.

[0013] In a second aspect, an embodiment of the present application provides a semiconductor device, which includes a substrate, a source, a gate, a fourth cap layer and a drain, wherein the substrate includes a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence, and the interface between the barrier layer and the channel layer is configured to generate a two-dimensional electron gas; the fourth cap layer is arranged on a side of the barrier layer facing away from the substrate, and the fourth cap layer includes a connection structure, a channel structure and a storage structure arranged in sequence along a first direction, the thickness of the channel structure is less than the thickness of the connection structure and the thickness of the channel structure is less than the thickness of the storage structure; the source is arranged on a side of the barrier layer facing away from the substrate, and the source is arranged in contact with the barrier layer and the connection structure at the same time; the drain is arranged on a side of the barrier layer facing away from the substrate, and the drain is spaced apart from the storage structure; the gate is arranged on a side of the fourth cap layer facing away from the substrate, and a third gate dielectric layer is arranged between the gate and the fourth cap layer.

[0014] In some optional embodiments, the orthographic projection of the channel structure on the substrate falls within the orthographic projection of the gate on the substrate, and the orthographic projection of the storage structure on the substrate at least partially falls within the orthographic projection of the gate on the substrate.

[0015] In a third aspect, an embodiment of the present application provides a method for using a semiconductor device, which is applied to the semiconductor device provided in any embodiment of the first aspect or the second aspect, and the method includes:

[0016] Supplying a first voltage or a second voltage to the gate for a first duration and then setting the gate voltage to zero, wherein the first voltage is a positive voltage and the second voltage is a negative voltage;

[0017] A read voltage is provided to the gate, the source is grounded and a third voltage is provided to the drain, the drain current is measured, and the storage state of the semiconductor device is determined according to the magnitude of the drain current.

[0018] In embodiments of the present application, a storage functional area and a control functional area are separately provided on the substrate of a semiconductor device. Unidirectional conduction in the control functional area can be used to accumulate positive charge in the first cap layer in the storage functional area, thereby causing a negative shift in the threshold voltage of the semiconductor device in the storage functional area. Alternatively, conduction of a parasitic heterojunction within the storage functional area can be used to accumulate negative charge in the first cap layer, thereby causing a positive shift in the threshold voltage of the semiconductor device in the storage functional area. Consequently, the leakage current in the storage functional area can exhibit two states, low current and high current, based on the shift in threshold voltage. These two states can be used to represent logic 0 or logic 1, respectively, effectively controlling the threshold voltage of the HEMT device while achieving a storage function. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 Schematic diagram of the structure of HEMT in the prior art;

[0021] Figure 2 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

[0022] Figure 3 for Figure 2 A schematic diagram of the three-dimensional structure of the semiconductor device shown;

[0023] Figure 4 A schematic cross-sectional view of a control functional area in a semiconductor device according to an embodiment of the first aspect of the present application;

[0024] Figure 5 for Figure 4 A schematic diagram of a layout of the semiconductor device shown;

[0025] Figure 6 A schematic cross-sectional view of a control functional area in a semiconductor device according to another embodiment of the first aspect of the present application;

[0026] Figure 7 A schematic cross-sectional view of a control functional area in a semiconductor device according to another embodiment of the first aspect of the present application;

[0027] Figure 8 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

[0028] Figure 9 A schematic cross-sectional view of a control functional area in a semiconductor device according to an embodiment of the first aspect of the present application;

[0029] Figure 10 This is a structural schematic diagram of a semiconductor device according to an embodiment of the second aspect of the present application.

[0030] The drawings are not necessarily drawn to scale.

[0031] The specific marking information in the accompanying drawings is as follows:

[0032] 110, substrate; 120, transition layer; 130, buffer layer; 140, channel layer; 150, barrier layer;

[0033] 200, storage functional area; 210, source; 211, first conductive metal; 212, second conductive metal; 220, drain; 231, first cap layer; 232, first ohmic electrode; 233, first gate dielectric layer; 234, gate; 240, passivation layer;

[0034] 300, control function region; 310, first electrode; 320, second electrode; 330, third electrode; 340, second cap layer; 351, second ohmic electrode; 352, third cap layer; 360, channel formation layer; 361, first region; 362, second region; 363, channel formation region; 370, second gate dielectric layer;

[0035] 410, fourth cap layer; 411, connection structure; 412, channel structure; 413, storage structure; 420, third gate dielectric layer;

[0036] 500, isolation structure;

[0037] First direction X; second direction Y; substrate thickness direction Z. DETAILED DESCRIPTION

[0038] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0040] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0041] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0043] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0044] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0045] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0046] Wide-bandgap semiconductors boast wider bandgap widths, higher critical breakdown electric fields, and higher electron mobility, and are widely used in high-voltage, high-frequency, and high-temperature applications. For example, the High Electron Mobility Transistor (HEMT) is a semiconductor device based on gallium nitride that utilizes polarization effects to form a high-concentration two-dimensional electron gas between the barrier layer and the channel layer. This device achieves very low on-resistance and high operating frequencies, and is widely used in fields such as communications.

[0047] At present, the application of HEMT devices is mainly based on normally-off devices. For specific structures, please refer to Figure 1Normally-off HEMTs generally achieve depletion of the two-dimensional electron gas beneath the gate by adding a layer of acceptor-doped gallium nitride material between the barrier layer and the gate, thereby improving the safety and reliability of the device when it is powered off.

[0048] However, when a non-ohmic contact, such as a Schottky contact or a metal-insulator-semiconductor (MIS) contact, is used between the acceptor-doped GaN material and the gate, the floating acceptor-doped GaN material may store net charge during the device switching process, easily causing the threshold voltage of the HEMT device to drift, negatively affecting the device's stability and service life.

[0049] The present invention provides a semiconductor device and a method of use thereof, which can utilize the threshold voltage drift of a HEMT device to realize the storage function of the device.

[0050] In a first aspect, the present invention provides a semiconductor device. Figure 2 and Figure 3 The semiconductor device includes a substrate, a storage functional area 200 and a control functional area 300. The storage functional area 200 and the control functional area 300 are arranged on the same side of the substrate. The storage functional area 200 includes a source 210, a gate control electrode and a drain 220 spaced apart along a first direction. The gate control electrode includes a first cap layer 231, a first ohmic electrode 232 and a gate 234 stacked along the thickness direction of the substrate. The first cap layer 231 is arranged in contact with the substrate and is acceptor-doped. The first ohmic electrode 232 is insulated from the gate 234. Setting; the control functional area 300 includes a first electrode 310 and a second electrode 320 spaced apart along a first direction, the first electrode 310 is electrically connected to the source 210, and the second electrode 320 is electrically connected to the first ohmic electrode 232, and the control functional area 300 can be switched on or off according to the potential of the first electrode 310 and the potential of the second electrode 320; wherein, the orthographic projection of the storage functional area 200 on the substrate and the orthographic projection of the control functional area 300 on the substrate do not overlap with each other and are spaced apart along the second direction, and the second direction intersects with the first direction.

[0051] Specifically, the substrate includes a substrate 110, a buffer layer 130, a channel layer 140, and a barrier layer 150, which are stacked in sequence. The interface between the channel layer 140 and the barrier layer 150 is configured to generate a two-dimensional electron gas. The storage functional area 200 and the control functional area 300 are disposed on one side of the substrate's barrier layer 150. In some embodiments, the substrate further includes a transition layer 120, which is disposed between the substrate 110 and the buffer layer 130 to balance the lattice fit between the substrate 110 and the buffer layer 130, reduce interfacial stress, and improve the growth quality of the buffer layer 130.

[0052] Optionally, the material of the substrate 110 includes at least one of a silicon substrate 110 , a sapphire substrate 110 , aluminum nitride, and silicon carbide.

[0053] Optionally, the material of the buffer layer 130 includes at least one of aluminum nitride and gallium nitride, and the buffer layer 130 is doped with carbon or iron to increase its own resistance, reduce the off-state leakage current of the device, and increase the breakdown voltage of the device.

[0054] Optionally, the material of the channel layer 140 includes gallium nitride, and the channel layer 140 is used to provide a conductive channel for the two-dimensional electron gas.

[0055] Optionally, the material of the barrier layer 150 includes at least one of aluminum gallium nitride, aluminum nitride, indium nitride, and aluminum indium gallium nitride.

[0056] It is understood that the semiconductor device further includes a passivation layer 240 covering the top. The passivation layer 240 is used to prevent water vapor impurities from invading the storage functional area 200, the control functional area 300, and the substrate. Optionally, the material of the passivation layer 240 includes at least one of aluminum oxide, silicon dioxide, silicon nitride, aluminum nitride, and hafnium oxide. Alternatively, the material of the passivation layer 240 also includes other materials commonly used for insulating the internal structure of semiconductor devices.

[0057] Optionally, the gate control electrode further includes a first gate dielectric layer 233, which is interposed between the gate 234 and the first ohmic electrode 232 to achieve insulation between the gate 234 and the first ohmic electrode 232. Optionally, the material of the first gate dielectric layer 233 includes at least one of aluminum oxide, silicon dioxide, silicon nitride, aluminum nitride, and hafnium oxide.

[0058] Optionally, to shorten the wiring distance, the first direction and the second direction are arranged perpendicular to each other, or the first direction and the second direction are arranged with an acute angle therebetween.

[0059] It will be appreciated that the semiconductor device further includes an isolation structure 500, which is used to electrically isolate the control functional region 300 from the storage functional region 200. Exemplarily, the isolation structure 500 includes an insulating dielectric layer disposed in contact with the barrier layer 150, the insulating dielectric layer being implanted with fluoride ions, and the insulating dielectric layer surrounding the control functional region 300. Alternatively, the isolation structure 500 is formed by implanting fluoride ions into the barrier layer and the channel layer, and the isolation structure 500 is disposed surrounding the control functional region 300.

[0060] Taking the write logic "1" of the semiconductor device provided in the embodiment of the first aspect of the present application as an example, a negative voltage, for example -5V, is provided to the gate 234. The potential of the first cap layer 231 is reduced under the action of capacitive coupling, so that the potential of the first ohmic electrode 232 and the second electrode 320 is reduced to a potential lower than that of the first electrode 310 and the source 210, and the control functional area 300 is turned on. In addition, the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas thereunder at the storage functional area 200 is turned off, and positive charge can be accumulated in the first cap layer 231 to form a negative drift of the threshold voltage.

[0061] Taking the writing logic "0" of the semiconductor device provided in the embodiment of the first aspect of the present application as an example, a positive voltage of, for example, 5V, is provided to the gate 234. The potential of the first cap layer 231 increases under the action of capacitive coupling, so that the potential of the first ohmic electrode 232 and the second electrode 320 increases to a level higher than the potential of the first electrode 310 and the source 210, and the control functional area 300 is turned off. In addition, the parasitic heterojunction formed between the first cap layer 231-the barrier layer 150-the channel layer 140 is turned on, and the positive charge in the first cap layer 231 is discharged through the parasitic heterojunction, thereby forming an accumulation of negative charge in the first cap layer 231, thereby realizing a positive drift of the threshold voltage.

[0062] Taking the reading of a semiconductor device provided in the first embodiment of the present application as an example, the source 210 is grounded, a fixed low voltage is applied to the drain 220 so that the drain 220 potential is higher than the source 210, and a reading voltage of, for example, 1V, is applied to the gate 234. The drain 220 electrode is read. If the current in the drain 220 is low, the semiconductor device is recorded as being in state "0"; if the current in the drain 220 is high, the semiconductor device is recorded as being in state "1." The reading voltage can be positive, negative, or zero, and this application does not specifically limit this.

[0063] Thus, the semiconductor device provided by the embodiment of the present application can switch the conduction of the control functional area 300 or the opening of the parasitic heterojunction by adjusting the gate voltage, thereby selectively allowing positive or negative charges to accumulate at the first cap layer 231, thereby achieving a negative or positive drift of the threshold voltage of the semiconductor device. Furthermore, when a read voltage is applied to the gate 234, based on the drift of the threshold voltage, the leakage current of the storage functional area 200 can exhibit two states: low current and high current. Ultimately, the reading of logic 0 or logic 1 is achieved by measuring the leakage current of the semiconductor device. The semiconductor device provided by the embodiment of the present application can use the acceptor-doped first cap layer 231 to control the direction of the threshold voltage drift of the storage functional area 200 to achieve the characterization of the two states, thereby realizing the storage function of the HEMT device.

[0064] According to some embodiments of the first aspect of the present application, the orthographic projection of the first ohmic electrode 232 on the substrate falls within the orthographic projection range of the first cap layer 231 on the substrate.

[0065] Specifically, the orthographic projection of the portion of the first ohmic electrode 232 located in the storage functional area 200 on the substrate falls within the orthographic projection range of the first cap layer 231 on the substrate.

[0066] Optionally, in one embodiment, the first cap layer 231 is only disposed in the storage functional area 200. In other words, along the second direction, the first cap layer 231 does not extend toward the control functional area 300 and the connection section between the storage functional area 200 and the control functional area 300.

[0067] According to some embodiments of the first aspect of this application, please refer to Figure 4 and Figure 5 The control functional region 300 further includes a second cap layer 340 . The second cap layer 340 is sandwiched between the first electrode 310 and the barrier layer 150 . The second cap layer 340 is acceptor-type doped.

[0068] Optionally, the orthographic projection of the first electrode 310 on the substrate falls within the orthographic projection range of the second cap layer 340 on the substrate.

[0069] Please refer to Figure 4The acceptor-doped second cap layer 340 can form a PN junction diode with the barrier layer 150 below it. The PN junction diode and the parasitic heterojunction are selectively turned on to achieve the writing of logic "1" or "0". Specifically, when a negative voltage is applied to the gate 234, the potential of the first ohmic electrode 232 decreases, the potential of the second electrode 320 is lower than the potential of the first electrode 310, the PN junction diode is turned on, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned off, and the storage functional area 200 is written with logic "1". When a positive voltage is applied to the gate 234, the potential of the first ohmic electrode 232 increases, the potential of the second electrode 320 is higher than the potential of the first electrode 310, the PN junction diode is reverse biased, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned on, and the storage functional area 200 is written with logic "0".

[0070] Optionally, the material of the second cap layer 340 includes gallium nitride.

[0071] Further optionally, the material of the second capping layer 340 is the same as that of the first capping layer 231 , and the second capping layer 340 and the first capping layer 231 can be simultaneously prepared by patterning to simplify the preparation of the semiconductor device in the embodiment of the present application.

[0072] Further optionally, the first capping layer 231 and the second capping layer 340 have the same ion doping concentration.

[0073] According to some embodiments of the first aspect of the present application, the first electrode 310 and the barrier layer 150 are in Schottky contact, and the work function of the first electrode 310 is greater than the work function of the barrier layer 150 .

[0074] Optionally, the work function of the first electrode 310 is greater than the electron affinity of the material of the barrier layer 150 .

[0075] Optionally, the first electrode 310 includes at least one of nickel, platinum, tungsten, and titanium nitride.

[0076] Optionally, the material of the first electrode 310 is the same as that of the source electrode 210 , and the first electrode 310 and the source electrode 210 can be simultaneously prepared by a patterning process.

[0077] Optionally, the first electrode 310 is prepared after the surface of the barrier layer 150 is subjected to a low-temperature annealing treatment, so as to optimize the interface quality and avoid the formation of ohmic contact.

[0078] See also Figure 6, the first electrode 310 can form a Schottky diode with the barrier layer 150 below it, and the Schottky diode and the parasitic heterojunction are selectively turned on to achieve the writing of logic "1" or "0". Specifically, when a negative voltage is applied to the gate 234, the potential of the first ohmic electrode 232 decreases, the potential of the second electrode 320 is lower than the potential of the first electrode 310, the Schottky diode is turned on, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned off, and the storage functional area 200 is written with logic "1"; when a positive voltage is applied to the gate 234, the potential of the first ohmic electrode 232 increases, the potential of the second electrode 320 is higher than the potential of the first electrode 310, the Schottky diode is reverse biased, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned on, and the storage functional area 200 is written with logic "0".

[0079] According to some embodiments of the first aspect of the present application, please refer to Figure 7 The control functional area 300 also includes a third cap layer 352 and a second ohmic electrode 351. The third cap layer 352 is arranged between the first electrode 310 and the second electrode 320 along the first direction. The second ohmic electrode 351 is arranged on the side of the third cap layer 352 away from the barrier layer 150. The second ohmic electrode 351 is electrically connected to the first electrode 310.

[0080] This embodiment provides a field-effect rectifier in the control functional area 300, wherein a first electrode 310 serves as the source of the field-effect rectifier, a second ohmic electrode 351 serves as the gate of the field-effect rectifier, and a second electrode 320 serves as the drain of the field-effect rectifier. Referring to the figure, the first electrode 310 and the second ohmic electrode 351 are short-circuited to form the anode of the control functional area 300, and the second electrode 320 serves as the cathode of the control functional area 300. The potential of the first ohmic electrode 232 is adjusted by the gate voltage of the storage functional area 200. The field-effect rectifier is switched on and off by lowering or raising the potential of the second electrode 320. The field-effect rectifier and the parasitic heterojunction are selectively turned on to write a logic "1" or "0".

[0081] Specifically, when a negative voltage is applied to the gate 234, the potential of the first ohmic electrode 232 decreases, the potential of the first electrode 310 and the second ohmic electrode 351 is higher than the potential of the second electrode 320, and the potential of the second ohmic electrode 351 is higher than the threshold voltage. A 2DEG exists under the third cap layer 352 to make the first electrode 310 and the second electrode 320 conductive, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas thereunder is turned off, and logic "1" is written to the storage functional area 200; when a positive voltage is applied to the gate 234, the potential of the first ohmic electrode 232 increases, the potential of the second electrode 320 is higher than the potential of the first electrode 310, i.e., the second ohmic electrode 351, the gate of the field-effect rectifier cannot reach the threshold voltage, and there is no conductive channel between the first electrode 310 and the second electrode 320. The field-effect rectifier is turned off, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas thereunder is turned on, and logic "0" is written to the storage functional area 200.

[0082] Optionally, the material of the third cap layer 352 includes gallium nitride.

[0083] Optionally, the third cap layer 352 is acceptor-type doped.

[0084] Further optionally, the third capping layer 352 and the first capping layer 231 are prepared synchronously through a patterning process step.

[0085] Optionally, the second ohmic electrode 351 is made of the same material as the first ohmic electrode 232 .

[0086] Further optionally, the second ohmic electrode 351 and the first ohmic electrode 232 are prepared synchronously through a patterning process step.

[0087] According to some embodiments of the first aspect of this application, please refer to Figure 8 and Figure 9 The control functional area 300 also includes a channel-forming layer 360 and a third electrode 330. The channel-forming layer 360 is arranged on the side of the barrier layer 150 away from the substrate 110. The channel-forming layer 360 is acceptor-type doped. The third electrode 330 is arranged on the side of the channel-forming layer 360 away from the substrate 110 and a second gate dielectric layer 370 is arranged between the third electrode 330 and the channel-forming layer 360. The third electrode 330 is arranged between the first electrode 310 and the second electrode 320 along the first direction.

[0088] In this embodiment, a P-type field effect transistor is provided in the control function area 300, the first electrode 310 serves as the source of the P-type field effect transistor, the third electrode 330 serves as the gate of the P-type field effect transistor, and the second electrode 320 serves as the drain of the P-type field effect transistor. The conduction or shutdown of the P-type field effect transistor is controlled by adjusting the voltage of the third electrode 330.

[0089] In this embodiment, the third electrode 330 is electrically connected to the gate 234 , and the on / off state of the P-type field effect transistor can be controlled by adjusting the voltage of the gate 234 .

[0090] Optionally, the material of the second gate dielectric layer 370 is the same as that of the first gate dielectric layer 233 .

[0091] Further optionally, the second gate dielectric layer 370 and the first gate dielectric layer 233 are simultaneously prepared through a patterning process.

[0092] Optionally, the material of the third electrode 330 is the same as that of the gate 234 of the storage functional area 200 .

[0093] Further optionally, the third electrode 330 and the gate 234 of the storage functional area 200 are prepared synchronously through a patterning process step.

[0094] Optionally, the material of the channel forming layer 360 is the same as that of the first capping layer 231 , so as to facilitate integration of the storage functional area 200 and the control functional area 300 while reducing parasitic effects.

[0095] Further optionally, the channel forming layer 360 and the first capping layer 231 are simultaneously prepared by a patterning process step.

[0096] According to some embodiments of the first aspect of the present application, please refer to Figure 9 The channel formation layer 360 includes a first region 361, a channel formation region 363 and a second region 362 arranged in sequence along the first direction. The thickness of the channel formation region 363 is less than the thickness of the first region 361, and the thickness of the channel formation region 363 is less than the thickness of the second region 362. The orthographic projection of the channel formation region 363 on the substrate falls within the orthographic projection range of the gate 234 on the substrate.

[0097] Thus, by thinning a portion of the channel-forming layer 360 to form a channel-forming region 363, a normally-off P-type field-effect transistor (P-type field-effect transistor) is provided in the control functional region 300. This normally-off P-type field-effect transistor and the parasitic heterojunction are selectively turned on to achieve the writing of a logic "1" or "0." Specifically, when a negative voltage is applied to the gate 234, the normally-off P-type field-effect transistor is turned on, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned off, and a logic "1" is written to the storage functional region 200. When a positive voltage is applied to the gate 234, the normally-off P-type field-effect transistor is turned off, and the parasitic heterojunction formed by the first cap layer 231 and the two-dimensional electron gas below it is turned on, and a logic "0" is written to the storage functional region 200.

[0098] The semiconductor device provided by the embodiments of the present application simplifies control conditions while achieving a storage function. A logic "0" or "1" can be written to the storage functional area 200 simply by adjusting the voltage of the gate 234 at the storage functional area 200. Furthermore, the semiconductor device provided by the embodiments of the first aspect of the present application can be implemented based on existing HEMT device fabrication methods. The integration of the control functional area 300 and the storage functional area 200 can be achieved through layout design, resulting in low production costs.

[0099] The present application also includes other embodiments that can integrate unidirectional conductive devices on the barrier layer 150 to form a control functional area 300. It is difficult for the present application to give exhaustive examples here, but the technical solutions obtained by those skilled in the art through equivalent replacement and other means on the basis of the embodiments disclosed in the present application should be included in the protection scope of the present application.

[0100] Second, see Figure 10 The embodiment of the present application provides a semiconductor device, which includes a substrate, a source electrode 210, a gate electrode 234, a fourth cap layer 410, and a drain electrode 220. The substrate includes a substrate 110, a buffer layer 130, a channel layer 140, and a barrier layer 150 stacked in sequence. The interface between the barrier layer 150 and the channel layer 140 is configured to generate a two-dimensional electron gas. The fourth cap layer 410 is arranged on a side of the barrier layer 150 facing away from the substrate 110. The fourth cap layer 410 includes a connection structure 411, a channel structure 412, and a storage structure 413 arranged in sequence along a first direction. The thickness of structure 412 is less than the thickness of connection structure 411 and the thickness of channel structure 412 is less than the thickness of storage structure 413; the source 210 is arranged on the side of barrier layer 150 away from substrate 110, and the source 210 is arranged in contact with barrier layer 150 and connection structure 411 at the same time; the drain 220 is arranged on the side of barrier layer 150 away from substrate 110, and the drain 220 is spaced apart from storage structure 413; the gate 234 is arranged on the side of fourth cap layer 410 away from substrate 110, and a third gate dielectric layer 420 is arranged between the gate 234 and the fourth cap layer 410.

[0101] The second embodiment of the present application provides a solution for direct on-chip integration of a P-type field effect transistor and a HEMT device, where the HEMT device and the P-type field effect transistor can share a source 210 and a gate 234 .

[0102] In some embodiments, the substrate further includes a transition layer 120 , which is disposed between the substrate 110 and the buffer layer 130 to balance the lattice adaptation between the substrate 110 and the buffer layer 130 , reduce interface stress, and improve the growth quality of the buffer layer 130 .

[0103] Optionally, the material of the third gate dielectric layer 420 includes at least one of aluminum oxide, silicon dioxide, silicon nitride, aluminum nitride, and hafnium oxide.

[0104] According to some embodiments of the second aspect of the present application, the source electrode 210 includes a first conductive metal 211 and a second conductive metal 212, and the first conductive metal 211 is electrically connected to the second conductive metal 212. The first conductive metal 211 is in ohmic contact with the barrier layer 150, and the second conductive metal 212 is in ohmic contact with the connection structure 411.

[0105] Optionally, the first conductive metal 211 is disposed on a side of the barrier layer 150 facing away from the substrate 110 .

[0106] Optionally, the first conductive metal 211 extends into the barrier layer 150 and is disposed on a side of the channel layer 140 facing away from the substrate 110 .

[0107] It can be understood that the first conductive metal 211 and the second conductive metal 212 are made of different materials to respectively achieve ohmic contact with the barrier layer 150 and the fourth cap layer 410 , which are made of two different materials.

[0108] Optionally, the second conductive metal 212 is partially disposed on a side of the connection structure 411 facing away from the barrier layer 150 .

[0109] Further optionally, the orthographic projection of the second conductive metal 212 on the substrate partially overlaps with the orthographic projection of the connection structure 411 on the substrate.

[0110] According to some embodiments of the second aspect of the present application, the orthographic projection of the channel structure 412 on the substrate falls within the orthographic projection of the gate 234 on the substrate, and the orthographic projection of the storage structure 413 on the substrate at least partially falls within the orthographic projection of the gate 234 on the substrate.

[0111] Optionally, the orthographic projection of the storage structure 413 on the substrate entirely falls within the orthographic projection of the gate 234 on the substrate.

[0112] Optionally, the orthographic projection of the gate 234 on the substrate is consistent with the orthographic projection range of the fourth cap layer 410 on the substrate.

[0113] Thus, by applying a negative voltage to the gate 234 , the P-type field effect transistor can be turned on and the parasitic heterojunction can be turned off synchronously, or by applying a positive voltage to the gate 234 , the P-type field effect transistor can be turned off and the parasitic heterojunction can be turned on synchronously.

[0114] According to some embodiments of the second aspect of the present application, the orthographic projection of the fourth cap layer 410 on the substrate falls within the orthographic projection range of the gate 234 on the substrate.

[0115] In a third aspect, an embodiment of the present application provides a method for using a semiconductor device, which is applied to the semiconductor device provided in any embodiment of the first aspect or the second aspect, and the method includes:

[0116] S200, providing a first voltage or a second voltage to the gate 234 for a first duration and then setting the gate 234 voltage to zero, wherein the first voltage is a positive voltage and the second voltage is a negative voltage;

[0117] S300 , providing a read voltage to the gate 234 , grounding the source 210 and providing a third voltage to the drain 220 , measuring the drain current, and determining the storage state of the semiconductor device according to the magnitude of the drain current.

[0118] Optionally, in step S300, the third voltage is a positive voltage.

[0119] Optionally, in step S300 , the read voltage is a positive voltage; or, the read voltage is a negative voltage; or, the read voltage is set to zero.

[0120] According to some embodiments of the third aspect of the present application, the method of use further includes:

[0121] S100 , providing a read voltage to the gate 234 , grounding the source 210 and providing a third voltage to the drain 220 to obtain an initial leakage current of the storage functional area 200 .

[0122] It can be understood that the drain current measured in step S300 can be judged with reference to the initial drain current to obtain the storage state of the semiconductor device.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate comprising a substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence, wherein an interface between the channel layer and the barrier layer is configured to generate a two-dimensional electron gas; a storage functional area, disposed on a side of the barrier layer facing away from the substrate, the storage functional area comprising a source electrode, a gate control electrode, and a drain electrode spaced apart along a first direction, the gate control electrode comprising a first cap layer, a first ohmic electrode, and a gate electrode stacked along a thickness direction of the substrate, the first cap layer being in contact with the barrier layer and being acceptor-doped, and the first ohmic electrode being insulated from the gate; a control functional area, disposed on a side of the barrier layer facing away from the substrate, the control functional area comprising a first electrode and a second electrode spaced apart along a first direction, the first electrode being electrically connected to the source electrode, the second electrode being electrically connected to the first ohmic electrode, and capable of switching the control functional area on or off according to the potential of the first electrode and the potential of the second electrode; The orthographic projection of the storage functional area on the substrate and the orthographic projection of the control functional area on the substrate do not overlap with each other and are arranged at intervals along a second direction, and the second direction intersects with the first direction.

2. The semiconductor device according to claim 1, wherein The orthographic projection of the first ohmic electrode on the substrate falls within the orthographic projection range of the first cap layer on the substrate.

3. The semiconductor device according to claim 1, wherein The control functional area further includes a second cap layer, which is sandwiched between the first electrode and the barrier layer, and is acceptor-doped.

4. The semiconductor device according to claim 1, wherein The first electrode and the barrier layer are in Schottky contact, and a work function of the first electrode is greater than a work function of the barrier layer.

5. The semiconductor device according to claim 1, wherein The control functional area also includes a third cap layer and a second ohmic electrode. The third cap layer is arranged between the first electrode and the second electrode along the first direction. The second ohmic electrode is arranged on the side of the third cap layer away from the barrier layer. The second ohmic electrode is electrically connected to the first electrode. The semiconductor device according to claim 1 , wherein: The control functional area also includes a channel formation layer and a third electrode. The channel formation layer is arranged on the side of the barrier layer away from the substrate. The channel formation layer is acceptor-type doped. The third electrode is arranged on the side of the channel formation layer away from the substrate and a second gate dielectric layer is arranged between the third electrode and the channel formation layer. The third electrode is arranged between the first electrode and the second electrode along the first direction.

7. The semiconductor device according to claim 6, wherein: The channel formation layer includes a first region, a channel formation region and a second region arranged in sequence along the first direction, the thickness of the channel formation region is less than the thickness of the first region, the thickness of the channel formation region is less than the thickness of the second region, and the orthographic projection of the channel formation region on the substrate falls within the orthographic projection range of the gate on the substrate.

8. A semiconductor device, characterized in that: include: A substrate comprising a substrate, a buffer layer, a channel layer, and a barrier layer stacked in sequence, wherein an interface between the barrier layer and the channel layer is configured to generate a two-dimensional electron gas; a fourth cap layer, disposed on a side of the barrier layer facing away from the substrate, the fourth cap layer comprising a connection structure, a channel structure, and a storage structure sequentially disposed along a first direction, wherein a thickness of the channel structure is smaller than a thickness of the connection structure, and a thickness of the channel structure is smaller than a thickness of the storage structure; a source electrode, disposed on a side of the barrier layer facing away from the substrate, the source electrode being in contact with both the barrier layer and the connection structure; a drain electrode, disposed on a side of the barrier layer facing away from the substrate, the drain electrode being spaced apart from the storage structure; A gate is arranged on a side of the fourth cap layer facing away from the substrate, and a third gate dielectric layer is arranged between the gate and the fourth cap layer.

9. The semiconductor device according to claim 8, wherein The orthographic projection of the channel structure on the substrate falls within the orthographic projection of the gate on the substrate, and the orthographic projection of the storage structure on the substrate at least partially falls within the orthographic projection of the gate on the substrate.

10. A method for using a semiconductor device, applied to the semiconductor device according to any one of claims 1 to 9, characterized in that: include: Supplying a first voltage or a second voltage to the gate for a first duration and then setting the gate voltage to zero, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; A read voltage is provided to the gate, the source is grounded and a third voltage is provided to the drain, the drain current is measured, and the storage state of the semiconductor device is determined according to the magnitude of the drain current.

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