Manufacturing method and application of combined passivation back contact battery capable of accurately setting reverse electric leakage channel

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a manufacturing method and application of a combined passivation back contact cell capable of accurately setting a reverse electric leakage channel, and the manufacturing method comprises the steps: S5, employing a laser crystallization technology, carrying out the crystallization processing of a part of a second semiconductor layer which is superposed on a first semiconductor layer and is close to the edge of a first opening region, and obtaining a crystallization region; s6, forming a second opening area which is arranged at an interval with the first opening area; s7, depositing a transparent conductive film layer on the back surface; and S8, an isolation groove is formed, at least part of the isolation groove corresponds to the crystallization area, and the crystallization area, the first doped polycrystalline silicon layer and the transparent conductive film layer form a reverse electric leakage channel PN junction. According to the invention, the reverse electric leakage capability of the PN junction of the reverse electric leakage channel is obviously improved, the effects of dispersing the reverse leakage current and reducing the hot spot effect of the battery are achieved, and meanwhile, relatively high battery efficiency is obtained; a bypass diode can be omitted, cost is reduced, battery attenuation is reduced, and generating capacity is increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and in particular relates to a method for preparing and applying a combined passivated back-contact battery with a precisely set reverse leakage channel. Background Art

[0002] Current research has shown that providing a reverse leakage path in back-contact solar cells is an effective method for reducing the hot spot effect and improving power generation in situations where the cells are partially obscured. One existing method, such as CN118630076A, discloses that at least part of the overlapping region between two semiconductors in a cross-digital structure is a reverse leakage region. By controlling the crystallization rate of the overlapping region (i.e., directly depositing a film with a certain crystallization rate overall) and combining this with etching patterns on the transparent conductive film, the location and distribution of the reverse leakage region can be controlled.

[0003] However, the aforementioned methods for creating reverse leakage channels all rely on controlling the coating process. Controlling the leakage channels during the coating process (e.g., controlling the crystallization rate of the film layer and / or micro-etching the surface of the polycrystalline film layer) has the following drawbacks: first, only all film layers, or the entire region of the film layer, can be processed uniformly; no single local or specific location can be processed separately, and thus individual parameters cannot be set for each leakage channel. Second, adjusting and controlling the coating process can cause changes in the parameters of the functional film layer, requiring simultaneous adjustments to the parameters of other film layers in the solar cell, increasing the difficulty of the process and thus affecting the cell efficiency.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art in that the method of making reverse leakage channels in back-contact batteries cannot be independently controlled and will affect the parameter changes of the functional film layer, thereby affecting the battery efficiency, battery attenuation and battery hot spot effect, and provide a combined passivation back-contact battery preparation method and application for accurately setting the reverse leakage channel. The preparation method of the present invention significantly increases the reverse leakage capacity of the PN junction of the reverse leakage channel, and can relatively accurately control the leakage effect of each reverse leakage channel to achieve the effect of dispersing the reverse leakage current and reducing the battery hot spot effect, while obtaining higher battery efficiency; the use of bypass diodes can be eliminated, reducing costs, reducing battery attenuation, and increasing power generation.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a combined passivated back contact cell with a precisely set reverse leakage channel, comprising: forming alternately spaced first semiconductor layers on the back side of a silicon wafer, forming a first opening region between two adjacent first semiconductor layers, wherein the silicon wafer in the first opening region is a textured surface, and then depositing a second semiconductor layer on the back side; wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer arranged in sequence, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence, wherein the second doped crystalline silicon layer is a correspondingly doped amorphous silicon or microcrystalline silicon, and further comprising the following steps: S5. Using laser crystallization technology, crystallize the portion of the second semiconductor layer superimposed on the first semiconductor layer and close to the edge of the first opening area to obtain a crystallized area, and the crystallized area corresponds to the position of the preset reverse leakage channel PN junction; and control the area of the crystallized area corresponding to the single preset reverse leakage channel to be within 0.0001mm 2 -0.5mm 2 ; S6, performing a second etching on a portion of the second semiconductor layer located on the first semiconductor layer to form a second opening region spaced apart from the first opening region; S7, depositing a transparent conductive film layer on the back side; S8, performing a third etching on a portion of the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second opening area to form an isolation trench, wherein at least a portion of the isolation trench corresponds to the crystallized area, and the crystallized area, the first doped polysilicon layer, and the transparent conductive film layer form a reverse leakage channel PN junction; S9, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

[0007] In some preferred embodiments of the present invention, the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled within 0.0015 mm in S5. 2 -0.05mm 2 .

[0008] In some preferred embodiments of the present invention, in S5 , the crystallization rate of the crystallized region of the locally crystallized second semiconductor layer is controlled to be between 2% and 60%.

[0009] In some preferred embodiments of the present invention, in S5, the crystallization treatment conditions include: controlling the laser pulse energy density to be 50-400 mJ / cm 2 , the laser pulse width is less than 100ns.

[0010] In some preferred embodiments of the present invention, the laser wavelength used in the laser crystallization technology is 248-805 nm.

[0011] In some preferred embodiments of the present invention, the laser crystallization technology uses ultraviolet nanosecond laser.

[0012] In some preferred embodiments of the present invention, the isolation trench extends to cross the first opening region, and the cross-section of the isolation trench in the first opening region is not provided with a reverse leakage channel, and the reverse leakage channel is provided on the overlapping region.

[0013] In some preferred embodiments of the present invention, the reverse leakage channel PN junctions are evenly distributed on the back side.

[0014] In some preferred embodiments of the present invention, the thickness of the crystallized region of the second semiconductor layer is smaller than the thickness of the uncrystallized portion of the second semiconductor layer.

[0015] In some preferred embodiments of the present invention, the first semiconductor layers are alternately arranged on the back of the silicon wafer, and a first opening area is formed between two adjacent first semiconductor layers. The silicon wafer in the first opening area is a texturing surface, and then the second semiconductor layer is deposited on the back. The process adopts the following post-texturing method: S1. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S2, performing a first etching on the back surface obtained in S1 to form a first opening area; S3, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer; S4. Depositing a second semiconductor layer on the back side.

[0016] In a second aspect, the present invention provides a combined passivated back contact battery, which is prepared by the combined passivated back contact battery preparation method with precisely set reverse leakage channels described in the first aspect.

[0017] In a third aspect, the present invention provides a back-contact battery module that does not require a bypass diode, which includes several combined passivated back-contact batteries as described in the second aspect. Several combined passivated back-contact batteries are connected in series to form a battery string, and no bypass diode is required at the end of the battery string.

[0018] Beneficial effects: The present invention adopts the above-mentioned technical solution, especially adopts the laser crystallization technology to perform local crystallization treatment on the second semiconductor layer after forming it, so that the film layer of local amorphous silicon or microcrystalline silicon is thinned and crystallized, and the degree of crystallization of the local second semiconductor layer is improved. The instantaneous high temperature of laser crystallization causes the amorphous silicon or microcrystalline silicon to crystallize, and at the same time, more defects are introduced at the interface, thereby increasing the leakage current and facilitating the formation of a reverse leakage channel. In combination with controlling the area of the crystallized region within an appropriate range and coordinating with other structural arrangements such as the isolation trench, a reverse leakage channel of a specific appropriate area can be provided at a specific position near the edge of the first opening region, and the reverse leakage capacity of the PN junction of the reverse leakage channel is significantly increased, so that the battery can achieve the effect of effectively dispersing the reverse current, thereby effectively improving the hot spot effect of the combined passivated back contact battery. In addition, the preparation method of the present invention can perform a separate crystallization treatment on each PN junction of the reverse leakage channel, and can independently control the laser crystallization area, so that the leakage effect of each reverse leakage channel can be relatively accurately controlled, so as to achieve the effect of dispersing the reverse leakage current and reducing the hot spot effect of the battery, while obtaining higher battery efficiency. The use of bypass diodes can be eliminated, reducing costs, reducing battery attenuation, and increasing power generation. Furthermore, the reverse leakage path within the crystallized region is independent of the film deposition process, and variations in the coating process will not affect the film's functional parameters. If the crystallized region is too large, the reverse resistance of the reverse leakage path will be too low, leading to excessive reverse leakage current and localized hot spots, potentially reducing battery efficiency. If the region is too small, the reverse leakage current will be too low, preventing the formation of a stable and effective leakage path, resulting in limited improvement in the hot spot effect.

[0019] Among them, the present invention adopts laser crystallization technology after forming the second semiconductor layer, combined with other structures such as passivation, which can significantly increase the reverse leakage capacity of the local reverse leakage channel PN junction. This is because, on the one hand, the film layer is thinned after laser crystallization (because the film layer is locally heated by laser, the local film layer is crystallized, and because the film layer's absorption of laser gradually decreases with the increase of film thickness, the laser absorption at the surface of the film layer is greater than that at the bottom, and the temperature is higher. The high temperature will cause the surface film layer to ablate, while the bottom is affected by the thermal effect and crystallizes accordingly, thereby thinning the film layer). After thinning, the longitudinal resistance is reduced, and the resistivity of the film layer is reduced after crystallization, and the conductivity is significantly increased; on the other hand, the thermal effect of the laser treatment process will cause more defects to be generated at the interface between the polycrystalline layer and the amorphous layer, increasing the reverse dark current of the reverse leakage channel PN junction. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A cross-sectional view of a back-contact battery according to a specific embodiment of the present invention.

[0022] Figure 2 for Figure 1 A partial enlarged view of .

[0023] Figure 3 This is the infrared distribution diagram of reverse pressurization of Example 1 of the present invention.

[0024] Description of Reference Numerals 1. Silicon wafer, 21. N-type doped polysilicon layer, 21a. Tunneling silicon oxide layer, 22. P-type doped amorphous silicon layer, 22a. Intrinsic amorphous silicon layer, 31. First transparent conductive film layer, 32. Second transparent conductive film layer, 4. Isolation trench, 41. Reverse leakage channel, 42. Crystallized region, 51. N-type fine gate electrode, 52. P-type fine gate electrode. DETAILED DESCRIPTION

[0025] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0026] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0027] The endpoints of the ranges and any values disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0028] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0029] In the present invention, the crystallization rate of the crystallized area is measured by taking a transmission electron microscope (TEM) image. Specifically, a sample of the crystallized area is prepared, and a high-resolution transmission electron microscope image of the film is obtained at the corresponding position. The image is analyzed, the number, size and distribution of the grains are counted, and the area ratio of the grains is calculated to obtain the crystallization rate.

[0030] In its first aspect, the present invention provides a method for fabricating a combined passivated back-contact cell with a precisely configured reverse leakage channel, comprising: forming alternating first semiconductor layers on the back side of a silicon wafer, forming a first opening region between two adjacent first semiconductor layers, wherein the silicon wafer within the first opening region is textured, and then depositing a second semiconductor layer on the back side; wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer disposed in sequence, and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped crystalline silicon layer disposed in sequence. The second doped crystalline silicon layer is amorphous silicon or microcrystalline silicon with the corresponding doping.

[0031] The preparation method of the present invention further comprises the steps of: S5. Using laser crystallization technology, crystallize a portion of the second semiconductor layer superimposed on the first semiconductor layer and close to the edge of the first opening region to obtain a crystallized region, wherein the crystallized region corresponds to a position of a preset reverse leakage channel PN junction; S6, performing a second etching on a portion of the second semiconductor layer located on the first semiconductor layer to form a second opening region spaced apart from the first opening region; S7, depositing a transparent conductive film layer on the back side; S8, performing a third etching on a portion of the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second opening area to form an isolation trench, wherein at least a portion of the isolation trench corresponds to the crystallized area, and the crystallized area, the first doped polysilicon layer, and the transparent conductive film layer form a reverse leakage channel PN junction; S9, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

[0032] Preferably, in S5, the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled to be within 0.0001 mm 2 -0.5mm 2 .

[0033] In some preferred embodiments of the present invention, the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled within 0.0015 mm in S5. 2 -0.05mm 2 , preferably 0.0015mm 2 -0.02mm 2The use of a narrow crystallized region is more conducive to accurately controlling the resistance of a single reverse leakage channel within an appropriate range, ensuring the normal operation of the battery while improving battery efficiency and effectively avoiding battery degradation.

[0034] In some preferred embodiments of the present invention, in S5, the crystallization rate of the crystallized region where the second semiconductor layer is locally crystallized is controlled to be between 2% and 60%, more preferably between 5% and 60%, and even more preferably between 5% and 18%. The present invention controls the crystallization rate of the crystallized region within a suitable range, which is more conducive to optimizing the distribution of the area and number of individual reverse leakage channels by adjusting the resistance of individual reverse leakage channels, further improving the effect of dispersing reverse leakage current and reducing the battery hot spot effect, while achieving higher battery efficiency.

[0035] In some preferred embodiments of the present invention, in S5, the crystallization treatment conditions include: controlling the laser pulse energy density to be 50-400 mJ / cm 2 , the laser pulse width is less than 100ns. The preferred crystallization treatment conditions of the present invention are more conducive to optimizing the energy absorption efficiency of different film layers according to the film structure, so that the target film layer absorbs energy to achieve the desired crystallization effect, avoiding damage to the film structure or poor crystallization effect caused by excessive or insufficient energy.

[0036] In some preferred embodiments of the present invention, the laser crystallization technology utilizes a laser wavelength between 248 and 805 nm. Any laser type capable of crystallizing amorphous silicon can be used in the present invention, such as quasi-infrared (805 nm), green (532 nm), ultraviolet (355 nm), and excimer (248 nm) lasers. The crystallized region obtained by laser crystallization in the present invention primarily refers to the region obtained by laser crystallization of the second doped crystalline silicon layer; the intrinsic amorphous silicon layer may also be crystallized to a certain extent, and the degree of crystallization varies depending on the laser crystallization conditions. Nevertheless, the excellent effects of the present invention can be achieved in all cases.

[0037] In some preferred embodiments of the present invention, the laser crystallization technology uses ultraviolet nanosecond laser, which is more conducive to improving the absorption of laser energy by the surface layer, i.e., the second doped crystalline silicon layer, improving the crystallization rate of the second doped crystalline silicon layer in the surface layer, and reducing excessive damage of the laser energy to the interface of the bottom film layer.

[0038] The isolation trench of the present invention can be located entirely or partially in the overlapping region. In some preferred embodiments of the present invention, the isolation trench extends to cross a portion of the first opening region, and the reverse leakage path is not provided in the cross-section of the isolation trench within the first opening region; instead, the reverse leakage path is provided in the overlapping region. In this preferred embodiment, a portion of the isolation trench is located in the overlapping region, while another portion is located in the region where the first opening region is located.

[0039] In some preferred embodiments of the present invention, the reverse leakage channel PN junctions are evenly distributed on the back side.

[0040] In some preferred embodiments of the present invention, the thickness of the crystallized region of the second semiconductor layer is smaller than the thickness of the uncrystallized portion of the second semiconductor layer.

[0041] In some preferred embodiments of the present invention, the first semiconductor layers are alternately arranged on the back of the silicon wafer, and a first opening area is formed between two adjacent first semiconductor layers. The silicon wafer in the first opening area is a texturing surface, and then the second semiconductor layer is deposited on the back. The process adopts the following post-texturing method: S1. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S2, performing a first etching on the back surface obtained in S1 to form a first opening area; S3, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer; S4. Depositing a second semiconductor layer on the back side.

[0042] The thicknesses and corresponding doping concentrations of the tunnel oxide layer, intrinsic amorphous silicon layer, first doped polysilicon layer, and second doped crystalline silicon layer of the present invention can refer to the ranges of the prior art and can all be used in the present invention. For example, the thickness of the tunnel oxide layer is 1-2nm, the thickness of the intrinsic amorphous silicon layer is 5-15nm; the thickness of the second doped crystalline silicon layer is 7-45nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 The thickness of the first doped polysilicon layer is 30-250 nm, and the effective doping concentration is greater than 5e18 cm -3 .

[0043] Preferably, the preparation method further comprises sequentially disposing a front passivation layer and an anti-reflection layer on the front side of the silicon wafer, either before or after depositing the second semiconductor layer. The front passivation layer and anti-reflection layer of the present invention can be prepared in accordance with existing techniques. Preferably, the front passivation layer is at least one of an amorphous silicon passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer. For example, the anti-reflection layer can be at least one of silicon nitride, aluminum oxide, and silicon oxide.

[0044] Preferably, the anti-reflection layer is a combination of silicon nitride and silicon oxide, the thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon oxide is 80-150 nm.

[0045] More preferably, the front passivation layer is a combination of silicon oxide and aluminum oxide, the thickness of the silicon oxide is 1-2 nm, and the thickness of the aluminum oxide is 3-4 nm.

[0046] In a second aspect, the present invention provides a combined passivated back contact battery, which is prepared by the combined passivated back contact battery preparation method with precisely set reverse leakage channels described in the first aspect.

[0047] In a third aspect, the present invention provides a back-contact cell module that does not require a bypass diode. The module comprises several of the combined passivated back-contact cells described in the second aspect, connected in series to form a cell string. No bypass diodes are required at the ends of the cell string. The back-contact cell module of the present invention protects cells from hot spot damage without requiring bypass diodes, while achieving higher cell efficiency. By eliminating the need for bypass diodes, the module reduces costs and increases power generation.

[0048] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0049] Example 1 A combined passivated back contact battery with a precisely set reverse leakage channel, the structure is as follows Figure 1 and Figure 2 As shown, the preparation method is as follows: S1. A first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer 1. The first semiconductor layer comprises a tunneling oxide layer (i.e., a tunneling silicon oxide layer 21a) with a thickness of 1.5 nm and a first doped polysilicon layer (i.e., an N-type doped polysilicon layer 21). The first doped polysilicon layer has a thickness of 100 nm and an effective doping concentration of 5e19 cm -3 ; S2, performing a first etching on the back surface obtained in S1 to form a first opening area; S3, forming a textured surface at least in the first opening area and also forming a textured surface on the front side of the silicon wafer 1 by texturing cleaning, and removing the mask layer; S4. A front passivation layer and an anti-reflection layer are sequentially provided on the front side of the silicon wafer 1, and then a second semiconductor layer is deposited on the back side. The second semiconductor layer comprises an intrinsic amorphous silicon layer 22a with a thickness of 5 nm and a second doped amorphous silicon layer (i.e., a P-type doped amorphous silicon layer 22) which are sequentially provided. The second doped crystalline silicon layer has a thickness of 10 nm and an effective doping concentration of 2e19 cm -3 ; S5. Using laser crystallization technology, a portion of the second semiconductor layer superimposed on the first semiconductor layer and close to the edge of the first opening region is crystallized to obtain a crystallized region 42. The crystallized region 42 corresponds to the PN junction position of the preset reverse leakage channel 41. The area of the crystallized region 42 corresponding to the single preset reverse leakage channel 41 is controlled to be within 0.005 mm. 2 The crystallization rate of the crystallized region 42 is 10%; the thickness of the crystallized region 42 of the second semiconductor layer is less than the thickness of the non-crystallized portion of the second semiconductor layer; Laser crystallization technology uses ultraviolet nanosecond laser with a pulse energy density of 100mJ / cm 2 , laser pulse width 50ns.

[0050] S6, performing a second etching on a portion of the second semiconductor layer located on the first semiconductor layer to form a second opening region spaced apart from the first opening region; S7, depositing a transparent conductive film layer on the back side; S8. Perform a third etching on the portion of the transparent conductive film layer corresponding to the overlapping region between the first opening region and the second opening region to form an isolation trench 4. The isolation trench 4 is located on the overlapping region, and at least a portion of the isolation trench 4 corresponds to the crystallized region 42. The crystallized region 42 and its corresponding intrinsic amorphous silicon layer 22a, the first doped polysilicon layer, and the transparent conductive film layer form a reverse leakage channel 41 PN junction. The reverse leakage channel 41 PN junction is evenly distributed on the back surface. The isolation trench 4 divides the transparent conductive film layer into a first transparent conductive film layer 31 corresponding to the N-type region and a second transparent conductive film layer 32 corresponding to the P-type region. S9 , forming an N-type fine gate electrode 51 and a P-type fine gate electrode 52 on the transparent conductive film layer in the first opening area and the second opening area, respectively, to form metal electrodes.

[0051] The obtained back contact battery was subjected to reverse pressure infrared test, and the infrared distribution was as follows Figure 3 As shown, it can be seen that the reverse leakage channel is divided into multiple points, and the reverse current is dispersed in multiple areas of the battery cell.

[0052] The obtained back-contact cells were assembled into a battery string module, specifically by connecting 20 back-contact cells in series, with the ends directly led out through wires without providing a bypass diode.

[0053] Example 2 The process is carried out in accordance with Example 1, except that the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled to be 0.025 mm in S5. 2 .

[0054] Example 3 The process is carried out in accordance with Example 1, except that in S5, the crystallization rate of the crystallized region for controlling the local crystallization of the second semiconductor layer is 20%. To meet this condition, the process parameters to be controlled are: the laser pulse energy density is 155 mJ / cm 2 .

[0055] Example 4 The process was carried out in accordance with Example 1, except that in S5, the pulse energy density was adjusted to 80 mJ / cm 2 , making the crystallization rate of the crystallized area 3%.

[0056] Example 5 The process is carried out in accordance with Example 1, except that the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled to be 0.0009 mm in S5. 2 .

[0057] Comparative Example 1 The process is carried out in accordance with Example 1, except that the crystallization treatment of S5 is not performed.

[0058] Comparative Example 2 The process is carried out with reference to Example 1, except that when forming the second doped crystalline silicon layer, the crystallization rate of the film layer is controlled to be the same as the crystallization rate of the crystallization region in Example 1, and the crystallization process of S5 is not performed.

[0059] Comparative Example 3 The process is carried out in accordance with Example 1, except that the area of the crystallized region corresponding to the single preset reverse leakage channel is controlled to be 0.6 mm in S5. 2 .

[0060] Test Case The battery string modules obtained in the above examples and comparative examples were subjected to performance testing, and the results are shown in Table 1. The battery IV parameters (fill factor, battery efficiency, and parallel resistance) and the reverse bias maximum temperature test values were all taken as the median values of all battery cells tested in the corresponding example grouping.

[0061] The test method for the maximum reverse bias temperature is as follows: for a single cell, reverse bias 15V for 2 minutes, and use an infrared thermal imager to test the maximum temperature reached by the cell.

[0062] The test method for the percentage of battery string power attenuation when a single battery cell is blocked is as follows: for a small module consisting of a single battery cell string connected in series, the battery string power when tested without any blocking is recorded as W1; the battery string power when tested with a black curtain blocking a single battery cell in the battery string is recorded as W2, T = (W2-W1) / W1×100%.

[0063] After the single cell blocks the outdoor hot spot test, the battery string power attenuation percentage is: the battery string power before the outdoor hot spot test is recorded as W0; the battery string power after the single cell blocks the outdoor hot spot test is recorded as W t The battery string module obtained from the corresponding example without the bypass diode installed was subjected to an outdoor hot spot simulation test for 60 days to compare the battery string power attenuation percentage before and after the test. The battery string power attenuation percentage is calculated as follows: t = (W t -W0) / W0×100%.

[0064] Table 1

[0065] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention significantly increases the reverse leakage capacity of the PN junction of the reverse leakage channel, and can relatively accurately control the leakage effect of each reverse leakage channel to achieve the effect of dispersing the reverse leakage current and reducing the battery hot spot effect, while obtaining higher battery efficiency; the use of the bypass diode can be eliminated, reducing costs, reducing battery attenuation, and increasing power generation.

[0066] Furthermore, according to Examples 1 and 2-5, it can be seen that the preferred scheme of the present invention is more conducive to controlling the battery parallel resistance Rsh within an appropriate range, avoiding the impact of Rsh being too small on battery efficiency, and at the same time avoiding the defects of Rsh being too large, resulting in excessive reverse bias temperature and more obvious attenuation of the battery string outdoor hot spot attenuation test.

[0067] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel, comprising: A first semiconductor layer is formed on the back side of a silicon wafer, and a first opening area is formed between two adjacent first semiconductor layers. The silicon wafer in the first opening area is a textured surface. Then, a second semiconductor layer is deposited on the back side. The first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer arranged in sequence. The second semiconductor layer includes an intrinsic amorphous silicon layer and a second doped crystalline silicon layer arranged in sequence. The second doped crystalline silicon layer is a correspondingly doped amorphous silicon or microcrystalline silicon. The method further includes the following steps: S5. Using laser crystallization technology, crystallize the portion of the second semiconductor layer superimposed on the first semiconductor layer and close to the edge of the first opening area to obtain a crystallized area, and the crystallized area corresponds to the position of the preset reverse leakage channel PN junction; and control the area of the crystallized area corresponding to the single preset reverse leakage channel to be within 0.0001mm 2 -0.5mm 2 ; S6, performing a second etching on a portion of the second semiconductor layer located on the first semiconductor layer to form a second opening region spaced apart from the first opening region; S7, depositing a transparent conductive film layer on the back side; S8, performing a third etching on a portion of the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second opening area to form an isolation trench, wherein at least a portion of the isolation trench corresponds to the crystallized area, and the crystallized area, the first doped polysilicon layer, and the transparent conductive film layer form a reverse leakage channel PN junction; S9, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

2. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 1, characterized in that: In S5, the area of the crystallized region corresponding to a single preset reverse leakage channel is controlled to be 0.0015 mm 2 -0.05mm 2 .

3. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 1, characterized in that: In S5 , the crystallization rate of the locally crystallized region of the second semiconductor layer is controlled to be 2%-60%.

4. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to any one of claims 1 to 3, characterized in that: In S5, the crystallization treatment conditions include: controlling the laser pulse energy density to 50-400 mJ / cm 2 , laser pulse width is less than 100ns; And / or, the laser wavelength used in the laser crystallization technology is 248-805 nm.

5. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 4, characterized in that: Laser crystallization technology uses ultraviolet nanosecond laser.

6. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 1, characterized in that: The isolation trench extends to the cross-over portion of the first opening area, and the cross-over portion of the isolation trench located in the first opening area is not provided with a reverse leakage channel, and the reverse leakage channel is provided on the overlapping area; And / or, the reverse leakage channel PN junctions are evenly distributed on the back side.

7. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 1, characterized in that: The thickness of the crystallized region of the second semiconductor layer is smaller than the thickness of the uncrystallized portion of the second semiconductor layer.

8. The method for preparing a combined passivated back contact battery with a precisely set reverse leakage channel according to claim 1, characterized in that: The first semiconductor layers are alternately arranged on the back of the silicon wafer, and a first opening area is formed between two adjacent first semiconductor layers. The silicon wafer in the first opening area is the texturing surface. Then, the second semiconductor layer is deposited on the back. The process adopts the following post-texturing method: S1. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S2, performing a first etching on the back surface obtained in S1 to form a first opening area; S3, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer; S4. Depositing a second semiconductor layer on the back side.

9. A combined passivated back contact battery, characterized in that: The battery is prepared by the method for preparing a combined passivation back contact battery with a precisely set reverse leakage channel as described in any one of claims 1 to 8.

10. A back-contact battery module without bypass diode, characterized in that: It comprises several combined passivated back contact cells as claimed in claim 9, wherein the combined passivated back contact cells are connected in series to form a cell string, and no bypass diode is required at the end of the cell string.

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