Display device and method for manufacturing display device

Abstract

The display device may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including a light emitting area; and a pixel disposed in each of the plurality of pixel regions. The pixel may include: a first electrode; a second electrode surrounding a periphery of the first electrode while being spaced apart from the first electrode; a third electrode surrounding a periphery of the second electrode while being spaced apart from the second electrode; a fourth electrode surrounding a periphery of the third electrode while being spaced apart from the third electrode; a plurality of light emitting elements disposed between the first to fourth electrodes; and first and second conductive lines disposed under the first to fourth electrodes, and an insulating layer interposed between the first and second conductive lines and the first to fourth electrodes. The first conductive line may be electrically connected to the first electrode, and the second conductive line may be electrically connected to the fourth electrode.

Description

[0001] This application is a divisional application of the invention patent application "Display device and method for manufacturing display device" with application date of October 19, 2020 and application number 202080077630.2. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] As interest in information display increases and demand for using portable information media increases, demand and commercialization of display devices are coming into focus. Summary of the Invention

[0004] Technical issues

[0005] An object of the present disclosure is to provide a display device having improved light output efficiency and a method of manufacturing the display device.

[0006] Technical Solution

[0007] According to an embodiment of the present disclosure, a display device may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas each including an emission area; and a pixel provided in each of the plurality of pixel areas.

[0008] In an embodiment of the present disclosure, a pixel may include: a first electrode; a second electrode spaced apart from the first electrode and surrounding the periphery of the first electrode; a third electrode spaced apart from the second electrode and surrounding the periphery of the second electrode; a fourth electrode spaced apart from the third electrode and surrounding the periphery of the third electrode; a plurality of light-emitting elements disposed between the first electrode to the fourth electrode; and a first conductive wire and a second conductive wire disposed below the first electrode to the fourth electrode, with an insulating layer interposed between the first conductive wire and the second conductive wire and the first electrode to the fourth electrode. Here, the first conductive wire may be electrically connected to the first electrode, and the second conductive wire may be electrically connected to the fourth electrode.

[0009] In an embodiment of the present disclosure, each of the second to fourth electrodes may have a ring shape when viewed in a plan view, and the first electrode may have an isolated circular island shape surrounded by the second to fourth electrodes.

[0010] In an embodiment of the present disclosure, the light emitting element may include: a first light emitting element disposed between the first electrode and the second electrode; a second light emitting element disposed between the second electrode and the third electrode; and a third light emitting element disposed between the third electrode and the fourth electrode.

[0011] In an embodiment of the present disclosure, the first light-emitting element can be arranged between the first electrode and the second electrode along a circumferential direction centered on the first electrode, the second light-emitting element can be arranged between the second electrode and the third electrode along a circumferential direction centered on the second electrode, and the third light-emitting element can be arranged between the third electrode and the fourth electrode along a circumferential direction centered on the third electrode.

[0012] In an embodiment of the present disclosure, the first conductive line and the second conductive line may be provided on the same layer.

[0013] In an embodiment of the present disclosure, the first conductive line and the second conductive line may be provided at different layers.

[0014] In an embodiment of the present disclosure, the insulating layer may include a first insulating layer and a second insulating layer sequentially stacked on the substrate.

[0015] In an embodiment of the present disclosure, the first conductive line may be provided on one of the first insulating layer and the second insulating layer, and the second conductive line may be provided on the other of the first insulating layer and the second insulating layer.

[0016] In an embodiment of the present disclosure, the pixel may further include: a third conductive line connected to the second electrode with an insulating layer interposed between the third conductive line and the second electrode; and a fourth conductive line connected to the third electrode with an insulating layer interposed between the fourth conductive line and the third electrode. Here, the third conductive line and the fourth conductive line may be in a floating state.

[0017] In an embodiment of the present disclosure, the third conductive line and the fourth conductive line may be provided on the same layer as the first conductive line and the second conductive line.

[0018] In an embodiment of the present disclosure, the third conductive line and the fourth conductive line may be provided at different layers.

[0019] In an embodiment of the present disclosure, the first light-emitting element may form a first level connected in parallel between the first electrode and the second electrode, the second light-emitting element may form a second level connected in parallel between the second electrode and the third electrode, and the third light-emitting element may form a third level connected in parallel between the third electrode and the fourth electrode.

[0020] In an embodiment of the present disclosure, the pixel may further include: a bank pattern disposed under each of the first to fourth electrodes; and contact electrodes disposed on the first to fourth electrodes, respectively.

[0021] In an embodiment of the present disclosure, the second electrode may include a 2-1 electrode surrounding one area of the first electrode and a 2-2 electrode spaced apart from the 2-1 electrode and surrounding another area of the first electrode. The third electrode may include a 3-1 electrode surrounding one area of the second electrode and a 3-2 electrode spaced apart from the 3-1 electrode and surrounding another area of the second electrode.

[0022] In an embodiment of the present disclosure, the 2-2 electrode and the 3-2 electrode may be in a floating state.

[0023] In an embodiment of the present disclosure, the 2-2nd electrode may be connected to the second conductive line, and the 3-2nd electrode may be connected to the first conductive line.

[0024] In an embodiment of the present disclosure, the first conductive line and the second conductive line may be provided on the same layer.

[0025] In an embodiment of the present disclosure, the pixel may further include a pixel circuit portion including at least one transistor electrically connected to the fourth electrode. Here, the first electrode may be a cathode electrode of the pixel, and the fourth electrode may be an anode electrode of the pixel.

[0026] The display device can be manufactured by arranging pixels including the pixel region. The step of arranging pixels can include forming a pixel circuit portion and forming a display element portion.

[0027] The step of forming the pixel circuit portion includes: forming at least one transistor and first to fourth conductive lines spaced apart from each other on a substrate; and forming a protection layer on the transistor and the first to fourth conductive lines.

[0028] The step of forming a display element portion may include: forming a first electrode connected to a first conductive line, a second electrode spaced apart from the first electrode and connected to a second conductive line, a third electrode spaced apart from the second electrode and connected to a third conductive line, and a fourth electrode spaced apart from the third electrode and connected to a fourth conductive line on a protective layer; aligning a plurality of light-emitting elements between the first electrode to the fourth electrode by forming an electric field between the first electrode and the second electrode, between the second electrode and the third electrode, and between the third electrode and the fourth electrode by applying an alignment signal corresponding to each of the first to fourth conductive lines; and forming a contact electrode on each of the first to fourth electrodes.

[0029] In an embodiment of the present disclosure, the method may further include removing a portion of each of the second conductive line and the third conductive line after forming the contact electrode.

[0030] In an embodiment of the present disclosure, the first electrode may be located at the center of the pixel area, the second electrode may surround the periphery of the first electrode, the third electrode may surround the periphery of the second electrode, and the fourth electrode may surround the periphery of the third electrode.

[0031] Beneficial effects

[0032] According to an embodiment of the present disclosure, a display device and a method for manufacturing the display device can be provided, which are advantageous for achieving high resolution and improving light output efficiency by fully ensuring the alignment area of the light-emitting element by setting a circular electrode at the center of a pixel area in a pixel area where one pixel is provided and setting at least one ring-shaped electrode around the circular electrode.

[0033] The effects according to the embodiments of the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0035] Figure 1b yes Figure 1a A cross-sectional view of a light-emitting element.

[0036] Figure 2a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0037] Figure 2b yes Figure 2a A cross-sectional view of a light-emitting element.

[0038] Figure 3a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0039] Figure 3b yes Figure 3a A cross-sectional view of a light-emitting element.

[0040] Figure 4a is a perspective view schematically showing a light emitting element according to still another embodiment of the present disclosure.

[0041] Figure 4b yes Figure 4a A cross-sectional view of a light-emitting element.

[0042] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, and particularly using Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b Schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0043] Figures 6a to 6e is a diagram showing various embodiments including Figure 5 A circuit diagram showing the electrical connection relationship between components in one pixel is shown in FIG.

[0044] Figures 7a to 7c is a diagram showing another embodiment including Figure 5 A circuit diagram showing the electrical connection relationship of components in one pixel is shown in FIG.

[0045] Figure 8 It is schematically shown Figure 5 A plan view of one of the pixels shown in .

[0046] Figure 9 It is along Figure 8 A cross-sectional view taken along line I-I'.

[0047] Figure 10 It is along Figure 8 A cross-sectional view taken along line II to II'.

[0048] Figure 11 According to another embodiment, Figure 10 The implementation of the first embankment shown in Figure 8 Cross-sectional view corresponding to line II~II'.

[0049] Figure 12 As Figure 10 The implementation of the display element layer shown in Figure 8 Cross-sectional view corresponding to line II~II'.

[0050] Figure 13 It is along Figure 8 A cross-sectional view taken along lines III-III' and IV-IV'.

[0051] Figure 14 According to another embodiment, Figure 9 The implementation of the fourth conductive line shown in Figure 8 A cross-sectional view corresponding to line I to I'.

[0052] Figure 15 According to another embodiment, Figure 13 The implementation of the second conductive line shown in Figure 8Cross-sectional view corresponding to line III-III' and line IV-IV'.

[0053] Figure 16 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and shows a driving current flowing through a pixel as an example. Figure 8 The driving current of the pixel flows.

[0054] Figures 17a to 17f is shown in order to manufacture Figure 8 Schematic plan view of the pixel approach shown in FIG.

[0055] Figures 18a to 18h is shown in order to manufacture Figure 9 A cross-sectional view of the pixel method is shown in FIG.

[0056] Figure 19 is a diagram showing a method according to another embodiment Figure 8 , and is a schematic plan view of a pixel having a partial structure including only a display element portion.

[0057] Figure 20 is a schematic plan view showing a pixel according to still another embodiment.

[0058] Figure 21 It is along Figure 20 A cross-sectional view taken along line V to V'.

[0059] Figure 22 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and for example shows a driving current flowing through a pixel. Figure 20 The driving current of the pixel flows.

[0060] Figure 23 is shown when the light emitting element is Figure 20 1 is a diagram showing the shape of a pixel when aligned, and is a schematic plan view of a pixel having a partial structure including only a display element portion. DETAILED DESCRIPTION

[0061] Since the present disclosure can be modified in various ways and have various forms, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents, and replacements within the technical scope of the present disclosure.

[0062] When describing each of the accompanying drawings, similar reference numerals are used for similar components. In the accompanying drawings, for the clarity of the present disclosure, the size of the structure is enlarged from the actual size. The terms "first", "second", etc. can be used to describe various components, but the components should not be limited by the terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0063] It should be understood that, in this application, the terms "including", "having", etc. are used to specify the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, but do not exclude the possibility of the pre-existence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof. In addition, when a part of a layer, film, region, plate, etc. is referred to as being "on" another part, this includes not only the case where the part is "directly on" the other part, but also the case where there is another part between the part and the other part. In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side or in the downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly "below" the other part, but also the case where there is another part between the part and the other part.

[0064] Hereinafter, preferred embodiments of the present disclosure and other matters required for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings.In the following description, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0065] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure, Figure 1b yes Figure 1a A cross-sectional view of a light-emitting element, Figure 2a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 2b yes Figure 2a A cross-sectional view of a light-emitting element, Figure 3a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 3b yes Figure 3a A cross-sectional view of a light-emitting element, Figure 4a is a perspective view schematically showing a light emitting element according to yet another embodiment of the present disclosure, and Figure 4b yes Figure 4aA cross-sectional view of a light-emitting element.

[0066] For the sake of convenience, the following description shows the light emitting element manufactured by the etching method. Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a and Figure 3b Next, a description is given showing the light emitting element manufactured by the growth method. Figure 4a and Figure 4b In the embodiments of the present disclosure, the type and / or shape of the light emitting element is not limited to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b The embodiment shown in FIG.

[0067] First, refer to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a and Figure 3b The light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as a light emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0068] According to an embodiment of the present disclosure, the light emitting element LD extends in one direction. When the extending direction of the light emitting element LD is referred to as a longitudinal direction, the light emitting element LD may have one side end and another side end along the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be provided at one side end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other side end of the light emitting element LD.

[0069] The light-emitting element LD can be provided in various shapes. For example, the light-emitting element LD can have a rod-like shape or a strip-like shape that is long in the longitudinal direction (i.e., the aspect ratio is greater than 1). In an embodiment of the present disclosure, the length L of the light-emitting element LD in the longitudinal direction can be greater than the diameter D (or the width of the cross section) of the light-emitting element LD. The light-emitting element LD may include, for example, a light-emitting diode that is manufactured to be extremely small so as to have a diameter D and / or length L of approximately micrometer or nanometer order. In an embodiment of the present disclosure, the size of the light-emitting element LD can be changed to meet the required conditions (or design conditions) of the lighting device or the self-luminous display device.

[0070] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may include an n-type semiconductor layer doped with a first conductive dopant (such as Si, Ge, or Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto, and various other materials may constitute the first semiconductor layer 11.

[0071] The active layer 12 can be provided on the first semiconductor layer 11 and can be formed in a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be changed differently depending on the type of the light-emitting element LD. The active layer 12 can emit light with a wavelength of 400nm to 900nm and can have a double heterostructure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed on and / or below the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material such as AlGaN or AlInGaN can be used to form the active layer 12, and various other materials can constitute the active layer 12.

[0072] When an electric field of a predetermined voltage or higher is applied to both ends of the light-emitting element LD, the light-emitting element LD emits light while electron-hole pairs are recombined in the active layer 12. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices including pixels of a display device.

[0073] The second semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor layer of a different type from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various other materials may constitute the second semiconductor layer 13.

[0074] In the embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) from each other in the length L direction of the light emitting element LD. For example, along the length L direction of the light emitting element LD, the first semiconductor layer 11 may have a relatively wider width (or thicker thickness) than the width (or thickness) of the second semiconductor layer 13. Figures 1a to 3b As shown in , the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11 .

[0075] According to an embodiment of the present disclosure, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. Figure 3a and Figure 3b As shown in , the light emitting element LD may further include another additional electrode 16 provided at one end of the first semiconductor layer 11 .

[0076] The additional electrodes 15 and 16 may be ohmic contact electrodes, but are not limited thereto, and may be Schottky contact electrodes according to embodiments. The additional electrodes 15 and 16 may include a metal or a metal oxide, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, ITO, etc., may be used alone or in combination, but the present disclosure is not limited thereto.

[0077] The materials included in each of the additional electrodes 15 and 16 may be the same as or different from each other. The additional electrodes 15 and 16 may be substantially transparent or translucent. Therefore, light generated by the light emitting element LD can pass through the additional electrodes 15 and 16 and be emitted to the outside of the light emitting element LD. According to an embodiment, when the light generated by the light emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light emitting element LD through an area other than both ends of the light emitting element LD, the additional electrodes 15 and 16 may include an opaque metal.

[0078] In the embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, according to the embodiment, the insulating film 14 may be omitted and may be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0079] The insulating film 14 can prevent electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, the formation of the insulating film 14 can improve the lifespan and efficiency of the light-emitting element LD by minimizing surface defects in the light-emitting element LD. Furthermore, when multiple light-emitting elements LD are closely arranged, the insulating film 14 can prevent unwanted short circuits between the light-emitting elements LD. As long as the active layer 12 can prevent short circuits with external conductive materials, the presence or absence of the insulating film 14 is not limited.

[0080] like Figure 1a and Figure 1b As shown in FIG, the insulating film 14 may be provided in a form that completely surrounds the outer circumferential surface of the light emitting stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15. Figure 1a A portion of the insulating film 14 is removed, and the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 included in the actual light emitting element LD may be surrounded by the insulating film 14 .

[0081] In the above-described embodiment, the insulating film 14 completely surrounds the outer circumferential surface of each of the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 , but the present disclosure is not limited thereto.

[0082] According to the embodiment, Figure 2a and Figure 2b As shown in , the insulating film 14 may surround the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not completely surround the outer circumferential surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a portion of the outer circumferential surface of the additional electrode 15 and may not surround the remaining portion of the outer circumferential surface of the additional electrode 15. However, the insulating film 14 may expose at least both ends of the light emitting element LD, for example, the insulating film 14 may expose one end of the first semiconductor layer 11 together with the additional electrode 15 provided at one end side of the second semiconductor layer 13. In addition, according to the embodiment, as Figure 3a and Figure 3b As shown in , when the additional electrodes 15 and 16 are provided at both ends of the light emitting element LD, the insulating film 14 may expose at least one region of each of the additional electrodes 15 and 16. Alternatively, in another embodiment, the insulating film 14 may not be provided.

[0083] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include one or more insulating materials selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto and various materials having insulating properties may be used.

[0084] When the insulating film 14 is provided to the light-emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode (not shown) can be prevented. Furthermore, by forming the insulating film 14, the lifespan and efficiency of the light-emitting element LD can be improved by minimizing surface defects in the light-emitting element LD. Furthermore, when multiple light-emitting elements LD are closely arranged, the insulating film 14 can prevent undesirable short circuits that may occur between the light-emitting elements LD.

[0085] The above-mentioned light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each emission area (for example, the emission area of each pixel or the emission area of each sub-pixel), each of the light-emitting elements LD can be subjected to surface treatment so that the light-emitting elements LD can be uniformly sprayed rather than unevenly aggregated in the solution.

[0086] The light-emitting device including the above-mentioned light-emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, when multiple light-emitting elements LD are arranged in the emission area of each pixel of a display panel, the light-emitting element LD can be used as a light source for each pixel. However, the application areas of the light-emitting element LD are not limited to the above examples. For example, the light-emitting element LD can be used in other types of devices (such as lighting devices) that require a light source.

[0087] Next, refer to Figure 4a and Figure 4b The light-emitting element LD manufactured by the growth method is described.

[0088] When describing the light-emitting element LD manufactured by the growth method, the present disclosure is described based on the points different from the above-mentioned embodiments, and the parts not specifically described in the light-emitting element LD manufactured by the growth method follow the above-mentioned embodiments, and the same figure marks are given to components similar to and / or identical to those of the above-mentioned embodiments.

[0089] Reference Figure 4a and Figure 4b The light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the light emitting element LD may include a light emitting pattern 10 having a core-shell structure including the first semiconductor layer 11 located at the center, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0090] The light emitting element LD can be arranged in a polygonal horn shape extending in one direction. For example, the light emitting element LD can be arranged in a hexagonal horn shape. When the extension direction of the light emitting element LD is referred to as the length L direction, the light emitting element LD can have one end (or lower end) and the other end (or upper end) along the length L direction. A portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 can be exposed at one end (or lower end) of the light emitting element LD, and a portion of the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be exposed at the other end (upper end) of the light emitting element LD. For example, a portion of the first semiconductor layer 11 can be exposed at one end (or lower end) of the light emitting element LD, and a portion of the second semiconductor layer 13 can be exposed at the other end (or upper end) of the light emitting element LD. In this case, when the light emitting element LD is applied as a light source of a display device, the exposed portion of the first semiconductor layer 11 can be in contact with one of the drive electrodes that drive the light emitting element LD, and the exposed portion of the second semiconductor layer 13 can be in contact with the other drive electrode.

[0091] According to an embodiment, when the light emitting element LD includes the additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In this case, when the light emitting element LD is applied as a light source of a display device, the exposed portion of the additional electrode 15 may be in contact with another driving electrode and may be electrically connected to the other driving electrode.

[0092] In an embodiment of the present disclosure, the first semiconductor layer 11 may be located at the core (i.e., the center of the light emitting element LD). The light emitting element LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal trumpet shape, the light emitting element LD and the light emitting pattern 10 may also have a hexagonal trumpet shape.

[0093] The active layer 12 may be provided and / or formed in a shape surrounding the outer circumferential surface of the first semiconductor layer 11 in the length L direction of the light emitting element LD. Specifically, the active layer 12 may be provided and / or formed in a shape surrounding the remaining area except for the other end of the light emitting element LD located at the lower side of both ends of the first semiconductor layer 11 in the length L direction.

[0094] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the length L direction of the light emitting element LD, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0095] In an embodiment of the present disclosure, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0096] As described above, the light emitting element LD may be configured in a hexagonal trumpet shape having both ends protruding, and may be implemented as a core-shell structured light emitting pattern 10 including a first semiconductor layer 11 provided at the center thereof, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be provided at one end (or lower end) of the light emitting element LD having the hexagonal trumpet shape, and the additional electrode 15 may be provided at the other end (or upper end) of the light emitting element LD.

[0097] In addition, according to the embodiment, the light emitting element LD may further include an insulating film 14 provided on the outer circumferential surface of the core-shell structured light emitting pattern 10. The insulating film 14 may include a transparent insulating material.

[0098] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, and particularly using Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b Schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0099] exist Figure 5 , for convenience, the structure of the display device is briefly shown based on the display area where the image is displayed. However, according to embodiments, at least one driving circuit unit (e.g., a scan driver, a data driver, etc.) and / or a plurality of signal lines not shown may also be provided in the display device.

[0100] Reference Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a 、 Figure 4b and Figure 5The display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL provided on the substrate SUB and including at least one light emitting element LD, a driver (not shown) provided on the substrate SUB and driving the pixels PXL, and a line unit (not shown) connecting the pixels PXL and the driver to each other.

[0101] Display devices can be classified into passive matrix display devices and active matrix display devices according to the method of driving the light emitting element LD. For example, when the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light emitting element LD, a switching transistor that transmits a data signal to the driving transistor, and the like.

[0102] Recently, active matrix display devices that select and light up each pixel PXL in terms of resolution, contrast, and operating speed have become mainstream, but the present disclosure is not limited to this, and a passive matrix display device in which lighting is performed for each pixel PXL group may also use components for driving the light-emitting element LD (e.g., a first electrode and a second electrode, etc.).

[0103] The substrate SUB may include a display area DA and a non-display area NDA.

[0104] According to an embodiment, the display area DA may be provided in the center area of the display device, and the non-display area NDA may be provided in the edge area of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0105] The display area DA may be an area where pixels PXL displaying an image are disposed, and the non-display area NDA may be an area where a driver for driving the pixels PXL and a portion of a line unit connecting the pixels PXL and the driver are disposed.

[0106] The display area DA can have various shapes. For example, the display area DA can be configured as a polygon with a closed shape formed by straight lines. In addition, the display area DA can be configured as a circular shape and / or an elliptical shape with curved lines. In addition, the display area DA can be configured as various shapes (such as a semicircle, a semiellipse, etc.) with straight and curved lines.

[0107] The non-display area NDA may be provided at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround a periphery (or edge) of the display area DA.

[0108] The substrate SUB may include a transparent insulating material and may transmit light.

[0109] The substrate SUB may be a rigid substrate. For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0110] In addition, the substrate SUB may be a flexible substrate. Here, the flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0111] However, the material constituting the substrate SUB may be variously changed and may include fiber reinforced plastic (FRP) or the like.

[0112] One area on the substrate SUB may be set as a display area DA for disposing the pixels PXL, and the remaining area on the substrate SUB may be provided as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which each pixel PXL is disposed, and a non-display area NDA disposed around the display area DA.

[0113] Each of the pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in the display area DA in a stripe or pentile array structure, but the present disclosure is not limited thereto.

[0114] Each pixel PXL may include at least one light-emitting element LD driven by corresponding scan signals and data signals. The light-emitting element LD may have a size as small as micrometers or nanometers and may be connected in parallel with adjacent light-emitting elements, but the present disclosure is not limited thereto. The light-emitting element LD may constitute the light source of each pixel PXL.

[0115] Each of the pixels PXL may include at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figures 1a to 4b At least one ultra-small light emitting element LD of a small size of about nanometer to micrometer order is shown in each of the embodiments. However, the type of light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0116] In an embodiment of the present disclosure, the color, type, number, etc. of the pixels PXL are not particularly limited, and for example, the color of light emitted from each pixel PXL may be variously changed.

[0117] The driver may provide a predetermined signal and a predetermined power supply to each pixel PXL through the line unit, thereby controlling the driving of the pixel PXL. Figure 5 In the figure, line units are omitted for ease of description.

[0118] The driver may include a scan driver that provides scan signals to the pixels PXL via scan lines, an emission driver that provides emission control signals to the pixels PXL via emission control lines, a data driver that provides data signals to the pixels PXL via data lines, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0119] Figures 6a to 6e is a diagram showing various embodiments Figure 5 1 is a circuit diagram showing the electrical connection relationship between components included in one pixel shown in FIG.

[0120] For example, Figures 6a to 6e The electrical connection relationship between components included in the pixel PXL applicable to the active type display device according to various embodiments is shown. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure can be applied are not limited thereto.

[0121] exist Figures 6a to 6e In, not only Figure 5 The components in each of the pixels shown in FIG and the area where the components are provided are referred to as a pixel PXL. According to an embodiment, Figures 6a to 6e Each pixel PXL shown in FIG. 1 may be included in Figure 5 The pixel PXL may have substantially the same or similar structure as any one of the pixels PXL in the display device of FIG.

[0122] Reference Figures 1a to 4b 、 Figure 5 as well as Figures 6a to 6e A pixel PXL (hereinafter referred to as a “pixel”) may include a light emitting unit EMU that generates light of brightness corresponding to a data signal. In addition, the pixel PXL may further optionally include a pixel circuit 144 for driving the light emitting unit EMU.

[0123] According to an embodiment, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a first driving power source VDD is applied and a second power line PL2 to which a second driving power source VSS is applied. For example, the light emitting unit EMU may include a first electrode EL1 (or "first alignment electrode") connected to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0124] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the light-emitting unit EMU may include a first end connected to a first driving power source VDD via a first electrode EL1 and a second end connected to a second driving power source VSS via a second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. In this case, during the light-emitting period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light-emitting element LD or higher.

[0125] As described above, the corresponding light emitting elements LD connected in parallel in the same direction (e.g., forward direction) between the first electrode EL1 and the second electrode EL2 supplied with voltages of different potentials can constitute corresponding effective light sources. Such effective light sources can be aggregated into the light emitting unit EMU forming the pixel PXL.

[0126] The light-emitting elements LD of the light-emitting units EMU can emit light having a brightness corresponding to the drive current supplied by the corresponding pixel circuit 144. For example, the pixel circuit 144 can supply a drive current corresponding to the grayscale value of the corresponding frame data to the light-emitting units EMU during each frame period. The drive current supplied to the light-emitting units EMU can be split and flow to the light-emitting elements LD connected in the same direction. Therefore, each of the light-emitting elements LD can emit light having a brightness corresponding to the current flowing through the light-emitting element LD, and the light-emitting units EMU can emit light with a brightness corresponding to the drive current.

[0127] at the same time, Figures 6a to 6eAn embodiment is shown in which the light emitting element LD is connected in the same direction between the first driving power source VDD and the second driving power source VSS, but the present disclosure is not limited thereto. According to an embodiment, in addition to the light emitting element LD constituting each effective light source, the light emitting unit EMU may further include at least one ineffective light source. For example, at least one reverse light emitting element LDr may also be connected between the first electrode EL1 and the second electrode EL2 of the light emitting unit EMU, as shown in FIG. Figure 6d and Figure 6e As shown in . The reverse light-emitting element LDr can be connected in parallel between the first electrode EL1 and the second electrode EL2 together with the light-emitting element LD constituting the effective light source, and can be connected between the first electrode EL1 and the second electrode EL2 in the opposite direction to the light-emitting element LD. Even if a predetermined driving voltage (for example, a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains in an inactive state, and thus substantially no current flows through the reverse light-emitting element LDr.

[0128] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is arranged in the i-th (i is a positive integer)-th row and the j-th (j is a positive integer)-th column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to an embodiment, the pixel circuit 144 may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst, as shown in FIG. Figure 6a and Figure 6b However, the structure of the pixel circuit 144 is not limited to Figure 6a and Figure 6b The embodiment shown in .

[0129] First, refer to Figure 6a , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0130] A first terminal of the second transistor T2 (switching transistor) can be connected to the data line Dj, and a second terminal can be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 can be different terminals. For example, when the first terminal is a source electrode, the second terminal can be a drain electrode. In addition, the gate electrode of the second transistor T2 can be connected to the scan line Si.

[0131] When a scan signal of a voltage (e.g., a low voltage) that can turn on the second transistor T2 is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1 to each other. At this time, the data signal of the corresponding frame is supplied to the data line Dj, and thus the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0132] A first terminal of the first transistor T1 (driving transistor) may be connected to a first driving power source VDD, and a second terminal may be electrically connected to a first electrode EL1 of each of the light-emitting elements LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 controls the amount of driving current supplied to the light-emitting element LD in response to a voltage at the first node N1.

[0133] One electrode of the storage capacitor Cst may be connected to the first driving power source VDD, and the other electrode may be connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until a data signal of the next frame is supplied.

[0134] Figure 6a and Figure 6b Each of them shows a pixel circuit 144, which includes a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light emitting element LD.

[0135] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be variously modified and implemented. For example, the pixel circuit 144 may further include other circuit elements, such as at least one transistor element (such as a transistor element for compensating for the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light emitting time of the light emitting element LD) or a boosting capacitor for boosting the voltage of the first node N1.

[0136] In addition, Figure 6a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0137] Next, refer to Figures 1a to 4b 、 Figure 5 and Figure 6bAccording to an embodiment of the present disclosure, the first transistor T1 and the second transistor T2 may be implemented as N-type transistors. In addition to the changes in the connection positions of some components due to the change in transistor type, Figure 6b The configuration or operation of the pixel circuit 144 shown in FIG. Figure 6a The configuration or operation of the pixel circuit 144 is the same. Therefore, a description thereof will be briefly provided.

[0138] In the embodiments of the present disclosure, Figure 6b The pixel circuit 144 shown in FIG may include a first transistor T1 and a second transistor T2 formed of N-type transistors and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are formed of N-type transistors, the light emitting unit EMU may be connected between the first driving power supply VDD and the pixel circuit 144 to charge the storage capacitor Cst of the voltage corresponding to the data signal supplied to the first node N1. However, the present disclosure is not limited thereto. According to embodiments, Figure 6b The light emitting unit EMU shown in FIG can be connected between the pixel circuit 144 and the second driving power supply VSS. In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 6a and Figure 6b For example, the pixel circuit 144 may be as shown in FIG. Figure 6c and Figure 6d The embodiment shown in FIG.

[0139] like Figure 6c and Figure 6d As shown in , the pixel circuit 144 can be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is arranged in the i-th row and j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0140] In addition, according to embodiments, the pixel circuit 144 may also be connected to at least one other scan line. For example, the pixel PXL arranged in the i-th row of the display area DA may also be connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In addition, according to embodiments, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 may also be connected to a third power supply. For example, the pixel circuit 144 may also be connected to an initialization power supply Vint.

[0141] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0142] One electrode (e.g., source electrode) of the first transistor T1 (driving transistor) may be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode (e.g., drain electrode) may be connected to one side of the light-emitting element LD via the sixth transistor T6. Furthermore, the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls a driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1.

[0143] The second transistor T2 (switching transistor) can be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to the pixel PXL. When a scan signal with a gate-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0144] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. Furthermore, a gate electrode of the third transistor T3 may be connected to the i-th scan line Si. When a scan signal of a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0145] The fourth transistor T4 may be connected between the first node N1 and an initialization power supply line to which the initialization power supply Vint is applied. Furthermore, the gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on to transmit the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0146] The fifth transistor T5 may be connected between the first driving power source VDD and the first transistor T1. Furthermore, the gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on otherwise.

[0147] The sixth transistor T6 may be connected between the first transistor T1 and a second node N2 electrically connected to one end of the light emitting element LD. Furthermore, a gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on otherwise.

[0148] The seventh transistor T7 can be connected between one end of the light-emitting element LD and the initialization power supply line. In addition, the gate electrode of the seventh transistor T7 can be connected to any one of the next scan lines, for example, the (i+1)th scan line Si+1. When a scan signal with a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on to supply the voltage of the initialization power supply Vint to one end of the light-emitting element LD.

[0149] The storage capacitor Cst may be connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0150] exist Figure 6c and Figure 6d , the transistors included in the pixel circuit 144 (eg, the first to seventh transistors T1 to T7) are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0151] In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figures 6a to 6d For example, the pixel circuit 144 may be as shown in FIG. Figure 6e The embodiment shown in FIG.

[0152] like Figure 6e As shown in FIG, the pixel circuit 144 can also be connected to the control line CLi and the sensing line SENj. For example, the pixel circuit 144 of the pixel PXL arranged in the i-th row and j-th column of the display area DA can be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. Figure 6a and Figure 6b In addition to the first transistor T1 and the second transistor T2 shown in FIG, the pixel circuit 144 may further include a third transistor T3 and a storage capacitor C OLED , storage capacitor C OLED The first electrode EL1 and the second electrode EL2 are connected to the light emitting unit EMU.

[0153] The third transistor T3 is connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 may be connected to one terminal (e.g., the source electrode) of the first transistor T1 connected to the first electrode EL1, and the other electrode of the third transistor T3 may be connected to the sensing line SENj. Meanwhile, when the sensing line SENj is omitted, the other electrode of the third transistor T3 may be connected to the data line Dj.

[0154] According to an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLi. Meanwhile, when the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 may be turned on by a control signal of a gate-on voltage (e.g., a high level) supplied to the control line CLi during a predetermined sensing period to electrically connect the sensing line SENj and the first transistor T1 to each other.

[0155] According to an embodiment, the sensing period may be a period for extracting characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA. During the above-mentioned sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage that can turn on the first transistor T1 to the first node N1 through the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. In addition, the first transistor T1 may be connected to the sensing line SENj by supplying a control signal of a gate-on voltage to the third transistor T3 to turn on the third transistor T3. Therefore, characteristic information of each pixel PXL, including the threshold voltage of the first transistor T1, etc., may be extracted through the sensing line SENj. The extracted characteristic information may be used to convert image data, thereby compensating for characteristic deviations between the pixels PXL. The capacitor C OLED It may be provided between the first electrode EL1 and the second electrode EL2.

[0156] at the same time, Figure 6e An embodiment is disclosed in which all of the first to third transistors T1 to T3 are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to third transistors T1 to T3 may be changed to a P-type transistor. In addition, Figure 6e An embodiment is disclosed in which the light emitting unit EMU is connected between the pixel circuit 144 and the second driving power source VSS, but the light emitting unit EMU may also be connected between the first driving power source VDD and the pixel circuit 144 .

[0157] in addition, Figures 6a to 6eAn embodiment in which all the light emitting elements LD of each light emitting unit EMU are connected in parallel is shown, but the present disclosure is not limited thereto. According to an embodiment, the light emitting unit EMU may be configured to include at least one series stage including a plurality of light emitting elements LD connected in parallel to each other. That is, the light emitting unit EMU may be configured in a series / parallel hybrid structure. This will be referred to later. Figures 7a to 7c Provide a description.

[0158] The structure of the pixel PXL applicable to the present disclosure is not limited to Figures 6a to 6e , and the corresponding pixels may have various structures. In addition, in another embodiment of the present disclosure, each pixel PXL may be constructed inside a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and each of the two ends of the light-emitting element LD included in the light-emitting unit EMU may be directly connected to each of the scan lines Si-1, Si, Si+1, the data line Dj, the first power line PL1 to which the first drive power VDD is applied, the second power line PL2 to which the second drive power VSS is applied, a predetermined control line, and the like.

[0159] Figures 7a to 7c is a diagram showing another embodiment including Figure 5 The circuit diagram of the electrical connection relationship of the components in one pixel is shown in FIG. Figures 7a to 7c In the description, the light emitting unit EMU of each pixel PXL may be constructed to include a plurality of series stages connected in series. Figures 7a to 7c In order to avoid repeated description, the following descriptions will be omitted. Figures 6a to 6e A detailed description of the configuration of the embodiments (e.g., pixel circuit 144) is similar or identical to that of the embodiments.

[0160] First, refer to Figure 7a The light-emitting unit EMU may include a plurality of light-emitting elements connected in series. For example, the light-emitting unit EMU may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4 connected in series in the forward direction between a first driving power source VDD and a second driving power source VSS to form an effective light source. In the following embodiments, at least one random light-emitting element among the first light-emitting element LD1 to the fourth light-emitting element LD4 or a combination of the first light-emitting element LD1 to the fourth light-emitting element LD4 may be referred to as a light-emitting element LD or a plurality of light-emitting elements LD.

[0161] One end of the first light emitting element LD1 (e.g., the second semiconductor layer) can be connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light emitting element LD1 (e.g., the first semiconductor layer) can be connected to one end of the second light emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series stage and the second series stage.

[0162] The one end (e.g., the second semiconductor layer) of the second light emitting element LD2 can be connected to the first intermediate electrode CTE1, and the other end (e.g., the first semiconductor layer) of the second light emitting element LD2 can be connected to one end (e.g., the second semiconductor layer) of the third light emitting element LD3 through the second intermediate electrode CTE2 connected between the second series stage and the third series stage.

[0163] The one end of the third light emitting element LD3 can be connected to the second intermediate electrode CTE2, and the other end of the third light emitting element LD3 (for example, the first semiconductor layer) can be connected to one end of the fourth light emitting element LD4 (for example, the second semiconductor layer) through the third intermediate electrode CTE3 connected between the third series stage and the fourth series stage.

[0164] The one end of the fourth light emitting element LD4 may be connected to the third intermediate electrode CTE3 , and the other end (eg, the first semiconductor layer) of the fourth light emitting element LD4 may be connected to the second driving power source VSS through the second electrode EL2 .

[0165] As described above, the first to fourth light emitting elements LD1 to LD4 may be connected in series between the first and second electrodes EL1 and EL2 of the light emitting unit EMU of the pixel PXL.

[0166] In the case of a light-emitting unit EMU having a structure in which the light-emitting elements LD are connected in series, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the magnitude of the driving current flowing through the light-emitting unit EMU can be reduced, compared to a light-emitting unit EMU having a structure in which the light-emitting elements LD are connected in parallel. Therefore, when the light-emitting unit EMU of each pixel PXL is configured in a series structure, the power consumption of the display device can be reduced.

[0167] According to an embodiment, at least one series stage may be provided in the form of a plurality of light emitting elements LD connected in parallel with each other. In this case, the light emitting unit EMU of each pixel PXL may be constructed in a series / parallel hybrid structure. For example, the light emitting unit EMU may be constructed as follows Figure 7b and Figure 7c As shown in .

[0168] Next, refer to Figure 7b and Figure 7c , the light-emitting unit EMU of the pixel PXL may include a plurality of series stages sequentially connected between a first driving power source VDD and a second driving power source VSS. In addition, each series stage may include one or more light-emitting elements LD connected in a forward direction between two electrodes of an electrode pair constituting the corresponding series stage. For example, the light-emitting unit EMU may include a first series stage SET1 to a third series stage SET3 sequentially connected between the first driving power source VDD and the second driving power source VSS. Each of the first series stage SET1 to the third series stage SET3 may include two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 constituting an electrode pair of the corresponding series stage, and a plurality of light-emitting elements LD connected in parallel in a forward direction (e.g., in the same direction) between each pair of two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4.

[0169] The first tandem stage SET1 may include a first electrode EL1 and a 2a-electrode EL2a, of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming an electrode pair included in the light emitting unit EMU, and may include at least one first light emitting element LD1 connected between the first electrode EL1 and the 2a-electrode EL2a. For example, the first tandem stage SET1 may include a first electrode EL1 connected to a first driving power source VDD via the pixel circuit 144, a 2a-electrode EL2a connected to a second driving power source VSS, and a plurality of first light emitting elements LD1 connected between the first electrode EL1 and the 2a-electrode EL2a. Each first light emitting element LD1 has one end (e.g., the second semiconductor layer) electrically connected to the first electrode EL1 of the first tandem stage SET1, and the other end (e.g., the first semiconductor layer) electrically connected to the 2a-electrode EL2a of the first tandem stage SET1. The first light emitting elements LD1 may be connected in parallel between the first electrode EL1 and the 2a-electrode EL2a of the first tandem stage SET1 and may be connected in the same direction (e.g., the forward direction) between the first electrode EL1 and the 2a-electrode EL2a. According to the embodiment, Figure 7cAs shown in FIG, at least one reverse light-emitting element LDr may also be connected to the first series stage SET1. The reverse light-emitting element LDr may be connected in parallel with the first light-emitting element LD1 constituting the effective light source between the first electrode EL1 and the 2a-electrode EL2a, and may be connected between the first electrode EL1 and the 2a-electrode EL2a in a direction opposite to that of the first light-emitting element LD1. For example, the first semiconductor layer of the reverse light-emitting element LDr may be connected to the first electrode EL1, and the second semiconductor layer thereof may be connected to the 2a-electrode EL2a. Even when a predetermined drive voltage (e.g., a forward drive voltage) is applied between the first electrode EL1 and the 2a-electrode EL2a, the reverse light-emitting element LDr remains in an inactive state, and thus substantially no current flows through the reverse light-emitting element LDr.

[0170] The second tandem stage SET2 may include a 2b-electrode EL2b and a 3a-electrode EL3a, of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 that form an electrode pair included in the light emitting unit EMU, and may include at least one second light emitting element LD2 connected between the 2b-electrode EL2b and the 3a-electrode EL3a. For example, the second tandem stage SET2 may include a 2b-electrode EL2b connected to a first driving power supply VDD via the first tandem stage SET1, a 3a-electrode EL3a connected to a second driving power supply VSS, and a plurality of second light emitting elements LD2 connected between the 2b-electrode EL2b and the 3a-electrode EL3a. Each second light emitting element LD2 has one end (e.g., the second semiconductor layer) electrically connected to the 2b-electrode EL2b of the second tandem stage SET2, and the other end (e.g., the first semiconductor layer) electrically connected to the 3a-electrode EL3a of the second tandem stage SET2. The second light emitting element LD2 may be connected in parallel between the 2b electrode EL2b and the 3a electrode EL3a of the second series stage SET2, and may be connected between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., forward direction) through the 2b electrode EL2b and the 3a electrode EL3a. Figure 7c As shown in FIG, at least one reverse light-emitting element LDr may also be connected between the 2b-electrode EL2b and the 3a-electrode EL3a. The reverse light-emitting element LDr may be connected in parallel between the 2b-electrode EL2b and the 3a-electrode EL3a, along with the second light-emitting element LD2 constituting the effective light source. Furthermore, the reverse light-emitting element LDr may be connected between the 2b-electrode EL2b and the 3a-electrode EL3a in a direction opposite to that of the second light-emitting element LD2. For example, the first semiconductor layer of the reverse light-emitting element LDr may be connected to the 2b-electrode EL2b, and the second semiconductor layer thereof may be connected to the 3a-electrode EL3a.

[0171] In the disclosed embodiment, the 2a-electrode EL2a of the first tandem stage SET1 and the 2b-electrode EL2b of the second tandem stage SET2 can be integrally provided and connected to each other. That is, the 2a-electrode EL2a of the first tandem stage SET1 and the 2b-electrode EL2b of the second tandem stage SET2 can constitute the second electrode EL2 that electrically connects the first tandem stage SET1 and the second tandem stage SET2. As described above, when the 2a-electrode EL2a of the first tandem stage SET1 and the 2b-electrode EL2b of the second tandem stage SET2 are integrally provided, the 2a-electrode EL2a and the 2b-electrode EL2b can be different regions of the second electrode EL2.

[0172] The third series stage SET3 may include a 3b-electrode EL3b and a fourth electrode EL4, of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming an electrode pair included in the light emitting unit EMU, and may include at least one third light emitting element LD3 connected between the 3b-electrode EL3b and the fourth electrode EL4. For example, the third series stage SET3 may include a 3b-electrode EL3b connected to the first driving power supply VDD via the pixel circuit 144 and the previous series stages (e.g., the first series stage SET1 and the second series stage SET2), a fourth electrode EL4 connected to the second driving power supply VSS, and a plurality of third light emitting elements LD3 connected between the 3b-electrode EL3b and the fourth electrode EL4. Each third light emitting element LD3 has one end (e.g., the second semiconductor layer) electrically connected to the 3b-electrode EL3b of the third series stage SET3, and the other end (e.g., the first semiconductor layer) electrically connected to the fourth electrode EL4 of the third series stage SET3. The third light emitting element LD3 may be connected in parallel between the 3b electrode EL3b and the fourth electrode EL4 of the third series stage SET3, and may be connected between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., forward direction) through the 3b electrode EL3b and the fourth electrode EL4. Figure 7c As shown in FIG, at least one reverse light-emitting element LDr may also be connected between the 3b-electrode EL3b and the fourth electrode EL4. The reverse light-emitting element LDr may be connected in parallel between the 3b-electrode EL3b and the fourth electrode EL4, along with the third light-emitting element LD3 constituting the effective light source. Furthermore, the reverse light-emitting element LDr may be connected between the 3b-electrode EL3b and the fourth electrode EL4 in a direction opposite to that of the third light-emitting element LD3. For example, the first semiconductor layer of the reverse light-emitting element LDr may be connected to the 3b-electrode EL3b, and the second semiconductor layer thereof may be connected to the fourth electrode EL4.

[0173] In the disclosed embodiment, the 3a-electrode EL3a of the second series stage SET2 and the 3b-electrode EL3b of the third series stage SET3 may be integrally provided and connected to each other. That is, the 3a-electrode EL3a of the second series stage SET2 and the 3b-electrode EL3b of the third series stage SET3 may constitute the third electrode EL3 that electrically connects the second series stage SET2 and the third series stage SET3. As described above, when the 3a-electrode EL3a of the second series stage SET2 and the 3b-electrode EL3b of the third series stage SET3 are integrally provided, the 3a-electrode EL3a and the 3b-electrode EL3b may be different regions of the third electrode EL3.

[0174] In the above embodiment, the first electrode EL1 of the first series stage SET1 may be the anode electrode of the light emitting unit EMU of each pixel PXL, and the fourth electrode EL4 of the third series stage SET3 may be the cathode electrode of the light emitting unit EMU.

[0175] As described above, the light emitting unit EMU of the pixel PXL including the light emitting elements LD connected in a series / parallel hybrid structure can easily adjust the driving current / voltage conditions according to the applied product specifications.

[0176] In particular, compared to a light-emitting unit EMU in which the light-emitting elements LD are connected in parallel, a light-emitting unit EMU in a pixel PXL including light-emitting elements LD connected in a series / parallel hybrid structure can reduce the driving current. In addition, compared to a light-emitting unit EMU in which all the light-emitting elements LD are connected in series, a light-emitting unit EMU in a pixel PXL including light-emitting elements LD connected in a series / parallel hybrid structure can reduce the driving voltage applied to both ends of the light-emitting unit EMU. In addition, in the case where all the light-emitting elements LD are connected in series, when at least one of the series-connected light-emitting elements LD is not fully connected in the forward direction (or includes a reverse light-emitting element LDr), the path through which the driving current can flow in the pixel PXL is blocked, thereby causing a dark spot defect. On the other hand, in the case where the light-emitting elements LD are connected in a series / parallel hybrid structure, even if some light-emitting elements LD are not connected in the forward direction (or include a reverse light-emitting element LDr) or defects occur in some light-emitting elements LD in each series stage, the driving current can flow through the other light-emitting elements LD in the corresponding series stage. Therefore, defects in the pixel PXL can be prevented or reduced.

[0177] Figure 8 It is schematically shown Figure 5 A plan view of one of the pixels shown in , Figure 9 It is along Figure 8 A cross-sectional view taken along line I to I', Figure 10 It is along Figure 8 A cross-sectional view taken along line II to II', Figure 11 According to another embodiment, Figure 10 The implementation of the first embankment shown in Figure 8 The cross-sectional view corresponding to line II to II', Figure 12 As Figure 10 The implementation of the display element layer shown in Figure 8 The cross-sectional view corresponding to line II to II', Figure 13 It is along Figure 8 The cross-sectional view taken along line III to III' and line IV to IV' is shown in FIG. Figure 14 According to another embodiment, Figure 9 The implementation of the fourth conductive line shown in Figure 8 The cross-sectional view corresponding to the line I to I', and Figure 15 According to another embodiment, Figure 13 The implementation of the second conductive line shown in Figure 8 Cross-sectional view corresponding to line III-III' and line IV-IV'.

[0178] Figure 8 The pixels shown in can be Figures 6a to 6e as well as Figures 7a to 7c Any one of the pixels shown in each of . For example, Figure 8 The pixels shown in can be Figure 7a and / or Figure 7c The pixels shown in .

[0179] exist Figure 8 In the figure, for convenience, the transistor connected to the light emitting element and the signal line connected to the transistor are omitted.

[0180] Figures 8 to 15 The structure of one pixel PXL is simplified and illustrated, such as illustrating each electrode as a single electrode layer and illustrating each insulating layer as a single insulating layer, but the disclosure is not limited thereto.

[0181] In addition, in the disclosed embodiments, “formed and / or disposed on the same layer” may mean formed in the same process, and “formed and / or disposed on different layers” may mean formed in different processes.

[0182] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 8 to 15 , the display device according to the embodiment may include a substrate SUB, a line unit, and a plurality of pixels PXL.

[0183] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate. During the manufacturing process of the display device, the material applied to the substrate SUB may preferably have tolerance (or heat resistance) to high process temperatures. The substrate SUB may include a display area DA including at least one pixel area PXA in which pixels PXL are disposed, and a non-display area NDA disposed around the display area DA.

[0184] The pixels PXL may be arranged in a matrix and / or stripe form on the substrate SUB in the display area DA along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 intersecting the first direction DR1, but the disclosure is not limited thereto. According to embodiments, the pixels PXL may be provided in the display area DA on the substrate SUB in various arrangements.

[0185] The pixel area PXA in which each pixel PXL is provided (or arranged) may include an emission area EMA in which light is emitted and a peripheral area surrounding the periphery of the emission area EMA. In the disclosed embodiment, the peripheral area may include a non-emission area in which light is not emitted.

[0186] Each pixel PXL may include a pixel circuit section PCL including a pixel circuit 144 and a display element section DPL including a plurality of light emitting elements LD. The light emitting elements LD may be located in an emission area EMA of a pixel region PXA of each pixel PXL.

[0187] The pixel circuit portion PCL may include a buffer layer BFL, a pixel circuit 144 including at least one transistor T, and a protective layer PSV. The display element portion DPL may include first and second bank patterns BNK1 and BNK2, first to fourth electrodes EL1 to EL4, a light emitting element LD, and a contact electrode CNE.

[0188] For convenience, the pixel circuit portion PCL is described first, and then the display element portion DPL is described.

[0189] The buffer layer BFL can prevent impurities from diffusing into the transistor T. The buffer layer BFL can be provided as a single layer, but can also be provided as a multilayer of at least two layers. When the buffer layer BFL is provided as a multilayer, each layer can be formed of the same material or different materials. The buffer layer BFL can be omitted depending on the material of the substrate SUB, process conditions, etc.

[0190] The transistor T may include a first transistor T1 as a driving transistor for controlling the amount of driving current supplied to the light emitting element LD and a second transistor T2 as a switching transistor. In an embodiment of the present disclosure, the first transistor T1 may be a reference transistor. Figure 6a 、 Figure 7b and Figure 7c The first transistor T1 and the second transistor T2 of the pixel circuit 144 described above may be referenced Figure 6a 、 Figure 7b and Figure 7c The second transistor T2 of the pixel circuit 144 is described. In the following embodiments, any one of the first transistor T1 and the second transistor T2 or a combination of the first transistor T1 and the second transistor T2 is referred to as a transistor T or a plurality of transistors T.

[0191] Each of the first transistor T1 and the second transistor T2 may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be either a source electrode or a drain electrode, and the second terminal DE may be another electrode. For example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0192] The transistor semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor panel formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region is a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

[0193] The gate electrode GE may be disposed and / or formed on the transistor semiconductor pattern SCL with the gate insulating layer GI interposed therebetween.

[0194] The respective first and second terminals SE and DE may make contact with the first and second contact regions of the transistor semiconductor pattern SCL through contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0195] In the above embodiment, the first terminal SE and the second terminal DE of each of the first transistor T1 and the second transistor T2 are described as being electrically connected to separate electrodes of the transistor semiconductor pattern SCL, but the present disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the first transistor T1 and the second transistor T2 may be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the first transistor T1 and the second transistor T2 may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the first transistor T1 and the second transistor T2 may be electrically connected to the light-emitting element LD of the corresponding pixel PXL via a separate connection method, such as a bridge electrode or a contact electrode.

[0196] In the embodiment of the present disclosure, the transistor T included in the pixel circuit 144 may be composed of an LTPS thin film transistor, but the present disclosure is not limited thereto. The transistor T included in the pixel circuit 144 may be composed of an oxide semiconductor thin film transistor according to the embodiment. In addition, as an example, the case where the transistor T is a thin film transistor with a top gate structure is described, but the present disclosure is not limited thereto. According to the embodiment, the transistor T may be a thin film transistor with a bottom gate structure.

[0197] The second interlayer insulating layer ILD2 may be disposed on the transistor T. The second interlayer insulating layer ILD2 may cover the transistor T. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0198] The protective layer PSV may be provided on the second interlayer insulating layer ILD2. The protective layer PSV may be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer. Here, the inorganic insulating layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ). The organic insulating layer may include an organic insulating material capable of transmitting light. The organic insulating layer may include at least one of acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0199] Meanwhile, the pixel circuit part PCL may include first to fourth conductive lines CL1 to CL4 .

[0200] The first and fourth conductive lines CL1 to CL4 among the first to fourth conductive lines CL1 to CL4 may have a strip shape extending in a second direction DR2 (e.g., a vertical direction) on the substrate SUB, and the second and third conductive lines CL2 to CL3 may have a strip shape extending in a first direction DR1 (e.g., a horizontal direction) that intersects the second direction DR2 on the substrate SUB. The extending direction and shape of each of the first to fourth conductive lines CL1 to CL4 are not limited to the above-described embodiment. According to an embodiment, the first and fourth conductive lines CL1 to CL4 may extend in the first direction DR1 or in a direction oblique to the first direction DR1 on the substrate SUB, and the second and third conductive lines CL2 to CL3 may extend in the second direction DR2 or in a direction oblique to the second direction DR2 on the substrate SUB. In addition, according to an embodiment, the first to fourth conductive lines CL1 to CL4 may extend in the same direction (e.g., in the first direction DR1 and / or the second direction DR2).

[0201] The first to fourth conductive lines CL1 to CL4 may be disposed at the same layer as the first terminal SE and the second terminal DE of each of the first and second transistors T1 and T2 and may include the same material. For example, the first to fourth conductive lines CL1 to CL4 may be disposed and / or formed on the first interlayer insulating layer ILD1.

[0202] A first conductive line CL1 may be disposed and / or formed on the first interlayer insulating layer ILD1. The first conductive line CL1 may be integrally disposed with the second terminal DE of the first transistor T1 to be connected to the second terminal DE of the first transistor T1. When the first conductive line CL1 and the second terminal DE of the first transistor T1 are integrally disposed, the first conductive line CL1 may be considered as a region of the second terminal DE of the first transistor T1, or the second terminal DE of the first transistor T1 may be considered as a region of the first conductive line CL1. Depending on the embodiment, the first conductive line CL1 may be non-integrally disposed with the second terminal DE of the first transistor T1 and may be electrically connected to the second terminal DE of the first transistor T1 via a separate connection method, such as a contact hole and a bridge electrode.

[0203] The first conductive line CL1 can be electrically connected to a portion of the display element portion DPL (e.g., the first electrode) by sequentially passing through the first contact hole CH1 of the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can transmit a predetermined alignment signal (or alignment voltage) to the first electrode EL1 to allow the first electrode EL1 to function as a first alignment electrode (or first alignment line). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can be electrically connected to the first transistor T1 to allow the first electrode EL1 to function as a driving electrode for the light-emitting element LD.

[0204] The second conductive line CL2 can be arranged and / or formed on the first interlayer insulating layer ILD1, and can be spaced apart from the first conductive line CL1 to be electrically and / or physically separated from the first conductive line CL1. The second conductive line CL2 can be electrically connected to a partial structure of the display element portion DPL (for example, the second electrode EL2) by sequentially passing through the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can transmit a predetermined alignment signal (or alignment voltage) to the second electrode EL2 to allow the second electrode EL2 to serve as a second alignment electrode (or second alignment line). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, a portion of the second conductive line CL2 can be removed or disconnected, and the second conductive line CL2 can be in a floating state. A detailed description related thereto will be provided later.

[0205] The third conductive line CL3 can be arranged and / or formed on the first interlayer insulating layer ILD1, and can be spaced apart from the first conductive line CL1 and the second conductive line CL2 to be electrically and / or physically separated from the first conductive line CL1 and the second conductive line CL2. The third conductive line CL3 can be electrically connected to a portion of the display element portion DPL (e.g., the third electrode EL3) by sequentially passing through the third contact hole CH3 of the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the third conductive line CL3 can transmit a predetermined alignment signal (or alignment voltage) to the third electrode EL3 to allow the third electrode EL3 to serve as a third alignment electrode (or third alignment line). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, a portion of the third conductive line CL3 can be removed or disconnected, and the third conductive line CL3 can be in a floating state. A detailed description related thereto will be provided later.

[0206] The fourth conductive line CL4 may be disposed and / or formed on the first interlayer insulating layer ILD1 and may be spaced apart from the first conductive line CL1, the second conductive line CL2, and the third conductive line CL3 to be electrically and / or physically separated from the first conductive line CL1, the second conductive line CL2, and the third conductive line CL3. The fourth conductive line CL4 may be electrically connected to a portion of the display element portion DPL (e.g., the fourth electrode EL4) through a fourth contact hole CH4 sequentially passing through the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, the fourth conductive line CL4 may be Figure 7b and Figure 7c , the second power line PL2 in the pixel PXL shown in FIG4 is applied with the second driving power VSS. When the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the fourth conductive line CL4 (PL2) can transmit a predetermined alignment signal (or alignment voltage) to the fourth electrode EL4 to allow the fourth electrode EL4 to function as a fourth alignment electrode (or fourth alignment line). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the fourth conductive line CL4 (PL2) can transmit the second driving power VSS to the fourth electrode EL4 to allow the fourth electrode EL4 to function as a driving electrode for the light-emitting element LD.

[0207] In the above embodiment, the first to fourth conductive lines CL1 to CL4 are disposed and / or formed on the first interlayer insulating layer ILD1, and thus the first to fourth conductive lines CL1 to CL4 are disposed on the same layer, but the present disclosure is not limited thereto. According to embodiments, the first to fourth conductive lines CL1 to CL4 may be disposed on different layers. For example, Figure 14 and Figure 15 As shown in FIG, the first conductive line CL1 and the third conductive line CL3 may be disposed and / or formed on the first interlayer insulating layer ILD1, and the second conductive line CL2 and the fourth conductive line CL4 may be disposed and / or formed on the second interlayer insulating layer ILD2. Alternatively, in the opposite case, the second conductive line CL2 and the fourth conductive line CL4 may be disposed and / or formed on the first interlayer insulating layer ILD1, and the first conductive line CL1 and the third conductive line CL3 may be disposed and / or formed on the second interlayer insulating layer ILD2. The position of each of the first to fourth conductive lines CL1 to CL4 is not limited to the above-described embodiment. When the second conductive line CL2 and the fourth conductive line CL4 are disposed and / or formed on the second interlayer insulating layer ILD2, the second conductive line CL2 may be electrically connected to the second electrode EL2 via a second contact hole CH2 passing through the protective layer PSV, and the fourth conductive line CL4 may be electrically connected to the fourth electrode EL4 via a fourth contact hole CH4 passing through the protective layer PSV.

[0208] Next, the display element portion DPL is described.

[0209] The first bank pattern BNK1 may be a support member or an insulating pattern that supports each of the first to fourth electrodes EL1 to EL4 to change a surface profile of each of the first to fourth electrodes EL1 to EL4 so that light emitted from the light emitting element LD travels further in an image display direction of the display device.

[0210] The first bank pattern BNK1 may be disposed and / or formed between the protection layer PSV and the first to fourth electrodes EL1 to EL4 in the emission area EMA of each pixel PXL. For example, the first bank pattern BNK1 may be disposed and / or formed between the protection layer PSV and the first electrode EL1, between the protection layer PSV and the second electrode EL2, between the protection layer PSV and the third electrode EL3, and between the protection layer PSV and the fourth electrode EL4.

[0211] The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. According to embodiments, the first bank pattern BNK1 may include a single organic insulating layer and / or a single inorganic insulating layer, but the present disclosure is not limited thereto. According to embodiments, the first bank pattern BNK1 may be provided in a multilayer form in which at least one organic insulating layer and at least one inorganic insulating layer are stacked.

[0212] The first bank pattern BNK1 may have a cross-section in a trapezoidal shape that narrows from one surface of the protective layer PSV toward the upper portion, but the present disclosure is not limited thereto. Figure 11 As shown in FIG, the first bank pattern BNK1 may include a curved surface having a cross-section having a semi-elliptical shape, a semi-circular shape, or the like, in which the width narrows from one surface of the protective layer PSV toward the upper portion. When viewed in cross-section, the shape of the first bank pattern BNK1 is not limited to the above-described embodiment and may be varied within a range capable of improving the efficiency of light emitted from each of the light-emitting elements LD. Adjacent first bank patterns BNK1 may be arranged on the same plane on the protective layer PSV and may have the same height (or thickness).

[0213] The second bank pattern BNK2 may surround at least one side of the peripheral area of each pixel PXL. The second bank pattern BNK2 is a structure that defines (or partitions) the emission area EMA between each pixel PXL and each of its adjacent pixels PXL and may be, for example, a pixel-defining layer. The second bank pattern BNK2 may be constructed to include at least one light-blocking material and / or reflective material to prevent light leakage defects in which light (or rays) leak between each pixel PXL and its adjacent pixels PXL. Depending on the embodiment, a layer of reflective material may be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL. The second bank pattern BNK2 may be formed and / or disposed on a layer different from the first bank pattern BNK1, but the present disclosure is not limited thereto. Depending on the embodiment, the second bank pattern BNK2 may be formed and / or disposed on the same layer as the first bank pattern BNK1. In embodiments of the present disclosure, the second bank pattern BNK2 may be formed on a layer different from the first bank pattern BNK1 and may be located on the first insulating layer INS1.

[0214] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 included in each pixel PXL may be spaced apart from each other. The second electrode EL2 and the third electrode EL3 may be disposed between the first electrode EL1 and the fourth electrode EL4. For example, the second electrode EL2 may be disposed between the first electrode EL1 and the third electrode EL3, and the third electrode EL3 may be disposed between the second electrode EL2 and the fourth electrode EL4. When viewed in a plan view, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be spaced apart from each other.

[0215] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may be spaced apart from each other by a predetermined distance, the second electrode EL2 and the third electrode EL3 may be spaced apart from each other by a predetermined distance, and the third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other by a predetermined distance. In the emission area EMA of each pixel PXL, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be the same. Therefore, the light-emitting element LD can be more uniformly aligned in the emission area EMA of each pixel PXL. However, the present disclosure is not limited to this, and according to embodiments, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be different from each other.

[0216] Each of the first to fourth electrodes EL1 to EL4 may be disposed and / or formed on the first bank pattern BNK1 to have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, each of the first to fourth electrodes EL1 to EL4 may include a protruding portion corresponding to the first bank pattern BNK1 and a flat portion corresponding to the protective layer PSV. Each of the first to fourth electrodes EL1 to EL4 may be formed of a material having a constant reflectivity to allow light emitted from each of the light-emitting elements LD to travel in the image display direction of the display device.

[0217] Each of the first to fourth electrodes EL1 to EL4 may be formed of a conductive material having a constant reflectivity. The conductive material may include an opaque metal that facilitates reflecting light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal may include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof. Depending on the embodiment, each of the first to fourth electrodes EL1 to EL4 may include a transparent conductive material. The transparent conductive material may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), or conductive polymers such as PEDOT. When each of the first to fourth electrodes EL1 to EL4 includes a transparent conductive material, it may also include a separate conductive layer formed of an opaque metal that reflects light emitted from the light-emitting element LD in the image display direction of the display device. However, the material of each of the first to fourth electrodes EL1 to EL4 is not limited to the above materials.

[0218] In addition, each of the first electrode EL1 to the fourth electrode EL4 can be provided and / or formed as a single layer, but the disclosure is not limited thereto. According to an embodiment, each of the first electrode EL1 to the fourth electrode EL4 can be provided and / or formed as a multilayer in which at least two materials of metal, alloy, conductive oxide and conductive polymer are stacked. Each of the first electrode EL1 to the fourth electrode EL4 can be formed as a multilayer of at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to both ends of each of the light-emitting elements LD. For example, each of the first electrode EL1 to the fourth electrode EL4 can be formed by a multilayer in which ITO / Ag / ITO are sequentially stacked.

[0219] As described above, since each of the first to fourth electrodes EL1 to EL4 has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed thereunder, light emitted from each of the light-emitting elements LD can be reflected by each of the first to fourth electrodes EL1 to EL4 to further travel in the image display direction of the display device. Consequently, the efficiency of light emitted from each of the light-emitting elements LD can be further improved.

[0220] The first bank pattern BNK1 and each of the first to fourth electrodes EL1 to EL4 may function as a reflective member for improving the light efficiency of the display device by guiding light emitted from the light-emitting element LD in a desired direction. In other words, the first bank pattern BNK1 and each of the first to fourth electrodes EL1 to EL4 may function as a reflective member for guiding light emitted from the light-emitting element LD in an image display direction of the display device, thereby improving the light output efficiency of the light-emitting element LD.

[0221] In an embodiment of the present disclosure, the fourth electrode EL4 among the first to fourth electrodes EL1 to EL4 may be located at the center (e.g., core) of the emission area EMA of each pixel PXL and may have a circular shape, but the present disclosure is not limited thereto. According to an embodiment, the fourth electrode EL4 may have an elliptical shape, a circular ring shape, or the like including a curve having a predetermined curvature. In addition, according to an embodiment, the fourth electrode EL4 may have a polygonal shape such as a quadrilateral shape, a triangular shape, or an octagonal shape. The fourth electrode EL4 may be electrically connected to the fourth conductive line CL4 (PL2) of the pixel circuit portion PCL through a fourth contact hole CH4.

[0222] The third electrode EL3 may have a shape that surrounds the periphery of the fourth electrode EL4 along the circumference of the fourth electrode EL4. For example, the third electrode EL3 may have a ring shape (or a closed loop shape) that surrounds at least one side of the fourth electrode EL4. The third electrode EL3 may have a circular ring shape, but the present disclosure is not limited to this. Depending on the embodiment, the third electrode EL3 is not limited to a circular ring shape and may have a polygonal ring shape (including a quadrilateral rectangular ring shape and an octagonal octagonal ring shape, etc.) that forms a closed circuit. In the above embodiment, the third electrode EL3 has a shape that completely surrounds the periphery of the fourth electrode EL4, but the present disclosure is not limited to this. Depending on the embodiment, the third electrode EL3 may have a shape that surrounds only the remaining area of the fourth electrode EL4 except for at least one area, for example, it may have a "C" shape in which any portion is open and does not form a perfect circle. The fourth electrode EL4 may be arranged as an isolated circular island surrounded by the third electrode EL3, but the present disclosure is not limited to this. The third electrode EL3 and the fourth electrode EL4 may be arranged on the corresponding first bank pattern BNK1, spaced apart from each other by a predetermined distance.

[0223] The second electrode EL2 may have a shape that surrounds the periphery of the third electrode EL3 along the circumference of the third electrode EL3. For example, the second electrode EL2 may have a ring shape (or a closed loop shape) that surrounds at least one side of the third electrode EL3. The second electrode EL2 may have a circular ring shape, but the present disclosure is not limited to this. Depending on the embodiment, the second electrode EL2 is not limited to a circular ring shape and may have a polygonal ring shape such as a quadrilateral or octagonal shape that forms a closed circuit. In the above embodiment, the second electrode EL2 has a shape that completely surrounds the periphery of the third electrode EL3, but the present disclosure is not limited to this. Depending on the embodiment, the second electrode EL2 may have a shape that surrounds only the remaining area of the third electrode EL3 except for at least one area, for example, it may have a "C" shape in which any portion is open and does not form a perfect circle. The third electrode EL3 may be arranged in an isolated ring shape surrounded by the second electrode EL2, but the present disclosure is not limited to this. The second electrode EL2 and the third electrode EL3 may be arranged on the corresponding first bank pattern BNK1, spaced apart by a predetermined distance.

[0224] The first electrode EL1 may have a shape that surrounds the periphery of the second electrode EL2 along the circumference of the second electrode EL2. For example, the first electrode EL1 may have a ring shape (or a closed loop shape) that surrounds at least one side of the second electrode EL2. The first electrode EL1 may have a closed loop shape that surrounds the second electrode EL2 and includes an inner surface formed by a curve having a predetermined curvature and an outer surface formed by straight lines, but the present disclosure is not limited to this. Depending on the embodiment, the first electrode EL1 may have a circular ring shape in which both the inner and outer surfaces are formed by curves, or may have a polygonal ring shape such as a quadrilateral or octagonal shape that forms a closed circuit. In the above embodiment, the first electrode EL1 has a shape that completely surrounds the periphery of the second electrode EL2, but the present disclosure is not limited to this. Depending on the embodiment, the first electrode EL1 may have a shape that surrounds only the remaining area of the second electrode EL2 except for at least one area, for example, it may have a "C" shape in which any portion is open and does not form a perfect circle. The second electrode EL2 may be provided as an isolated ring shape surrounded by the first electrode EL1, but the present disclosure is not limited to this. The first and second electrodes EL1 and EL2 may be disposed on the corresponding first bank pattern BNK1 to be spaced apart from each other by a predetermined distance.

[0225] As described above, when the fourth electrode EL4 is located at the center of the emission area EMA of each pixel PXL, the third electrode EL3 surrounds the periphery of the fourth electrode EL4, the second electrode EL2 surrounds the periphery of the third electrode EL3, and the first electrode EL1 surrounds the periphery of the second electrode EL2, the first electrode EL1 to the fourth electrode EL4 can form a concentric circle structure.

[0226] In the emission area EMA of each pixel PXL, a plurality of light-emitting elements LD may be aligned and / or disposed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. In the emission area EMA, the first to fourth electrodes EL1 to EL4 and the light-emitting elements LD may constitute a light-emitting unit EMU of each pixel PXL. The first electrode EL1 may be an anode electrode of the light-emitting unit EMU of each pixel PXL, and the fourth electrode EL4 may be a cathode electrode of the light-emitting unit EMU of each pixel PXL.

[0227] In an embodiment of the present disclosure, the first electrode EL1 can be electrically connected to the pixel circuit portion PCL through the first contact hole CH1. For example, the first electrode EL1 can be electrically connected to the first conductive line CL1 and the first transistor T1 of the pixel circuit portion PCL through the first contact hole CH1. Therefore, a signal (or voltage) applied to the first transistor T1 can be transmitted to the first electrode EL1.

[0228] The second electrode EL2 can be connected to the pixel circuit portion PCL through the second contact hole CH2. For example, the second electrode EL2 can be electrically connected to the second conductive line CL2 of the pixel circuit portion PCL through the second contact hole CH2. In the embodiment of the present disclosure, since the second conductive line CL2 is in a floating state after alignment of the light-emitting element LD, any signal (or voltage) from the second conductive line CL2 may not be applied to the second electrode EL2.

[0229] The third electrode EL3 can be connected to the pixel circuit unit PCL through the third contact hole CH3. For example, the third electrode EL3 can be electrically connected to the third conductive line CL3 of the pixel circuit unit PCL through the third contact hole CH3. In an embodiment of the present disclosure, since the third conductive line CL3 is in a floating state after alignment of the light-emitting element LD, any signal (or voltage) from the third conductive line CL3 may not be applied to the third electrode EL3.

[0230] The fourth electrode EL4 can be electrically connected to the pixel circuit portion PCL through the fourth contact hole CH4. For example, the fourth electrode EL4 can be electrically connected to the fourth conductive line CL4 (PL2) through the fourth contact hole CH4. Therefore, the second driving power VSS applied to the fourth conductive line CL4 (PL2) can be transmitted to the fourth electrode EL4.

[0231] In the above-mentioned embodiment, each of the light-emitting elements LD can be an ultra-small light-emitting element using an inorganic crystal structure material, for example, having a size as small as nanometer to micrometer level. For example, each of the light-emitting elements LD can be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method. However, the type, size, shape, etc. of the light-emitting element LD can be changed differently. At least two to dozens of light-emitting elements LD can be aligned and / or arranged in the emission area EMA of each pixel PXL, but the number of light-emitting elements LD is not limited thereto. According to the embodiment, the number of light-emitting elements LD aligned and / or arranged in the emission area EMA of each pixel PXL can be changed differently.

[0232] In the emission area EMA, the light emitting elements LD may be radially aligned and / or arranged relative to the fourth electrode EL4. For example, a portion of the light emitting elements LD may be aligned along the circumferential direction of the fourth electrode EL4 and / or arranged between the fourth electrode EL4 and the third electrode EL3, another portion of the light emitting elements LD may be aligned along the circumferential direction of the third electrode EL3 and / or arranged between the third electrode EL3 and the second electrode EL2, and yet another portion of the light emitting elements LD may be aligned along the circumferential direction of the second electrode EL2 and / or arranged between the second electrode EL2 and the first electrode EL1.

[0233] The light emitting element LD may be provided in a dispersed form in the solution and may be injected into the emission area EMA of the pixel PXL.

[0234] In the disclosed embodiments, the light-emitting element LD can be injected into the emission area EMA of each pixel PXL by an inkjet printing method, a slit coating method, or various other methods. For example, the light-emitting element LD can be mixed with a volatile solvent and supplied to the emission area EMA of each pixel PXL by an inkjet printing method or a slit coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4 located in the emission area EMA of each pixel PXL is applied, an electric field can be formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. Therefore, the light-emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. At this time, due to the shape of the first to fourth electrodes EL1 to EL4, the light-emitting element LD can be aligned and / or arranged in a radial shape (or radially) along the circumferential direction of the fourth electrode EL4 located at the center (or middle) (e.g., the core) of the emission area EMA of each pixel PXL.

[0235] After the light emitting element LD is aligned, the solvent may be evaporated or removed by other methods, so that the light emitting element LD may be finally aligned and / or disposed in the emission area EMA of each pixel PXL.

[0236] The light-emitting element LD may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3. For example, the light-emitting element LD includes a plurality of first light-emitting elements LD1 disposed between the first electrode EL1 and the second electrode EL2, a plurality of second light-emitting elements LD2 disposed between the second electrode EL2 and the third electrode EL3, and a plurality of third light-emitting elements LD3 disposed between the third electrode EL3 and the fourth electrode EL4.

[0237] When the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, each of the first electrode EL1 to the fourth electrode EL4 can receive a predetermined alignment signal (or alignment voltage) from the corresponding conductive line to serve as an alignment electrode (or alignment line) for aligning the light-emitting element LD. For example, the first electrode EL1 can be a first alignment electrode (or first alignment line) that receives a first alignment signal (or first alignment voltage) from the first conductive line CL1, and the second electrode EL2 can be a second alignment electrode (or second alignment line) that receives a second alignment signal (or second alignment voltage) from the second conductive line CL2. In addition, the third electrode EL3 can be a third alignment electrode (or third alignment line) that receives a third alignment signal (or third alignment voltage) from the third conductive line CL3, and the fourth electrode EL4 can be a fourth alignment electrode (or fourth alignment line) that receives a fourth alignment signal (or fourth alignment voltage) from the fourth conductive line CL4. In an embodiment of the present disclosure, the first to fourth alignment signals can have different voltage levels. The first to fourth alignment signals can be signals with a voltage difference and / or phase difference that corresponds to the degree to which the light-emitting element LD can be aligned between the first electrode EL1 to the fourth electrode EL4. At least some of the above-mentioned first to fourth alignment signals may be AC signals, but the present disclosure is not limited thereto.

[0238] When a corresponding alignment signal is applied to each of the first to fourth electrodes EL1 to EL4, an electric field may be formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. The light emitting element LD may be aligned and / or disposed in the emission area EMA of each pixel PXL by the electric field formed between the two adjacent electrodes.

[0239] After the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, a portion of each of the second conductive line CL2 and the third conductive line CL3 can be removed or disconnected, and each of the second conductive line CL2 and the third conductive line CL3 can be in a floating state. For example, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can be in a floating state by removing one side thereof (for example, a portion that is not in contact with the second electrode EL2 or a portion connected to an alignment pad (or "pad") (not shown) to which a second alignment signal (or second alignment voltage) is applied). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the third conductive line CL3 can be in a floating state by removing one side thereof (for example, a portion that is not in contact with the third electrode EL3 or a portion connected to an alignment pad (not shown) to which a third alignment signal (or third alignment voltage) is applied).

[0240] After the light emitting element LD is aligned in the emission area EMA of each pixel PXL, the first to fourth electrodes EL1 to EL4 may serve as driving electrodes for driving the light emitting element LD.

[0241] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the light-emitting element LD supplied to the emission area EMA can be aligned to be relatively deflected by controlling the alignment signal (or alignment voltage) applied to each of the first electrode EL1 to the fourth electrode EL4 or forming a magnetic field.

[0242] Each of the light-emitting elements LD may include a light-emitting element manufactured by an etching method or a light-emitting element of a core-shell structure manufactured by a growth method. When each of the light-emitting elements LD is a light-emitting element manufactured by an etching method, each light-emitting element LD may include a light-emitting stack (or stacking pattern) in which a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15 are sequentially stacked. In addition, when each of the light-emitting elements LD is a light-emitting element of a core-shell structure manufactured by a growth method, each light-emitting element LD may include a light-emitting pattern 10, which includes a first semiconductor layer 11 located at the center (e.g., a core), an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0243] Each of the light-emitting elements LD may include a first end EP1 and a second end EP2, the first end EP1 being electrically connected to one of two electrodes adjacent to each other in the emission area EMA, and the second end EP2 being electrically connected to the remaining electrode of the two adjacent electrodes. In the disclosed embodiment, the first end EP1 of each light-emitting element LD may be a first semiconductor layer 11 including an n-type semiconductor layer, and the second end EP2 may be a second semiconductor layer 13 including a p-type semiconductor layer. That is, in the emission area EMA of the pixel PXL, each light-emitting element LD may be connected between two adjacent electrodes at a predetermined distance in the forward direction. As described above, the light-emitting element LD connected between two adjacent electrodes in the forward direction may constitute the light-emitting unit EMU of each pixel PXL.

[0244] The light-emitting element LD may include a first light-emitting element LD1 aligned and / or arranged between the first electrode EL1 and the second electrode EL2, a second light-emitting element LD2 aligned and / or arranged between the second electrode EL2 and the third electrode EL3, and a third light-emitting element LD3 aligned and / or arranged between the third electrode EL3 and the fourth electrode EL4.

[0245] In an embodiment of the present disclosure, one end EP1 of the two ends EP1 and EP2 of each of the first light-emitting elements LD1 can be electrically connected to the second electrode EL2, and the other end EP2 thereof can be electrically connected to the first electrode EL1. One end EP1 of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 can be electrically connected to the third electrode EL3, and the other end EP2 thereof can be electrically connected to the second electrode EL2. One end EP1 of the two ends EP1 and EP2 of each of the third light-emitting elements LD3 can be electrically connected to the fourth electrode EL4, and the other end EP2 thereof can be electrically connected to the third electrode EL3.

[0246] In the emission area EMA of each pixel PXL, the first electrode EL1 and the second electrode EL2 can form a series stage (hereinafter referred to as the "first series stage") together with the first light-emitting element LD1 connected in parallel between the first electrode EL1 and the second electrode EL2. In the emission area EMA of each pixel PXL, the second electrode EL2 and the third electrode EL3 can form another series stage (hereinafter referred to as the "second series stage") together with the second light-emitting element LD2 connected in parallel between the second electrode EL2 and the third electrode EL3. In the emission area EMA of each pixel PXL, the third electrode EL3 and the fourth electrode EL4 can form another series stage (hereinafter referred to as the "third series stage") together with the third light-emitting element LD3 connected in parallel between the third electrode EL3 and the fourth electrode EL4. In an embodiment of the present disclosure, the first to third series stages can be set in the emission area EMA of each pixel PXL, and the first to third series stages can constitute the light-emitting unit EMU of the corresponding pixel PXL. The first electrode EL1 included in the first series stage of each pixel PXL may be an anode electrode of the light emitting unit EMU of the corresponding pixel PXL, and the fourth electrode EL4 included in the third series stage may be a cathode electrode of the light emitting unit EMU.

[0247] Depending on the embodiment, at least one reverse light-emitting element LDr connected in the reverse direction may be provided between two adjacent electrodes in each series stage, or at least one defective light-emitting element (e.g., an invalid light source (not shown)) not connected to both electrodes may be provided between two adjacent electrodes in each series stage. For example, in the first series stage, at least one reverse light-emitting element LDr aligned and / or arranged in the direction opposite to the first light-emitting element LD1 may be provided between the first electrode EL1 and the second electrode EL2. In the second series stage, at least one reverse light-emitting element LDr aligned and / or arranged in the direction opposite to the second light-emitting element LD2 may be provided between the second electrode EL2 and the third electrode EL3. In the third series stage, at least one reverse light-emitting element LDr aligned and / or arranged in the direction opposite to the third light-emitting element LD3 may be provided between the third electrode EL3 and the fourth electrode EL4.

[0248] The light emitting element LD may be disposed in the emission area EMA of each pixel PXL and / or formed on the first insulating layer INS1 .

[0249] A first insulating layer INS1 may be formed and / or disposed below each of the light-emitting elements LD, each of which is aligned in the emission area EMA of each pixel PXL and / or disposed between two electrodes constituting each series stage. The first insulating layer INS1 may fill the space between each of the light-emitting elements LD and the protective layer PSV to stably support the light-emitting element LD and prevent the light-emitting element LD from being separated from the protective layer PSV.

[0250] In addition, in the emission area EMA of each pixel PXL, the first insulating layer INS1 may expose one region of each of the two electrodes constituting each series stage and may cover the remaining region except the one region. Here, the contact electrode CNE may be provided and / or formed on one region of each of the exposed electrodes, so that each of the electrodes and the contact electrode CNE may be electrically and / or physically connected to each other.

[0251] The first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In the disclosed embodiment, the first insulating layer INS1 may be formed of an inorganic insulating layer that facilitates protecting the light-emitting element LD from the pixel circuit portion PCL of each pixel PXL, but the disclosure is not limited thereto. Depending on the embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that facilitates flattening the support surface of the light-emitting element LD.

[0252] A second insulating layer INS2 may be provided and / or formed on each of the light-emitting elements LD. The second insulating layer INS2 may be provided and / or formed on each of the light-emitting elements LD to cover a portion of the upper surface of each of the light-emitting elements LD and to expose both ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed in an independent pattern in the emission area EMA of each pixel PXL, but the disclosure is not limited thereto.

[0253] The second insulating layer INS2 can be composed of a single layer or multiple layers and can include an inorganic insulating layer containing at least one inorganic material or an organic insulating layer containing at least one organic material. The second insulating layer INS2 can also fix each of the light-emitting elements LD aligned in the emission area EMA of each pixel PXL. In the disclosed embodiment, the second insulating layer INS2 can include an inorganic insulating layer that helps protect the active layer 12 of each light-emitting element LD from external oxygen, moisture, etc. However, the disclosure is not limited to this. The second insulating layer INS2 can also include an organic insulating layer containing an organic material, depending on the design conditions of the display device in which the light-emitting element LD is applied.

[0254] In the disclosed embodiment, after the alignment of the light emitting element LD is completed in the emission area EMA of each pixel PXL, the light emitting element LD can be prevented from being separated from the aligned position by forming a second insulating layer INS2 on the light emitting element LD. Figure 12 As shown in FIG, when a gap (or space) exists between the first insulating layer INS1 and the light-emitting element LD before forming the second insulating layer INS2, the gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light-emitting element LD can be constructed of an organic insulating layer that facilitates filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0255] In the disclosed embodiment, a second insulating layer INS2 may be formed on the light emitting elements LD to prevent the active layer 12 of each of the light emitting elements LD from contacting an external conductive material. The second insulating layer INS2 may cover only a portion of the surface of each of the light emitting elements LD so that both ends EP1 and EP2 of each of the light emitting elements LD are exposed to the outside.

[0256] The contact electrode CNE may be provided on each of the first to fourth electrodes EL1 to EL4. The contact electrode CNE may be a configuration for more stably electrically connecting each of the first to fourth electrodes EL1 to EL4 with the corresponding light emitting element LD.

[0257] The contact electrode CNE can be formed from various transparent conductive materials. For example, the contact electrode CNE can include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and can be substantially transparent or translucent to meet a predetermined light transmittance. However, the material of the contact electrode CNE is not limited to the above embodiment, and depending on the embodiment, the contact electrode CNE can be formed from various opaque conductive materials. In the embodiment of the present disclosure, the contact electrode CNE may include a first contact electrode CNE1 disposed on the first electrode EL1, a second contact electrode CNE2 disposed on the second electrode EL2, a third contact electrode CNE3 disposed on the third electrode EL3, and a fourth contact electrode CNE4 disposed on the fourth electrode EL4.

[0258] The first contact electrode CNE1 can connect the first electrode EL1 to one of the two ends EP1 and EP2 of each first light-emitting element LD1 in the emission area EMA of each pixel PXL. When viewed in plan, the first contact electrode CNE1 can overlap one end of each first light-emitting element LD1 and each of the first electrodes EL1 and can be provided in a circular ring shape. The shape of the first contact electrode CNE1 is not limited to the above embodiment. The first contact electrode CNE1 can be provided in various shapes, including an elliptical ring shape, a polygonal ring shape, and the like, as long as it covers the one end of each first light-emitting element LD1 and the first electrode EL1.

[0259] The second contact electrode CNE2 may connect one side of the second electrode EL2 to the remaining end of each of the two ends EP1 and EP2 of each of the first light-emitting elements LD1 in the emission area EMA of each pixel PXL. Furthermore, the second contact electrode CNE2 may connect the other side of the second electrode EL2 to one of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 in the emission area EMA of each pixel PXL. When viewed in plan, the second contact electrode CNE2 may overlap the remaining end of each of the first light-emitting elements LD1, the one end of each of the second light-emitting elements LD2, and each of the second electrode EL2, and may fully cover the second electrode EL2, the remaining end of each of the first light-emitting elements LD1, and the one end of each of the second light-emitting elements LD2. The second contact electrode CNE2 may be provided in a circular ring shape surrounding the periphery of the third contact electrode CNE3. The shape of the second contact electrode CNE2 is not limited to the above-described embodiment. The second contact electrode CNE2 may be provided in various shapes including an elliptical ring shape, a polygonal ring shape, etc. within a range capable of covering the remaining end of each of the first light emitting elements LD1 , the one end of each of the second light emitting elements LD2 , and the second electrode EL2 .

[0260] The third contact electrode CNE3 may connect one side of the third electrode EL3 to the remaining end of each of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 in the emission area EMA of each pixel PXL. Furthermore, the third contact electrode CNE3 may connect the other side of the third electrode EL3 to one of the two ends EP1 and EP2 of each of the third light-emitting elements LD3 in the emission area EMA of each pixel PXL. When viewed in plan, the third contact electrode CNE3 may overlap the remaining end of each of the second light-emitting elements LD2, the one end of each of the third light-emitting elements LD3, and each of the third electrode EL3, and may fully cover the third electrode EL3, the remaining end of each of the second light-emitting elements LD2, and the one end of each of the third light-emitting elements LD3. The third contact electrode CNE3 may be arranged in a circular ring shape surrounding the periphery of the fourth contact electrode CNE4. The shape of the third contact electrode CNE3 is not limited to the above-described embodiment. The third contact electrode CNE3 may be provided in various shapes including an elliptical ring shape, a polygonal ring shape, etc. within a range capable of covering the third electrode EL3 , the remaining end of each of the second light emitting element LD2 , and the one end of each of the third light emitting element LD3 .

[0261] The fourth contact electrode CNE4 may connect the fourth electrode EL4 to the remaining end of each of the third light-emitting elements LD3 in the emission area EMA of each pixel PXL. When viewed in plan, the fourth contact electrode CNE4 may overlap with each of the remaining ends of the fourth electrode EL4 and the third light-emitting element LD3 and may fully cover the remaining ends of the fourth electrode EL4 and the third light-emitting element LD3. The fourth contact electrode CNE4 may be provided in the shape of an isolated circular island surrounded by the third electrode EL3. The shape of the fourth contact electrode CNE4 is not limited to the above embodiment. The fourth contact electrode CNE4 may be provided in various shapes, including an elliptical shape and a polygonal shape, as long as it can cover the remaining ends of the fourth electrode EL4 and the third light-emitting element LD3.

[0262] As described above, when the first contact electrode CNE1 having a circular shape surrounds the periphery of the second contact electrode CNE2 having a circular shape, the second contact electrode CNE2 having a circular shape surrounds the periphery of the third contact electrode CNE3 having a circular shape, and the third contact electrode CNE3 surrounds the periphery of the fourth contact electrode CNE4 having a circular shape, the first to fourth contact electrodes CNE1 to CNE4 may configure a concentric circle structure in the emission area EMA of each pixel PXL.

[0263] In embodiments of the present disclosure, an encapsulation layer ENC may be provided and / or formed on the first to fourth contact electrodes CNE1 to CNE4. The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure in which at least one inorganic insulating layer or at least one organic insulating layer is alternately stacked. The encapsulation layer ENC may completely cover the display element portion DPL to prevent water or moisture from entering the display element portion DPL including the light-emitting element LD from the outside.

[0264] A capping layer (not shown) may be provided and / or formed in the emission area EMA of each pixel PXL. The capping layer may be provided and / or formed between each of the first to fourth electrodes EL1 to EL4 and the contact electrode CNE formed on each of the first to fourth electrodes EL1 to EL4. For example, the capping layer may be provided and / or formed between the first electrode EL1 and the first contact electrode CNE1, between the second electrode EL2 and the second contact electrode CNE2, between the third electrode EL3 and the third contact electrode CNE3, and between the fourth electrode EL4 and the fourth contact electrode CNE4. The capping layer may prevent damage to each of the first to fourth electrodes EL1 to EL4 due to defects occurring during the manufacturing process of the display device, and may also enhance the adhesion between each of the first to fourth electrodes EL1 to EL4 and the protective layer PSV. The capping layer may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each of the light-emitting elements LD and reflected by each of the first to fourth electrodes EL1 to EL4 in the image display direction of the display device.

[0265] According to the above embodiment, a circular fourth electrode EL4 is disposed at the center (or middle) (e.g., core) of the emission area EMA of each pixel PXL, the third electrode EL3 is disposed around the fourth electrode EL4, the second electrode EL2 is disposed around the third electrode EL3, and the first electrode EL1 is disposed around the second electrode EL2. Furthermore, a predetermined alignment signal is applied to each of the first to fourth electrodes EL1 to EL4 via separate (or corresponding) conductive lines, thereby forming an electric field between two adjacent electrodes among the first to fourth electrodes EL1 to EL4. Due to the electric field formed between the two adjacent electrodes, the light-emitting element LD can be aligned between the first to fourth electrodes EL1 to EL4.

[0266] At this time, the light emitting element LD can be aligned and / or arranged in a radial shape (or radially) relative to the fourth electrode EL4 formed in the shape of a circular island, and the fourth electrode EL4 is located at the center (or middle) (e.g., core) of the emission area EMA of each pixel PXL. Therefore, the light emitting element LD may not be aligned and / or set to be biased in a specific direction in the emission area EMA of each pixel PXL. Therefore, the light emitted from each of the light emitting elements LD may not be concentrated in a specific direction. Therefore, the amount (or intensity) of light emitted from the emission area EMA of each pixel PXL may be similar to or substantially the same as the amount (or intensity) of light emitted from the emission area EMA of the adjacent pixel PXL. Finally, the display device according to an embodiment of the present disclosure may have a uniform light output distribution throughout the entire display area DA in which the image is displayed.

[0267] According to the above embodiment, the first and second electrodes EL1 and EL2, spaced apart from each other, and the first light-emitting element LD1 connected in parallel between the first and second electrodes EL1 and EL2, constitute a first series stage. The second and third electrodes EL2 and EL3, spaced apart from each other, and the second light-emitting element LD2 connected in parallel between the second and third electrodes EL2 and EL3, constitute a second series stage. Furthermore, the third and fourth electrodes EL3 and EL4, spaced apart from each other, and the third light-emitting element LD3 connected in parallel between the third and fourth electrodes EL3 and EL4, constitute a third series stage. The light-emitting elements LD included in each of the two consecutive series stages can share a common electrode for electrical connection. That is, the first light-emitting element LD1 included in the first series stage and the second light-emitting element LD2 included in the second series stage can share the second electrode EL2 for electrical connection. Furthermore, the second light-emitting element LD2 included in the second series stage and the third light-emitting element LD3 included in the third series stage can share the third electrode EL3 for electrical connection. In this way, the light emitting unit EMU of each pixel PXL may be constructed by connecting the light emitting elements LD aligned in the emission area EMA of each pixel PXL in a series / parallel hybrid structure.

[0268] According to the above embodiment, each pixel PXL can be stably driven by configuring the light emitting unit EMU in a series / parallel hybrid structure, so the driving current flowing through the display panel of the display device can be reduced, thereby improving power consumption efficiency.

[0269] According to the above embodiment, the fourth electrode EL4 can be positioned at the center of the emission area EMA of each pixel PXL, the third electrode EL3 can be positioned around the fourth electrode EL4, the second electrode EL2 can be positioned around the third electrode EL3, and the first electrode EL1 can be positioned around the second electrode EL2, so that the first electrode EL1 to the fourth electrode EL4 can have a concentric circular structure. In this case, the alignment and / or integration of the light-emitting element LD positioned in the emission area EMA of each pixel PXL can be improved, thereby further ensuring the alignment area of the light-emitting element LD. Therefore, the display device according to the embodiment of the present disclosure can more easily achieve high resolution.

[0270] Figure 16 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and shows a driving current flowing through a pixel as an example. Figure 8 The driving current of the pixel flows. Figure 16 In, when Figure 8 When the pixel PXL is driven to emit light in response to a data signal of a predetermined grayscale, the flow of a driving current flowing through the pixel PXL is shown by a dotted arrow.

[0271] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 8 to 16 If a driving current flows from the first power line PL1 to the fourth conductive line CL4 (PL2) through the first transistor T1 (e.g., the driving transistor) of the pixel circuit unit PCL included in each pixel PXL, the driving current can flow through the first conductive line CL1 and the first contact hole CH1 to the light-emitting unit EMU of each pixel PXL. For example, the driving current is supplied to the first electrode EL1 through the first conductive line CL1 and the first contact hole CH1, and the driving current flows to the second electrode EL2 via the first light-emitting element LD1. Therefore, the first light-emitting element LD1 disposed between the first and second electrodes EL1 and EL2 can emit light with a brightness corresponding to the current allocated to each of the first light-emitting elements LD1. The driving current flowing through the second electrode EL2 flows to the third electrode EL3 via the second light-emitting element LD2 disposed between the second and third electrodes EL3. Therefore, the second light-emitting element LD2 can emit light with a brightness corresponding to the current allocated to each of the second light-emitting elements LD2. The driving current flowing through the third electrode EL3 flows to the fourth electrode EL4 via the third light-emitting element LD3 disposed between the third and fourth electrodes EL4. Therefore, the third light emitting elements LD3 may emit light having brightness corresponding to the current allocated to each of the third light emitting elements LD3.

[0272] In the above method, the driving current of each pixel PXL can flow while sequentially passing through the first light-emitting element LD1 disposed between the first electrode EL1 and the second electrode EL2, the second light-emitting element LD2 disposed between the second electrode EL2 and the third electrode EL3, and the third light-emitting element LD3 disposed between the third electrode EL3 and the fourth electrode EL4. Therefore, each pixel PXL can emit light having a brightness corresponding to the data signal supplied during each frame period.

[0273] Figures 17a to 17f is shown in order to manufacture Figure 8 A schematic plan view of the pixel method shown in FIG. Figures 18a to 18h is shown in order to manufacture Figure 9 A cross-sectional view of the pixel method is shown in FIG.

[0274] In the following, according to the combination Figures 17a to 17f as well as Figures 18a to 18h The manufacturing method is described sequentially Figure 8 and Figure 9 Pixel according to an embodiment of the present disclosure is shown in FIG.

[0275] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 17a and Figure 18a The pixel circuit portion PCL included in each pixel PXL is formed on the substrate SUB. The pixel area PXA in which the pixel PXL is disposed (or prepared) may include an emission area EMA that emits light and a peripheral area surrounding the periphery of the emission area EMA.

[0276] The pixel circuit portion PCL may include a pixel circuit 144 including at least one transistor T, first to fourth conductive lines CL1 to CL4, and at least one insulating layer. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, first and second interlayer insulating layers ILD1 and ILD2, and a protection layer PSV sequentially formed on a substrate SUB.

[0277] Each of the second interlayer insulating layer ILD2 and the protective layer PSV may include a first contact hole CH1 exposing a portion of the first conductive line CL1 integrally provided with the second terminal DE of the first transistor T1 included in the pixel circuit 144, a second contact hole CH2 exposing a portion of the second conductive line CL2, a third contact hole CH3 exposing a portion of the third conductive line CL3, and a fourth contact hole CH4 exposing a portion of the fourth conductive line CL4.

[0278] Each of the first to fourth conductive lines CL1 to CL4 may be formed on the first interlayer insulating layer ILD1. When viewed in a plan view, each of the first to fourth conductive lines CL1 to CL4 may extend in a direction and may be spaced apart from each other to be electrically and / or physically separated from each other. For example, the first conductive line CL1 and the fourth conductive line CL4 may extend along a second direction DR2 (e.g., a vertical direction), and the second conductive line CL2 and the third conductive line CL3 may extend along a first direction DR1 that intersects (e.g., is orthogonal to) the second direction DR2.

[0279] In an embodiment of the present disclosure, each of the first to fourth conductive lines CL1 to CL4 can be electrically connected to a different alignment pad (not shown) provided in the non-display area NDA of the display device DD. For example, the first conductive line CL1 can be electrically connected to the first alignment pad, the second conductive line CL2 can be electrically connected to the second alignment pad, the third conductive line CL3 can be electrically connected to the third alignment pad, and the fourth conductive line CL4 can be electrically connected to the fourth alignment pad. Different alignment signals (or alignment voltages) can be applied to the corresponding first to fourth alignment pads.

[0280] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Figure 17b 、 Figure 18a and Figure 18b , a first bank pattern BNK1 is formed on the protective layer PSV. On the protective layer PSV, the first bank pattern BNK1 may be spaced apart from adjacent first bank patterns BNK1 by a predetermined distance. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0281] When viewed in a plan view, the first bank pattern BNK1 may be formed in a circular ring shape (or a closed ring shape) and may form a concentric circle structure with adjacent first bank patterns BNK1 in each emission area EMA. The shape of the first bank pattern BNK1 is not limited to the above-described embodiment and may be provided in various shapes within a range capable of further ensuring the amount of light traveling in the image display direction of the display device through the first to fourth electrodes EL1 to EL4.

[0282] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Figure 17c as well as Figures 18a to 18c, first to fourth electrodes EL1 to EL4 including a conductive material (or substance) having high reflectivity are formed on the protection layer PSV including the first bank pattern BNK1.

[0283] Each of the first to fourth electrodes EL1 to EL4 may be formed on the first bank pattern BNK1 .

[0284] The fourth electrode EL4 may be located at the center (or middle) (e.g., core) of the emission area EMA of each pixel PXL, and the fourth electrode EL4 may be formed in an isolated circular island shape. The third electrode EL3 may be formed in a circular ring shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. The second electrode EL2 may be formed in a circular ring shape surrounding the periphery of the third electrode EL3 along the circumferential direction of the third electrode EL3. The first electrode EL1 may be located at the outermost portion of the emission area EMA of each pixel PXL, and the first electrode EL1 may be formed in a polygonal ring shape surrounding the periphery of the second electrode EL2 along the circumferential direction of the second electrode EL2.

[0285] In an embodiment of the present disclosure, the first electrode EL1 can be electrically connected to the first conductive line CL1 through the first contact hole CH1, the second electrode EL2 can be electrically connected to the second conductive line CL2 through the second contact hole CH2, the third electrode EL3 can be electrically connected to the third conductive line CL3 through the third contact hole CH3, and the fourth electrode EL4 can be electrically connected to the fourth conductive line CL4 through the fourth contact hole CH4.

[0286] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 as well as Figures 18a to 18d An insulating material layer INSM is formed on the protective layer PSV including the first to fourth electrodes EL1 to EL4. The insulating material layer INSM may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0287] Subsequently, a second bank pattern BNK2 is formed in the peripheral area of each pixel PXL. At this time, the second bank pattern BNK2 may be formed on the insulating material layer INSM. The second bank pattern BNK2 may be a structure (e.g., a pixel defining layer) that defines (or partitions) the emission area EMA between each pixel PXL and the adjacent pixels PXL.

[0288] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Figure 17d as well as Figures 18a to 18e By applying a corresponding alignment signal (or alignment voltage) to each of the first to fourth electrodes EL1 to EL4 via the first to fourth conductive lines CL1 to CL4, an electric field is formed between the first to fourth electrodes EL1 to EL4. For example, when an AC power source or a DC power source having a predetermined voltage and period is repeatedly applied to each of the first to fourth electrodes EL1 to EL4 several times, an electric field corresponding to the potential difference between two adjacent electrodes among the first to fourth electrodes EL1 to EL4 can be formed.

[0289] In an embodiment of the present disclosure, the first electrode EL1 may receive a first alignment signal from a first alignment pad via a first conductive line CL1, the second electrode EL2 may receive a second alignment signal from a second alignment pad via a second conductive line CL2, the third electrode EL3 may receive a third alignment signal from a third alignment pad via a third conductive line CL3, and the fourth electrode EL4 may receive a fourth alignment signal from a fourth alignment pad via a fourth conductive line CL4. The first to fourth alignment signals may have different voltage levels.

[0290] As described above, in a state in which an electric field is formed between the first electrode EL1 to the fourth electrode EL4, a mixed solution including the light-emitting element LD is injected (or supplied) to the emission area EMA of each pixel PXL using an inkjet printing method or the like. For example, an inkjet nozzle may be provided on the insulating material layer INSM, and a solvent in which a plurality of light-emitting elements LD are mixed may be injected (or supplied) to the emission area EMA of each pixel PXL through the inkjet nozzle. Here, the solvent may be any one or more of acetone, water, ethanol and toluene, but the present disclosure is not limited thereto. For example, the solvent may be in the form of ink or paste. The method of injecting (or supplying) the light-emitting element LD into the emission area EMA of each pixel PXL is not limited to the above-described embodiment, and the method of injecting (or supplying) the light-emitting element LD may be changed differently.

[0291] After the light emitting element LD is injected (or supplied) into the emission area EMA of each pixel PXL, the solvent may be removed.

[0292] When the light-emitting element LD is implanted into the emission area EMA, the electric field formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4 can induce self-alignment of the light-emitting element LD. Therefore, the light-emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. At this time, the light-emitting element LD can be aligned and / or disposed on the insulating material layer INSM between two corresponding adjacent electrodes in the emission area EMA of each pixel PXL. For example, the first light-emitting element LD1 can be aligned on the insulating material layer INSM between the first electrode EL1 and the second electrode EL2, the second light-emitting element LD2 can be aligned on the insulating material layer INSM between the second electrode EL2 and the third electrode EL3, and the third light-emitting element LD3 can be aligned on the insulating material layer INSM between the third electrode EL3 and the fourth electrode EL4.

[0293] According to an embodiment, the light-emitting element LD may include at least one reverse light-emitting element LDr, which is connected in a direction opposite to the forward direction in the emission area EMA of each pixel PXL according to the waveform, intensity, etc. of the alignment signal applied to each of the first electrode EL1 to the fourth electrode EL4.

[0294] As described above, by controlling the direction or intensity of the electric field formed between the first electrode EL1 to the fourth electrode EL4 by adjusting the alignment signal applied in the step of aligning the light-emitting element LD, the proportion of the light-emitting elements (for example, the reverse light-emitting elements LDr) connected to the direction opposite to the light-emitting element LD in the forward direction in the emission area EMA of each pixel PXL can be adjusted, or the light-emitting elements LD in the forward direction can be densely arranged at a specific position.

[0295] In an embodiment of the present disclosure, the light-emitting element LD may be aligned and / or arranged in a radial shape (or radially) relative to the fourth electrode EL4 in the emission area EMA of each pixel PXL. After the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, each of the first to fourth alignment pads may stop supplying the corresponding alignment signal to the corresponding conductive line. According to an embodiment, after the light-emitting element LD is aligned, each of the first to fourth alignment pads may be electrically disconnected from the corresponding conductive line, and thus each of the first to fourth alignment pads may not supply the corresponding alignment signal to the corresponding conductive line.

[0296] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 as well as Figures 18a to 18f After the light emitting element LD is aligned in the emission area EMA of each pixel PXL, a second insulating layer INS2 is formed on each of the light emitting elements LD. The second insulating layer INS2 may cover at least a portion of the upper surface of each of the light emitting elements LD so that both ends EP1 and EP2 except for the active layer 12 of each of the light emitting elements LD are exposed to the outside.

[0297] The insulating material layer INSM may be etched to expose a portion of each of the first to fourth electrodes EL1 to EL4 through a process of forming the second insulating layer INS2 or an etching process performed before and after the process of forming the second insulating layer INS2 , thereby forming the first insulating layer INS1 .

[0298] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Figure 17e as well as Figures 18a to 18g , first to fourth contact electrodes CNE1 to CNE4 are formed on the protection layer PSV including the second insulating layer INS2 .

[0299] A first contact electrode CNE1 may be formed directly on the first electrode EL1 and one of the two ends EP1 and EP2 of each of the first light-emitting elements LD1. A second contact electrode CNE2 may be formed directly on the second electrode EL2, the remaining ends of the two ends EP1 and EP2 of each of the first light-emitting elements LD1, and one of the two ends EP1 and EP2 of each of the second light-emitting elements LD2. A third contact electrode CNE3 may be formed directly on the third electrode EL3, the remaining ends of the two ends EP1 and EP2 of each of the second light-emitting elements LD2, and one of the two ends EP1 and EP2 of each of the third light-emitting elements LD3. A fourth contact electrode CNE4 may be formed directly on the fourth electrode EL4 and the remaining ends EP1 and EP2 of each of the third light-emitting elements LD3.

[0300] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Figure 17f as well as Figures 18a to 18h, a portion of each of the second conductive line CL2 and the third conductive line CL3 is removed to place each of the second conductive line CL2 and the third conductive line CL3 in a floating state. Therefore, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 aligned in the emission area EMA of each pixel PXL can be connected in series, so that a driving current can flow from the first power line PL1 to the fourth conductive line CL4 (PL2) through the first transistor T1 (e.g., a driving transistor) of the pixel circuit 144 included in each pixel PXL.

[0301] When a portion of each of the second and third conductive lines CL2 and CL3 is removed, a portion of the first electrode EL1 between each pixel PXL and its adjacent pixel PXL may be removed. Therefore, each pixel PXL may be driven independently (or separately) from its adjacent pixel PXL.

[0302] Subsequently, an encapsulation layer ENC covering the first to fourth contact electrodes CNE1 to CNE4 is formed. The encapsulation layer ENC may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked.

[0303] Figure 19 is a diagram showing a method according to another embodiment Figure 8 , and is a schematic plan view of a pixel having a partial structure including only a display element portion.

[0304] exist Figure 19 , the structure of the pixel PXL is simplified, such as only illustrating first to fourth conductive lines, first to fourth electrodes, and a plurality of light emitting elements included in the pixel PXL, but the present disclosure is not limited thereto.

[0305] about Figure 19 Pixels, omitting the above Figure 8 The configuration of the embodiments is the same or similar to the detailed description of the configuration.

[0306] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figure 19 The pixel area PXA in which each pixel PXL is disposed may include an emission area EMA that emits light and a peripheral area surrounding the emission area EMA. Each pixel PXL may include first to fourth conductive lines CL1 to CL4, first to fourth electrodes EL1 to EL4, and a plurality of light emitting elements LD.

[0307] The fourth electrode EL4 may be located at the center (or middle) (e.g., core) of the emission area EMA of each pixel PXL and may have a circular island shape. The third electrode EL3 may have a ring shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. In this case, the third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other by a predetermined distance and may be electrically separated from each other. That is, the third electrode EL3 and the fourth electrode EL4 may be insulated from each other. The fourth electrode EL4 may be surrounded by the third electrode EL3 and may be isolated.

[0308] The second electrode EL2 may have a circular ring shape surrounding the periphery of the third electrode EL3 along the circumferential direction of the third electrode EL3. In this case, the second electrode EL2 and the third electrode EL3 may be spaced apart from each other by a predetermined distance and may be electrically isolated from each other. In other words, the second electrode EL2 and the third electrode EL3 may be insulated from each other. The third electrode EL3 may be surrounded by the second electrode EL2 and may be isolated.

[0309] The first electrode EL1 may have a polygonal ring shape surrounding the periphery of the second electrode EL2 along the circumferential direction of the second electrode EL2. Specifically, the first electrode EL1 may have a polygonal shape (e.g., an octagonal shape), in which the inner surface adjacent to the second electrode EL2 has a circular ring shape formed by a curve with a predetermined curvature, and the outer surface located at the outermost portion of the emission area EMA is formed by a straight line. The first electrode EL1 and the second electrode EL2 having the above-mentioned shape may be spaced apart from each other by a predetermined distance and may be electrically separated from each other. That is, the first electrode EL1 and the second electrode EL2 may be insulated from each other. The second electrode EL2 may be surrounded by the first electrode EL1 and may be isolated. In the above embodiment, the first electrode EL1 has a polygonal ring shape, but the present disclosure is not limited thereto. According to an embodiment, the first electrode EL1 may have the same circular ring shape as the second electrode EL2 and the third electrode EL3.

[0310] In the emission area EMA of each pixel PXL, the first electrode EL1 to the fourth electrode EL4 may have a concentric circle structure. The light-emitting element LD may be aligned and / or arranged between the first electrode EL1 to the fourth electrode EL4. The light-emitting element LD may be aligned and / or arranged in a radial shape (or radially) relative to the fourth electrode EL4 in the emission area EMA. Therefore, the light-emitting element LD may not be aligned and / or arranged to be biased in a specific direction in the emission area EMA of each pixel PXL. Therefore, the light emitted from each of the light-emitting elements LD may travel in various directions without being concentrated in a specific direction.

[0311] Figure 20 is a schematic plan view showing a pixel according to still another embodiment, Figure 21 It is along Figure 20 A cross-sectional view taken along line V to V', Figure 22 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and for example shows a driving current flowing through Figure 20 The driving current of the pixel flows, and Figure 23 is shown when the light emitting element is Figure 20 1 is a diagram showing the shape of a pixel when aligned, and is a schematic plan view of a pixel having a partial structure including only a display element portion.

[0312] about Figures 20 to 23 Pixels, mainly describe the differences from the above embodiment to avoid repeated description. Parts not specifically described in this disclosure are based on the above embodiment, and the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0313] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 20 to 23 Each pixel PXL may include a pixel circuit section PCL including a pixel circuit 144 and a display element section DPL including a plurality of light emitting elements LD. The light emitting elements LD may be located in an emission area EMA of a pixel area PXA in which each pixel PXL is provided.

[0314] The pixel circuit portion PCL may include at least one transistor T, first and second conductive lines CL1 and CL2, and at least one insulating layer. The display element portion DPL may include first to fourth electrodes EL1 to EL4, a plurality of light emitting elements LD, first and second bank patterns BNK1 and BNK2, and a contact electrode CNE.

[0315] The first conductive line CL1 and the second conductive line CL2 may have a strip shape extending in a second direction DR2 (e.g., a vertical direction) on the substrate SUB. The first conductive line CL1 and the second conductive line CL2 may be disposed and / or formed on the first interlayer insulating layer ILD1. The first conductive line CL1 may be integrally disposed with the second terminal DE of the driving transistor (e.g., the first transistor T1) included in the pixel circuit portion PCL to be electrically connected to the second terminal DE of the first transistor T1. According to an embodiment, the first conductive line CL1 may be non-integrally disposed with the second terminal DE of the first transistor T1 and may be electrically connected to the second terminal DE of the first transistor T1 through a separate connection method such as a contact hole and a bridge electrode.

[0316] The first conductive line CL1 can be electrically connected to the first electrode EL1 of the display element portion DPL via a first contact hole CH1 that passes through the second interlayer insulating layer ILD2 and the protective layer PSV. Furthermore, the first conductive line CL1 can be electrically connected to a portion of the third electrode EL3 of the display element portion DPL (e.g., the 3-2nd electrode EL3_2) via a third contact hole CH3 that passes through the second interlayer insulating layer ILD2 and the protective layer PSV. Here, the 3-2nd electrode EL3_2 can be in an electrically isolated state, e.g., in a floating state. That is, the first conductive line CL1 can be connected to the 3-2nd electrode EL3_2, which is a floating electrode, via the third contact hole CH3.

[0317] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can allow each of the first electrode EL1 and the third electrode EL3 to serve as a first alignment electrode (or first alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the first electrode EL1 and the third electrode EL3. In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can be electrically connected to the driving transistor (e.g., the first transistor T1) of the pixel circuit unit PCL to allow the first electrode EL1 to serve as a driving electrode for the light-emitting element LD. In addition, after the light-emitting element LD is aligned, by removing a portion of the third electrode EL3, the first conductive line CL1 can be connected to the 3-2 electrode EL3_2 in a floating state.

[0318] The second conductive line CL2 can be electrically connected to the fourth electrode EL4 of the display element portion DPL through the fourth contact hole CH4 passing through the second interlayer insulating layer ILD2 and the protective layer PSV. In addition, the second conductive line CL2 can be electrically connected to a portion of the second electrode EL2 of the display element portion DPL (for example, the 2-2 electrode EL2_2) through the second contact hole CH2 passing through the second interlayer insulating layer ILD2 and the protective layer PSV. Here, the 2-2 electrode EL2_2 can be in an electrically isolated state, for example, in a floating state. That is, the second conductive line CL2 can be connected to the 2-2 electrode EL2_2 as a floating electrode through the second contact hole CH2. The second conductive line CL2 can be in Figure 7b and Figure 7c The second power line PL2 to which the second driving power VSS is applied in the pixel PXL shown in FIG.

[0319] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can transmit a predetermined alignment signal (or alignment voltage) to the second electrode EL2 and the fourth electrode EL4, allowing each of the second electrode EL2 and the fourth electrode EL4 to function as a second alignment electrode (or second alignment line). In addition, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can transmit the second drive power supply VSS to the fourth electrode EL4, allowing the fourth electrode EL4 to function as a drive electrode for the light-emitting element. In addition, after the light-emitting element LD is aligned, by removing a portion of the second electrode EL2, the second conductive line CL2 can be connected to the 2-2 electrode EL2_2 in a floating state.

[0320] In an embodiment of the present disclosure, the fourth electrode EL4 may have a circular shape disposed at the center (or middle) (eg, core) of the emission area EMA of each pixel PXL.

[0321] The third electrode EL3 may be spaced apart from the fourth electrode EL4 and may have a shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. In an embodiment of the present disclosure, the third electrode EL3 may include a 3-1st electrode EL3_1 having at least one open region and a 3-2nd electrode EL3_2 spaced apart from the 3-1st electrode EL3_1. For example, the 3-1st electrode EL3_1 may have a "C" shape.

[0322] Before the light emitting element LD is aligned in the emission area EMA of each pixel PXL, the third electrode EL3 may be provided in an elliptical ring shape surrounding the fourth electrode EL4, as shown in FIG. Figure 23 As shown in . When the light emitting element LD is aligned in the emission area EMA, the third electrode EL3 can serve as a first alignment electrode for aligning the light emitting element by receiving a first alignment signal (or a first alignment voltage) from the first conductive line CL1 together with the first electrode EL1. That is, when the light emitting element LD is aligned in the emission area EMA, the same alignment signal (e.g., the first alignment signal) can be transmitted to the first electrode EL1 and the third electrode EL3 through the first conductive line CL1.

[0323] When alignment of the light-emitting element LD is complete, a portion of the third electrode EL3 can be removed or disconnected. Therefore, after alignment of the light-emitting element LD is complete, the third electrode EL3 can be configured to include a 3-1 electrode EL3_1, at least one region of which is open, and a 3-2 electrode EL3_2, which is spaced apart and electrically isolated from the 3-1 electrode EL3_1. When alignment of the light-emitting element LD is complete, the 3-1 electrode EL3_1 can serve as a connection path for applying a drive current to the light-emitting element LD aligned between the third electrode EL3 and an electrode adjacent to the third electrode EL3, and the 3-2 electrode EL3_2 can be in a floating state. In an embodiment of the present disclosure, the 3-1 electrode EL3_1 can be configured to surround one region of the fourth electrode EL4, and the 3-2 electrode EL3_2 can be configured to surround another region of the fourth electrode EL4. When viewed in plan, the 3-2 electrode EL3_2 can be disposed and / or formed within one of the open regions of the third electrode EL3.

[0324] The second electrode EL2 may be spaced apart from the third electrode EL3 and may have a shape surrounding the periphery of the third electrode EL3. In an embodiment of the present disclosure, the second electrode EL2 may include a 2-1st electrode EL2_1 having at least one open (or open) region and a 2-2nd electrode EL2_2 spaced apart from the 2-1st electrode EL2_1. For example, the 2-1st electrode EL2_1 may have a "C" shape.

[0325] Before the light emitting element LD is aligned in the emission area EMA of each pixel PXL, the second electrode EL2 may have an elliptical ring shape surrounding the third electrode EL3, as shown in FIG. Figure 23 As shown in . When the light emitting element LD is aligned in the emission area EMA, the second electrode EL2 can be used as a second alignment electrode for aligning the light emitting element by receiving a second alignment signal (or a second alignment voltage) from the second conductive line CL2 together with the fourth electrode EL4. That is, when the light emitting element LD is aligned in the emission area EMA, the same alignment signal (e.g., the second alignment signal) can be transmitted to the second electrode EL2 and the fourth electrode EL4 through the second conductive line CL2.

[0326] When alignment of the light-emitting element LD is complete, a portion of the second electrode EL2 can be removed or disconnected. Therefore, after alignment of the light-emitting element LD is complete, the second electrode EL2 can be configured to include a 2-1 electrode EL2_1, at least one region of which is open, and a 2-2 electrode EL2_2, which is spaced apart and electrically isolated from the 2-1 electrode EL2_1. When alignment of the light-emitting element LD is complete, the 2-1 electrode EL2_1 can serve as a connection path for applying a drive current to the light-emitting element LD aligned between the second electrode EL2 and an electrode adjacent to the second electrode EL2, and the 2-2 electrode EL2_2 can be in a floating state. In an embodiment of the present disclosure, the 2-1 electrode EL2_1 can be configured to surround one region of the third electrode EL3, and the 2-2 electrode EL2_2 can be configured to surround another region of the third electrode EL3. When viewed in plan, the 2-2 electrode EL2_2 can be disposed and / or formed within one of the open regions of the second electrode EL2.

[0327] The first electrode EL1 may be spaced apart from the second electrode EL2 and may have a shape surrounding the periphery of the second electrode EL2. For example, the first electrode EL1 may have a diamond ring shape surrounding the periphery of the second electrode EL2.

[0328] The first to fourth electrodes EL1 to EL4 may have a concentric circular structure in the emission area EMA of each pixel PXL. Therefore, the light emitting element LD may be radially aligned with respect to the fourth electrode EL4 located at the core of the emission area EMA.

[0329] The light emitting element LD may include at least one first light emitting element LD1 aligned between the first electrode EL1 and the second electrode EL2, at least one second light emitting element LD2 aligned between the second electrode EL2 and the third electrode EL3, and at least one third light emitting element LD3 aligned between the third electrode EL3 and the fourth electrode EL4.

[0330] In the emission area EMA of each pixel PXL, the first and second electrodes EL1 and EL2 and the first light-emitting element LD1 connected in parallel between the first and second electrodes EL1 and EL2 may constitute a first series connection, the second and third electrodes EL2 and EL3 and the second light-emitting element LD2 connected in parallel between the second and third electrodes EL2 and EL3 may constitute a second series connection, and the third and fourth electrodes EL3 and EL4 and the third light-emitting element LD3 connected in parallel between the third and fourth electrodes EL3 and EL4 may constitute a third series connection. At least one reverse light-emitting element LDr connected in the reverse direction may also be provided between two adjacent electrodes in each series connection.

[0331] When a driving current flows from the first power line PL1 to the second conductive line CL2 through the first transistor T1 of the pixel circuit unit PCL included in each pixel PXL, the driving current can flow into the first electrode EL1 through the first conductive line CL1 and the first contact hole CH1. The driving current flowing into the first electrode EL1 flows to the 2-1st electrode EL2_1 via the first light-emitting element LD1. Therefore, the first light-emitting element LD1 disposed between the first electrode EL1 and the 2-1st electrode EL2_1 can emit light with a brightness corresponding to the current allocated to each of the first light-emitting elements LD1. The driving current flowing through the 2-1st electrode EL2_1 flows through the second light-emitting element LD2 to the 3-1st electrode EL3_1. Therefore, the second light-emitting element LD2 can emit light with a brightness corresponding to the current allocated to each of the second light-emitting elements LD2. The driving current flowing through the 3-1st electrode EL3_1 flows through the third light-emitting element LD3 to the fourth electrode EL4. Therefore, the third light-emitting element LD3 can emit light with a brightness corresponding to the current allocated to each of the third light-emitting elements LD3.

[0332] In the above method, the driving current of each pixel PXL can flow while sequentially passing through the first light-emitting element LD1 disposed between the first electrode EL1 and the 2-1st electrode EL2_1, the second light-emitting element LD2 disposed between the 2-1st electrode EL2_1 and the 3-1st electrode EL3_1, and the third light-emitting element LD3 disposed between the 3-1st electrode EL3_1 and the fourth electrode EL4. Therefore, each pixel PXL can emit light having a brightness corresponding to the data signal supplied during each frame period.

[0333] Although the above content has been described with reference to the preferred embodiments of the present disclosure, those skilled in the art or those having ordinary knowledge of the corresponding technical field will understand that the present disclosure may be variously changed and modified without departing from the technical scope of the present disclosure described in the claims.

[0334] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area, wherein the display area includes a plurality of pixel areas each including an emission area; and a pixel provided in each of the plurality of pixel regions, The pixels include: a first electrode; a second electrode spaced apart from the first electrode and surrounding a periphery of the first electrode; a third electrode spaced apart from the second electrode and surrounding a periphery of the second electrode; a fourth electrode spaced apart from the third electrode and surrounding a periphery of the third electrode; a plurality of light-emitting elements, disposed between the first electrode to the fourth electrode; and The first conductive line and the second conductive line are arranged below the first electrode to the fourth electrode, and the insulating layer is placed between the first conductive line and the second conductive line and the first electrode to the fourth electrode, The first conductive line is electrically connected to the first electrode, and the second conductive line is electrically connected to the fourth electrode, Wherein, the plurality of light-emitting elements include: a first light-emitting element, disposed between the first electrode and the second electrode; a second light emitting element disposed between the second electrode and the third electrode; and The third light emitting element is provided between the third electrode and the fourth electrode.

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