Display device and method for manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate including an emission area and a non-emission area; a bank structure positioned in the emission region of the substrate and having an undercut shape; a pixel electrode positioned on the bank structure; a first light emitting layer positioned on the pixel electrode; a first cathode electrode positioned on the first light emitting layer; a first capping layer positioned on the first cathode electrode; a connection electrode positioned on the first capping layer; a pixel defining layer positioned in the non-emission region of the substrate and defining a first opening; an inorganic layer positioned on the pixel defining layer and defining a second opening; and an organic layer positioned on the inorganic layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0017882 filed on February 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images is growing and diversifying. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device or an organic light emitting display device. Among such flat panel display devices, because each of the pixels of the display panel can include a light emitting element that can emit light by itself, the light emitting display device can display an image without a backlight portion that provides light to the display panel.

[0005] Recently, display devices have been applied to glasses-type devices for providing virtual reality and augmented reality. Display devices can be implemented in very small sizes of 2 inches or less for application in glasses-type devices, but should have high pixel integration to achieve high resolution. For example, the display device can have a high pixel integration of 1000 pixels per inch (PPI) or more.

[0006] In the case where a display device is implemented in a very small size but with high pixel integration as described above, the size of the emission region where the light emitting element is set is reduced, and therefore, it is difficult to implement light emitting elements separated from each other for each emission region through a mask process. Summary of the Invention

[0007] Aspects of the present disclosure provide a display device having high pixel integration and a method of manufacturing the display device that is easy in manufacturing.

[0008] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0009] Details of other embodiments are described in the detailed description and are shown in the accompanying drawings.

[0010] According to aspects of the present disclosure, a display device may include: a substrate having an emission area and a non-emission area; a levee structure positioned in the emission area of the substrate and having an undercut shape; a pixel electrode positioned on the levee structure; a first light-emitting layer positioned on the pixel electrode; a first cathode electrode positioned on the first light-emitting layer; a first capping layer positioned on the first cathode electrode; a connecting electrode positioned on the first capping layer; a pixel defining layer positioned in the non-emission area of the substrate and defining a first opening; an inorganic layer positioned on the pixel defining layer and defining a second opening; and an organic layer positioned on the inorganic layer.

[0011] In an embodiment, the bank structure may include: a first bank layer; and a second bank layer positioned on the first bank layer and including a tip protruding more toward the non-emission region than a side surface of the first bank layer.

[0012] In an embodiment, the first bank layer and the second bank layer may include different inorganic insulating materials.

[0013] In an embodiment, a height of the first bank layer in a direction perpendicular to the substrate may be greater than a height of the second bank layer in the direction perpendicular to the substrate.

[0014] In an embodiment, a side surface of the first bank layer may be completely covered by the pixel defining layer.

[0015] In an embodiment, the second bank layer may include a first surface facing the pixel electrode, a second surface facing the first bank layer, and a side surface connecting the first surface and the second surface.

[0016] In an embodiment, a first surface and a side surface of the second bank layer may be in contact with the pixel electrode, and a second surface may be in contact with the pixel defining layer.

[0017] In an embodiment, the display device may further include a residual pattern positioned in the non-emission region of the substrate, wherein the residual pattern and the pixel electrode may include the same material, and the residual pattern may be spaced apart from the pixel electrode.

[0018] In an embodiment, the pixel defining layer may completely cover the residual pattern.

[0019] In an embodiment, the display device may further include: a second light-emitting layer, which is spaced apart from the first light-emitting layer in a direction parallel to the substrate, and the organic layer is arranged between the first light-emitting layer and the second light-emitting layer; a second cathode electrode, which is positioned on the second light-emitting layer; and a second capping layer, which is positioned on the second cathode electrode, wherein the first cathode electrode and the second cathode electrode can be spaced apart from each other, and the first capping layer and the second capping layer can be spaced apart from each other.

[0020] In an embodiment, the first capping layer may be electrically connected to the first cathode electrode, and the second capping layer may be electrically connected to the second cathode electrode.

[0021] In an embodiment, the connection electrode may include a first portion contacting the first capping layer, a second portion contacting the second capping layer, and a third portion contacting the organic layer.

[0022] In an embodiment, the first portion and the second portion may be spaced apart from each other, and the third portion is disposed between the first portion and the second portion.

[0023] In an embodiment, the inorganic layer may include: a first inorganic layer surrounding an edge of the first capping layer; and a second inorganic layer surrounding an edge of the second capping layer, wherein the first inorganic layer and the second inorganic layer may be spaced apart from each other, and the organic layer is disposed between the first inorganic layer and the second inorganic layer.

[0024] In an embodiment, in plan view, the first opening may be completely surrounded by the second opening.

[0025] According to aspects of the present disclosure, a method for manufacturing a display device may include: forming a first embankment layer on a substrate and forming a second embankment layer on the first embankment layer; etching a portion of the first embankment layer and a portion of the second embankment layer so that the second embankment layer may include a tip that protrudes much more than a side surface of the first embankment layer; forming a pixel electrode on the second embankment layer and forming a residual pattern on the substrate; forming a pixel defining layer surrounding the edge of the pixel electrode and covering the residual pattern; forming a light-emitting layer, a cathode electrode and a capping layer on the pixel electrode; and forming a connecting electrode on the capping layer.

[0026] In an embodiment, forming the pixel electrode may not include a separate etching process because the second bank layer may include a tip.

[0027] In an embodiment, when the cathode electrode and the capping layer are formed, the cathode electrode may completely cover the light emitting layer, and the capping layer may completely cover the cathode electrode.

[0028] In an embodiment, the method of manufacturing a display device may further include forming an inorganic layer and an organic layer after forming the capping layer and before forming the connecting electrode, wherein when forming the inorganic layer, the inorganic layer may surround an edge of the capping layer and may cover a portion of the residual pattern.

[0029] In an embodiment, when forming the connection electrode, the connection electrode may extend to the capping layer, the inorganic layer, and the organic layer, and the cathode electrode may be electrically connected to the connection electrode through the capping layer.

[0030] According to the display device and the method for manufacturing the display device according to the embodiment, the display device can include a dam structure having an undercut structure under the pixel electrode, so that the gap between the plurality of pixel electrodes can be minimized and the light-emitting element can be easily manufactured. Therefore, according to the display device and the method for manufacturing the display device according to the embodiment, a high-resolution display device that is easy to manufacture can be provided.

[0031] The effects of the present disclosure are not limited to the above-described effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view showing a head-mounted electronic device according to an embodiment;

[0034] Figure 2 yes Figure 1 An exploded perspective view of a head-mounted electronic device;

[0035] Figure 3 is a perspective view showing a head-mounted electronic device according to an embodiment;

[0036] Figure 4 is an exploded perspective view showing a display device according to an embodiment;

[0037] Figure 5 yes Figure 4 An enlarged plan view of a display area of a display panel;

[0038] Figure 6 According to the implementation method Figure 5 A schematic cross-sectional view of the display panel taken along line X1-X1' in FIG.

[0039] Figure 7 is Figure 6 an enlarged schematic cross-sectional view of a light emitting element layer and an encapsulation layer positioned to overlap with a first emission region;

[0040] Figure 8 is an enlarged schematic cross-sectional view of a light emitting element layer and an encapsulation layer positioned to overlap a non-emitting region positioned between a first emission region and a second emission region;

[0041] Figure 9 According to the implementation method Figure 5 A schematic cross-sectional view of the display panel taken along line X3-X3' in FIG.

[0042] Figures 10 to 232 are schematic cross-sectional views sequentially illustrating a process of manufacturing a light emitting element layer of a display panel according to an embodiment. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of the various embodiments or examples of the present disclosure. As used herein, "embodiment" and "embodiment" are interchangeable words that are non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment can be used or implemented in another embodiment.

[0044] Unless otherwise specified, the embodiments shown should be understood to provide features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0045] The use of cross hatching and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. In addition, similar figure numerals and / or reference symbols represent similar elements.

[0046] When an element (or layer) is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to another element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" can refer to a physical connection, an electrical connection and / or a fluid connection with or without intervening elements. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can be different directions that are not perpendicular to each other.

[0047] For the purposes of this disclosure, “at least one of A and B” may be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0049] Spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes and thereby describe the relationship of one element(s) to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, elements described as being "below" or "beneath" other elements or features will then be oriented as being "above" the other elements or features. Thus, the term "below" can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0050] The terms used herein are used to describe the purpose of specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an" and "the" are intended to also include the plural forms. In addition, the terms "comprise", "include", "contain" and / or "comprising", when used in this specification, specify the existence of the described features, integral bodies, steps, operations, elements, parts and / or groups thereof, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and therefore, are used to allow for the inherent deviations in the measured values, calculated values and / or provided values that will be recognized by those of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of embodiments and / or intermediate structures. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated areas, but should include deviations in shapes, for example, caused by manufacturing. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore, are not necessarily intended to be limiting.

[0052] As a convention in this area, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, parts and / or modules. It will be understood by those skilled in the art that these blocks, parts and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits), discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing technology or other manufacturing technology. When a block, part and / or module is implemented by a microprocessor or other similar hardware, software (for example, microcode) can be used to program and control the block, part and / or module to perform the various functions discussed herein, and firmware and / or software can be used to drive the block, part and / or module alternatively. It is also conceivable that each block, part and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs certain functions and a processor (for example, one or more programmed microprocessors and related circuits) that performs other functions. In addition, without departing from the scope of the present invention, each block, part and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, parts and / or modules. Furthermore, the blocks, parts and / or modules of some embodiments may be physically combined into more complex blocks, parts and / or modules without departing from the scope of the inventive concept.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless clearly defined as such herein.

[0054] Figure 1 1 is a perspective view showing a head mounted electronic device 1 according to an embodiment. Figure 2 yes Figure 1 An exploded perspective view of the head-mounted electronic device 1.

[0055] refer to Figure 1 and Figure 2 According to an embodiment, the head-mounted electronic device 1 may include a display device 10, a display device shell part 110, a shell part cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, an intermediate frame 160, a first optical member 151, a second optical member 152 and a control circuit board 170.

[0056] The display device 10 may include a first display device 10_1 and a second display device 10_2. The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 4 and Figure 5 The display device 10 is described in detail.

[0057] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131, and the second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first and second optical members 151 and 152 may include at least one convex lens.

[0058] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170 and between the second display device 10_2 and the control circuit board 170. The middle frame 160 may be used to support and fix the first and second display devices 10_1 and 10_2 and the control circuit board 170.

[0059] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing portion 110. The control circuit board 170 may be electrically connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 170 may convert an image source input from the outside into digital video data and transmit the digital video data to the first display device 10_1 and the second display device 10_2 via the connector.

[0060] The control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. As another example, the control circuit board 170 may transmit the same digital video data to both the first display device 10_1 and the second display device 10_2.

[0061] The display device housing portion 110 may be used to house the display device 10, the middle frame 160, the first optical member 151, the second optical member 152, and the control circuit board 170. The housing portion cover 120 may be provided to cover the opening surface of the display device housing portion 110. The housing portion cover 120 may include a first eyepiece 131 on which the user's left eye may be provided and a second eyepiece 132 on which the user's right eye may be provided. Figure 1 and Figure 2 1 and 132 may be provided separately, but the embodiments of the present disclosure are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into one eyepiece.

[0062] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Thus, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0063] The head-mounted strap 140 is used to fix the display device housing portion 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing portion cover 120 can be kept in a state where they can be placed on the user's left eye and right eye, respectively. In the case where the display device housing portion 110 is implemented to have a light weight and a small size, the head-mounted electronic device 1 may include, for example, Figure 3 The eyeglass frame is shown in FIG, excluding the headband 140.

[0064] The head-mounted electronic device 1 may further include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port, and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a wireless fidelity (WiFi) module, or a Bluetooth module.

[0065] Figure 3 1 is a perspective view showing a head mounted electronic device 1 according to an embodiment.

[0066] refer to Figure 3 The head-mounted electronic device 1_1 according to an embodiment may be a glasses-type electronic device in which the display device housing portion 120_1 may be implemented as a light-weight and small-sized glasses-type electronic device. The head-mounted electronic device 1_1 according to an embodiment may include a display device 10, a left-eye lens 311, a right-eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and the display device housing portion 120_1.

[0067] Figure 3 The display device 10 shown in FIG may include a third display device 10_3. The third display device 10_3 may be substantially the same as Figure 2 The first display device 10_1 and the second display device 10_2 shown in FIG are identical. Figure 4 and Figure 5 The display device 10 is described.

[0068] The display device housing portion 120_1 can accommodate the display device 10, the optical member 320, and the optical path conversion member 330. The image displayed on the display device 10 can be magnified by the optical member 320, converted in the optical path by the optical path conversion member 330, and provided to the user's right eye through the right-eye lens 312. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10 viewed through his / her right eye and a real image viewed through the right-eye lens 312 can be combined with each other.

[0069] Figure 3 3. The display device cover portion 120_1 is shown as being disposed at the right end of the support frame 350, but embodiments of the present disclosure are not limited thereto. For example, the display device cover portion 120_1 may be disposed at the left end of the support frame 350, and the image of the display device 10 may be provided to the user's left eye. As another example, the display device cover portion 120_1 may be disposed at both the left and right ends of the support frame 350, and the user may view the image displayed on the display device 10 through both his / her left eye and right eye.

[0070] Figure 4 is an exploded perspective view showing the display apparatus 10 according to the embodiment.

[0071] refer to Figure 4 , the display device 10 according to the embodiment can be a device for displaying moving images or still images. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display portion of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As another example, the display device 10 can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0072] The display device 10 according to the embodiment may include a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0073] The display panel 410 may have a shape similar to a rectangular shape in a plan view. For example, in a plan view, the display panel 410 may have a shape similar to a rectangular shape having a short side in a first direction X and a long side in a second direction Y intersecting the first direction X. In the display panel 410, the corner where the short side in the first direction X and the long side in the second direction Y meet may be rounded with a curvature (e.g., a predetermined curvature or a selectable curvature) or may be a right angle. The shape of the display panel 410 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape. The shape of the display device 10 in a plan view may follow the shape of the display panel 410 in a plan view, but embodiments of the present disclosure are not limited thereto.

[0074] The display panel 410 may include a display area DA and a non-display area NDA. The display area DA may be located at the center of the display panel 410 and may occupy most of the area of the display panel 410. The non-display area NDA may surround an edge of the display area DA.

[0075] The heat dissipation layer 420 may overlap the display panel 410 in a third direction Z, which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be provided on a surface (e.g., a rear surface) of the display panel 410. The heat dissipation layer 420 may be used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a layer made of graphite having high thermal conductivity or a metal such as silver (Ag), copper (Cu), aluminum (Al), or a combination thereof.

[0076] The circuit board 430 may be positioned in the non-display area NDA of the display panel 410 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 4 4. The circuit board 430 is shown as being unbent, but the circuit board 430 may be bent. One end of the circuit board 430 may be disposed on the rear surface of the display panel 410. The one end of the circuit board 430 may be an end opposite to the other end of the circuit board 430 that is electrically connected to the plurality of pads of the pad region of the display panel 410 using a conductive adhesive member.

[0077] The driving circuit 440 may receive digital video data and a timing signal from the outside and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0078] The power supply circuit 450 can generate a plurality of panel driving voltages according to an external source voltage. For example, the power supply circuit 450 can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT), and provide the first driving voltage, the second driving voltage, and the third driving voltage to the display panel 410.

[0079] Each of the driving circuit 440 and the power supply circuit 450 may be an integrated circuit (IC) and attached to a surface of the circuit board 430 .

[0080] Figure 5 yes Figure 4 FIG. 4 is an enlarged plan view of the display area DA of the display panel 410 .

[0081] refer to Figure 5 , the display area DA according to an embodiment may include an emission area EA and a non-emission area NLA.

[0082] The emission area EA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit red light, green light, or blue light, respectively, and the color of the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be selected according to the light emitting element ED to be described later (refer to FIG. Figure 6 ) types. For example, the first emission area EA1 may emit red light of a first color, the second emission area EA2 may emit green light of a second color, and the third emission area EA3 may emit blue light of a third color, but the present disclosure is not limited thereto. Although the first emission area EA1, the second emission area EA2, and the third emission area EA3 are shown as having the same size and shape, the present disclosure is not limited thereto. The size and shape of each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can be freely adjusted according to the desired characteristics.

[0083] The first, second, and third emission areas EA1, EA2, and EA3 may be defined by first and second openings OP1 and OP2. The second opening OP2 may completely surround the first opening OP1 in a plan view and may be completely surrounded by the non-emission area NLA in a plan view.

[0084] In some embodiments, at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3, which may be disposed adjacent to each other, may constitute a pixel group PXG. Pixel group PXG may be the smallest unit for emitting white light. However, depending on the embodiment, the type and / or number of the first emission area EA1, the second emission area EA2, and the third emission area EA3 constituting the pixel group PXG may be variously modified.

[0085] The non-emission area NLA may be positioned around the emission area EA. The non-emission area NLA may shield light emitted from each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. To this end, the non-emission area NLA may assist so that the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 may not mix.

[0086] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may include a ninth conductive portion VA9 therein. For ease of illustration, the ninth conductive portion VA9 may be positioned within the first opening OP1 in the drawings, but the present disclosure is not limited thereto. Depending on the embodiment, in a plan view, the ninth conductive portion VA9 may be positioned between the first opening OP1 and the second opening OP2, or in a portion overlapping the non-emission area NLA. The ninth conductive portion VA9 will be described later.

[0087] Figure 6 It is along Figure 5 Schematic cross-sectional view of a display panel 410 according to an embodiment, taken along line X1 - X1 ′ in FIG.

[0088] refer to Figure 6 The display panel 410 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, and a cover layer CVL.

[0089] The semiconductor base plate SBP may include a semiconductor substrate SSUB including a plurality of transistors PTR, a plurality of semiconductor insulating films covering the transistors PTR, and a plurality of contact terminals CTE electrically connected to the transistors PTR, respectively.

[0090] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions may be provided in the upper surface of the semiconductor substrate SSUB. The well regions may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, if the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. As another example, if the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0091] Each of the well regions may include a source region SA corresponding to a source electrode of the transistor PTR, a drain region DR corresponding to a drain electrode of the transistor PTR, and a channel region CH disposed between the source region SA and the drain region DR.

[0092] Each of the source region SA and the drain region DR may be a region doped with first type impurities. The gate electrode GE of the transistor PTR may overlap with the well region in the third direction Z. The channel region CH may overlap with the gate electrode GE in the third direction Z. The source region SA may be provided on one side of the gate electrode GE, and the drain region DR may be provided on the other side of the gate electrode GE.

[0093] The first insulating layer SINS1 may be provided on the semiconductor substrate SSUB. The first insulating layer SINS1 may be based on silicon carbonitride (SiCN) or silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0094] The second insulating layer SINS2 may be provided on the first insulating layer SINS1. The second insulating layer SINS2 may be based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0095] Contact terminals CTE may be provided on the second insulating layer SINS2 . Each of the contact terminals CTE may be electrically connected to any one of the gate electrode GE, source region SA, and drain region DR of each of the transistors PTR through a hole passing through the first and second insulating layers SINS1 and SINS2 .

[0096] Each of the contact terminals CTE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), alloys thereof, and combinations thereof.

[0097] The third insulating layer SINS3 may be provided on the side surface of the contact terminal CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third insulating layer SINS3. The third insulating layer SINS3 may be based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0098] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate). The thin film transistor can be provided on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0099] The light emitting element backplane EBP may include first to eighth metal layers ML1 to ML8 , a plurality of first to eighth conductive portions VA1 to VA8 , and first to ninth interlayer insulating layers INS1 to INS9 .

[0100] The first to eighth metal layers ML1 to ML8 are used to implement circuits of the light emitting elements ED1 to ED3 by connecting contact terminals CTE exposed from the semiconductor base plate SBP to one another.

[0101] A first interlayer insulating layer INS1 may be disposed on the semiconductor substrate SBP. Each of the first conductive vias VA1 may extend through the first interlayer insulating layer INS1 to a contact terminal CTE exposed from the semiconductor substrate SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating layer INS1 and may extend to the first conductive vias VA1.

[0102] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the second conductive portions VA2 may extend through the second interlayer insulating layer INS2 to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and may extend to the second conductive portions VA2.

[0103] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the third conductive portions VA3 may extend through the third interlayer insulating layer INS3 to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may extend to the third conductive portion VA3.

[0104] A fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the fourth conductive portions VA4 may extend through the fourth interlayer insulating layer INS4 to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may extend to the fourth conductive portion VA4.

[0105] A fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the fifth conductive portions VA5 may extend through the fifth interlayer insulating layer INS5 to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may extend to the fifth conductive portion VA5.

[0106] A sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the sixth conductive portions VA6 may extend through the sixth interlayer insulating layer INS6 to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating layer INS6 and may extend to the sixth conductive portion VA6.

[0107] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the seventh conductive portions VA7 may pass through the seventh interlayer insulating layer INS7 to extend to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating layer INS7 and may extend to the seventh conductive portion VA7.

[0108] An eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the eighth conductive portions VA8 may extend through the eighth interlayer insulating layer INS8 to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating layer INS8 and may extend to the eighth conductive portion VA8.

[0109] The contact terminal CTE of the semiconductor base plate SBP and the first to sixth metal layers ML1 to ML6 of the light emitting element base plate EBP can be electrically connected to the drain region DR, the source region SA, and the gate electrode GE of the transistor PTR. The seventh and eighth metal layers ML7 and ML8 can be electrically connected to the drain region DR instead of the source region SA and the gate electrode GE.

[0110] The first to eighth metal layers ML1 to ML8 and the first to eighth conductive portions VA1 to VA8 may be made of substantially the same material. Each of the first to eighth metal layers ML1 to ML8 and the first to eighth conductive portions VA1 to VA8 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), alloys thereof, and combinations thereof. The first to eighth conductive portions VA1 to VA8 may be made of substantially the same material. The first to eighth interlayer insulating layers INS1 to INS8 may be silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0111] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be based on silicon oxide (SiO x ) of the inorganic film, but the embodiments of the present disclosure are not limited thereto.

[0112] The light emitting element layer EML may be disposed on the light emitting element backplane EBP and may include a bank structure BNS, a light emitting element ED, a residual pattern AEP, a pixel defining layer PDL, an inorganic layer IL, and an organic layer OL.

[0113] The bank structure BNS according to an embodiment may be positioned in a portion overlapping the emission area EA. The bank structure BNS may be positioned on the ninth interlayer insulating layer INS9. The bank structure BNS may include a first bank layer BN1 and a second bank layer BN2 that may be sequentially stacked on each other.

[0114] The first bank layer BN1 according to an embodiment may include a plurality of patterns, and the respective patterns may be separated or spaced apart from each other in the first direction X in portions overlapping with the first emission region EA1, the second emission region EA2, and the third emission region EA3. For example, the first bank layer BN1 may have an island-shaped pattern. Each island of the first bank layer BN1 may have a circular shape or a polygonal shape such as a triangular shape or a rectangular shape in a plan view.

[0115] The second bank layer BN2 according to an embodiment may be provided on the first bank layer BN1. The second bank layer BN2 may include a plurality of patterns, and the respective patterns may be separated or spaced apart from each other in the first direction X in portions overlapping with the first emission region EA1, the second emission region EA2, and the third emission region EA3. In an embodiment, the second bank layer BN2 may have an island-shaped pattern. Each island of the second bank layer BN2 may have a circular shape or a polygonal shape such as a triangular shape or a rectangular shape in a plan view.

[0116] The second bank layer BN2 according to an embodiment may have a tip TIP that protrudes more toward the non-emission area NLA than the first bank layer BN1. An undercut may be formed between the tips TIP of the first and second bank layers BN1 and BN2. Details will be described later.

[0117] According to an embodiment, the light-emitting element ED may be disposed on the second bank layer BN2 and the pixel defining layer PDL. The light-emitting element ED may include a first light-emitting element ED1 disposed in the first emission area EA1, a second light-emitting element ED2 disposed in the second emission area EA2, and a third light-emitting element ED3 disposed in the third emission area EA3. The first light-emitting element ED1 may include a pixel electrode AE, a first light-emitting layer EL1, a first cathode electrode CE1, a first capping layer CCP1, and a connecting electrode CTCE, the second light-emitting element ED2 may include a pixel electrode AE, a second light-emitting layer EL2, a second cathode electrode CE2, a second capping layer CCP2, and a connecting electrode CTCE, and the third light-emitting element ED3 may include a pixel electrode AE, a third light-emitting layer EL3, a third cathode electrode CE3, a third capping layer CCP3, and a connecting electrode CTCE.

[0118] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, which overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, may emit light of different colors depending on the material of the light-emitting layer EL. For example, the first light-emitting element ED1 may emit red light, which may be light of the first color, the second light-emitting element ED2 may emit green light, which may be light of the second color, and the third light-emitting element ED3 may emit blue light, which may be light of the third color. However, the present disclosure is not limited thereto, and the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, which overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, may also emit light of the same color.

[0119] The pixel electrode AE according to the embodiment may be arranged on the second bank layer BN2. The display panel 410 according to the embodiment may include a bank structure BNS forming an undercut under the pixel electrode AE, and therefore, the pixel electrode AE positioned to overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3 can be formed without a separate etching process. In other words, in the display panel 410 according to the embodiment, the second bank layer BN2 may include a tip TIP that protrudes much more than the first bank layer BN1, and therefore, a plurality of pixel electrodes AE positioned to be spaced apart from each other can be formed without a separate etching process. For this reason, in the display panel 410 according to the embodiment, pixel electrodes AE adjacent to each other can be formed to have a very small gap between them, and for this reason, the display panel 410 can be applied to electronic devices requiring high resolution. The manufacturing method will be described later.

[0120] The pixel electrode AE according to an embodiment may include a first layer AE1 and a second layer AE2 which may be sequentially stacked on each other.

[0121] The first layer AE1 may include a metal, and for example, the first layer AE1 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and combinations thereof. According to an embodiment, the first layer AE1 may be formed of a single layer or may have a double-layer structure in which a metal material and a transparent conductive oxide (TCO) may be stacked on each other.

[0122] The second layer AE2 may include a transparent conductive oxide (TCO) and, for example, may include one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO).

[0123] A residual pattern AEP according to an embodiment may be provided on the ninth interlayer insulating layer INS9 in a portion overlapping the non-emission area NLA. The residual pattern AEP will be described later.

[0124] The pixel defining layer PDL according to an embodiment may be positioned on the pixel electrode AE and the ninth interlayer insulating layer INS9 . The pixel defining layer PDL may define a first opening OP1 and expose the pixel electrode AE in a portion overlapping the first opening OP1 .

[0125] The light-emitting layer EL according to an embodiment may be positioned on the pixel electrode AE and the pixel-defining layer PDL. The light-emitting layer EL according to an embodiment may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 positioned to overlap with a first emission area EA1, a second emission area EA2, and a third emission area EA3, respectively. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may emit light of different wavelengths. For example, the first light-emitting layer EL1 disposed in the first emission area EA1 may emit red light having a peak wavelength in the range of approximately 610 nm to approximately 650 nm, the second light-emitting layer EL2 disposed in the second emission area EA2 may emit green light having a peak wavelength in the range of approximately 510 nm to approximately 550 nm, and the third light-emitting layer EL3 disposed in the third emission area EA3 may emit blue light having a peak wavelength in the range of approximately 440 nm to approximately 480 nm. The first emission area EA1 to the third emission area EA3 constituting a pixel may include light-emitting elements ED emitting light of different colors to represent a white gradient. As another example, the light emitting layer EL may include a plurality of materials emitting light of different colors, so that a single light emitting layer EL may emit mixed light.

[0126] According to an embodiment, the light-emitting layer EL may include a dam structure BNS having an undercut formed thereunder, and thus, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, which are positioned to overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, can be formed without a separate fine metal mask. In other words, in the display panel 410 according to an embodiment, the second bank layer BN2 may include a tip TIP that protrudes significantly more than the first bank layer BN1, and thus, multiple light-emitting layers EL positioned to be spaced apart from each other can be formed without a separate fine metal mask. For this reason, in the display panel 410 according to an embodiment, adjacent light-emitting layers EL can be formed with a very small gap between them, and for this reason, the display panel 410 can be applied to electronic devices requiring high resolution. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 can be spaced apart from each other in a direction parallel to the semiconductor substrate SSUB. The manufacturing method will be described later.

[0127] The cathode electrode CE according to the embodiment may be disposed on the light emitting layer EL and the pixel defining layer PDL.

[0128] The cathode electrode CE according to an embodiment may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3 positioned to overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 according to an embodiment may be spaced apart from each other in the first direction X. The first cathode electrode CE1 may be disposed on the first light emitting layer EL1, the second cathode electrode CE2 may be disposed on the second light emitting layer EL2, and the third cathode electrode CE3 may be disposed on the third light emitting layer EL3.

[0129] The cathode electrode CE according to an embodiment may include a dam structure BNS having an undercut formed thereunder, and thus the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, positioned so as to overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively, can be formed without a separate fine metal mask. In other words, in the display panel 410 according to an embodiment, the second bank layer BN2 may include a tip TIP that protrudes significantly more than the first bank layer BN1, and thus a plurality of cathode electrodes CE positioned so as to be spaced apart from each other can be formed without a separate fine metal mask. The process for forming the cathode electrode CE according to an embodiment may have a higher step coverage than the process for forming the light-emitting layer EL. Therefore, the cathode electrode CE according to an embodiment may completely cover the light-emitting layer EL. The manufacturing method will be described later.

[0130] The cathode electrode CE may include a transparent conductive material. As an example, the cathode electrode CE may be made of a transparent conductive material (TCO) capable of transmitting light therethrough (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the cathode electrode CE is made of a semi-transmissive conductive material, the microcavity can improve the luminous efficiency.

[0131] The capping layer CCP according to an embodiment may be disposed on the cathode electrode CE and the pixel defining layer PDL. The capping layer CCP according to an embodiment may serve as an etching stopper and protect the cathode electrode CE from moisture penetration during a manufacturing process of the display panel 410.

[0132] The capping layer CCP according to an embodiment may include a first capping layer CCP1, a second capping layer CCP2, and a third capping layer CCP3 positioned to overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3 according to an embodiment may be spaced apart from each other in the first direction X. The first capping layer CCP1 may be positioned on the first cathode electrode CE1, the second capping layer CCP2 may be positioned on the second cathode electrode CE2, and the third capping layer CCP3 may be positioned on the third cathode electrode CE3.

[0133] The capping layer CCP may include a transparent conductive oxide (TCO), and for example may include one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO).

[0134] The inorganic layer IL according to an embodiment may be positioned on the pixel defining layer PDL and the capping layer CCP in a portion overlapping the non-emission area NLA. The inorganic layer IL according to an embodiment may define a second opening OP2 and expose the capping layer CCP in a portion overlapping the second opening OP2.

[0135] The inorganic layer IL according to an embodiment may protect the light emitting element ED from an etching process included in a manufacturing process of the display panel 410 .

[0136] The inorganic layer IL may include a first inorganic layer IL1 surrounding the first emission area EA1, a second inorganic layer IL2 surrounding the second emission area EA2, and a third inorganic layer IL3 surrounding the third emission area EA3. The first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be spaced apart from each other in a portion overlapping with the non-emission area NLA. The first inorganic layer IL1 may cover a portion of the first light-emitting element ED1, the second inorganic layer IL2 may cover a portion of the second light-emitting element ED2, and the third inorganic layer IL3 may cover a portion of the third light-emitting element ED3.

[0137] The inorganic layer IL may include an inorganic insulating material, and, for example, may include at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0138] The organic layer OL according to an embodiment may be positioned on the pixel defining layer PDL in a portion overlapping the non-emission area NLA. The organic layer OL according to an embodiment may planarize steps formed by the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 in a portion overlapping the non-emission area NLA.

[0139] The organic layer OL may include an organic insulating material having fluidity such as hexamethyldisiloxane (HMDSO).

[0140] The connection electrode CTCE according to an embodiment may be positioned on the capping layer CCP and the organic layer OL. The connection electrode CTCE may be a common layer positioned entirely in a portion overlapping the emission area EA and the non-emission area NLA.

[0141] The connection electrode CTCE may be electrically connected to the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3. Specifically, the connection electrode CTCE may be in contact with the first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3, and electrically connected to the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 through the first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3.

[0142] The connection electrode CTCE according to an embodiment may include a transparent conductive oxide (TCO), and for example, may include one or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO).

[0143] The encapsulation layer TFE may be disposed on the light-emitting element layer EML. The encapsulation layer TFE may prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFE may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3, which may be sequentially stacked on top of each other. The first encapsulation layer TFE1 may be disposed on the connection electrode CTCE, the second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1, and the third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2.

[0144] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be made of an inorganic insulating material. As an example, the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), aluminum oxide (AlO x ) or a combination thereof.

[0145] The second encapsulation layer TFE2 may be made of an organic material, for example, acrylic resin, epoxy resin, silicone resin, silicone acrylic resin, phenolic resin, polyamide resin, polyimide resin, etc., or a combination thereof.

[0146] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0147] The optical layer OPL may include a plurality of first, second, and third color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL.

[0148] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant (such as a dye or pigment that absorbs light of a wavelength band other than light of a specific wavelength band) and may be disposed to correspond to the color of light emitted from the emission area EA.

[0149] The first color filter CF1 may be a red color filter disposed to overlap with the first emission area EA1, and may transmit only red light through the first color filter CF1. The second color filter CF2 may be a green color filter disposed to overlap with the second emission area EA2, and may transmit only green light through the second color filter CF2. The third color filter CF3 may be a blue color filter disposed to overlap with the third emission area EA3, and may transmit only blue light through the third color filter CF3.

[0150] Lenses LNS may be disposed on the first, second, and third color filters CF1, CF2, and CF3, respectively. The lenses LNS may be a structure for increasing the ratio of light directed toward the front surface of the display panel 410. The lenses LNS may have a convex cross-sectional shape convex in an upward direction.

[0151] A filling layer FIL may be disposed on the lens LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index or a selectable refractive index) such that light travels in a third direction Z at the interface between the lens LNS and the filling layer FIL. The filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or a combination thereof.

[0152] The cover layer CVL may be provided on the optical layer OPL. The cover layer CVL may be a glass substrate, or may be a resin substrate that may include a polymer resin. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. The filling layer FIL may be used to bond the cover layer CVL. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In the case where the cover layer CVL is a resin substrate that includes a polymer resin, the cover layer CVL may be applied (e.g., directly applied) to the filling layer FIL.

[0153] Figure 7 is Figure 6 FIG. 1 is an enlarged schematic cross-sectional view of the light emitting element layer EML and the encapsulation layer TFE positioned to overlap with the first emission area EA1.

[0154] refer to Figure 7 , the bank structure BNS according to an embodiment may include a first bank layer BN1 and a second bank layer BN2 having different materials.

[0155] The first bank layer BN1 according to an embodiment may be positioned in a portion overlapping the first emission area EA1 and may not overlap the non-emission area NLA. The first bank layer BN1 may be positioned on the ninth interlayer insulating layer INS9.

[0156] In some embodiments, the first bank layer BN1 may include a side surface 1c. The side surface 1c of the first bank layer BN1 may be a surface facing the non-emission area NLA. The side surface 1c of the first bank layer BN1 may be completely covered by the pixel defining layer PDL, and the entire side surface 1c of the first bank layer BN1 may be in contact with the pixel defining layer PDL.

[0157] The first bank layer BN1 may include an inorganic insulating material, and for example, may include any one of silicon nitride, silicon oxynitride, silicon oxide, and a combination thereof.

[0158] The second bank layer BN2 according to an embodiment may be positioned on the first bank layer BN1.

[0159] In some embodiments, the second bank layer BN2 may include an upper surface 2a, a lower surface 2b, and a side surface 2c. The upper surface 2a of the second bank layer BN2 may be a surface facing the pixel electrode AE, the lower surface 2b of the second bank layer BN2 may be a surface facing the first bank layer BN1, and the side surface 2c of the second bank layer BN2 may be a surface connecting the upper surface 2a and the lower surface 2b. The side surface 2c of the second bank layer BN2 may be a surface facing the non-emission area NLA.

[0160] The upper surface 2a and side surface 2c of the second bank layer BN2 may be covered by and in contact with the pixel electrode AE, and the lower surface 2b of the second bank layer BN2 may be covered by and in contact with the pixel defining layer PDL.

[0161] In the manufacturing process of the bank structure BNS, the first bank layer BN1 and the second bank layer BN2 can be formed by performing the same etching process. At this time, the second bank layer BN2 can have a higher etching resistance than the first bank layer BN1. In other words, with respect to the same etchant, the etching rate of the second bank layer BN2 can be lower than the etching rate of the first bank layer BN1. Therefore, the second bank layer BN2 can have a tip TIP that protrudes much more than the first bank layer BN1, and for this reason, the side surface 2c of the second bank layer BN2 can protrude much more toward the non-emitting area NLA than the side surface 1c of the first bank layer BN1. For example, an undercut can be formed between the side surface 1c of the first bank layer BN1 and the tip TIP of the second bank layer BN2. The manufacturing method will be described later.

[0162] The second bank layer BN2 may include an inorganic insulating material, such as any one of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof. As described above, the first bank layer BN1 and the second bank layer BN2 may include different materials. Therefore, in the case where the first bank layer BN1 is one of silicon nitride, silicon oxynitride, silicon oxide, and combinations thereof, the second bank layer BN2 may include a material different from that of the first bank layer BN1. For example, in the case where the first bank layer BN1 is silicon nitride, the second bank layer BN2 may be any one of silicon oxynitride and silicon oxide, excluding silicon nitride.

[0163] In some embodiments, a height H1 of the first bank layer BN1 in a direction perpendicular to the semiconductor substrate SSUB may be greater than a height H2 of the second bank layer BN2 in the direction perpendicular to the semiconductor substrate SSUB.

[0164] The pixel electrode AE may be disposed on and cover the upper surface 2a and side surfaces 2c of the second bank layer BN2. Specifically, the first layer AE1 of the pixel electrode AE may cover and contact the upper surface 2a and side surfaces 2c of the second bank layer BN2. The second layer AE2 of the pixel electrode AE may cover the upper surface 2a and side surfaces 2c of the second bank layer BN2. Depending on the embodiment, the second layer AE2 may not cover the side surfaces 2c of the second bank layer BN2. The residual pattern AEP will be described later.

[0165] The pixel defining layer PDL may be positioned on the pixel electrode AE and the residual pattern AEP. The pixel defining layer PDL may be positioned to surround the edge of the pixel electrode AE. In other words, the pixel defining layer PDL may expose the pixel electrode AE at a portion overlapping with the first opening OP1 and may surround the first opening OP1.

[0166] The pixel defining layer (PDL) may be formed with the same thickness according to the contours of the underlying structure. Therefore, the pixel defining layer (PDL) may include steps. The pixel defining layer (PDL) may contact portions of the pixel electrode (AE), portions of the lower surface (2b) of the second bank (BN2), and the side surface (1c) of the first bank (BN1).

[0167] The pixel defining layer PDL may include an inorganic insulating material such as at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, and amorphous silicon, but is not limited thereto.

[0168] The first light-emitting layer EL1 according to an embodiment may be positioned on the pixel electrode AE. The first light-emitting layer EL1 may be positioned in a portion overlapping the first emission area EA1 and the non-emission area NLA. Specifically, the first light-emitting layer EL1 may contact the pixel electrode AE in a portion overlapping the first opening OP1, and may contact the pixel defining layer PDL in a portion overlapping the second opening OP2. The first light-emitting layer EL1 according to an embodiment may be formed on the pixel electrode AE in a manufacturing process without a separate fine metal mask. The manufacturing method will be described later.

[0169] The first cathode electrode CE1 according to an embodiment may be positioned on the first light-emitting layer EL1. The first cathode electrode CE1 may be positioned in a portion overlapping the first emission area EA1 and the non-emission area NLA. Specifically, the first cathode electrode CE1 may contact the first light-emitting layer EL1 in the portion overlapping the first emission area EA1, and may contact the pixel-defining layer PDL in the portion overlapping the non-emission area NLA. As described above, since the first cathode electrode CE1 may be formed using a process having a higher step coverage than the first light-emitting layer EL1, the first cathode electrode CE1 may completely cover the first light-emitting layer EL1. The manufacturing method will be described later.

[0170] The first capping layer CCP1 according to an embodiment may be positioned on the first cathode electrode CE1. The first capping layer CCP1 may be positioned in a portion overlapping with the first emission area EA1 and the non-emission area NLA. Specifically, the first capping layer CCP1 may be in contact with the first cathode electrode CE1 in a portion overlapping with the first emission area EA1, and may be in contact with the pixel defining layer PDL in a portion overlapping with the non-emission area NLA. As described above, the first capping layer CCP1 may be formed by a process having a higher step coverage than that of the first cathode electrode CE1. Therefore, the first capping layer CCP1 may completely cover the first cathode electrode CE1, and may cover a portion of the pixel defining layer PDL that is not covered by the first cathode electrode CE1. The manufacturing method will be described later.

[0171] The connection electrode CTCE may be positioned on the first capping layer CCP1 in a portion overlapping the first opening OP1. The connection electrode CTCE may contact the first capping layer CCP1 at a portion overlapping the first opening OP1. The connection electrode CTCE may be electrically connected to the first cathode electrode CE1 through the first capping layer CCP1.

[0172] The related structures of the connection electrode CTCE, the first inorganic layer IL1, and the organic layer OL in the portion overlapping the non-emission area NLA will be described later.

[0173] The first encapsulation layer TFE1 and the second encapsulation layer TFE2 may be completely formed on the connection electrode CTCE. The first encapsulation layer TFE1 may contact the connection electrode CTCE. The first encapsulation layer TFE1 and the second encapsulation layer TFE2 may overlap with the tip TIP of the second bank layer BN2 in the third direction Z. Other redundant descriptions will be omitted.

[0174] For ease of description, the light emitting element layer EML and the encapsulation layer TFE positioned in the portion overlapping the first emission area EA1 may be illustrated and described, but the light emitting element layer EML and the encapsulation layer TFE positioned in the portion overlapping the second emission area EA2 and the third emission area EA3 may also have the same structure and characteristics. Redundant descriptions will be omitted.

[0175] Figure 8 is an enlarged schematic cross-sectional view of the light emitting element layer EML and the encapsulation layer TFE positioned to overlap the non-emission area NLA positioned between the first emission area EA1 and the second emission area EA2.

[0176] refer to Figure 8 , the first emission area EA1 and the second emission area EA2 may be spaced apart from the non-emission area NLA between the first emission area EA1 and the second emission area EA2.

[0177] The residual pattern AEP according to the embodiment may be positioned on the ninth interlayer insulating layer INS9 in a portion overlapping the non-emission area NLA. The residual pattern AEP according to the embodiment may be formed as a result of the material forming the pixel electrode AE during the manufacturing process of the pixel electrode AE being disconnected (or spaced apart) from the pixel electrode AE due to the tip TIP of the second bank layer BN2 and not being electrically connected to the pixel electrode AE. Therefore, the residual pattern AEP and the pixel electrode AE may include the same material. In the case where the pixel electrode AE is a multi-layer structure, the stacking structure of the residual pattern AEP may be the same as the stacking structure of the pixel electrode AE.

[0178] The pixel defining layer PDL according to an embodiment may be positioned on the ninth interlayer insulating layer INS9 and the residual pattern AEP in a portion overlapping the non-emission area NLA. The pixel defining layer PDL covering the edge of the first light-emitting element ED1 and the pixel defining layer PDL covering the edge of the second light-emitting element ED2 may be integral with each other. In other words, the pixel defining layer PDL overlapping the first emission area EA1 and the pixel defining layer PDL overlapping the second emission area EA2 may extend to each other through the portion of the pixel defining layer PDL covering the residual pattern AEP.

[0179] The inorganic layer IL according to an embodiment may be positioned on the pixel defining layer PDL and the capping layer CCP. The inorganic layer IL may be in contact with the pixel defining layer PDL and the capping layer CCP. The inorganic layer IL may be positioned around an edge of the capping layer CCP.

[0180] The inorganic layer IL may include a first inorganic layer IL1 and a second inorganic layer IL2 spaced apart from each other in a portion overlapping the non-emission area NLA. The first inorganic layer IL1 and the second inorganic layer IL2 may be spaced apart in the first direction X, with the organic layer OL between the first inorganic layer IL1 and the second inorganic layer IL2. The first inorganic layer IL1 may cover the first light-emitting element ED1 and the embankment structure BNS positioned below the first light-emitting element ED1, and the second inorganic layer IL2 may cover the second light-emitting element ED2 and the embankment structure BNS positioned below the second light-emitting element ED2. In other words, the first inorganic layer IL1 may be positioned to surround the edge of the first light-emitting element ED1, and the second inorganic layer IL2 may be positioned to surround the edge of the second light-emitting element ED2.

[0181] According to an embodiment, the organic layer OL may be positioned on the pixel defining layer PDL and the inorganic layer IL in a portion overlapping the non-emission area NLA. The organic layer OL may be positioned between the first inorganic layer IL1 and the second inorganic layer IL2 in a portion overlapping the non-emission area NLA. As described above, the organic layer OL may flatten the step formed between the first inorganic layer IL1 and the second inorganic layer IL2. Therefore, the connection electrode CTCE positioned to overlap the first emission area EA1 and the connection electrode CTCE positioned to overlap the second emission area EA2 may be electrically connected without a disconnection defect through the portion of the connection electrode CTCE positioned to overlap the non-emission area NLA.

[0182] In some embodiments, the connection electrode CTCE may include a first portion ct1 in contact with the first capping layer CCP1, a second portion ct2 in contact with the second capping layer CCP2, a third portion ct3 in contact with the organic layer OL, and a fourth portion ct4 in contact with the inorganic layer IL. The first and second portions ct1 and ct2 may be spaced apart from the third portion ct3 disposed between the first and second portions ct1 and ct2.

[0183] The first cathode electrode CE1, which may be electrically connected to the first capping layer CCP1, may be electrically connected to the first portion ct1 of the connection electrode CTCE. The second cathode electrode CE2, which may be electrically connected to the second capping layer CCP2, may be electrically connected to the second portion ct2 of the connection electrode CTCE. The first portion ct1 and the second portion ct2 of the connection electrode CTCE may be electrically connected to each other via the third portion ct3 and the fourth portion ct4. For example, the first cathode electrode CE1 and the second cathode electrode CE2 may be electrically connected to each other via the connection electrode CTCE. Redundant descriptions may be omitted.

[0184] The first encapsulation layer TFE1 according to an embodiment may contact the connection electrode CTCE at a portion overlapping the non-emission area NLA. The first encapsulation layer TFE1 and the second encapsulation layer TFE2 may overlap the residual pattern AEP, the inorganic layer IL, and the organic layer OL in a portion overlapping the non-emission area NLA in the third direction Z. Other redundant descriptions will be omitted.

[0185] Figure 9 According to the implementation method Figure 5 Schematic cross-sectional view of the display panel 410 taken along line X3-X3' in FIG.

[0186] refer to Figure 9, the pixel electrode AE included in the display panel 410 according to the embodiment can be electrically connected to the eighth metal layer ML8 through the ninth conductive portion VA9. The ninth conductive portion VA9 can pass through the bank structure BNS and the ninth interlayer insulating layer INS9. The pixel electrode AE can be electrically connected to the eighth metal layer ML8 through the ninth conductive portion VA9, and then electrically connected to the drain region DR or the source region SA of the transistor PTR through the first conductive portion VA1 to the eighth conductive portion VA8, the first metal layer ML1 to the seventh metal layer ML7, and the contact terminal CTE. In other words, when the pixel electrode AE according to the embodiment receives a voltage corresponding to the data voltage through the transistor PTR and the cathode electrode CE receives a low potential voltage, a potential difference can be formed between the pixel electrode AE and the cathode electrode CE, and thus the light-emitting layer EL can emit light.

[0187] The ninth conductive portion VA9 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), alloys thereof, and combinations thereof. Other redundant descriptions will be omitted.

[0188] Figures 10 to 23 1 is a schematic cross-sectional view sequentially illustrating a manufacturing process of the light emitting element layer EML of the display panel 410 according to an embodiment. Figure 6 . The manufacturing process of the light emitting element layer EML is shown in FIG.

[0189] refer to Figure 10 and Figure 11 , a first bank material layer BN1L and a second bank material layer BN2L may be formed on the entire surface of the light emitting element base plate EBP. Although not shown in the drawings, the detailed structure of the light emitting element base plate EBP may be the same as that described above. Figure 6 The description is the same.

[0190] Subsequently, a photoresist pattern PR may be formed on the second bank material layer BN2L. The photoresist pattern PR may be formed, and some of the photoresist patterns PR may be spaced apart from each other. Next, a first etching process (first etching) may be performed using the photoresist pattern PR as a mask.

[0191] With respect to the same etchant, the first bank material layer BN1L according to an embodiment may have a higher etching rate than the second bank material layer BN2L. Therefore, when the same etching process is performed, the second bank layer BN2 may have a more protruding tip TIP than the first bank layer BN1, and the bank structure BNS may have an undercut shape. The etchant mentioned above may include all chemical solutions or gases used in the etching process.

[0192] In this process, the first bank material layer BN1L and the second bank material layer BN2L in a portion where the photoresist PR may not be formed may be removed, and for this reason, a Figure 6 A hole HOL may be formed in a portion where the first and second bank material layers BN1L and BN2L may be removed, and the light emitting element base plate EBP may be exposed in a portion overlapping with the hole HOL.

[0193] Next, refer to Figure 12 , a pixel electrode AE may be formed on the second bank layer BN2. The pixel electrode AE may be formed by thermal evaporation.

[0194] Because the second bank layer BN2 may include a pointed tip TIP, the material forming the pixel electrodes AE according to the embodiment can be formed to be spaced apart on the bank structure BNS without a separate etching process. For example, because the pixel electrodes AE are not manufactured using a separate photolithography process and an etching process, the gaps between the pixel electrodes AE can be designed to be extremely small, thereby enabling a high-resolution display device to be realized.

[0195] The material forming the pixel electrode AE may be positioned not only on the bank structure BNS but also on the light emitting element base plate EBP in a portion not overlapping with the bank structure BNS. The material forming the pixel electrode AE positioned on the light emitting element base plate EBP may become Figure 6 Therefore, the residual pattern AEP and the pixel electrode AE may include the same material, and the residual pattern AEP and the pixel electrode AE may be spaced apart from each other.

[0196] Next, refer to Figure 13 and Figure 14 The pixel defining material layer PDLL may be formed over the entire pixel electrode AE and the residual pattern AEP. The pixel defining material layer PDLL may include an inorganic insulating material and may be formed with the same thickness according to the contour of the underlying structure.

[0197] Subsequently, a plurality of photoresist patterns PR may be formed on the pixel defining material layer PDLL in portions overlapping the residual pattern AEP, and a second etching process (second etching) may be performed using the photoresist patterns PR as masks.

[0198] In this process, the pixel defining material layer PDLL may be removed in a portion where the photoresist pattern PR may not be formed, and the pixel defining material layer PDLL may become Figure 6 The pixel defining layer PDL is shown in FIG. The pixel defining layer PDL may be positioned to surround the edge of the pixel electrode AE and cover the residual pattern AEP.

[0199] Next, refer to Figures 15 to 17 , a first light emitting layer EL1 may be formed on the pixel electrode AE. The first light emitting layer EL1 according to an embodiment may be formed by a thermal evaporation process.

[0200] Since the display panel 410 according to the embodiment may include a bank structure BNS having an undercut, the material forming the first light-emitting layer EL1 can be formed on the pixel electrode AE without a separate fine metal mask. The material forming the first light-emitting layer EL1 according to the embodiment may be positioned on the entire pixel electrode AE and may also be positioned on the pixel defining layer PDL in a portion overlapping with the residual pattern AEP. The material forming the first light-emitting layer EL1 positioned on the residual pattern AEP and the material forming the first light-emitting layer EL1 positioned on the pixel electrode AE may be spaced apart from each other.

[0201] Next, a first cathode electrode CE1 may be formed on the first light emitting layer EL1. The first cathode electrode CE1 according to an embodiment may be formed through a thermal evaporation process.

[0202] Since the display panel 410 according to the embodiment may include a bank structure BNS having an undercut, the material forming the first cathode electrode CE1 can be formed on the first light-emitting layer EL1 without a separate fine metal mask. The material forming the first cathode electrode CE1 according to the embodiment may be positioned on the entire first light-emitting layer EL1 and may also be deposited on the material forming the first light-emitting layer EL1 in a portion overlapping with the residual pattern AEP. The material forming the first cathode electrode CE1 positioned on the residual pattern AEP and the material forming the first cathode electrode CE1 positioned on the pixel electrode AE may be spaced apart from each other.

[0203] Compared to the deposition process used to form the first light-emitting layer EL1, the deposition process used to form the first cathode electrode CE1 according to the embodiment may be performed at an angle to the upper surface of the pixel electrode AE. To this end, the deposition material used to form the first cathode electrode CE1 may completely cover the material used to form the first light-emitting layer EL1. For example, the step coverage of the deposition process used to form the first cathode electrode CE1 may be higher than the step coverage of the deposition process used to form the first light-emitting layer EL1.

[0204] Subsequently, a first capping layer CCP1 may be formed on the first cathode electrode CE1. The first capping layer CCP1 according to an embodiment may be formed through a sputtering process.

[0205] Since the display panel 410 according to the embodiment may include a dam structure BNS having an undercut, the material forming the first capping layer CCP1 can be formed on the first cathode electrode CE1 without a separate fine metal mask. The material forming the first capping layer CCP1 according to the embodiment may be positioned on the entire first cathode electrode CE1 and may also be deposited on the material forming the first cathode electrode CE1 in a portion overlapping with the residual pattern AEP. The material forming the first capping layer CCP1 positioned on the residual pattern AEP and the material forming the first capping layer CCP1 positioned on the pixel electrode AE may be spaced apart from each other.

[0206] The sputtering deposition process for forming the first capping layer CCP1 according to an embodiment may have a higher step coverage than the thermal evaporation process for forming the first cathode electrode CE1. To this end, the deposition material forming the first capping layer CCP1 may completely cover the material forming the first cathode electrode CE1. The deposition material forming the first capping layer CCP1 may also cover a portion of the pixel defining layer PDL.

[0207] Through this process, it is possible to form Figure 6 The first light emitting element ED1 is shown in FIG.

[0208] Next, a photoresist pattern PR may be formed on the first capping layer CCP1 in a portion overlapping the first light emitting element ED1 , and a third etching process (third etching) may be performed using the photoresist pattern PR as a mask.

[0209] In this process, the material forming the first light-emitting layer EL1, the material forming the first cathode electrode CE1, and the material forming the first capping layer CCP1 may be removed in a portion where the photoresist pattern PR may not be formed, and the pixel defining layer PDL and the pixel electrode AE that do not overlap with the first light-emitting element ED1 may be exposed.

[0210] Next, refer to Figure 18 , a first inorganic material layer IL1L may be formed on the first light-emitting element ED1. The first inorganic material layer IL1L may be formed by a chemical vapor deposition process (PECVD). The first inorganic material layer IL1L may be formed on the entire surface so as to overlap not only the first light-emitting element ED1 but also the residual pattern AEP. Subsequently, a photoresist pattern PR may be formed on the first inorganic material layer IL1L in the portion overlapping the first light-emitting element ED1, and then a fourth etching process (fourth etching) may be performed using the photoresist pattern PR as a mask. In this process, a portion of the first inorganic material layer IL1L where the photoresist pattern PR may not be formed may be removed.

[0211] like Figure 19As shown in FIG, the first inorganic material layer IL1L may completely cover the first light emitting element ED1 and the bank structure BNS, and may also cover the undercut portion of the bank structure BNS. The pixel defining layer PDL and the pixel electrode AE overlapping the portion where the first inorganic material layer IL1L is not formed may be exposed.

[0212] refer to Figures 20 to 22 The above-described process may be repeated to form a second light-emitting element ED2 and a second inorganic material layer IL2L covering the second light-emitting element ED2, and then to form a third light-emitting element ED3 and a third inorganic material layer IL3L covering the third light-emitting element ED3. Each of the first inorganic material layer IL1L, the second inorganic material layer IL2L, and the third inorganic material layer IL3L may be spaced apart in the first direction X, and the pixel defining layer PDL positioned between the first inorganic material layer IL1L, the second inorganic material layer IL2L, and the third inorganic material layer IL3L spaced apart from each other may be exposed.

[0213] Next, an organic material layer OLL may be formed on the inorganic material layer ILL. The organic material layer OLL may be formed on the entire surface, completely covering the inorganic material layer ILL, and planarizing steps formed by the inorganic material layer ILL.

[0214] Subsequently, a photoresist pattern PR may be formed on the organic material layer OLL in the region overlapping with the residual pattern AEP, and a fifth etching process (fifth etching) may be performed using the plurality of photoresist patterns PR as a mask. For example, the fifth etching process (fifth etching) may be performed as a dry etching process. Since the capping layer CCP according to an embodiment has high etching resistance in a dry etching process, the fifth etching process (fifth etching) may be performed until a portion of the capping layer CCP is exposed.

[0215] Through this process, the organic material layer OLL and the inorganic material layer ILL may be removed in portions where the photoresist pattern PR may not be formed to produce Figure 6 The inorganic layer IL and the organic layer OL are shown in FIG. A portion of the first capping layer CCP1, a portion of the second capping layer CCP2, and a portion of the third capping layer CCP3 can be exposed by this process. In other words, the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 can be positioned to surround the edge of each of the first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3, respectively, and the organic layer OL can also be positioned to surround the edge of the first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3.

[0216] Finally, if Figure 23As shown in FIG, a connection electrode CTCE may be deposited on the capping layer CCP, the inorganic layer IL, and the organic layer OL to form Figure 6 The light emitting element layer EML shown in FIG.

[0217] The connection electrode CTCE may be formed by a sputtering deposition process and may be completely formed on the capping layer CCP, the inorganic layer IL, and the organic layer OL. The connection electrode CTCE may contact the capping layer CCP, the inorganic layer IL, and the organic layer OL, and the first capping layer CCP1, the second capping layer CCP2, and the third capping layer CCP3 may be electrically connected via the connection electrode CTCE.

[0218] As a result, the display panel 410 according to the embodiment may include a bank structure BNS having an undercut below the light-emitting element ED, thereby allowing the formation of multiple pixel electrodes AE without a separate etching process. By including an organic layer OL that flattens the steps formed between the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3, the connection electrode CTCE can be formed without disconnection defects. Therefore, the first cathode electrode CE1, the second cathode electrode CE2, and the third cathode electrode CE3 included in the embodiment can be electrically connected via the connection electrode CTCE.

[0219] Embodiments have been disclosed herein, and although terms may be used, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. Display devices, including: a substrate including an emitting region and a non-emitting region; a dam structure positioned in the emission region of the substrate and having an undercut shape; a pixel electrode positioned on the bank structure; a first light-emitting layer, positioned on the pixel electrode; a first cathode electrode positioned on the first light-emitting layer; a first capping layer positioned on the first cathode electrode; a connecting electrode positioned on the first capping layer; a pixel defining layer positioned in the non-emitting region of the substrate and defining a first opening; an inorganic layer positioned on the pixel defining layer and defining a second opening; as well as An organic layer is positioned on the inorganic layer.

2. The display device according to claim 1, wherein The embankment structure includes: a first bank layer; and The second bank layer is positioned on the first bank layer and includes a tip that protrudes more toward the non-emission region than a side surface of the first bank layer.

3. The display device according to claim 2, wherein The first bank layer and the second bank layer include different inorganic insulating materials.

4. The display device according to claim 3, wherein A height of the first bank layer in a direction perpendicular to the substrate is greater than a height of the second bank layer in the direction perpendicular to the substrate.

5. The display device according to claim 3, wherein The side surface of the first bank layer is completely covered by the pixel defining layer. The display device according to claim 3 , wherein: The second bank layer includes a first surface facing the pixel electrode, a second surface facing the first bank layer, and a side surface connecting the first surface and the second surface.

7. The display device according to claim 6, wherein The first surface and the side surface of the second bank layer are in contact with the pixel electrode, and The second surface contacts the pixel defining layer.

8. The display device according to claim 1, further comprising: a residual pattern positioned in the non-emitting region of the substrate, wherein The residual pattern and the pixel electrode include the same material, and The residual pattern is spaced apart from the pixel electrode.

9. The display device according to claim 8, in, The pixel defining layer completely covers the residual pattern.

10. The display device according to claim 1, further comprising: a second light-emitting layer, spaced apart from the first light-emitting layer in a direction parallel to the substrate, and the organic layer is disposed between the first light-emitting layer and the second light-emitting layer; a second cathode electrode positioned on the second light-emitting layer; as well as a second capping layer positioned on the second cathode electrode, The first cathode electrode and the second cathode electrode are spaced apart from each other, and the first capping layer and the second capping layer are spaced apart from each other.

11. The display device according to claim 10, wherein The first capping layer is electrically connected to the first cathode electrode, and The second capping layer is electrically connected to the second cathode electrode.

12. The display device according to claim 11, wherein The connecting electrode comprises: a first portion in contact with the first capping layer; a second portion in contact with the second capping layer; and The third part contacts the organic layer.

13. The display device according to claim 12, wherein The first portion and the second portion are spaced apart from each other, and the third portion is disposed between the first portion and the second portion.

14. The display device according to claim 10, wherein The inorganic layer comprises: a first inorganic layer surrounding an edge of the first capping layer; and a second inorganic layer surrounding the edge of the second capping layer, The first inorganic layer and the second inorganic layer are spaced apart from each other, and the organic layer is disposed between the first inorganic layer and the second inorganic layer.

15. The display device according to claim 1, wherein In a plan view, the first opening is completely surrounded by the second opening.

16. A method for manufacturing a display device, the method comprising: forming a first bank layer on a substrate and forming a second bank layer on the first bank layer; etching a portion of the first bank layer and a portion of the second bank layer so that the second bank layer includes a tip that protrudes more than a side surface of the first bank layer; forming a pixel electrode on the second bank layer and forming a residual pattern on the substrate; forming a pixel defining layer surrounding an edge of the pixel electrode and covering the residual pattern; forming a light-emitting layer, a cathode electrode and a capping layer on the pixel electrode; as well as A connecting electrode is formed on the capping layer.

17. The method according to claim 16, wherein Forming the pixel electrode does not include a separate etching process because the second bank layer includes the tip.

18. The method according to claim 17, wherein: When the cathode electrode and the capping layer are formed, the cathode electrode completely covers the light emitting layer, and the capping layer completely covers the cathode electrode.

19. The method according to claim 18, further comprising: After forming the capping layer and before forming the connecting electrode, an inorganic layer and an organic layer are formed, When the inorganic layer is formed, the inorganic layer surrounds an edge of the capping layer and covers a portion of the residual pattern.

20. The method according to claim 19, wherein When forming the connection electrode, the connection electrode extends to the capping layer, the inorganic layer, and the organic layer, and The cathode electrode is electrically connected to the connection electrode through the capping layer.

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