Display device

Abstract

The display device includes a display panel including a circuit layer and a light emitting element layer. The circuit layer comprises a transistor; a connection electrode electrically connecting the transistor and the light emitting element layer; a data line; and an insulating layer provided with a contact hole limited to pass through the insulating layer. The light emitting element layer includes: a first electrode electrically connected to the connection electrode through the contact hole; a light emitting layer disposed on the first electrode; and a second electrode disposed on the light emitting layer. The first electrode includes a first portion, a second portion extending from the first portion in a first direction, a third portion extending from the first portion in the first direction, and a fourth portion protruding from one of the first portion, the second portion, and the third portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2024-0018197, filed on February 6, 2024, and Korean Patent Application No. 10-2024-0145231, filed on October 22, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device with improved display quality. Background Art

[0004] Various display devices applied to multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game devices are being developed.

[0005] As the fields of application for these display devices have diversified, the types of display panels used to display images on these display devices have also diversified.

[0006] The display panel includes a light-emitting display panel, and the light-emitting display panel includes an organic light-emitting display panel or a quantum dot light-emitting display panel. Summary of the Invention

[0007] The present disclosure provides a display device with improved display quality.

[0008] An embodiment of the present inventive concept provides a display device comprising a display panel including a base layer, a circuit layer, and a light-emitting element layer disposed on the circuit layer. The circuit layer includes: a transistor disposed on the base layer; a connecting electrode electrically connecting the transistor and the light-emitting element layer; a data line disposed on the transistor; and an insulating layer disposed on the connecting electrode and provided with a contact hole defined as passing through the insulating layer. The light-emitting element layer includes: a first electrode disposed on the insulating layer and electrically connected to the connecting electrode through the contact hole; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer. The first electrode includes a first portion, a second portion extending from the first portion in a first direction, a third portion extending from the first portion in the first direction, and a fourth portion protruding from one of the first portion, the second portion, and the third portion. The second portion and the third portion are spaced apart from each other in the second direction and face each other.

[0009] In an embodiment, the first portion, the second portion, the third portion and the fourth portion are provided integrally with each other.

[0010] In an embodiment, the data line is disposed between the second portion and the third portion and does not overlap with the second portion and the third portion in a plan view.

[0011] In an embodiment, the contact hole overlaps with the fourth portion in a plan view.

[0012] In an embodiment, the light emitting layer does not overlap with the contact hole in a plan view.

[0013] In an embodiment, the data line overlaps only the first portion in a plan view.

[0014] In an embodiment, the data line is provided in the same layer as the connection electrode.

[0015] In an embodiment, the light emitting layer includes a first light emitting portion having a shape corresponding to that of the first portion, a second light emitting portion having a shape corresponding to that of the second portion, and a third light emitting portion having a shape corresponding to that of the third portion.

[0016] In an embodiment, the first light emitting portion, the second light emitting portion, and the third light emitting portion are provided integrally with each other.

[0017] In an embodiment, the light emitting layer emits blue light.

[0018] An embodiment of the present inventive concept provides a display device comprising a display panel including a circuit layer and a light-emitting element layer disposed on the circuit layer. The circuit layer comprises: a transistor; a connecting electrode electrically connecting the transistor and the light-emitting element layer; and an insulating layer disposed on the connecting electrode and provided with a contact hole defined as passing through the insulating layer. The light-emitting element layer comprises a first electrode disposed on the insulating layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer. The light-emitting layer comprises a first light-emitting portion and a second light-emitting portion spaced apart from the first light-emitting portion by a first width, and the first electrode comprises a first portion, a second portion spaced apart from the first portion by a second width smaller than the first width, a connecting portion electrically connecting the first portion and the second portion, and a protruding portion protruding from one of the first portion, the second portion, and the connecting portion.

[0019] In an embodiment, the first electrode further includes a third portion spaced apart from the second portion in the first direction, and the second portion is spaced apart from the first portion in the first direction.

[0020] In an embodiment, the first portion, the second portion, the third portion, the connecting portion, and the protruding portion are provided integrally with one another.

[0021] In an embodiment, the light emitting layer emits blue light.

[0022] In an embodiment, the contact hole overlaps with the protruding portion in a plan view.

[0023] In an embodiment, the light emitting layer does not overlap with the contact hole in a plan view.

[0024] In an embodiment, the light emitting layer further includes a third light emitting portion spaced apart from the second light emitting portion by a first width.

[0025] An embodiment of the present inventive concept provides a display device comprising a display panel including a circuit layer and a light-emitting element layer disposed on the circuit layer. The circuit layer comprises: a transistor; a connecting electrode electrically connecting the transistor and the light-emitting element layer; and an insulating layer disposed on the connecting electrode and provided with a contact hole defined as passing through the insulating layer. The light-emitting element layer comprises a first electrode disposed on the insulating layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer. The light-emitting layer comprises a first light-emitting portion and a second light-emitting portion spaced apart from the first light-emitting portion by a first width, and the first electrode comprises a first portion, a second portion spaced apart from the first portion by a second width smaller than the first width, and a connecting portion electrically connecting the first portion and the second portion.

[0026] In an embodiment, the first electrode further includes a third portion spaced apart from the second portion in the first direction, and the second portion is spaced apart from the first portion in the first direction.

[0027] In an embodiment, the first portion, the second portion, the third portion and the connecting portion are provided integrally with each other.

[0028] In an embodiment, the contact hole overlaps with the connection portion in a plan view.

[0029] In an embodiment, the first electrode further includes a third portion spaced apart from the first portion in the first direction and a fourth portion spaced apart from the second portion in the first direction, and the second portion is spaced apart from the first portion in a second direction intersecting the first direction.

[0030] In an embodiment, the first portion, the second portion, the third portion, the fourth portion, and the connecting portion are provided integrally with one another.

[0031] In an embodiment, the light emitting layer does not overlap with the contact hole in a plan view.

[0032] In an embodiment, the contact hole overlaps the second portion and does not overlap the first portion in a plan view.

[0033] According to the above, the third data line is disposed between the second and third portions of the first electrode. Since the third data line does not overlap with the second and third portions in plan view, the parasitic capacitance generated between the third data line and the second and third portions is reduced. Therefore, an increase in the load of the data signal applied to the third data line due to the parasitic capacitance is prevented, and insufficient charging of the third data line is prevented. As a result, the reliability of the display device is improved.

[0034] According to the above, since there is a gap between the second portion and the third portion, exhaust gas generated during the process is smoothly discharged. As a result, pixel shrinkage is reduced and the lifespan of the third light-emitting layer is increased. As a result, the reliability of the display device is improved.

[0035] As described above, the third light-emitting layer does not overlap with the third contact hole in a plan view. Therefore, when defining the third contact hole, the insulating layer disposed below the third light-emitting layer is stacked flatly. As a result, the light reflectivity of the third light-emitting layer remains constant, preventing color deviation. Consequently, the display quality of the display device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other advantages of the present disclosure will become apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a perspective view of an embodiment of a display device according to the present disclosure;

[0038] Figure 2 is an exploded perspective view of an embodiment of a display device according to the present disclosure;

[0039] Figure 3 is a block diagram of an embodiment of a display device according to the present disclosure;

[0040] Figure 4 is a cross-sectional view of an embodiment of a display device according to the present disclosure;

[0041] Figure 5 is an equivalent circuit diagram of an embodiment of a pixel according to the present disclosure;

[0042] Figure 6 is a plan view of a portion of an embodiment of a display device according to the present disclosure;

[0043] Figure 7 According to the present disclosure Figure 6 A sectional view taken along line II';

[0044] Figure 8 is a plan view of a portion of an embodiment of a display device according to the present disclosure;

[0045] Figure 9 is a plan view of a portion of an embodiment of a display device according to the present disclosure;

[0046] Figure 10 is a plan view of an embodiment of a portion of a display device according to the present disclosure; and

[0047] Figure 11is a plan view of a portion of an embodiment of a display device according to the present disclosure. DETAILED DESCRIPTION

[0048] In this disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0049] Like reference numerals always represent like elements. In the accompanying drawings, the thickness, ratio and size of the components are exaggerated to effectively describe the technical content. As used herein, the term "and / or" can include any and all combinations of one or more of the related listed items.

[0050] It will be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "an", and "the" are intended to also include plural forms.

[0051] For ease of description, spatially relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings.

[0052] It will also be understood that the terms “include” and / or “including” when used in this specification specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0053] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view of an embodiment of a display device according to the present disclosure, and Figure 2 is an exploded perspective view of an embodiment of a display device according to the present disclosure.

[0057] refer to Figure 1 and Figure 2 The display device DD may be a device that is activated in response to an electrical signal. The display device DD may be applied to large-scale display devices such as televisions or monitors, or to relatively small and medium-sized display devices such as mobile phones, tablet computers, notebook computers, car navigation units, gaming units, and the like. However, these are merely illustrative embodiments, and the display device DD may be applied to other display devices as long as they do not deviate from the concepts of the present disclosure. The display device DD may have a quadrilateral shape in plan view, for example, a rectangular shape defined by long sides extending in a first direction DR1 and short sides extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD should not be limited to a quadrilateral shape (e.g., a rectangular shape), and the display device DD may have a variety of shapes. The display device DD may display an image IM toward a third direction DR3 via a display surface IS that is substantially parallel to each of the first direction DR1 and the second direction DR2. The display surface IS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0058] In the illustrated embodiment, the front (or upper) surface and the rear (or lower) surface of each member can be defined relative to the direction in which the image IM is displayed. The front surface and the rear surface can be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be substantially parallel to the third direction DR3.

[0059] The spacing distance between the front and rear surfaces in the third direction DR3 may correspond to the thickness of the display device DD in the third direction DR3. Directions indicated by the first, second, and third directions DR1, DR2, and DR3 may be opposite to each other and may be changed to other directions.

[0060] The display device DD can sense external input applied to it from the outside. The external input may include various forms of input provided from the outside of the display device DD. The display device DD can sense external input generated by the user and applied to the display device DD. The user's external input may include one of various forms of external input, such as a part of the user's body, light, heat, gaze or pressure, or any combination thereof. In addition, the display device DD can sense external input applied by the user to the side surface or rear surface of the display device DD according to the structure of the display device DD, however, it should not be limited to this or thereby. In an embodiment, the external input may include input generated by an input device (e.g., a stylus, an active pen, a touch pen, an electronic pen, an e-pen, etc.).

[0061] The display surface IS of the display device DD may include a display area DA and a non-display area NDA. The display area DA may be an area in which an image IM is displayed. A user may view the image IM through the display area DA. In the illustrated embodiment, the display area DA may have a quadrilateral shape with rounded vertices in plan view; however, this is merely one embodiment. The display area DA may have various shapes and is not particularly limited.

[0062] The non-display area NDA may be defined as being adjacent to (adjacent to) the display area DA. The non-display area NDA may have a predetermined color. The non-display area NDA may surround the display area DA. Thus, the display area DA may have a shape substantially defined by the non-display area NDA, however, this is only one embodiment. In an embodiment, the non-display area NDA may be provided to be adjacent to (adjacent to) only one side of the display area DA, or may be omitted. The display device DD may include various embodiments and should not be particularly limited.

[0063] refer to Figure 2 The display device DD may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0064] The display panel DP may be a light-emitting display panel. In embodiments, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots or quantum rods.

[0065] The display panel DP may output an image IM, and the output image IM may be displayed through the display surface IS.

[0066] The input sensing layer ISP may be disposed on the display panel DP and may sense external input. The input sensing layer ISP may be disposed directly on the display panel DP. In the illustrated embodiment, the input sensing layer ISP may be formed on the display panel DP through a continuous process. That is, when the input sensing layer ISP is disposed directly on the display panel DP, an internal adhesive film may not be disposed between the input sensing layer ISP and the display panel DP. However, in an embodiment, an internal adhesive film may be disposed between the input sensing layer ISP and the display panel DP. In this case, the input sensing layer ISP may not be manufactured through a process continuous with the display panel DP, and the input sensing layer ISP may be fixed to the upper surface of the display panel DP through the internal adhesive film after being manufactured through a separate process.

[0067] The window WM may include a transparent material through which the image IM is transmitted. In an embodiment, the window WM may include, for example, glass, sapphire, or plastic. The window WM is shown as a single layer, however, it should not be limited to this or thereby. The window WM may include multiple layers.

[0068] Although not shown in the drawings, the non-display area NDA of the display device DD can be obtained by printing a material having a predetermined color in the area of the window WM. In an embodiment, the window WM may include a light-blocking pattern to define the non-display area NDA. The light-blocking pattern may be a colored organic layer and may be formed by a coating method.

[0069] The window WM may be coupled to the display module DM via an adhesive film. In an embodiment, the adhesive film may include an optically clear adhesive film ("OCA"). However, the adhesive film should not be limited thereto or thereby, and the adhesive film may include a conventional adhesive. In an embodiment, the adhesive film may include, for example, an optically clear resin ("OCR") or a pressure-sensitive adhesive film ("PSA").

[0070] An anti-reflection layer may also be provided between the window WM and the display module DM. The anti-reflection layer can reduce the reflectivity of external light incident on the window WM from above. The anti-reflection layer according to the present disclosure may include a retarder and a polarizer. The retarder may be a thin film type or a liquid crystal coating type. The polarizer may also be a thin film type or a liquid crystal coating type. The thin film polarizer and thin film retarder may include a stretched synthetic resin film, and the liquid crystal coating polarizer and liquid crystal coating retarder may include liquid crystals arranged in a predetermined pattern. The retarder and polarizer may be implemented as a single polarizing film.

[0071] In an embodiment, the anti-reflection layer may include a color filter. The arrangement of the color filter may be considered by considering the pixels PX (refer to Figure 3) is determined by the color of the light generated. In this case, the anti-reflection layer may further include a light blocking pattern disposed between the color filters.

[0072] The display module DM can display an image IM in response to an electrical signal and can transmit / receive information regarding external input. The display module DM may include an active area AA and a non-active area NAA defined therein. The active area AA may be defined as the area through which the image IM provided by the display panel DP is emitted, i.e., the area through which the image IM is displayed. Furthermore, the active area AA may be defined as the area in which the input sensing layer ISP senses external input applied thereto. In embodiments, the active area AA of the display module DM may correspond to or overlap at least a portion of the display area DA.

[0073] The non-active area NAA can be defined as being adjacent to (adjacent to) the active area AA. The non-active area NAA can be an area in which the image IM is not displayed. In an embodiment, for example, the non-active area NAA can surround the active area AA. However, this is only one embodiment, and the non-active area NAA can be defined in various shapes and should not be particularly limited. According to an embodiment, the non-active area NAA of the display module DM can correspond to or overlap at least a portion of the non-display area NDA.

[0074] The display device DD may further include a plurality of flexible films FF. The driving chip DC may be provided (eg, mounted) on each of the flexible films FF. In an embodiment, the driving chip DC may be provided in plurality, and the data driver DIC (refer to FIG. Figure 3 ) can be implemented by a driving chip DC, and the driving chip DC can be respectively provided (for example, mounted) on the flexible film FF.

[0075] The display device DD may further include at least one circuit board PCB coupled with the flexible film FF. Figure 2 The structure in which the display device DD includes two circuit boards PCB is shown, however, the number of circuit boards PCB should not be limited to two. Among the circuit boards PCB, two circuit boards PCB adjacent to each other can be electrically connected to each other through a connection film CF. In addition, at least one of the circuit boards PCB can be electrically connected to the main board. The timing controller TCON (refer to Figure 3 ) can be set (e.g., mounted) on at least one of the circuit boards PCB.

[0076] Figure 2A structure in which the driver chip DC is separately provided (e.g., mounted) on the flexible film FF is shown, however, the present disclosure should not be limited thereto or thereby. In an embodiment, the driver chip DC may be directly provided (e.g., mounted) on the display panel DP. In this case, the portion of the display panel DP on which the driver chip DC is provided (e.g., mounted) may be curved and may be provided on the rear surface of the display device DD.

[0077] The input sensing layer ISP may be electrically connected to the circuit board PCB via the flexible film FF, however, the present disclosure should not be limited thereto or thereby. That is, the display module DM may further include a separate flexible film to electrically connect the input sensing layer ISP to the circuit board PCB.

[0078] The display device DD may also include a housing HOU that houses the display module DM. A window WM may be coupled to the housing HOU to define the appearance of the display device DD. The housing HOU can absorb external impact and prevent foreign matter and moisture from entering the display module DM, thereby protecting the components housed within the housing HOU. In embodiments, the housing HOU may be formed by assembling multiple housing members.

[0079] The display device DD may further include an electronic module, a power module, and a bracket, wherein the electronic module includes various functional modules to operate the display module DM, the power module (e.g., a battery) supplies the power required for the overall operation of the display device DD, and the bracket is connected to the display module DM and / or the housing HOU to divide the internal space of the display device DD.

[0080] Figure 3 is a block diagram of an embodiment of a display device according to the present disclosure.

[0081] refer to Figure 3 , the display device DD may include a display panel DP, a timing controller TCON, a data driver DIC, and a voltage generator VGR.

[0082] The timing controller TCON may receive input data RGB and a control signal D-CS from an external controller (not shown). In an embodiment, the external controller (not shown) may be a graphics processing unit ("GPU"). The control signal D-CS may include various signals. In an embodiment, the control signal D-CS may include an input vertical synchronization signal, an input horizontal synchronization signal, a master clock signal, and a data enable signal.

[0083] The timing controller TCON may convert the data format of the input data RGB into a data format suitable for an interface between the data driver DIC and the timing controller TCON, and may generate the image data DS.

[0084] The timing controller TCON may generate a scan control signal SCS, a data control signal DCS, a light emitting control signal ECS, and a voltage control signal VCS based on the control signal D-CS.

[0085] The data driver DIC can output grayscale voltages in response to a data control signal DCS and image data DS from a timing controller TCON to drive a plurality of data lines DL1 to DLm, where m is a natural number greater than 1. The data driver DIC can be implemented as an integrated circuit and can be directly provided (e.g., mounted) on a predetermined portion of the display panel DP, or can be provided (e.g., mounted) on a separate printed circuit board using a chip-on-film method and then electrically connected to the display panel DP, but this should not be particularly limited. In an embodiment, the data driver DIC can be formed using the same process as the circuit layer of the display panel DP.

[0086] The display panel DP may include a display area DA and a non-display area NDA. Pixels PX may be arranged in the display area DA, and a scan driver SDC and a light emitting driver EDC may be provided in the non-display area NDA.

[0087] The display panel DP may include a plurality of scan lines SL1 to SLn (where n is a natural number greater than 1), data lines DL1 to DLm, a plurality of emission control lines EML1 to EMLn, pixels PX, a scan driver SDC, and an emission driver EDC. Each of the pixels PX may be connected to a corresponding data line among the data lines DL1 to DLm and a corresponding scan line among the scan lines SL1 to SLn. The scan lines SL1 to SLn may include a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines. The scan lines SL1 to SLn will be referred to as Figure 5 Each of the pixels PX may be connected to a corresponding light emitting control line among the light emitting control lines EML1 to EMLn.

[0088] The scan driver SDC may be disposed at a first side of the display panel DP. The scan lines SL1 to SLn may extend from the scan driver SDC toward a first direction DR1.

[0089] The light emitting driver EDC may be disposed at the second side of the display panel DP. The light emitting control lines EML1 to EMLn may extend from the light emitting driver EDC in a direction opposite to the first direction DR1.

[0090] The scan lines SL1 to SLn may be arranged to be spaced apart from each other in the second direction DR2 , and the light emission control lines EML1 to EMLn may be arranged to be spaced apart from each other in the second direction DR2 .

[0091] The data lines DL1 to DLm may extend from the data driver DIC in a direction opposite to the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1 .

[0092] like Figure 3 As shown in FIG, the scanning driver SDC and the light emitting driver EDC may be arranged to face each other with the pixel PX interposed therebetween, however, the present disclosure should not be limited thereto or thereby. In an embodiment, the scanning driver SDC and the light emitting driver EDC may be disposed adjacent to (beside) each other at a first side or a second side of the display panel DP. In an embodiment, the scanning driver SDC and the light emitting driver EDC may be implemented as a single circuit.

[0093] The pixels PX may be electrically connected to the scan lines SL1 to SLn, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm.

[0094] Each of the pixels PX may receive a driving voltage ELVDD, a power voltage ELVSS, an initialization voltage VINT, an anode initialization voltage VAINT, and a bias voltage Vbias from a voltage generator VGR.

[0095] The scan driver SDC may receive a scan control signal SCS from the timing controller TCON. The scan driver SDC may output a scan signal to the scan lines SL1 to SLn in response to the scan control signal SCS.

[0096] The light emitting driver EDC may receive a light emitting control signal ECS from the timing controller TCON and may output a light emitting signal to the light emitting control lines EML1 to EMLn in response to the light emitting control signal ECS.

[0097] The voltage generator VGR may receive a voltage control signal VCS from the timing controller TCON. The voltage generator VGR may generate voltages required for the operation of the display panel DP in response to the voltage control signal VCS. In the illustrated embodiment, the voltage generator VGR may generate a driving voltage ELVDD, a power voltage ELVSS, an initialization voltage VINT, an anode initialization voltage VAINT, and a bias voltage Vbias.

[0098] Figure 4 is a cross-sectional view of an embodiment of a display device according to the present disclosure.

[0099] refer to Figure 4 The display device DD may include a display panel DP and an input sensing layer ISP. The display panel DP may include a base layer 110 , a circuit layer 120 , a light emitting element layer 130 , and an encapsulation layer 140 .

[0100] The base layer 110 may provide a base surface on which the circuit layer 120 is disposed. The base layer 110 may be a glass substrate, a metal substrate, or a polymer substrate. However, the present disclosure should not be limited thereto or thereby, and in an embodiment, the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer.

[0101] The base layer 110 may have a multi-layer structure. In an embodiment, the base layer 110 may include, for example, a first synthetic resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may also be referred to as a base barrier layer.

[0102] Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin. Furthermore, each of the first synthetic resin layer and the second synthetic resin layer may include at least one of an acrylic acid-based resin, a methacrylic acid-based resin, a polyisoprene-based resin, an ethylene-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In the present disclosure, as used herein, the term "X-based resin" refers to a resin including a functional group of X.

[0103] The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and signal lines. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 through a coating process or a deposition process. The insulating layer, the semiconductor layer, and the conductive layer may then be selectively patterned through various photolithography processes. The semiconductor pattern, the conductive pattern, and the signal lines included in the circuit layer 120 may be formed.

[0104] The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element. In an embodiment, the light emitting element layer 130 may include, for example, an organic light emitting material, quantum dots, quantum rods, micro light emitting diodes ("micro-LEDs"), or nano-LEDs.

[0105] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from moisture, oxygen, and foreign substances such as dust particles.

[0106] The input sensing layer ISP can be formed on the display panel DP through a continuous process. In this case, the input sensing layer ISP can be directly disposed on the display panel DP. In the following description, the phrase "the input sensing layer ISP is directly disposed on the display panel DP" means that there are no intervening elements between the input sensing layer ISP and the display panel DP. In other words, a separate adhesive member can be disposed between the input sensing layer ISP and the display panel DP. In an alternative embodiment, the input sensing layer ISP can be coupled to the display panel DP via an adhesive member. The adhesive member can be a conventional adhesive.

[0107] Figure 5 is an equivalent circuit diagram of an embodiment of a pixel according to the present disclosure.

[0108] Pixel PX (reference Figure 3 ) can include at least one sub-pixel PXSij. Figure 5 An equivalent circuit diagram of a subpixel PXSij connected to an i-th data line DLi among the data lines DL1 to DLm, a j-th scan line SLj among the scan lines SL1 to SLn, and a j-th emission control line EMLj among the emission control lines EML1 to EMLn is shown.

[0109] refer to Figure 4 and Figure 5 The sub-pixel PXSij may include a pixel circuit PXC and at least one light emitting element ED. The pixel circuit PXC may be provided in the circuit layer 120, and the light emitting element ED may be provided in the light emitting element layer 130. The pixel circuit PXC may control emission of the light emitting element ED.

[0110] The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor Cst, and a second capacitor Cse. The light-emitting element ED may be a light-emitting diode. In the illustrated embodiment, a structure in which one subpixel PXSij includes one light-emitting element ED will be described as an illustrative embodiment.

[0111] The first transistor T1 to the eighth transistor T8 may be N-type transistors each including an oxide semiconductor as its semiconductor layer, however, the present disclosure should not be limited thereto or thereby. In an embodiment, the first transistor T1 to the eighth transistor T8 may be P-type transistors each including a low temperature polysilicon ("LTPS") semiconductor layer. In an embodiment, at least one of the first transistor T1 to the eighth transistor T8 may be an N-type transistor, and the remaining one (another) transistor or the remaining some (other) transistors of the first transistor T1 to the eighth transistor T8 may be P-type transistors. In addition, the configuration of the pixel circuit PXC according to the present disclosure should not be limited to Figure 5 The configuration shown in . Figure 5 The pixel circuit PXC shown in FIG. 1 is only one of the embodiments, and the configuration of the pixel circuit PXC may be changed.

[0112] The scan lines SLj may include a first scan line GILj, a second scan line GCLj, a third scan line GWLj, and a fourth scan line GBLj. The first scan line GILj, the second scan line GCLj, the third scan line GWLj, and the fourth scan line GBLj may transmit a first scan signal GIj, a second scan signal GCj, a third scan signal GWj, and a fourth scan signal GBj, respectively. The emission control line EMLj may transmit an emission control signal EMj. The data line DLi may transmit a data signal Di.

[0113] The data signal Di may have the same value as that input to the display panel DP (reference Figure 3 ) in the input data RGB (reference Figure 3 ) corresponding voltage level. The first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the fourth voltage line VL4 and the fifth voltage line VL5 can respectively transmit the driving voltage ELVDD, the power voltage ELVSS, the initialization voltage VINT, the anode initialization voltage VAINT and the bias voltage Vbias.

[0114] The first transistor T1 may include a first electrode connected to the first voltage line VL1 via the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED via the sixth transistor T6, and a gate electrode connected to one end of the first capacitor Cst. The first transistor T1 may receive a data signal Di transmitted by the data line DLi in response to a switching operation of the second transistor T2 and may provide a driving current Ied to the light emitting element ED.

[0115] The second transistor T2 may include a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the third scan line GWLj. The second transistor T2 may be turned on in response to a third scan signal GWj applied thereto via the third scan line GWLj and may transmit a data signal Di applied thereto via the data line DLi to the first electrode of the first transistor T1.

[0116] The third transistor T3 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line GCLj. The third transistor T3 may be turned on in response to a second scan signal GCj applied thereto via the second scan line GCLj, and may connect the gate electrode and the second electrode of the first transistor T1 to each other to allow the first transistor T1 to be connected in a diode configuration. The third transistor T3 may be implemented as a dual transistor.

[0117] The fourth transistor T4 may include a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to a third voltage line VL3 through which an initialization voltage VINT is transmitted, and a gate electrode connected to a first scan line GILj. The fourth transistor T4 may be turned on in response to a first scan signal GIj applied thereto via the first scan line GILj. The turned-on fourth transistor T4 may transmit the initialization voltage VINT to the gate electrode of the first transistor T1 to initialize the voltage of the gate electrode of the first transistor T1. The fourth transistor T4 may be implemented as a dual transistor.

[0118] The fifth transistor T5 may include a first electrode connected to the first voltage line VL1 , a second electrode connected to the first electrode of the first transistor T1 , and a gate electrode connected to the light emitting control line EMLj.

[0119] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1 , a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the light emitting control line EMLj.

[0120] The fifth transistor T5 and the sixth transistor T6 may be turned on substantially simultaneously in response to the emission control signal EMj applied thereto via the emission control line EMLj, and thus the driving voltage ELVDD may be compensated by the first transistor T1 connected in a diode configuration and may be transmitted to the light emitting element ED.

[0121] The seventh transistor T7 may include a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the fourth voltage line VL4, and a gate electrode connected to the fourth scan line GBLj. The seventh transistor T7 may be turned on in response to the fourth scan signal GBj applied thereto via the fourth scan line GBLj and may bypass current of the anode of the light emitting element ED to the fourth voltage line VL4.

[0122] The eighth transistor T8 may include a first electrode connected to the first electrode of the first transistor T1, a second electrode connected to the fifth voltage line VL5, and a gate electrode connected to the fourth scan line GBLj. The eighth transistor T8 may be turned on in response to the fourth scan signal GBj applied thereto via the fourth scan line GBLj and may transmit the bias voltage Vbias to the first electrode of the first transistor T1.

[0123] One end of the first capacitor Cst may be connected to the gate electrode of the first transistor T1, and an opposite end of the first capacitor Cst may be connected to the first voltage line VL1. The cathode of the light-emitting element ED may be connected to the second voltage line VL2 transmitting the power supply voltage ELVSS. One end of the second capacitor Cse may be connected to the first electrode of the first transistor T1, and an opposite end of the second capacitor Cse may be connected to the first voltage line VL1.

[0124] The structure of the sub-pixel PXSij should not be limited to Figure 5 The structure shown in , and the number of transistors and the number of capacitors included in one sub-pixel PXSij and their connection relationship can be changed in various ways.

[0125] Figure 6 is a plan view of a portion of an embodiment of a display device according to the present disclosure.

[0126] Figure 6 The first subpixel PXR, the second subpixel PXG, and the third subpixel PXB shown in FIG. 4 may have substantially the same Figure 5 The equivalent circuit of the sub-pixel PXSij shown in FIG.

[0127] refer to Figures 4 to 6 , the display panel DP may include pixels PX and data lines DL. Figure 6 Four pixels among the pixels PX are shown. The data lines DL may include a first data line DL1, a second data line DL2, and a third data line DL3.

[0128] The pixels PX may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. The second pixel PX2 may be spaced apart from the first pixel PX1 in a first direction DR1. The third pixel PX3 may be spaced apart from the first pixel PX1 in a direction opposite to the second direction DR2. The fourth pixel PX4 may be spaced apart from the second pixel PX2 in a direction opposite to the second direction DR2. The first to fourth pixels PX1 to PX4 may include the same components, and only the arrangement of the components of the first to fourth pixels PX1 to PX4 may differ from each other.

[0129] The first pixel PX1 may include a first subpixel PXR, a second subpixel PXG, and a third subpixel PXB. Each of the first subpixel PXR, the second subpixel PXG, and the third subpixel PXB may correspond to a subpixel PXSij.

[0130] The second subpixel PXG may be disposed spaced apart from the first subpixel PXR in a direction opposite to the second direction DR2. In this case, the distance between the first subpixel PXR and the second subpixel PXG may also be referred to as a first width WD1. In an embodiment, the first width WD1 may be in a range of approximately 3.50 micrometers (μm) to approximately 6.40 μm. Specifically, the first width WD1 may be approximately 3.89 μm.

[0131] The third subpixel PXB may be disposed to be spaced apart from the first subpixel PXR by a second width WD2 in the first direction DR1. The second width WD2 may be in a range of about 3.0 μm to about 6.0 μm. In an embodiment, the second width WD2 may be about 3.1 μm.

[0132] The third subpixel PXB may be disposed to be spaced apart from the second subpixel PXG by a third width WD3 in the first direction DR1. The third width WD3 may be in a range of about 12.50 μm to about 15.20 μm. In an embodiment, the third width WD3 may be about 12.66 μm.

[0133] The first, second, and third data lines DL1 , DL2 , and DL3 may be arranged in the circuit layer 120 .

[0134] The light emitting element ED of the first subpixel PXR may include a first anode electrode AER and a first light emitting layer ELR. The first anode electrode AER and the first light emitting layer ELR may be provided on the light emitting element layer 130.

[0135] The first anode electrode AER may be electrically connected to the pixel circuit PXC of the first subpixel PXR through the first contact hole CNT1. The first light emitting layer ELR may be disposed on the first anode electrode AER. The first light emitting layer ELR may emit red light.

[0136] In a plan view, the first anode AER may overlap with the first data line DL1, and the first light emitting layer ELR may not overlap with the first data line DL1.

[0137] In a plan view, the first anode AER may cover the first light emitting layer ELR. That is, in a plan view, the first anode AER may have an area larger than that of the first light emitting layer ELR.

[0138] The first anode AER disposed under the first light-emitting layer ELR may have a fourth width WD4 in the first direction DR1. The fourth width WD4 may be in a range of about 28.40 μm to about 31.00 μm. In an embodiment, the fourth width WD4 may be about 30.96 μm. The first anode AER disposed under the first light-emitting layer ELR may have a fifth width WD5 in the second direction DR2. The fifth width WD5 may be in a range of about 34.40 μm to about 36.70 μm. In an embodiment, the fifth width WD5 may be about 36.64 μm.

[0139] The first anode electrode AER disposed on the first contact hole CNT1 may have a sixth width WD6 in the first direction DR1. The sixth width WD6 may be in a range of about 6.7 μm to about 9.5 μm. In an embodiment, the sixth width WD6 may be about 9.2 μm.

[0140] The portion of the first anode electrode AER that connects the portion of the first anode electrode AER disposed on the first contact hole CNT1 and the portion of the first anode electrode AER disposed under the first light emitting layer ELR may have a seventh width WD7. The seventh width WD7 may be in a range of about 3.40 μm to about 6.00 μm. In an embodiment, the seventh width WD7 may be about 5.91 μm.

[0141] The light emitting element ED of the second subpixel PXG may include a second anode electrode AEG and a second light emitting layer ELG. The second anode electrode AEG and the second light emitting layer ELG may be provided on the light emitting element layer 130.

[0142] The second anode electrode AEG may be electrically connected to the pixel circuit PXC of the second sub-pixel PXG through the second contact hole CNT2. The second light emitting layer ELG may be disposed on the second anode electrode AEG. The second light emitting layer ELG may emit green light.

[0143] In a plan view, the second anode electrode AEG may overlap the first data line DL1 , and the second light emitting layer ELG may not overlap the first data line DL1 .

[0144] The second anode electrode AEG may cover the second light emitting layer ELG in a plan view. That is, the second anode electrode AEG may have an area larger than that of the second light emitting layer ELG in a plan view.

[0145] The second anode electrode AEG disposed below the second light-emitting layer ELG may have an eighth width WD8 in the first direction DR1. The eighth width WD8 may be in a range of approximately 28.40 μm to approximately 31.00 μm. In an embodiment, the eighth width WD8 may be approximately 30.96 μm. The second anode electrode AEG disposed below the second light-emitting layer ELG may have a ninth width WD9 in the second direction DR2. The ninth width WD9 may be in a range of approximately 40.30 μm to approximately 42.90 μm. In an embodiment, the ninth width WD9 may be approximately 42.84 μm.

[0146] The second anode electrode AEG disposed on the second contact hole CNT2 may have a tenth width WD10 in the first direction DR1. The tenth width WD10 may be in a range of about 6.6 μm to about 9.3 μm. In an embodiment, the tenth width WD10 may be about 9.2 μm.

[0147] The light emitting element ED of the third subpixel PXB may include a third anode electrode AEB and a third light emitting layer ELB. The third anode electrode AEB and the third light emitting layer ELB may be provided on the light emitting element layer 130.

[0148] The third anode AEB may be electrically connected to the pixel circuit PXC of the third subpixel PXB through the third contact hole CNT3. The third light emitting layer ELB may be disposed on the third anode AEB. The third light emitting layer ELB may emit blue light.

[0149] In a plan view, the third anode AEB may cover the third light emitting layer ELB. That is, in a plan view, the third anode AEB may have an area larger than that of the third light emitting layer ELB.

[0150] The third anode electrode AEB disposed under the third light emitting layer ELB may have an eleventh width WD11 in the second direction DR2. The eleventh width WD11 may be in a range of about 76.90 μm to about 79.50 μm. In an embodiment, the eleventh width WD11 may be about 79.42 μm.

[0151] The third anode AEB may include a first portion AEB1 , a second portion AEB2 , a third portion AEB3 , and a fourth portion AEB4 .

[0152] The first portion AEB1, the second portion AEB2, and the third portion AEB3 may be disposed under the third light emitting layer ELB. That is, in a plan view, the first portion AEB1, the second portion AEB2, and the third portion AEB3 may overlap the third light emitting layer ELB.

[0153] The fourth portion AEB4 may be disposed on the third contact hole CNT3. That is, in a plan view, the fourth portion AEB4 may overlap with the third contact hole CNT3.

[0154] The first portion AEB1 , the second portion AEB2 , the third portion AEB3 , and the fourth portion AEB4 may be provided integrally with one another.

[0155] The first portion AEB1 may have a twelfth width WD12 in the second direction DR2. The twelfth width WD12 may be in a range of about 38.10 μm to about 40.70 μm. In an embodiment, the twelfth width WD12 may be about 40.64 μm.

[0156] The second portion AEB2 may extend from the first portion AEB1 and protrude in a direction parallel to the second direction DR2. The second portion AEB2 may have a thirteenth width WD13 in the first direction DR1. The thirteenth width WD13 may be in a range of about 20.20 μm to about 22.80 μm. In an embodiment, the thirteenth width WD13 may be about 22.71 μm.

[0157] The third portion AEB3 may extend from the first portion AEB1 and protrude in a direction parallel to the second direction DR2. The third portion AEB3 may have a fourteenth width WD14 in the first direction DR1. The fourteenth width WD14 may be in a range of about 20.20 μm to about 22.80 μm. In an embodiment, the fourteenth width WD14 may be about 22.71 μm.

[0158] The second portion AEB2 and the third portion AEB3 may be spaced apart from each other in the first direction DR1 and may face each other. The distance between the second portion AEB2 and the third portion AEB3 may also be referred to as a fifteenth width WD15. The fifteenth width WD15 may be in a range of about 3.0 μm to about 6.0 μm. In an embodiment, the fifteenth width WD15 may be about 3.10 μm.

[0159] In a plan view, the first portion AEB1 may overlap the third data line DL3 , and the second and third portions AEB2 and AEB3 may not overlap the third data line DL3 . The third data line DL3 may have a width smaller than the fifteenth width WD15 .

[0160] The fourth portion AEB4 may extend from the first portion AEB1 and protrude in the first direction DR1, but should not be limited thereto. In an embodiment, the fourth portion AEB4 may extend from the second portion AEB2 or the third portion AEB3 and protrude therefrom. In other words, the fourth portion AEB4 may protrude from one of the first portion AEB1 to the third portion AEB3.

[0161] The fourth portion AEB4 may have a sixteenth width WD16 in the second direction DR2. The sixteenth width WD16 may be in a range of about 7.60 μm to about 10.3 μm. In an embodiment, the sixteenth width WD16 may be about 10.20 μm.

[0162] The third light emitting layer ELB may be disposed on the third anode AEB. The third light emitting layer ELB may include a first light emitting portion ELB1, a second light emitting portion ELB2, and a third light emitting portion ELB3. The first to third light emitting portions ELB1 to ELB3 may be disposed on the first to third portions AEB1 to AEB3, respectively.

[0163] The first light emitting part ELB1 may have a shape corresponding to that of the first portion AEB1. In a plan view, the first light emitting part ELB1 may overlap with the first portion AEB1.

[0164] The second light emitting part ELB2 may have a shape corresponding to that of the second portion AEB2. In a plan view, the second light emitting part ELB2 may overlap with the second portion AEB2.

[0165] The third light emitting part ELB3 may have a shape corresponding to that of the third portion AEB3. In a plan view, the third light emitting part ELB3 may overlap with the third portion AEB3.

[0166] In a plan view, the third light emitting layer ELB may not overlap with the fourth portion AEB4.

[0167] The first light emitting part ELB1, the second light emitting part ELB2, and the third light emitting part ELB3 may be provided integrally with each other.

[0168] The first subpixel PXR and the second subpixel PXG of the second pixel PX2 may be spaced apart from the first to third portions AEB1 to AEB3 of the third subpixel PXB of the first pixel PX1 by a seventeenth width WD17 in the first direction DR1. The seventeenth width WD17 may be in a range of about 12.60 μm to about 15.20 μm. In an embodiment, the seventeenth width WD17 may be about 12.66 μm.

[0169] The first subpixel PXR of the third pixel PX3 may be spaced apart from the second subpixel PXG of the first pixel PX1 by an eighteenth width WD18 in a direction parallel to the second direction DR2. The eighteenth width WD18 may be in a range of about 12.60 μm to about 15.20 μm. In an embodiment, the eighteenth width WD18 may be about 12.66 μm.

[0170] The third subpixel PXB of the third pixel PX3 may be spaced apart from the third subpixel PXB of the first pixel PX1 by a nineteenth width WD19 in a direction parallel to the second direction DR2. The nineteenth width WD19 may be in a range of about 3.0 μm to about 6.0 μm. In an embodiment, the nineteenth width WD19 may be about 3.10 μm.

[0171] The second portion AEB2 and the third portion AEB3 of the first pixel PX1 may be disposed to face the second portion AEB2 and the third portion AEB3 of the third pixel PX3 , respectively.

[0172] The third subpixel PXB of the fourth pixel PX4 may be spaced apart from the third subpixel PXB of the second pixel PX2 by a twentieth width WD20 in a direction parallel to the second direction DR2. The twentieth width WD20 may be greater than the nineteenth width WD19. The twentieth width WD20 may be within a range of approximately 47.60 μm to approximately 50.20 μm. In an embodiment, the twentieth width WD20 may be approximately 47.66 μm. The first portion AEB1 of the fourth pixel PX4 may be disposed so as to face the first portion AEB1 of the second pixel PX2.

[0173] Unlike the present disclosure, there may not be a gap between the second portion and the third portion. That is, in a plan view, the second portion and the third portion may overlap with the third data line. In this case, parasitic capacitance is generated between the third anode and the third data line, and thus, the load of the data signal applied to the third data line increases. As a result, the third data line may not be fully charged. However, according to the present disclosure, the third data line DL3 can be arranged between the second portion AEB2 and the third portion AEB3. In a plan view, since the third data line DL3 does not overlap with the second portion AEB2 and the third portion AEB3, the parasitic capacitance between the third data line DL3 and the second portion AEB2 and the third portion AEB3 can be reduced. This can prevent the load of the data signal applied to the third data line DL3 from increasing due to the parasitic capacitance, and thus prevent the third data line DL3 from being fully charged. Therefore, the reliability of the display device DD can be improved.

[0174] Furthermore, unlike the present disclosure, when there is no gap between the second portion AEB2 and the third portion AEB3, exhaust gas generated from the circuit layer is not discharged externally, and the lifespan of the third light-emitting layer ELB is shortened. However, according to the present disclosure, a gap exists between the second portion AEB2 and the third portion AEB3, and exhaust gas generated from the circuit layer 120 can be smoothly discharged. As a result, the pixel shrinkage phenomenon can be reduced, and the lifespan of the third light-emitting layer ELB can be increased. As a result, the reliability of the display device DD can be improved.

[0175] Figure 7 According to the present disclosure Figure 6 A cross-sectional view taken along line II'.

[0176] refer to Figure 6 and Figure 7 , the display panel DP may include a base layer 110 , a circuit layer 120 , a light emitting element layer 130 and an encapsulation layer 140 .

[0177] At least one inorganic layer may be formed on the upper surface of the base layer 110. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. The inorganic layer formed into multiple layers may form a barrier layer and / or a buffer layer.

[0178] The base layer 110 may have a multi-layer structure. In an embodiment, the base layer 110 may include, for example, a first synthetic resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second synthetic resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may also be referred to as a base barrier layer.

[0179] In the illustrated embodiment, the display panel DP may include a buffer layer BFL. The buffer layer BFL may increase adhesion between the base layer 110 and the semiconductor pattern. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the buffer layer BFL may have a stacked structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0180] The semiconductor pattern may correspond to one of the patterns of the semiconductor layer disposed on the buffer layer BFL. The semiconductor pattern may include a metal oxide. The semiconductor pattern may include polysilicon, however, it should not be limited thereto or thereby. The semiconductor pattern may include amorphous silicon, relatively low temperature polysilicon, or an oxide semiconductor.

[0181] The metal oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor. In an embodiment, the oxide semiconductor may include a metal oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc., or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc. and their oxides. The oxide semiconductor may include indium tin oxide ("ITO"), indium gallium zinc oxide ("IGZO"), zinc oxide (ZnO), indium zinc oxide ("IZO"), zinc indium oxide ("ZIO"), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide ("IZTO"), zinc tin oxide ("ZTO"), etc.

[0182] The semiconductor pattern may include a plurality of regions distinguished from each other according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter also referred to as the reduction region) may have a higher conductivity than the region where the metal oxide is not reduced (hereinafter also referred to as the non-reduction region). The reduction region may be substantially used as a signal line or the source / drain of a transistor. The non-reduction region may substantially correspond to the semiconductor region (or channel) of the transistor. In other words, a portion of the semiconductor pattern may be the semiconductor region of the transistor, another portion of the semiconductor pattern may be the source / drain of the transistor, and the remaining (other) portion of the semiconductor pattern may be a signal transmission region.

[0183] Each of the pixels may have an equivalent circuit including five transistors, two capacitors, and a light emitting element; however, the equivalent circuit of the pixel may be changed in various ways. Figure 7 One transistor T1 and a light emitting element ED included in a pixel are shown.

[0184] The source region SC, the active region AL, and the drain region DR of the transistor T1 may be formed of a semiconductor pattern. The source region SC and the drain region DR may extend from the active region AL in opposite directions to each other in a cross section.

[0185] Figure 7 A portion of a connection signal line SCL formed of a semiconductor pattern is shown Although not shown in the drawings, the connection signal line SCL may be electrically connected to the drain region DR of the transistor T1 in a plane.

[0186] The first insulating layer 10 may be provided on the buffer layer BFL. The first insulating layer 10 may overlap with the pixels in common and may cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the illustrated embodiment, the first insulating layer 10 may have a silicon oxide layer with a single-layer structure. Not only the first insulating layer 10, but also the insulating layer of the circuit layer 120 described later may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, however, it should not be limited thereto.

[0187] The gate GT of the first transistor T1 may be disposed on the first insulating layer 10. The first transistor T1 may be disposed on the base layer 110. The gate GT may be part of a metal pattern. The gate GT may overlap with the active area AL. The gate GT may be used as a mask in a process of doping the semiconductor pattern.

[0188] The second insulating layer 20 may be provided on the first insulating layer 10 and may cover the gate electrode GT. The second insulating layer 20 may overlap with the pixel in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the illustrated embodiment, the second insulating layer 20 may have a multi-layer structure of a silicon oxide layer and a silicon nitride layer.

[0189] The third insulating layer 30 may be provided on the second insulating layer 20. The third insulating layer 30 may have a single layer structure or a multi-layer structure. In an embodiment, the third insulating layer 30 may have a multi-layer structure of a silicon oxide layer and a silicon nitride layer.

[0190] The first transistor T1 may be electrically connected to the light emitting element layer 130 through the third contact hole CNT3. The third contact hole CNT3 may include contact holes CNT-1, CNT-2, and CNT-3.

[0191] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL via a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0192] The fourth insulating layer 40 may be provided on the third insulating layer 30. The fourth insulating layer 40 may have a silicon oxide layer having a single layer structure. The fifth insulating layer 50 may be provided on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0193] The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40 and the fifth insulating layer 50.

[0194] The third data line DL3 may be disposed on the fifth insulating layer 50. The third data line DL3 may be disposed in the same layer as the second connection electrode CNE2. The third data line DL3 may be disposed on the first transistor T1. However, the present disclosure is not limited thereto, and the arrangement of the third data line DL3 is not limited thereto. In an embodiment, the third data line DL3 may be disposed between the first transistor T1 and the third anode (also referred to as the first electrode) AEB.

[0195] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connection electrode CNE2 and the third data line DL3 . The sixth insulating layer 60 may be an organic layer.

[0196] The light-emitting element layer 130 may be provided on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element ED and a pixel defining layer 70. In an embodiment, the light-emitting element layer 130 may include, for example, an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. Hereinafter, an organic light-emitting element will be described as the light-emitting element ED, however, the light-emitting element should not be particularly limited.

[0197] The light emitting element ED may include a third anode AEB, a third light emitting layer ELB, and a cathode (also referred to as a second electrode) CE.

[0198] The third anode AEB may be disposed on the sixth insulating layer 60. The third anode AEB may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined through the sixth insulating layer 60. That is, the connection electrode CNE may electrically connect the first transistor T1 and the light emitting element layer 130.

[0199] The portions of the third anode AEB may be arranged to be spaced apart from each other by a predetermined distance. Figure 7 The portion on the left side of the diagram may be the second portion AEB2 (reference Figure 6 ), and the third anode AEB is set at Figure 7 The portion on the right side of the diagram may be the third portion AEB3 (reference Figure 6 ).

[0200] In a plan view, the third data line DL3 may not overlap with the second portion AEB2 and the third portion AEB3. That is, the third data line DL3 may be disposed between the second portion AEB2 and the third portion AEB3.

[0201] In a plan view, the third data line DL3 may not overlap at least a portion of the third anode AEB. This reduces the parasitic capacitance generated between the third anode AEB and the third data line DL3. This prevents an increase in the load of the data signal applied to the third data line DL3 due to the parasitic capacitance, thereby preventing insufficient charging of the third data line DL3. Consequently, the reliability of the display device DD can be improved.

[0202] The pixel defining layer 70 may be disposed on the sixth insulating layer 60 and may cover a portion of the third anode AEB. An opening 70-OP may be defined through the pixel defining layer 70. At least a portion of the third anode AEB may be exposed through the opening 70-OP of the pixel defining layer 70.

[0203] Display area DA (reference Figure 1 ) may include a light emitting region PXA and a non-light emitting region NPXA adjacent to (adjacent to) the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. In the illustrated embodiment, the light emitting region PXA may be defined to correspond to a portion of the third anode electrode AEB exposed through the opening 70-OP.

[0204] The third light-emitting layer ELB may be disposed on the third anode AEB. The third light-emitting layer ELB may be disposed in a region corresponding to the opening 70-OP. The third light-emitting layer ELB may emit blue light. In a plan view, the third light-emitting layer ELB may not overlap with the third contact hole CNT3.

[0205] The cathode CE may be disposed on the third light emitting layer ELB. The cathode CE may have a unitary shape and may be commonly disposed throughout the pixels.

[0206] Although not shown in the drawings, a hole control layer may be provided between the third anode electrode AEB and the third light-emitting layer ELB. The hole control layer is commonly provided in the light-emitting region PXA and the non-light-emitting region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer may be provided between the third light-emitting layer ELB and the cathode electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer may typically be formed in multiple pixels using an open mask or inkjet process.

[0207] The encapsulation layer 140 may be provided on the light-emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and an inorganic layer stacked in sequence, however, the layers of the encapsulation layer 140 should not be limited thereto or thereby. The inorganic layer may protect the light-emitting element layer 130 from moisture and oxygen, and the organic layer may protect the light-emitting element layer 130 from foreign matter such as dust particles. Each of the inorganic layers may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic-based organic layer, however, it should not be limited thereto or thereby.

[0208] Unlike the present disclosure, in a plan view, the third light emitting layer may overlap with the third contact hole. In this case, since the third contact hole is defined, the fourth insulating layer provided under the third light emitting layer may not be flat. Therefore, since the light reflectivity of the third light emitting layer varies according to its area, color deviation may occur. However, according to the present disclosure, in a plan view, the third light emitting layer ELB may not overlap with the third contact hole CNT3. When the third contact hole CNT3 is defined, the insulating layer provided under the third light emitting layer ELB may be stacked flatly. Therefore, the light reflectivity of the third light emitting layer ELB may be maintained at a constant level, and therefore, color deviation may be prevented. Therefore, the display device DD (reference Figure 1 ) display quality.

[0209] Figure 8 is a plan view of a portion of an embodiment of a display device according to the present disclosure. Figure 8 In the Figure 6 , and therefore, detailed description of the same elements will be omitted.

[0210] refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 8 , display panel (reference Figure 4 DP) may include multiple pixels (reference Figure 3 PX) and data line DL. Figure 8 Four pixels among the pixels PX are shown.

[0211] The pixels PX may include a first pixel PX1-1, a second pixel PX2-1, a third pixel PX3-1, and a fourth pixel PX4-1. The second pixel PX2-1 may be spaced apart from the first pixel PX1-1 in a first direction DR1. The third pixel PX3-1 may be spaced apart from the first pixel PX1-1 in a direction parallel to the second direction DR2. The fourth pixel PX4-1 may be spaced apart from the second pixel PX2-1 in a direction parallel to the second direction DR2. The first to fourth pixels PX1-1 to PX4-1 may include the same components, and only the arrangement of the components of the first to fourth pixels PX1-1 to PX4-1 may differ from each other.

[0212] The first pixel PX1-1 may include a first sub-pixel PXR, a second sub-pixel PXG, and a third sub-pixel PXB-1. Each of the first sub-pixel PXR, the second sub-pixel PXG, and the third sub-pixel PXB-1 may be aligned with a sub-pixel (refer to Figure 5 PXSij) corresponds to.

[0213] The third subpixel PXB- 1 may be spaced apart from the first subpixel PXR by a second width WD2 in the first direction DR1 .

[0214] The third subpixel PXB- 1 may be spaced apart from the second subpixel PXG by a third width WD3 in the first direction DR1 .

[0215] The light emitting element ED of the third sub-pixel PXB-1 may include a third anode AEB-1 and a third light emitting layer ELB-1. The third anode AEB-1 and the third light emitting layer ELB-1 may be provided on the light emitting element layer (refer to FIG. Figure 4 130).

[0216] The third anode AEB-1 may be electrically connected to the pixel circuit PXC of the third subpixel PXB-1 through the third contact hole CNT3-1. The third light emitting layer ELB-1 may be disposed on the third anode AEB-1. The third light emitting layer ELB-1 may emit blue light.

[0217] The third anode AEB-1 may cover the third light emitting layer ELB-1 in a plan view. That is, the third anode AEB-1 may have an area larger than that of the third light emitting layer ELB-1 in a plan view.

[0218] The third anode AEB- 1 may include a first portion AEB1 - 1 , a second portion AEB2 - 1 , a third portion AEB3 - 1 , and a fourth portion AEB4 - 1 .

[0219] The first, second, and third portions AEB1-1, AEB2-1, and AEB3-1 may be disposed below the third light emitting layer ELB-1. That is, in a plan view, the first, second, and third portions AEB1-1, AEB2-1, and AEB3-1 may overlap the third light emitting layer ELB-1.

[0220] The fourth portion AEB4-1 may be disposed on the third contact hole CNT3-1. That is, in a plan view, the fourth portion AEB4-1 may overlap with the third contact hole CNT3-1.

[0221] The first portion AEB1 - 1 , the second portion AEB2 - 1 , the third portion AEB3 - 1 , and the fourth portion AEB4 - 1 may be provided integrally with each other.

[0222] The second portion AEB2-1 may be a portion extending from the first portion AEB1-1 and protruding in a direction parallel to the first direction DR1. The third portion AEB3-1 may be a portion extending from the first portion AEB1-1 and protruding in a direction parallel to the first direction DR1. The second portion AEB2-1 and the third portion AEB3-1 may be spaced apart from each other and may face each other in the second direction DR2.

[0223] In a plan view, the first portion AEB1 - 1 may not overlap the third data line DL3 , but it should not be limited thereto or thereby. In an embodiment, the first portion AEB1 - 1 may overlap the third data line DL3 .

[0224] The fourth portion AEB4-1 may extend from the second portion AEB2-1 and protrude in the first direction DR1, however, the present disclosure should not be limited thereto or thereby. In an embodiment, the fourth portion AEB4-1 may extend from the first portion AEB1-1 and the third portion AEB3-1 to protrude. In other words, the fourth portion AEB4-1 may protrude from one of the first portion AEB1-1 to the third portion AEB3-1.

[0225] The third light-emitting layer ELB-1 may be disposed on the third anode AEB-1. The third light-emitting layer ELB-1 may include a first light-emitting portion ELB1-1, a second light-emitting portion ELB2-1, and a third light-emitting portion ELB3-1. The first to third light-emitting portions ELB1-1 to ELB3-1 may be disposed on the first to third portions AEB1-1 to AEB3-1, respectively.

[0226] The first light emitting part ELB1-1 may have a shape corresponding to that of the first part AEB1-1. In a plan view, the first light emitting part ELB1-1 may overlap with the first part AEB1-1.

[0227] The second light emitting part ELB2-1 may have a shape corresponding to that of the second portion AEB2-1. In a plan view, the second light emitting part ELB2-1 may overlap with the second portion AEB2-1.

[0228] The third light emitting part ELB3-1 may have a shape corresponding to that of the third portion AEB3-1. In a plan view, the third light emitting part ELB3-1 may overlap with the third portion AEB3-1.

[0229] In a plan view, the third light emitting layer ELB-1 may not overlap with the fourth portion AEB4-1.

[0230] The first light emitting part ELB1 - 1 , the second light emitting part ELB2 - 1 , and the third light emitting part ELB3 - 1 may be provided integrally with each other.

[0231] Unlike the present disclosure, in a plan view, the third anode may overlap with the third data line. In this case, parasitic capacitance may be generated between the third anode and the third data line, thereby increasing the load of the data signal applied to the third data line. As a result, the third data line may be insufficiently charged. However, according to the present disclosure, the second portion AEB2-1 and the third portion AEB3-1 may be spaced apart from each other, and a space may be defined between the second portion AEB2-1 and the third portion AEB3-1 in a plan view. The third data line DL3 may be arranged to overlap with this space. In a plan view, at least a portion of the third data line DL3 may not overlap with the third anode AEB-1. Compared to when the third data line DL3 overlaps with the third anode, the parasitic capacitance generated between the third data line DL3 and the third anode AEB-1 can be reduced. This can prevent an increase in the load of the data signal applied to the third data line DL3 due to the parasitic capacitance, thereby preventing insufficient charging of the third data line DL3. Consequently, the reliability of the display device DD can be improved.

[0232] Furthermore, unlike the present disclosure, when there is no gap between the second and third portions, exhaust gas generated from the circuit layer is not discharged, shortening the lifespan of the third light-emitting layer. However, according to the present disclosure, the presence of a gap between the second portion AEB2-1 and the third portion AEB3-1 allows exhaust gas generated from the circuit layer 120 to be discharged smoothly. Consequently, pixel shrinkage can be reduced, and the lifespan of the third light-emitting layer ELB-1 can be increased. Consequently, the reliability of the display device DD can be improved.

[0233] Figure 9 is a plan view of a portion of an embodiment of a display device according to the present disclosure.

[0234] refer to Figure 3、 Figure 4 、 Figure 5 and Figure 9 , display panel (reference Figure 4 DP) may include multiple pixels (reference Figure 3 PX) and multiple data lines (reference Figure 3 DL1 to DLm). Figure 9 A third data line DL3 among the data lines DL1 to DLm is shown. The pixel PX may include a fifth pixel PX5.

[0235] The third data line DL3 may be provided on the circuit layer (refer to Figure 4 120).

[0236] The fifth pixel PX5 may include a first sub-pixel PXR-1, a second sub-pixel PXG-1, and a third sub-pixel PXBa. Each of the first sub-pixel PXR-1, the second sub-pixel PXG-1, and the third sub-pixel PXBa may be aligned with the sub-pixel (refer to Figure 5 PXSij) corresponds to.

[0237] The light emitting element ED of the first sub-pixel PXR-1 may be electrically connected to the pixel circuit PXC of the first sub-pixel PXR-1 through the first contact hole CNT1-1. The light emitting element ED of the first sub-pixel PXR-1 may include a first anode AER-1 and a first light emitting layer ELR-1. The first anode AER-1 and the first light emitting layer ELR-1 may be provided on the light emitting element layer (refer to FIG. Figure 4 130).

[0238] The first anode electrode AER-1 may be electrically connected to the pixel circuit PXC of the first subpixel PXR-1 through the first contact hole CNT1-1. The first light emitting layer ELR-1 may be disposed on the first anode electrode AER-1. The first light emitting layer ELR-1 may emit red light.

[0239] The first anode AER-1 disposed under the first light-emitting layer ELR-1 may have a twenty-first width WD21 in the first direction DR1. The twenty-first width WD21 may be in the range of about 32.50 μm to about 34.00 μm. In an embodiment, the twenty-first width WD21 may be about 33.09 μm. The first anode AER-1 disposed under the first light-emitting layer ELR-1 may have a twenty-second width WD22 in the second direction DR2. The twenty-second width WD22 may be in the range of about 48.50 μm to about 50.00 μm. In an embodiment, the twenty-second width WD22 may be about 49.06 μm.

[0240] The light-emitting element ED of the second subpixel PXG-1 can be electrically connected to the pixel circuit PXC of the second subpixel PXG-1 through the second contact hole CNT2-1. The light-emitting element ED of the second subpixel PXG-1 may include a second anode AEG-1 and a second light-emitting layer ELG-1. The second anode AEG-1 and the second light-emitting layer ELG-1 may be disposed on the light-emitting element layer 130.

[0241] The second anode AEG-1 may be electrically connected to the pixel circuit PXC of the second subpixel PXG-1 through the second contact hole CNT2-1. The second light emitting layer ELG-1 may be disposed on the second anode AEG-1. The second light emitting layer ELG-1 may emit green light.

[0242] The portion of the second anode electrode AEG-1 disposed below the second light-emitting layer ELG-1 may have a twenty-third width WD23 in the first direction DR1. The twenty-third width WD23 may be in a range of approximately 24.00 μm to approximately 26.00 μm. In an embodiment, the twenty-third width WD23 may be approximately 25.69 μm. The second anode electrode AEG-1 disposed below the second light-emitting layer ELG-1 may have a twenty-fourth width WD24 in the second direction DR2. The twenty-fourth width WD24 may be in a range of approximately 62.00 μm to approximately 64.00 μm. In an embodiment, the twenty-fourth width WD24 may be approximately 63.25 μm.

[0243] The light-emitting element ED of the third subpixel PXBa can be electrically connected to the pixel circuit PXC of the third subpixel PXBa through a third contact hole CNT3a. In an embodiment, the pixel circuit PXC of the third subpixel PXBa can be connected to the third anode AEBa through a third contact hole CNT3a. The light-emitting element ED of the third subpixel PXBa may include a third anode AEBa and a third light-emitting layer ELBa. The third anode AEBa and the third light-emitting layer ELBa may be disposed on the light-emitting element layer 130.

[0244] The third anode electrode AEBa disposed under the third light emitting layer ELBa may have a twenty-fifth width WD25 in the first direction DR1. The twenty-fifth width WD25 may be in a range of about 91.00 μm to about 94.00 μm. In an embodiment, the twenty-fifth width WD25 may be about 93.54 μm.

[0245] The third anode AEBa may include a first portion AEB1a, a second portion AEB2a, a third portion AEB3a, and a plurality of connection portions AEBNa.

[0246] The second portion AEB2a may be spaced apart from the first portion AEB1a in a direction opposite to the second direction DR2. The distance between the first portion AEB1a and the second portion AEB2a may be a twenty-sixth width WD26. The twenty-sixth width WD26 may be in a range of about 2.50 μm to about 4.00 μm. In an embodiment, the twenty-sixth width WD26 may be about 3.1 μm.

[0247] The third portion AEB3a may be disposed to be spaced apart from the second portion AEB2a in a direction opposite to the second direction DR2. A distance between the second portion AEB2a and the third portion AEB3a may be a twenty-sixth width WD26.

[0248] The third data line DL3 may be disposed under the third anode electrode AEBa. In a plan view, a portion of the third data line DL3 may not overlap with the third anode electrode AEBa.

[0249] The connection portion AEBNa may electrically connect the first portion AEB1a, the second portion AEB2a, and the third portion AEB3a that are spaced apart from each other. Each of the connection portions AEBNa may have a twenty-seventh width WD27 in the first direction DR1. The twenty-seventh width WD27 may be in a range of about 5 μm to about 7 μm. In an embodiment, the twenty-seventh width WD27 may be about 6 μm.

[0250] The first portion AEB1a, the second portion AEB2a, the third portion AEB3a, and the connecting portion AEBNa may be provided integrally with each other.

[0251] In a plan view, the third contact hole CNT3a may overlap with the second portion AEB2a and may not overlap with the first portion AEB1a and the third portion AEB3a. The third light-emitting layer ELBa may be disposed on the third anode AEBa. The third light-emitting layer ELBa may include a first light-emitting portion ELB1a, a second light-emitting portion ELB2a, and a third light-emitting portion ELB3a. The first to third light-emitting portions ELB1a to ELB3a may be disposed on the first to third portions AEB1a to AEB3a, respectively.

[0252] The first light emitting part ELB1a may have a shape corresponding to the first part AEB1a, the second light emitting part ELB2a may have a shape corresponding to the second part AEB2a, and the third light emitting part ELB3a may have a shape corresponding to the third part AEB3a.

[0253] Unlike the present disclosure, when the first, second, and third light-emitting sections are integrally provided, exhaust gas generated from the circuit layer is not exhausted, and thus the lifespan of the third light-emitting layer may be shortened. However, according to the present disclosure, since gaps exist between the first to third light-emitting sections ELB1a and ELB3a, exhaust gas generated from the circuit layer 120 can be smoothly exhausted. Consequently, pixel shrinkage can be reduced, and the lifespan of the third light-emitting layer ELBa can be increased. Consequently, the reliability of the display device DD can be improved.

[0254] Unlike the present disclosure, in a plan view, the third light-emitting layer may overlap with the third contact hole. In this case, since the third contact hole is defined, the portion of the circuit layer disposed below the third light-emitting layer may not be flat. Therefore, due to changes in the light reflectivity of the third light-emitting layer, color deviation may occur. However, according to the present disclosure, in a plan view, the third light-emitting layer ELBa may not overlap with the third contact hole CNT3a. When the third contact hole CNT3a is defined to pass through the circuit layer 120, the portion of the circuit layer 120 disposed below the third light-emitting layer ELBa may be flat. Therefore, the light reflectivity of the third light-emitting layer ELBa can be maintained at a constant level, and therefore, color deviation can be prevented. Therefore, the display quality of the display device DD can be improved.

[0255] Unlike the present disclosure, in a plan view, the third anode may overlap with the third data line. In this case, parasitic capacitance may be generated between the third anode and the third data line, thereby increasing the load of the data signal applied to the third data line. As a result, the third data line may not be fully charged. However, according to the present disclosure, the first portion AEB1a and the second portion AEB2a may be spaced apart from each other, and a first space may be defined between the first portion AEB1a and the second portion AEB2a in a plan view. The second portion AEB2a and the third portion AEB3a may be spaced apart from each other, and a second space may be defined between the second portion AEB2a and the third portion AEB3a in a plan view. The third data line DL3 may be arranged to overlap with the first and second spaces. In a plan view, at least a portion of the third data line DL3 may not overlap with the third anode AEBa. This reduces the parasitic capacitance generated between the third data line DL3 and the third anode AEBa compared to when the third data line DL3 overlaps with the third anode. The load of the data signal applied to the third data line DL3 due to the parasitic capacitance can be prevented from increasing, and thus, the third data line DL3 can be prevented from being insufficiently charged. Therefore, the reliability of the display device DD can be improved.

[0256] Figure 10 is a plan view of a portion of an embodiment of a display device according to the present disclosure. Figure 10In the Figure 9 , and therefore, detailed description of the same elements will be omitted.

[0257] refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 10 , display panel (reference Figure 4 DP) may include multiple pixels (reference Figure 3 The pixel PX may include a fifth pixel PX5-1.

[0258] The fifth pixel PX5-1 may include a first sub-pixel PXR-1, a second sub-pixel PXG-1, and a third sub-pixel PXBb. Each of the first sub-pixel PXR-1, the second sub-pixel PXG-1, and the third sub-pixel PXBb may be aligned with a sub-pixel (refer to Figure 5 PXSij) corresponds to.

[0259] The light emitting element ED of the third sub-pixel PXBb may be electrically connected to the pixel circuit PXC of the third sub-pixel PXBb through the third contact hole CNT3b. In an embodiment, the pixel circuit PXC of the third sub-pixel PXBb may be connected to the third anode AEBb through a third contact hole CNT3b. The light emitting element ED of the third sub-pixel PXBb may include a third anode AEBb and a third light emitting layer ELBb. The third anode AEBb and the third light emitting layer ELBb may be provided in the light emitting element layer (refer to FIG. Figure 4 130).

[0260] The third anode electrode AEBb disposed under the third light emitting layer ELBb may have a twenty-fifth width WD25 in the first direction DR1. The twenty-fifth width WD25 may be in a range of about 91.00 μm to about 94.00 μm. In an embodiment, the twenty-fifth width WD25 may be about 93.54 μm.

[0261] The third anode electrode AEBb may include a first portion AEB1b, a second portion AEB2b, a third portion AEB3b, a plurality of connection portions AEBNb, and a protruding portion AEBP.

[0262] The second portion AEB2b may be disposed spaced apart from the first portion AEB1b in a direction opposite to the second direction DR2. The distance between the first portion AEB1b and the second portion AEB2b may also be referred to as a twenty-sixth width WD26. The twenty-sixth width WD26 may be in a range of approximately 2.50 μm to approximately 4.00 μm. In an embodiment, the twenty-sixth width WD26 may be approximately 3.1 μm.

[0263] The third portion AEB3b may be disposed to be spaced apart from the second portion AEB2b in a direction opposite to the second direction DR2. A distance between the second portion AEB2b and the third portion AEB3b may be the same as the twenty-sixth width WD26.

[0264] The third data line DL3 may be disposed under the third anode electrode AEBb. In a plan view, a portion of the third data line DL3 may not overlap with the third anode electrode AEBb.

[0265] The connection portion AEBNb may electrically connect the first portion AEB1b, the second portion AEB2b, and the third portion AEB3b. Each of the connection portions AEBNb may have a twenty-seventh width WD27 in the first direction DR1. The twenty-seventh width WD27 may be in a range of about 5 μm to about 7 μm. In an embodiment, the twenty-seventh width WD27 may be about 6 μm.

[0266] The protruding portion AEBP may be a portion extending from the first portion AEB1b and protruding in the first direction DR1, however, the present disclosure should not be limited thereto or thereby. In an embodiment, the protruding portion AEBP may be a portion extending from the second portion AEB2b, the third portion AEB3b, or the connecting portion AEBNb. In other words, the protruding portion AEBP may be a portion extending from one of the first portion AEB1b, the second portion AEB2b, the third portion AEB3b, and the connecting portion AEBNb.

[0267] The first portion AEB1a, the second portion AEB2a, the third portion AEB3a, the connecting portion AEBNa, and the protruding portion AEBP may be provided integrally with one another.

[0268] In a plan view, the third contact hole CNT3b may overlap with the protruding portion AEBP and may not overlap with the first to third portions AEB1b to AEB3b. The third light-emitting layer ELBb may be disposed on the third anode AEBb. The third light-emitting layer ELBb may include a first light-emitting portion ELB1b, a second light-emitting portion ELB2b, and a third light-emitting portion ELB3b. The first to third light-emitting portions ELB1b to ELB3b may be disposed on the first to third portions AEB1b to AEB3b, respectively.

[0269] The first light emitting part ELB1b may have a shape corresponding to the first part AEB1b, the second light emitting part ELB2b may have a shape corresponding to the second part AEB2b, and the third light emitting part ELB3b may have a shape corresponding to the third part AEB3b.

[0270] Unlike the present disclosure, when the first, second, and third light-emitting sections are integrally arranged, exhaust gas generated from the circuit layer is not exhausted, and thus the lifespan of the third light-emitting layer may be shortened. However, according to the present disclosure, gaps exist between the first to third light-emitting sections ELB1b and ELB3b, and exhaust gas generated from the circuit layer 120 can be smoothly exhausted. Consequently, pixel shrinkage can be reduced, and the lifespan of the third light-emitting layer ELBb can be increased. Consequently, the reliability of the display device DD can be improved.

[0271] Unlike the present disclosure, in a plan view, the third light-emitting layer may overlap with the third contact hole. In this case, due to the definition of the third contact hole, the portion of the circuit layer disposed below the third light-emitting layer may be uneven. Therefore, due to the change in the light reflectivity of the third light-emitting layer, color deviation may occur. However, according to the present disclosure, in a plan view, the third light-emitting layer ELBb may not overlap with the third contact hole CNT3b. When the third contact hole CNT3b is defined to pass through the circuit layer 120, the circuit layer 120 disposed below the third light-emitting layer ELBb can be flat. Therefore, the light reflectivity of the third light-emitting layer ELBb can be maintained at a constant level, and thus, color deviation can be prevented. Therefore, the display quality of the display device DD can be improved.

[0272] Unlike the present disclosure, in a plan view, the third anode may overlap with the third data line. In this case, parasitic capacitance may be generated between the third anode and the third data line, thereby increasing the load of the data signal applied to the third data line. As a result, the third data line may not be fully charged. However, according to the present disclosure, the first portion AEB1b and the second portion AEB2b may be spaced apart from each other, and a first space may be defined between the first portion AEB1b and the second portion AEB2b in a plan view. The second portion AEB2b and the third portion AEB3b may be spaced apart from each other, and a second space may be defined between the second portion AEB2b and the third portion AEB3b in a plan view. The third data line DL3 may be arranged to overlap with the first and second spaces. In a plan view, at least a portion of the third data line DL3 may not overlap with the third anode AEBb. This reduces the parasitic capacitance generated between the third data line DL3 and the third anode AEBb compared to when the third data line DL3 overlaps with the third anode. The load of the data signal applied to the third data line DL3 due to the parasitic capacitance can be prevented from increasing, and thus, the third data line DL3 can be prevented from being insufficiently charged. Therefore, the reliability of the display device DD can be improved.

[0273] Figure 11 is a plan view of a portion of an embodiment of a display device according to the present disclosure. Figure 11In the Figure 6 , and therefore, detailed description of the same elements will be omitted.

[0274] refer to Figure 3 、 Figure 4 、 Figure 5 and Figure 11 , display panel (reference Figure 4 DP) may include multiple pixels (reference Figure 3 The pixel PX may include a sixth pixel PX6.

[0275] The sixth pixel PX6 may include a first sub-pixel PXR-2, a second sub-pixel PXG-2, and a third sub-pixel PXB-2. Each of the first sub-pixel PXR-2, the second sub-pixel PXG-2, and the third sub-pixel PXB-2 may be aligned with the sub-pixel (refer to Figure 5 PXSij) corresponds to.

[0276] The light emitting element ED of the first sub-pixel PXR-2 may be electrically connected to the pixel circuit PXC of the first sub-pixel PXR-2 through the first contact hole CNT1-2. The light emitting element ED of the first sub-pixel PXR-2 may include a first anode AER-2 and a first light emitting layer ELR-2. The first anode AER-2 and the first light emitting layer ELR-2 may be provided in the light emitting element layer (refer to FIG. Figure 4 130).

[0277] The first anode electrode AER-2 may be electrically connected to the pixel circuit PXC of the first subpixel PXR-2 through the first contact hole CNT1-2. The first light emitting layer ELR-2 may be disposed on the first anode electrode AER-2. The first light emitting layer ELR-2 may emit red light.

[0278] The first light emitting layer ELR-2 may have a twenty-eighth width WD28 in the first direction DR1. The twenty-eighth width WD28 may be in a range of about 24.50 μm to about 26.50 μm. In an embodiment, the twenty-eighth width WD28 may be about 25.69 μm.

[0279] The first light emitting layer ELR-2 may have a twenty-ninth width WD29 in the second direction DR2. The twenty-ninth width WD29 may be in a range of about 40.50 μm to about 42.50 μm. In an embodiment, the twenty-ninth width WD29 may be about 41.66 μm.

[0280] The light-emitting element ED of the second subpixel PXG-2 can be electrically connected to the pixel circuit PXC of the second subpixel PXG-2 through the second contact hole CNT2-2. The light-emitting element ED of the second subpixel PXG-2 may include a second anode AEG-2 and a second light-emitting layer ELG-2. The second anode AEG-2 and the second light-emitting layer ELG-2 may be disposed on the light-emitting element layer 130.

[0281] The second anode electrode AEG-2 may be electrically connected to the pixel circuit PXC of the second sub-pixel PXG-2 through the second contact hole CNT2-2. The second light emitting layer ELG-2 may be disposed on the second anode electrode AEG-2. The second light emitting layer ELG-2 may emit green light.

[0282] The second light emitting layer ELG-2 may be spaced apart from the first light emitting layer ELR-2 by a thirtieth width WD30 in a direction opposite to the second direction DR2. The thirtieth width WD30 may be in a range of about 17.50 μm to about 20.00 μm. In an embodiment, the thirtieth width WD30 may be about 18.47 μm.

[0283] The second light emitting layer ELG-2 may have the same width as the twenty-eighth width WD28 in the first direction DR1. The twenty-eighth width WD28 may be in the range of about 24.50 μm to about 26.50 μm. In an embodiment, the twenty-eighth width WD28 may be about 25.69 μm.

[0284] The second light emitting layer ELG-2 may have a thirty-first width WD31 in the second direction DR2. The thirty-first width WD31 may be in a range of about 54.50 μm to about 56.50 μm. In an embodiment, the thirty-first width WD31 may be about 55.86 μm.

[0285] The light-emitting element ED of the third subpixel PXB-2 can be electrically connected to the pixel circuit PXC of the third subpixel PXB-2 through a third contact hole CNT3-2. In an embodiment, the pixel circuit PXC of the third subpixel PXB-2 can be connected to the third anode AEB-2 through a third contact hole CNT3-2. The light-emitting element ED of the third subpixel PXB-2 may include a third anode AEB-2 and a third light-emitting layer ELB-2. The third anode AEB-2 and the third light-emitting layer ELB-2 may be disposed on the light-emitting element layer 130.

[0286] The third light emitting layer ELB-2 may be spaced apart from each of the first and second light emitting layers ELR-2 and ELG-2 by a thirty-second width WD32 in the first direction DR1. The thirty-second width WD32 may be in a range of about 17.50 μm to about 20.00 μm. In an embodiment, the thirty-second width WD32 may be about 18.47 μm.

[0287] The third anode AEB-2 may include a first portion AEB1-2, a second portion AEB2-2, a third portion AEB3-2, a fourth portion AEB4-2, and a connecting portion AEBN-1.

[0288] The second portion AEB2 - 2 may be disposed to be spaced apart from the first portion AEB1 - 2 in the first direction DR1 .

[0289] The third portion AEB3 - 2 may be disposed to be spaced apart from the first portion AEB1 - 2 in a direction opposite to the second direction DR2 .

[0290] The fourth portion AEB4 - 2 may be disposed to be spaced apart from the second portion AEB2 - 2 in a direction opposite to the second direction DR2 .

[0291] The third data line DL3 may be disposed under the third anode electrode AEB-2. In a plan view, a portion of the third data line DL3 may not overlap with the third anode electrode AEB-2.

[0292] The connection portion AEBN-1 may electrically connect the first portion AEB1-2, the second portion AEB2-2, the third portion AEB3-2, and the fourth portion AEB4-2 to one another.

[0293] The first portion AEB1-2, the second portion AEB2-2, the third portion AEB3-2, the fourth portion AEB4-2, and the connecting portion AEBN-1 may be provided integrally with one another.

[0294] In a plan view, the second portion AEB2-2 may overlap with the third contact hole CNT3-2, and the first portion AEB1-2, the third portion AEB3-2, and the fourth portion AEB4-2 may not overlap with the third contact hole CNT3-2.

[0295] The third light-emitting layer ELB-2 may be disposed on the third anode AEB-2. The third light-emitting layer ELB-2 may include a first light-emitting portion ELB1-2, a second light-emitting portion ELB2-2, a third light-emitting portion ELB3-2, and a fourth light-emitting portion ELB4-2. The first to fourth light-emitting portions ELB1-2 to ELB4-2 may be disposed on the first to fourth portions AEB1-2 to AEB4-2, respectively.

[0296] The first light emitting part ELB1-2 may have a shape corresponding to that of the first part AEB1-2, the second light emitting part ELB2-2 may have a shape corresponding to that of the second part AEB2-2, the third light emitting part ELB3-2 may have a shape corresponding to that of the third part AEB3-2, and the fourth light emitting part ELB4-2 may have a shape corresponding to that of the fourth part AEB4-2.

[0297] The second light emitting part ELB2-2 may be spaced apart from the first light emitting part ELB1-2 by a thirty-third width WD33 in the first direction DR1. The thirty-third width WD33 may be in a range of about 10.50 μm to about 12.50 μm. In an embodiment, the thirty-third width WD33 may be about 11.65 μm.

[0298] The third light emitting part ELB3-2 may be spaced apart from the first light emitting part ELB1-2 by a thirty-fourth width WD34 in a direction opposite to the second direction DR2. The thirty-fourth width WD34 may be in a range of about 9.50 μm to about 11.50 μm. In an embodiment, the thirty-fourth width WD34 may be about 10.50 μm.

[0299] The first light emitting part ELB1-2 may have a thirty-fifth width WD35 in the first direction DR1. The thirty-fifth width WD35 may be in the range of about 32.50 μm to about 34.50 μm. In an embodiment, the thirty-fifth width WD35 may be about 33.82 μm.

[0300] The first light emitting portion ELB1-2 may have a thirty-sixth width WD36 in the second direction DR2. The thirty-sixth width WD36 may be within a range of about 45.50 μm to about 47.50 μm. In an embodiment, the thirty-sixth width WD36 may be about 46.08 μm.

[0301] The second light emitting portion ELB2 - 2 may have a thirty-seventh width WD37 in the first direction DR1 . The thirty-seventh width WD37 may be in the range of about 25.50 μm to about 27.50 μm. In an embodiment, the thirty-seventh width WD37 may be about 26.36 μm.

[0302] The second light emitting portion ELB2 - 2 may have the same width as the thirty-sixth width WD36 in the second direction DR2 .

[0303] The third light emitting portion ELB3 - 2 may have the same width as the thirty-fifth width WD35 in the first direction DR1 .

[0304] The third light emitting portion ELB3 - 2 may have a thirty-eighth width WD38 in the second direction DR2 . The thirty-eighth width WD38 may be within a range of about 44.50 μm to about 46.50 μm. In an embodiment, the thirty-eighth width WD38 may be about 45.09 μm.

[0305] The fourth light emitting portion ELB4 - 2 may have the same width as the thirty-seventh width WD37 in the first direction DR1 .

[0306] The fourth light emitting portion ELB4 - 2 may have the same width as the thirty-eighth width WD38 in the second direction DR2 .

[0307] Unlike the present disclosure, when the first light emitting portion, the second light emitting portion, the third light emitting portion, and the fourth light emitting portion are provided integrally with each other, the exhaust gas generated from the circuit layer is not exhausted, and therefore, the life of the third light emitting layer may be shortened. However, according to the present disclosure, there are gaps between the first light emitting portion ELB1-2 to the fourth light emitting portion ELB4-2, and the exhaust gas generated from the circuit layer (refer to Figure 4 The exhaust gas generated by the third light emitting layer (120) can be smoothly discharged. Therefore, the pixel shrinkage phenomenon can be reduced and the life of the third light emitting layer ELB-2 can be increased. Therefore, the reliability of the display device DD can be improved.

[0308] Unlike the present disclosure, in a plan view, the third light-emitting layer may overlap with the third contact hole. In this case, due to the definition of the third contact hole, the portion of the circuit layer disposed below the third light-emitting layer may be uneven. Therefore, due to the change in the light reflectivity of the third light-emitting layer, color deviation may occur. However, according to the present disclosure, in a plan view, the third light-emitting layer ELB-2 may not overlap with the third contact hole CNT3-2. When the third contact hole CNT3-2 is defined to pass through the circuit layer 120, the circuit layer 120 disposed below the third light-emitting layer ELB-2 may be flat. Therefore, the light reflectivity of the third light-emitting layer ELB-2 can be maintained at a constant level, and therefore, color deviation can be prevented. Therefore, the display quality of the display device DD can be improved.

[0309] Unlike the present disclosure, the third anode may overlap with the third data line in plan view. In this case, parasitic capacitance may be generated between the third anode and the third data line, thereby increasing the load of the data signal applied to the third data line. As a result, the third data line may not be fully charged. However, according to the present disclosure, the first portion AEB1-2 and the second portion AEB2-2 may be spaced apart from each other, and a first space may be defined between the first portion AEB1-2 and the second portion AEB2-2 in plan view. The third portion AEB3-2 and the fourth portion AEB4-2 may be spaced apart from each other, and a second space may be defined between the third portion AEB3-2 and the fourth portion AEB4-2 in plan view. The third data line DL3 may be arranged to overlap with the first and second spaces. In plan view, at least a portion of the third data line DL3 may not overlap with the third anode AEB-2. Compared to when the third data line DL3 overlaps with the third anode, the parasitic capacitance generated between the third data line DL3 and the third anode AEB-2 can be reduced. The load of the data signal applied to the third data line DL3 due to the parasitic capacitance can be prevented from increasing, and thus, the third data line DL3 can be prevented from being insufficiently charged. Therefore, the reliability of the display device DD can be improved.

[0310] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of the present disclosure as claimed in the claims. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept will be determined according to the appended claims.

Claims

1. A display device comprising: Display panel, including: base layer; Circuit layer, including: a transistor, disposed on the base layer; a connecting electrode electrically connected to the transistor; a data line disposed on the transistor; and an insulating layer disposed on the connection electrode and provided with a contact hole defined through the insulating layer; and a light-emitting element layer, disposed on the circuit layer and electrically connected to the transistor via the connection electrode, the light-emitting element layer comprising: A first electrode is provided on the insulating layer and is electrically connected to the connection electrode through the contact hole, wherein the first electrode comprises: Part I; a second portion extending from the first portion in a first direction; a third portion extending from the first portion toward the first direction; and a fourth portion protruding from one of the first portion, the second portion, and the third portion; a light-emitting layer, disposed on the first electrode; and a second electrode disposed on the light-emitting layer, The second portion and the third portion are spaced apart from each other in a second direction perpendicular to the first direction and face each other.

2. The display device according to claim 1, wherein The first portion, the second portion, the third portion, and the fourth portion are provided integrally with one another.

3. The display device according to claim 1, wherein The data line is disposed between the second portion and the third portion and does not overlap with the second portion and the third portion in a plan view.

4. The display device according to claim 1, wherein The contact hole overlaps with the fourth portion in a plan view.

5. The display device according to claim 4, wherein The light emitting layer does not overlap with the contact hole in the plan view. The display device according to claim 1 , wherein: The data line overlaps only with the first portion in a plan view.

7. The display device according to claim 1, wherein The data line is provided in the same layer as the connection electrode.

8. The display device according to claim 1, wherein The light-emitting layer includes: a first light emitting portion having a shape corresponding to that of the first portion; a second light emitting portion having a shape corresponding to that of the second portion; and The third light emitting portion has a shape corresponding to the shape of the third portion.

9. The display device according to claim 8, wherein The first light emitting portion, the second light emitting portion, and the third light emitting portion are provided integrally with each other.

10. The display device according to claim 1, wherein The light-emitting layer emits blue light.

11. A display device comprising: Display panel, including: Circuit layer, including: transistor; a connecting electrode electrically connected to the transistor; and an insulating layer disposed on the connection electrode and provided with a contact hole defined through the insulating layer; and a light-emitting element layer, disposed on the circuit layer and electrically connected to the transistor via the connection electrode, the light-emitting element layer comprising: A first electrode is provided on the insulating layer, wherein the first electrode comprises: Part I; a second portion spaced apart from the first portion by a second width; a connecting portion electrically connecting the first portion and the second portion; and a protruding portion protruding from one of the first portion, the second portion, and the connecting portion; a light-emitting layer, disposed on the first electrode, comprising: a first light emitting portion; and a second light emitting portion spaced apart from the first light emitting portion by a first width greater than the second width; and The second electrode is arranged on the light-emitting layer.

12. The display device according to claim 11, wherein The first electrode further includes a third portion spaced apart from the second portion in a first direction, and the second portion is spaced apart from the first portion in the first direction.

13. The display device according to claim 12, wherein: The first portion, the second portion, the third portion, the connecting portion, and the protruding portion are provided integrally with one another.

14. The display device according to claim 11, wherein The light-emitting layer emits blue light.

15. The display device according to claim 11, wherein The contact hole overlaps with the protruding portion in a plan view.

16. The display device according to claim 11, wherein The light emitting layer does not overlap with the contact hole in a plan view.

17. The display device according to claim 11, wherein The light emitting layer further includes a third light emitting portion spaced apart from the second light emitting portion by the first width.

18. A display device comprising: Display panel, including: Circuit layer, including: transistor; a connecting electrode electrically connected to the transistor; and an insulating layer disposed on the connection electrode and provided with a contact hole defined through the insulating layer; and a light-emitting element layer, disposed on the circuit layer and electrically connected to the transistor via the connection electrode, the light-emitting element layer comprising: A first electrode is provided on the insulating layer, wherein the first electrode comprises: Part I; a second portion spaced apart from the first portion by a second width; and a connecting portion electrically connecting the first portion and the second portion; a light-emitting layer, disposed on the first electrode, comprising: a first light emitting portion; and a second light emitting portion spaced apart from the first light emitting portion by a first width greater than the second width; and The second electrode is arranged on the light-emitting layer.

19. The display device according to claim 18, wherein The first electrode further includes a third portion spaced apart from the second portion in a first direction, and the second portion is spaced apart from the first portion in the first direction.

20. The display device according to claim 19, wherein The first portion, the second portion, the third portion, and the connecting portion are provided integrally with one another.

21. The display device according to claim 19, wherein The contact hole overlaps with the connection portion in a plan view.

22. The display device according to claim 18, wherein The first electrode further comprises: a third portion spaced apart from the first portion in the first direction; and A fourth portion is spaced apart from the second portion in the first direction, and the second portion is spaced apart from the first portion in a second direction intersecting the first direction.

23. The display device according to claim 22, wherein: The first portion, the second portion, the third portion, the fourth portion, and the connecting portion are provided integrally with one another.

24. The display device according to claim 18, wherein The light emitting layer does not overlap with the contact hole in a plan view.

25. The display device according to claim 18, wherein The contact hole overlaps with the second portion and does not overlap with the first portion in a plan view.

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