Display device

Abstract

A display device is provided. The display device includes a substrate including a light emitting region, a circuit layer, and an element layer. The circuit layer includes a cathode auxiliary electrode disposed in a portion of a non-light-emitting region between the light-emitting regions. The element layer includes an anode electrode, a pixel defining layer, a first common layer, a light emitting layer, a second common layer, and a cathode electrode. A portion of each of the top portions overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode are exposed to the second common layer through the cathode connection hole. In an undercut structure formed by the top portion, a gap is formed in which the second common layer is separated. The cathode electrode is electrically connected to the cathode auxiliary electrode through the cathode connection hole and a gap in the second common layer.

Description

Technical Field

[0001] The disclosure relates to a display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms is increasing. For example, display devices have been applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Here, the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device or a nano-light-emitting display device including a micro-light-emitting element or a nano-light-emitting element.

[0004] Organic light-emitting display devices display images using light-emitting elements, each of which includes a light-emitting layer made of an organic light-emitting material. When these self-luminous elements are used to display images, they can offer superior performance compared to other display devices in terms of power consumption, response speed, emission efficiency, brightness, and wide viewing angles.

[0005] The surface of the display device may be a display surface including a display area displaying an image, and a light emitting area emitting light having corresponding brightness and color may be arranged (set) in the display area. Summary of the Invention

[0006] The display device may include an anode electrode separately arranged in the light-emitting area, a first common layer arranged on the anode electrode, a light-emitting layer arranged on the first common layer, a second common layer entirely covering the light-emitting layer of the display area, and a cathode electrode arranged on the second common layer.

[0007] Because the cathode electrode is provided throughout the display area, it may have a width wider than that of each of the anode electrodes. Therefore, since it may be difficult to uniformly maintain the potential of the cathode electrode throughout the display area, partial brightness differences may occur, which may lead to degradation of image quality.

[0008] In order to prevent such a problem, the display device may further include a cathode auxiliary electrode disposed in some of the non-light emitting regions between the light emitting regions.

[0009] However, since the second common layer is provided between the cathode electrode and the cathode auxiliary electrode, a mask process may be added to partially remove the second common layer for electrical connection between the cathode electrode and the cathode auxiliary electrode. Since the process of manufacturing a display device may become more complicated with the addition of the mask process, it may be difficult to reduce the cost and time consumed in manufacturing a display device including a cathode auxiliary electrode.

[0010] The disclosed aspects provide a display device in which electrical connection between a cathode electrode and a cathode auxiliary electrode can be achieved without separately adding a mask process for a second common layer.

[0011] However, the aspects of the disclosure are not limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0012] According to the disclosed aspects, a display device is provided, which may include: a substrate including a display area in which a light-emitting area is provided; a circuit layer provided on the substrate; and an element layer provided on the circuit layer. The circuit layer may include a cathode auxiliary electrode provided in a portion of a non-light-emitting area between the light-emitting areas in the display area. The element layer may include: an anode electrode provided in the light-emitting area; a pixel defining layer provided in the non-light-emitting area and overlapping an edge of each of the anode electrodes; a first common layer provided on the anode electrode; a light-emitting layer provided on the first common layer; a second common layer provided on the pixel defining layer and the light-emitting layer; and a cathode electrode provided on the second common layer. A portion of each of the top portions overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode may be exposed from the second common layer through a cathode connection hole. In the undercut structure formed by the top portion, a gap may be formed in which the second common layer is separated. The cathode electrode may be electrically connected to the cathode auxiliary electrode through the cathode connection hole and the gap in the second common layer.

[0013] The light-emitting regions may include: a first light-emitting region emitting light of a first color; a second light-emitting region emitting light of a second color having a wavelength band lower than that of the first light-emitting region; and a third light-emitting region emitting light of a third color having a wavelength band lower than that of the second light-emitting region. The first light-emitting regions may be parallel to each other in a first direction. The second light-emitting regions may be parallel to each other in the first direction. Each of the third light-emitting regions may be adjacent to a portion of each of the first light-emitting regions and a portion of each of the second light-emitting regions in the first direction. The first and second light-emitting regions may be arranged alternately in a second direction intersecting the first direction. The third light-emitting regions may be parallel to each other in the second direction. A first spacing region having a first width may be arranged between two or more third light-emitting regions that are parallel in the second direction among the third light-emitting regions, and a second spacing region having a second width greater than the first width may be arranged between two or more third light-emitting regions and another two or more third light-emitting regions.

[0014] The cathode auxiliary electrode may be disposed in the second spacing region.

[0015] The third spacing region may be disposed at one side of the two or more third light emitting regions in the first direction. The cathode auxiliary electrode may be disposed in the first spacing region and the third spacing region.

[0016] The circuit layer may include: an interlayer insulating layer, arranged on a substrate; a first source-drain conductive layer, arranged on the interlayer insulating layer; a first planarization layer, stacked with the first source-drain conductive layer; a second source-drain conductive layer, arranged on the first planarization layer; and a second planarization layer, stacked with the second source-drain conductive layer.

[0017] The cathode auxiliary electrode may be provided as a first source / drain conductive layer. The top portion may be provided as a second source / drain conductive layer. The cathode connection hole may include: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion may protrude significantly more than the second hole. A gap in the second common layer may be formed in an undercut structure between the top portion and the second hole.

[0018] The substrate may further include: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer may further include: two or more auxiliary top portions disposed as a second source / drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surrounding the hole region; and one or more separation grooves located between the two or more auxiliary top portions and penetrating the first planarization layer. A portion of an edge of each of the two or more auxiliary top portions may protrude significantly beyond the one or more separation grooves. The portion of the second common layer disposed in the hole peripheral region may be separated from the undercut structure formed between the two or more auxiliary top portions and the one or more separation grooves.

[0019] The second source-drain conductive layer may include: a main conductive layer; and a sub-conductive layer disposed on the main conductive layer and comprising a metal material different from that of the main conductive layer. The cathode auxiliary electrode may be provided as the first source-drain conductive layer. The top portion may be provided as the second source-drain conductive layer. The cathode connection hole may include: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. The portion of the top portion exposed by the cathode connection hole may include an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer. The gap in the second common layer may be formed in the undercut structure of a portion of the top portion.

[0020] The substrate may further include: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer may further include: two or more auxiliary top portions disposed as a second source / drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surrounding the hole region; and one or more separation grooves located between the two or more auxiliary top portions and penetrating the first planarization layer. The portion of the edge of each of the two or more auxiliary top portions exposed by the one or more separation grooves may include an undercut structure in which the sub-conductive layer protrudes significantly more than the main conductive layer. The portion of the second common layer disposed in the hole peripheral region may be separated from the undercut structure of the two or more auxiliary top portions.

[0021] The cathode auxiliary electrode may be provided as the first source / drain conductive layer. The top portion may be provided on the second planarization layer and on the same layer as the anode electrode. The cathode connection hole may include: a first hole penetrating the pixel defining layer; and a second hole penetrating the second planarization layer and the first planarization layer. A portion of the top portion may protrude significantly more than the second hole. A gap in the second common layer may be formed in an undercut structure between the top portion and the second hole.

[0022] The cathode auxiliary electrode may be provided as a second source / drain conductive layer. The top portion may be provided on the second planarization layer and on the same layer as the anode electrode. The cathode connection hole may include: a first hole penetrating the pixel defining layer; and a second hole penetrating the second planarization layer. A portion of the top portion may protrude significantly more than the second hole. A gap in the second common layer may be formed in an undercut structure between the top portion and the second hole.

[0023] The circuit layer may further include a power auxiliary electrode, which is provided as the first source-drain conductive layer and is electrically connected to the cathode auxiliary electrode.

[0024] The circuit layer may further include an auxiliary insulating layer disposed on the interlayer insulating layer and overlapping the first source-drain conductive layer. Each of the interlayer insulating layer and the auxiliary insulating layer may include an inorganic insulating material. Each of the first planarization layer, the second planarization layer, and the pixel defining layer may include an organic insulating material. The cathode auxiliary electrode may be provided as the first source-drain conductive layer. The cathode connection hole may be connected to an additional connection hole that penetrates the pixel defining layer, the second planarization layer, and the first planarization layer, and may penetrate the auxiliary insulating layer. The top portion may be a portion of the first planarization layer that is disposed around the additional connection hole and protrudes much more than the auxiliary insulating layer. The gap in the second common layer may be formed in an undercut structure between the top portion and the auxiliary insulating layer.

[0025] According to the disclosed aspects, a display device is provided, which may include: a substrate including a display area in which a light-emitting area is provided; a circuit layer provided on the substrate; and a component layer provided on the circuit layer. The circuit layer may include: an interlayer insulating layer provided on the substrate; a first source-drain conductive layer provided on the interlayer insulating layer; a first planarization layer overlapping the first source-drain conductive layer; a second source-drain conductive layer provided on the first planarization layer; a second planarization layer overlapping the second source-drain conductive layer; and a cathode auxiliary electrode provided as one of the first source-drain conductive layer and the second source-drain conductive layer in a portion of a non-light-emitting area between the light-emitting areas of the display area. The component layer may include: an anode electrode provided in the light-emitting area; a pixel-defining layer provided in the non-light-emitting area and overlapping an edge of each of the anode electrodes; a first common layer provided on the anode electrode; a light-emitting layer provided on the first common layer; a second common layer provided on the pixel-defining layer and the light-emitting layer; and a cathode electrode provided on the second common layer. The portion of each top portion overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode can be exposed from the second common layer through the cathode connection hole. In the undercut structure formed by the top portion, a gap can be formed to separate the second common layer. The cathode electrode can be electrically connected to the cathode auxiliary electrode through the cathode connection hole and the gap between the second common layer.

[0026] The cathode auxiliary electrode may be provided as a first source / drain conductive layer. The top portion may be provided as a second source / drain conductive layer. The cathode connection hole may include: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion may protrude significantly more than the second hole. A gap in the second common layer may be formed in an undercut structure between the top portion and the second hole.

[0027] The substrate may further include: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer may further include: two or more auxiliary top portions disposed as a second source / drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surrounding the hole region; and one or more separation grooves located between the two or more auxiliary top portions and penetrating the first planarization layer. A portion of an edge of each of the two or more auxiliary top portions may protrude significantly beyond the one or more separation grooves. The portion of the second common layer disposed in the hole peripheral region may be separated from the undercut structure formed between the two or more auxiliary top portions and the one or more separation grooves.

[0028] The second source-drain conductive layer may include: a main conductive layer; and a sub-conductive layer disposed on the main conductive layer and comprising a metal material different from that of the main conductive layer. The cathode auxiliary electrode may be provided as the first source-drain conductive layer. The top portion may be provided as the second source-drain conductive layer. The cathode connection hole may include: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. The portion of the top portion exposed by the cathode connection hole may include an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer. The gap in the second common layer may be formed in the undercut structure of a portion of the top portion.

[0029] The substrate may further include: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer may further include: two or more auxiliary top portions disposed as a second source / drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surrounding the hole region; and one or more separation grooves located between the two or more auxiliary top portions and penetrating the first planarization layer. The portion of the edge of each of the two or more auxiliary top portions exposed by the one or more separation grooves may include an undercut structure in which the sub-conductive layer protrudes significantly more than the main conductive layer. The portion of the second common layer disposed in the hole peripheral region may be separated from the undercut structure of the two or more auxiliary top portions.

[0030] The light-emitting regions may include: a first light-emitting region emitting light of a first color; a second light-emitting region emitting light of a second color having a wavelength band lower than that of the first light-emitting region; and a third light-emitting region emitting light of a third color having a wavelength band lower than that of the second light-emitting region. The first light-emitting regions may be parallel to each other in a first direction. The second light-emitting regions may be parallel to each other in the first direction. Each of the third light-emitting regions may be adjacent to a portion of each of the first light-emitting regions and a portion of each of the second light-emitting regions in the first direction. The first and second light-emitting regions may be arranged alternately in a second direction intersecting the first direction. The third light-emitting regions may be parallel to each other in the second direction. A first spacing region having a first width may be provided between two or more third light-emitting regions that are parallel in the second direction among the third light-emitting regions, and a second spacing region having a second width greater than the first width may be provided between two or more third light-emitting regions and another two or more third light-emitting regions. A cathode auxiliary electrode may be provided in the second spacing region.

[0031] The third spacing region may be disposed on one side of the two or more third light emitting regions in the first direction. The cathode auxiliary electrode may also be disposed in the third spacing region.

[0032] The display device according to the embodiment may include a substrate, a circuit layer disposed on the substrate and including a cathode auxiliary electrode, and an element layer disposed on the circuit layer and including an anode electrode, a first common layer, a light emitting layer, a second common layer, and a cathode electrode.

[0033] According to an embodiment, a portion of each of the top portions overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode may be exposed through the cathode connection hole, and a gap separating the second common layer may be formed in the undercut structure formed by the top portions. The cathode electrode may be electrically connected to the cathode auxiliary electrode through the gap between the cathode connection hole and the second common layer.

[0034] According to the embodiment, the electrical connection between the cathode electrode and the cathode auxiliary electrode can be achieved through the undercut structure provided by the top portion without adding a mask process for partially removing the second common layer. Therefore, the cost and time required to manufacture a display device including the cathode auxiliary electrode can be reduced.

[0035] However, the effects according to the disclosed embodiments are not limited to those examples above, and various other effects are included therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings, in which: Figure 1is a schematic perspective view showing a display device according to an embodiment; Figure 2 It shows Figure 1 A schematic plan view of a display device; Figure 3 It is along Figure 2 A schematic cross-sectional view taken along line AA'; Figure 4 It shows Figure 2 A schematic plan view of part B of FIG. Figure 5 It shows Figure 4 A schematic diagram of an equivalent circuit of a light-emitting pixel driver; Figure 6 It shows Figure 5 a schematic cross-sectional view of a first transistor, a second transistor, a fourth transistor, and a sixth transistor and a light-emitting element; Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A schematic plan view of a cathode auxiliary electrode in part B of FIG. Figure 8 According to the embodiment of the invention Figure 7 A schematic cross-sectional view taken along line CC'; Figure 9 is a schematic plan view showing a display device according to another embodiment; Figure 10 It is along Figure 9 A schematic cross-sectional view taken along line D-D'; Figure 11 It shows Figure 9 A schematic plan view of a portion E of FIG. Figure 12 is based on Figure 8 Along the lines of Figure 11 A schematic cross-sectional view taken along line FF'; Figure 13 It shows Figure 12 An enlarged schematic diagram of part G; Figure 14 According to the embodiment of the invention Figure 7 A schematic cross-sectional view taken along line CC'; Figure 15 is based on Figure 14 Along the lines of Figure 11 A schematic cross-sectional view taken along line FF'; Figure 16 It shows Figure 15 An enlarged schematic diagram of part H; Figure 17 、 Figure 18 、 Figure 19and Figure 20 Each is according to an embodiment along Figure 7 A schematic cross-sectional view taken along line CC' of FIG. Figure 21 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Schematic plan view of the cathode auxiliary electrode in part B. DETAILED DESCRIPTION

[0037] The disclosed embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0038] In order to more clearly describe the disclosed embodiments, some of the components not related to the description may not be provided.

[0039] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0040] Furthermore, the phrase "in a plan view" refers to when viewing an object portion from above, and the phrase "in a schematic cross-sectional view" refers to when viewing a schematic cross-section taken by vertically cutting an object portion from the side. The term "superimposed" or variations thereof refers to that a first object can be above or below or to one side of a second object, or vice versa. In addition, the term "superimposed" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "not superimposed" may include meanings such as "spaced apart from" or "offset from" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may refer to that a first object can be directly or indirectly opposite to a second object. In the case where a third object is between the first and second objects, the first and second objects, although still facing each other, may be understood to be indirectly opposite to each other.

[0041] For ease of description, spatially relative terms such as "below," "under," "down," "above," "up," etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is turned over, a device that is "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0042] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms “comprises” and variations thereof, “having” and variations thereof, and / or “includes” and variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0043] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or to facilitate description and explanation thereof. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be named in a similar manner without departing from the spirit and scope disclosed herein.

[0044] As used herein, the terms "about," "approximately," and "substantially" are inclusive of the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0045] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or a disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0046] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the disclosure belongs. It will also be understood that, unless expressly defined in the specification, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0048] Figure 1 is a schematic perspective view showing a display device according to an embodiment. Figure 2 It shows Figure 1 Schematic plan view of a display device. Figure 3 It is along Figure 2 Schematic cross-sectional view taken along line AA'. Figure 4 It shows Figure 2 Schematic plan view of portion B of FIG.

[0049] Reference Figure 1 and Figure 2 The display device 100 is a device that displays moving images or still images and can be used as a display screen for each of various products (such as TVs, laptop computers, monitors, billboards, and Internet of Things (IOT) devices) and portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, or ultra mobile PCs (UMPCs)).

[0050] The display device 100 may be a light-emitting display device such as an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro-light-emitting display device using micro-LEDs or nano-LEDs (micro-LEDs or nano-LEDs). The following description will primarily focus on the fact that the display device 100 is an organic light-emitting display device. However, the disclosure is not limited thereto and may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0051] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved surface portions having a constant curvature or a variable curvature formed at its left and right distal ends. The display device 100 may be flexibly formed to be curved, bent, folded, or rolled.

[0052] like Figure 1 、 Figure 2 and Figure 3 As shown in , the display device 100 may include a substrate 110 .

[0053] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub-area SBA protruding from one side of the main area MA.

[0054] like Figure 2 As shown in FIG, the main area MA may include a display area DA disposed at a large portion of the center and a non-display area NDA disposed around the display area DA.

[0055] The display area DA may be formed in a rectangular plane having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined or selected curvature, or may be formed at right angles. The planar shape of the display area DA is not limited to a quadrilateral, and the display area DA may be formed in other polygonal, circular, or elliptical shapes.

[0056] The non-display area NDA may be disposed at an edge of the main area MA to surround the display area DA.

[0057] The sub-region SBA may be a region protruding from the non-display area NDA of the main region MA to one side in the second direction DR2 .

[0058] Figure 2 and Figure 3 The display device 100 is shown with a curved portion of the sub-area SBA.

[0059] like Figure 2 and Figure 3 As shown in , when a portion of the sub-area SBA is deformed into a curved shape, another portion of the sub-area SBA may be disposed on the rear surface of the substrate 110 opposite to the display surface.

[0060] Reference Figure 3 , the display device 100 according to the embodiment may include a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and an element layer 130 disposed on the circuit layer 120 .

[0061] The display device 100 according to the embodiment may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140 .

[0062] The display device 100 according to the embodiment may further include a polarizing layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0063] The display device 100 according to an embodiment may further include a cover window disposed on the polarizing layer 160 and a bracket disposed below the rear surface of the substrate 110. The cover window may face the substrate 110 and may be attached to the polarizing layer 160 or bonded to the bracket using a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The bracket may accommodate the substrate 110 and the circuit board 300.

[0064] The cover window can be made of an inorganic material such as glass, or can also be made of an organic material such as plastic or polymer material. The cover window can protect the touch sensor layer 150, the sealing layer 140, the element layer 130 and the circuit layer 120 from electrical and physical shocks to the display surface.

[0065] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, and rolled.

[0066] In other embodiments, the substrate 110 may be made of an insulating material such as glass.

[0067] The circuit layer 120 may include a conductive layer, one or more semiconductor layers, and an insulating layer interposed between the conductive layer and / or the one or more semiconductor layers. The circuit layer 120 may include transistors provided with one or more semiconductor layers and one or more conductive layers, and signal lines each provided with at least one of the conductive layers.

[0068] The element layer 130 may include a light emitting element that emits light according to a driving current applied from the circuit layer 120 .

[0069] The sealing layer 140 may cover the circuit layer 120 and the element layer 130 , and may block oxygen or moisture from penetrating into the element layer 130 .

[0070] The touch sensor layer 150 may be provided in the main area MA on the sealing layer 140. The touch sensor layer 150 may include a touch electrode for sensing a touch of a person or an object.

[0071] The polarizing layer 160 can prevent the reduction of image visibility due to reflection of external light by blocking external light reflected from the touch sensor layer 150, the sealing layer 140, the element layer 130 and the circuit layer 120, and the interface between the touch sensor layer 150, the sealing layer 140, the element layer 130 and the circuit layer 120.

[0072] The display driving circuit 200 may be provided as an integrated circuit (IC) chip.

[0073] The display driving circuit 200 may be mounted in the sub-area SBA of the substrate 110 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner, but is not limited thereto.

[0074] For example, the display driving circuit 200 may be attached to the circuit board 300 in a chip on film (COF) manner.

[0075] The display driving circuit 200 can be provided to the circuit layer ( Figure 3 120) data line ( Figure 5 DL in the supply data signal.

[0076] The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0077] The circuit board 300 may be bonded to a signal pad disposed at an edge of the sub-area SBA of the substrate 110 using a low-resistance, high-reliability material such as anisotropic conductive film or SAP, and may be electrically connected to the circuit layer 120 .

[0078] The display device 100 may further include a touch driving circuit 400 for driving the touch sensor layer 150 .

[0079] The touch driving circuit 400 may be provided as an integrated circuit (IC) chip and mounted on the circuit board 300 .

[0080] The touch driving circuit 400 may apply a touch driving signal to the driving electrodes provided in the touch sensor layer 150 , may receive a touch sensing signal from the touch node through the sensing electrode, and may sense a change in charge of the mutual capacitance based on the touch sensing signal.

[0081] The touch drive circuit 400 can determine whether a user has performed a touch, whether the user has approached the display device 100, etc. based on the touch sensing signal of the touch node. The user's touch refers to when an object such as a user's finger or a pen is in direct contact with the front surface of the display device 100. The user's approach refers to when an object such as a user's finger or a pen is positioned away from the front surface of the display device 100 (such as hovering).

[0082] The substrate 110 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0083] Reference Figure 4 , the display area DA of the substrate 110 of the display device 100 according to the embodiment may include the emission area EA. The display area DA may further include a non-emission area NEA disposed between the emission areas EA (see Figure 12 ).

[0084] Component layer ( Figure 3 130) may include light emitting elements ( Figure 5 and Figure 6 LE in ).

[0085] Circuit layer ( Figure 3 The display area DA may include light emitting pixel drivers EPD arranged in parallel with each other in the first direction DR1 and the second direction DR2 in the display area DA. The light emitting pixel drivers EPD may be electrically connected to the light emitting elements ( Figure 5 and Figure 6 LE in ).

[0086] The light emitting area EA may have a rectangular planar shape or a rhombus planar shape. However, this is only an example, and the planar shape of the light emitting area EA according to the embodiment is not limited to Figure 4 For example, the light emitting area EA may have a polygonal plan shape such as a square, a pentagon, or a hexagon, or a circular or elliptical plan shape including curved edges.

[0087] The light-emitting area EA may include a first light-emitting area EA1 that emits light of a first color in a predetermined or selected band, a second light-emitting area EA2 that emits light of a second color in a band lower than the band of the first color of light, and a third light-emitting area EA3 that emits light of a third color in a band lower than the band of the second color of light.

[0088] As an example, the first color may be red in a wavelength band of approximately 600 nm to approximately 750 nm, the second color may be green in a wavelength band of approximately 480 nm to approximately 560 nm, and the third color may be blue in a wavelength band of approximately 370 nm to approximately 460 nm.

[0089] The first light emitting areas EA1 may be arranged parallel to each other in the first direction DR1.

[0090] The second light emitting areas EA2 may be arranged parallel to each other in the first direction DR1.

[0091] Each of the third light emitting areas EA3 may be adjacent to a portion of the first light emitting area EA1 corresponding to the first light emitting area EA1 and a portion of the second light emitting area EA2 corresponding to the second light emitting area EA2 in the first direction DR1.

[0092] In the second direction DR2, the first light emitting areas EA1 and the second light emitting areas EA2 may be arranged alternately and parallel to each other.

[0093] In the second direction DR2, the third light emitting areas EA3 may be arranged parallel to each other.

[0094] Among the first, second, and third light emitting areas EA1, EA2, and EA3, the third light emitting area EA3 may be provided with the largest area, and the first light emitting area EA1 may be provided with the smallest area.

[0095] As an example, the first light-emitting area EA1, the second light-emitting area EA2 and the third light-emitting area EA3 may have the same or similar width in the first direction DR1, among the first light-emitting area EA1, the second light-emitting area EA2 and the third light-emitting area EA3, the third light-emitting area EA3 may have the largest width in the second direction DR2, and the first light-emitting area EA1 may have the smallest width in the second direction DR2.

[0096] A first spacing region having a first width ( Figure 7 GA1 in the third light emitting region EA3) may be disposed between two or more third light emitting regions EA3 parallel in the second direction DR2 among the third light emitting regions EA3 and have a second spacing region ( Figure 7 GA2 in the figure) may be disposed between the two or more third light emitting areas EA3 and another two or more third light emitting areas EA3.

[0097] The first spacer area ( Figure 7 GA1 in the second spacer region ( Figure 7 GA2 in the figure may be alternately arranged in the first direction DR1.

[0098] In this way, since the light-emitting area EA includes the first light-emitting area EA1, the second light-emitting area EA2 and the third light-emitting area EA3, the light-emitting pixel driver EPD may include a first light-emitting pixel driver EPD1 electrically connected to the light-emitting element LE of the first light-emitting area EA1, a second light-emitting pixel driver EPD2 electrically connected to the light-emitting element LE of the second light-emitting area EA2, and a third light-emitting pixel driver EPD3 electrically connected to the light-emitting element LE of the third light-emitting area EA3.

[0099] The pixels PX displaying each brightness and color may be provided by the first, second, and third light emitting areas EA1, EA2, and EA3 adjacent to each other among the light emitting areas EA.

[0100] In other words, the pixel PX may be a basic unit that displays various colors including white at a predetermined or selected brightness.

[0101] Each of the pixels PX may include at least one first light emitting area EA1, at least one second light emitting area EA2, and at least one third light emitting area EA3 adjacent to each other. Therefore, each of the pixels PX may display various colors by mixing the light emitted from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other.

[0102] Figure 5 It shows Figure 4 Schematic diagram of the equivalent circuit of the light-emitting pixel driver. Figure 5 , one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0103] For example, the anode electrode of the light emitting element LE may be electrically connected to the light emitting pixel driver EPD, and the second power ELVSS having a lower voltage level than the first power ELVDD may be applied to the cathode electrode of the light emitting element LE.

[0104] The capacitor Cel may be connected in parallel with the light emitting element LE, and represents parasitic capacitance between the anode electrode and the cathode electrode.

[0105] The circuit layer 120 may include a data line DL transmitting a data signal Vdata, a first power line VDL transmitting a first power ELVDD, a first initialization voltage line VIL transmitting a first initialization voltage VINT, and a second initialization voltage line VAIL transmitting a second initialization voltage VAINT.

[0106] The circuit layer 120 may further include a scan write line GWL transmitting a scan write signal GW, a scan initialization line GIL transmitting a scan initialization signal GI, an emission control line ECL transmitting an emission control signal EC, and a bias control line GBL transmitting a bias control signal GB.

[0107] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 generating a driving current for driving the light emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1 or the light emitting element LE, and pixel capacitors PC1 and PC2.

[0108] The first transistor T1 may be disposed between a first node N1 and a second node N2. The first node N1 may be electrically connected to a first electrode (eg, a source electrode) of the first transistor T1. The second node N2 may be electrically connected to a second electrode (eg, a drain electrode) of the first transistor T1.

[0109] The first pixel capacitor PC1 may be connected between the first power line VDL and a third node N3. The third node N3 may be electrically connected to the gate electrode of the first transistor T1.

[0110] For example, the gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first pixel capacitor PC1 .

[0111] Therefore, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged in the first power line VDL.

[0112] The second transistor T2 may be electrically connected between the data line DL and the first node N1 .

[0113] In other words, the second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL.

[0114] The second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL. The second pixel capacitor PC2 may be connected between the second transistor T2 and the third node N3.

[0115] For example, the first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0116] The third transistor T3 may be disposed between the second node N2 and the third node N3. For example, the third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of a gate control line GCL.

[0117] A voltage difference between the second node N2 and the third node N3 may be initialized by the turned-on third transistor T3 .

[0118] The fourth transistor T4 may be electrically connected between the first initialization voltage line VIL and the third node N3. For example, the fourth transistor T4 may be electrically connected between the gate electrode of the first transistor T1 and the first initialization voltage line VIL. The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0119] The potential of the third node N3 may be initialized by the turned-on fourth transistor T4.

[0120] The fifth transistor T5 may be electrically connected between the first node N1 and the first power line VDL.

[0121] The sixth transistor T6 may be electrically connected between the second node N2 and a fourth node N4. The fourth node N4 may be electrically connected to the anode electrode of the light emitting element LE.

[0122] For example, the fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0123] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element LE.

[0124] In other words, the first electrode (eg, source electrode) of the first transistor T1 can be electrically connected to the first power line VDL through the fifth transistor T5, and the second electrode (eg, drain electrode) of the first transistor T1 can be electrically connected to the anode electrode of the light emitting element LE through the sixth transistor T6.

[0125] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0126] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may be the voltage difference between the first power ELVDD and the data signal Vdata.

[0127] When a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., a gate-source voltage difference) is a threshold voltage or greater, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0128] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0129] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0130] The seventh transistor T7 may be electrically connected between the fourth node N4 and the second initialization voltage line VAIL. The seventh transistor T7 may be electrically connected between the anode electrode of the light emitting element LE and the second initialization voltage line VAIL. The seventh transistor T7 may be turned on by a bias control signal GB of a bias control line GBL.

[0131] The potential of the fourth node N4 may be initialized by the turned-on seventh transistor T7.

[0132] According to an embodiment, among the first to seventh transistors T1 to T7 , the third and fourth transistors T3 and T4 may be N-type MOSFETs, and the remaining transistors T1 , T2 , and T5 to T7 excluding the third and fourth transistors T3 and T4 may be P-type MOSFETs.

[0133] For example, among the first to seventh transistors T1 to T7 included in the light-emitting pixel driver EPD, the third transistor T3 and the fourth transistor T4 can be set as N-type MOSFETs, and the remaining transistors T1, T2 and T5 to T7 except the third transistor T3 and the fourth transistor T4 can be set as P-type MOSFETs.

[0134] Therefore, according to an embodiment, the circuit layer 120 may include a first semiconductor layer ( Figure 6 CH1, E11, E21, CH2, E12, E22, CH6, E16 and E26) and the second semiconductor layer ( Figure 7 CH4, E14 and E24 in the diet).

[0135] The first semiconductor layer may include a channel portion, a first electrode portion, and a second electrode portion of each of the P-type MOSFETs (i.e., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) of each of the first to seventh transistors T1 to T7 of the light-emitting pixel driver (EPD). In each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the channel portion may overlap with the gate electrode. In each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, the first electrode portion and the second electrode portion may be connected to both ends of the channel portion. The first electrode portion may be the first electrode of the transistor, and the second electrode portion may be the second electrode of the transistor.

[0136] The second semiconductor layer may include a channel portion, a first electrode portion, and a second electrode portion of each of the N-type MOSFETs (i.e., the third transistor T3 and the fourth transistor T4) of each of the first to seventh transistors T1 to T7 in the light-emitting pixel driver (EPD). In the third transistor T3 and the fourth transistor T4, the channel portion may be disposed between the first and second gate electrodes that overlap each other, and may overlap the first and second gate electrodes. In each of the third transistor T3 and the fourth transistor T4, the first and second electrode portions may be connected to both ends of the channel portion. The first electrode portion may be a first electrode, and the second electrode portion may be a second electrode.

[0137] Figure 6 It shows Figure 5 Schematic cross-sectional view of a first transistor, a second transistor, a fourth transistor, and a sixth transistor and a light emitting element.

[0138] Reference Figure 6 , the display device 100 according to the embodiment may include a substrate 110 , a circuit layer 120 on the substrate 110 , and an element layer 130 on the circuit layer 120 .

[0139] The display device 100 may further include a sealing layer 140 on the element layer 130 .

[0140] According to an embodiment, the circuit layer 120 may include an interlayer insulating layer 126 disposed on the substrate 110, a first source-drain conductive layer ANCE1, CNE2 and DCE disposed on the interlayer insulating layer 126, a first planarization layer 127 covering the first source-drain conductive layer, a second source-drain conductive layer DL and ANCE2 disposed on the first planarization layer 127, and a second planarization layer 128 covering the second source-drain conductive layer.

[0141] According to an embodiment, the circuit layer 120 may further include first semiconductor layers CH1, E11, E21, CH2, E12, E22, CH6, E16, and E26 disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layers, first gate conductive layers G1, G2, and G6 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layers, second gate conductive layers CAE and LB2 disposed on the second gate insulating layer 123, an additional interlayer insulating layer 124 covering the second gate conductive layers, second semiconductor layers CH4, E14, and E24 disposed on the additional interlayer insulating layer 124, a third gate insulating layer 125 covering the second semiconductor layers, and a third gate conductive layer G4 disposed on the third gate insulating layer 125. In this case, the interlayer insulating layer 126 may cover the third gate conductive layer G4 on the third gate insulating layer 125.

[0142] According to an embodiment, the circuit layer 120 may further include a buffer layer 121 covering the substrate 110. In this case, the first semiconductor layer may be provided on the buffer layer 121. The buffer layer 121 may cover the first light blocking portion LB1 on the substrate 110.

[0143] The first light blocking portion LB1 may overlap the channel portion CH1 of the first transistor T1 .

[0144] As mentioned above Figure 5 As described above, the circuit layer 120 may include light emitting pixel drivers EPDs each electrically connected to the light emitting elements LE disposed in the light emitting area EA and lines transmitting various signals and voltages to the light emitting pixel drivers EPDs.

[0145] The light emitting pixel driver EPD may include a first transistor T1 and two or more transistors T2 to T7 electrically connected to the first transistor T1 or the light emitting element LE.

[0146] like Figure 6 As shown in FIG, according to an embodiment, the first transistor T1 may include a channel portion CH1 disposed in a first semiconductor layer on a substrate 110, first and second electrode portions E11 and E21, and a gate electrode G1 disposed in a first gate conductive layer on a first gate insulating layer 122.

[0147] The first electrode portion E11 may be connected to one side of the channel portion CH1 , and the second electrode portion E21 may be connected to the other side of the channel portion CH1 .

[0148] The first and second electrode portions E11 and E21 may be doped at a higher concentration than the channel portion CH1 .

[0149] The gate electrode G1 may overlap the channel portion CH1 .

[0150] Likewise, the second transistor T2 may include a channel portion CH2 disposed in the first semiconductor layer on the substrate 110 , first and second electrode portions E12 and E22 , and a gate electrode G2 disposed in the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0151] The sixth transistor T6 may include a channel portion CH6 disposed in the first semiconductor layer on the substrate 110 , first and second electrode portions E16 and E26 , and a gate electrode G6 disposed in the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0152] The first electrode portion E12 of the second transistor T2 may be electrically connected to the data line DL through the data link electrode DCE.

[0153] The data connection electrode DCE may be disposed in the first source-drain conductive layer on the interlayer insulating layer 126 and may be electrically connected to the first electrode portion E12 of the second transistor T2 through a data auxiliary connection hole DCAH. The data auxiliary connection hole DCAH may penetrate the interlayer insulating layer 126, the third gate insulating layer 125, the additional interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0154] The data line DL may be disposed in the second source drain conductive layer on the first planarization layer 127 and may be electrically connected to the data link electrode DCE through a data connection hole DCH penetrating the first planarization layer 127 .

[0155] The second electrode portion E22 of the second transistor T2 may be connected to the first electrode portion E11 of the first transistor T1 .

[0156] The second electrode portion E21 of the first transistor T1 may be connected to the first electrode portion E16 of the sixth transistor T6 .

[0157] The second electrode portion E26 of the sixth transistor T6 may be electrically connected to the anode electrode 131 through the first and second anode connection electrodes ANCE1 and ANCE2 .

[0158] The first anode connection electrode ANCE1 may be disposed in the first source drain conductive layer on the interlayer insulating layer 126 and may be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode contact hole ANCH1 .

[0159] The first anode contact hole ANCH1 may penetrate the interlayer insulating layer 126 , the third gate insulating layer 125 , the additional interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0160] The second anode connection electrode ANCE2 may be disposed in the second source drain conductive layer on the first planarization layer 127 and may be electrically connected to the first anode connection electrode ANCE1 through a second anode contact hole ANCH2 penetrating the first planarization layer 127 .

[0161] The anode electrode 131 may be disposed on the second planarization layer 128 and may be electrically connected to the second anode connection electrode ANCE2 through a third anode contact hole ANCH3 penetrating the second planarization layer 128 .

[0162] According to an embodiment, since the fifth transistor ( Figure 5 T5 in) and the seventh transistor ( Figure 5 The first transistor T1, the second transistor T2, and the sixth transistor T6 may have substantially the same structure as that of the first transistor T1, the second transistor T2, and the sixth transistor T6, and thus redundant descriptions will be omitted below.

[0163] The first gate conductive layer on the first gate insulating layer 122 may include a gate electrode of each of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 .

[0164] The first gate conductive layer on the first gate insulating layer 122 may further include a scan write line GWL electrically connected to the gate electrode G2 of the second transistor T2 and a bias control line GBL electrically connected to the gate electrode of the seventh transistor T7 .

[0165] The first gate conductive layer may further include a scan initialization line GIL extending in the first direction DR1.

[0166] The first gate conductive layer may further include an emission control line ECL electrically connected to the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 .

[0167] According to an embodiment, the circuit layer 120 may further include a capacitor electrode CAE overlapping the gate electrode G1 of the first transistor T1 .

[0168] The capacitor electrode CAE may be disposed in the second gate conductive layer on the second gate insulating layer 123 .

[0169] The capacitor electrode CAE may be electrically connected to the first power line ( Figure 5As an example, the first power line VDL may be provided in the second gate conductive layer on the second gate insulating layer 123 , and the capacitor electrode CAE may be provided as a portion of the first power line VDL.

[0170] The first pixel capacitor PC1 may be provided at a position between the gate electrode G1 of the first transistor T1 and the first power line ( Figure 5 between the VDL in the

[0171] According to an embodiment, unlike the first transistor T1 , the second transistor T2 , and the sixth transistor T6 which are P-type MOSFETs, the fourth transistor T4 may be an N-type MOSFET.

[0172] Therefore, the fourth transistor T4 may include a channel portion CH4 disposed in the second semiconductor layer on the additional interlayer insulating layer 124, a first electrode portion E14 and a second electrode portion E24, and a gate electrode G4 disposed in the third gate conductive layer on the third gate insulating layer 125 and overlapping the channel portion CH4.

[0173] The fourth transistor T4 may further include a second light blocking portion LB2 disposed under and overlapping the channel portion CH4 .

[0174] The second light blocking portion LB2 may be a bottom gate electrode electrically connected to the gate electrode G4 .

[0175] As an example, the second light blocking portion LB2 may be a portion of the scan initialization line GIL.

[0176] The scan initialization line GIL may be disposed in the second gate conductive layer on the second gate insulating layer 123 .

[0177] According to an embodiment, since the third transistor T3 may have substantially the same structure as the fourth transistor T4 , redundant descriptions will be omitted below.

[0178] The first electrode portion E14 of the fourth transistor T4 may be electrically connected to the first initialization voltage line ( Figure 5 in VIL).

[0179] The second connection electrode CNE2 may be disposed in the first source-drain conductive layer on the interlayer insulating layer 126 .

[0180] The second connection electrode CNE2 may be electrically connected to the first electrode portion E14 of the fourth transistor T4 within the second semiconductor layer on the additional interlayer insulating layer 124 through the second connection hole CNH12 .

[0181] The element layer 130 may be disposed on the circuit layer 120 and may include light emitting elements LE corresponding to the light emitting areas EA, respectively.

[0182] Each of the light emitting elements LE may include an anode electrode 131 and a cathode electrode 134 facing each other, and a light emitting layer 133 disposed between the anode electrode 131 and the cathode electrode 134. Each of the light emitting elements LE may also include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133, and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134.

[0183] For example, the element layer 130 may include an anode electrode 131 arranged in the light-emitting area EA, a pixel defining layer 132 arranged in the non-light-emitting area NEA between the light-emitting areas EA and covering the edge of the anode electrode 131, a first common layer 135 arranged on the anode electrode 131, a light-emitting layer 133 arranged on the first common layer 135, a second common layer 136 arranged on the light-emitting layer 133 and the pixel defining layer 132, and a cathode electrode 134 arranged on the second common layer 136.

[0184] The anode electrode 131 may be provided in each of the emission areas EA and electrically connected to one emission pixel driver EPD of the circuit layer 120. Such an anode electrode 131 may be referred to as a pixel electrode.

[0185] The anode electrode 131 may be electrically connected to the second anode connection electrode ANCE2 through a third anode contact hole ANCH3 penetrating the second planarization layer 128 .

[0186] The first common layer 135 may include an organic material having a hole transport property or a hole injection property.

[0187] The light emitting layer 133 may include an organic light emitting material that converts electron-hole pairs into light.

[0188] The second common layer 136 may include an organic material having electron transport properties or electron injection properties.

[0189] The cathode electrode 134 may be entirely disposed in the display area DA including the emission area EA. The second power ELVSS may be commonly applied to the cathode electrodes 134. Such cathode electrodes 134 may be referred to as a common electrode.

[0190] The sealing layer 140 may be disposed on the circuit layer 120 and cover the element layer 130 .

[0191] As an example, the sealing layer 140 may include a first sealing layer 141 disposed on the element layer 130 and made of an inorganic insulating material, a second sealing layer 142 disposed on the first sealing layer 141, overlapping the element layer 130 and made of an organic insulating material, and a third sealing layer 143 disposed on the first sealing layer 141, covering the second sealing layer 142 and made of an inorganic insulating material.

[0192] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Schematic plan view of the cathode auxiliary electrode in part B. Figure 8 According to the embodiment of the invention Figure 7 Schematic cross-sectional view taken along line CC'.

[0193] Reference Figure 7 , the circuit layer 120 of the display device 100 according to the embodiment may include a cathode auxiliary electrode CASE disposed in a portion of the non-emission area NEA between the emission areas EA.

[0194] The first spacing area GA1 having a first width may be disposed between two or more third light-emitting areas EA31 and EA32 and between the third light-emitting areas EA33 and EA34 that are parallel in the second direction DR2 among the third light-emitting areas EA3. A second spacing area GA2 having a second width greater than the first width may be disposed between the two or more third light-emitting areas EA31 and EA32 and another two or more third light-emitting areas EA33 and EA34.

[0195] For example, the non-luminous area NEA may include a first spacing area GA1 and a second spacing area GA2, and the first spacing area GA1 with a first width is arranged between two or more third luminous areas EA31 and EA32 and between the third luminous area EA33 and the third luminous area EA34 parallel to the second direction DR2, and the second spacing area GA2 is arranged between the two or more third luminous areas EA31 and EA32 and another two or more third luminous areas EA33 and EA34.

[0196] The cathode auxiliary electrode CASE may be disposed in the second spacing area GA2 having a relatively wide second width.

[0197] The cathode auxiliary electrode CASE may be disposed in the display area DA and may be electrically connected to the cathode auxiliary electrode CASE for transmitting the second power ( Figure 5 The second power line (ELVSS) Figure 5 in VSL).

[0198] Second power line ( Figure 5VSL) can be set to the first gate insulating layer ( Figure 6 122) on the first gate conductive layer, on the second gate insulating layer ( Figure 6 123) on the second gate conductive layer and on the third gate insulating layer ( Figure 6 At least one of the third gate conductive layers 125).

[0199] In other embodiments, the second power line ( Figure 5 VSL) can be used on the substrate ( Figure 6 110) on the first light blocking portion ( Figure 6 LB1 in the same layer.

[0200] Reference Figure 8 A portion of each of the roof portions RF overlapping one side of the cathode auxiliary electrode CASE and the cathode auxiliary electrode CASE may be exposed from the second common layer 136 through the cathode connection hole CTCH.

[0201] In the undercut structure UC caused by the top portion RF, a gap separating the second common layer 136 may be formed.

[0202] For example, a portion of the second common layer 136 overlapping the cathode connection hole CTCH may include a first separation portion 1361 disposed on the cathode auxiliary electrode CASE and a second separation portion 1362 contacting the top portion RF and spaced apart from the first separation portion 1361 .

[0203] In other words, the second common layer 136 can be divided into the first partition portion 1361 and the second partition portion 1362 by the undercut structure UC formed by the top portion RF and between the first partition portion 1361 and the second partition portion 1362, and the cathode auxiliary electrode CASE can be formed through the gap between the first partition portion 1361 and the second partition portion 1362.

[0204] Therefore, the cathode electrode 134 may be electrically connected to the cathode auxiliary electrode CASE by making contact with the cathode auxiliary electrode CASE through the gap of the second common layer 136 and the cathode connection hole CTCH.

[0205] The top portion RF may overlap only a portion of the edge of the cathode auxiliary electrode CASE. In this manner, the second common layer 136 (i.e., the first partition 1361) and the cathode electrode 134 overlapping the cathode auxiliary electrode CASE may extend to the emission area EA through a portion of the side surface of the cathode connection hole CTCH where the top portion RF does not protrude.

[0206] According to the embodiment, Figure 8As shown in FIG, the cathode auxiliary electrode CASE may be provided as a first source-drain conductive layer on the interlayer insulating layer 126 .

[0207] The top portion RF may be provided as a second source-drain conductive layer on the first planarization layer 127 .

[0208] In this case, the cathode connection hole CTCH may include a first hole H1 penetrating the pixel defining layer 132 and the second planarization layer 128 and a second hole H2 penetrating the first planarization layer 127 .

[0209] A portion of the second hole H2 may be disposed below the top portion RF and may have a more recessed shape than the top portion RF. For example, when a portion of the top portion RF protrudes more than the second hole H2, an undercut structure UC may be formed.

[0210] A gap in the second common layer 136 (ie, between the first and second separation parts 1361 and 1362 ) may be formed in the undercut structure UC between the top portion RF and the second hole H2 .

[0211] Figure 9 is a schematic plan view showing a display device according to other embodiments. Figure 10 It is along Figure 9 A schematic cross-sectional view taken along line DD'. Figure 11 It shows Figure 9 Schematic plan view of portion E of . Figure 12 is based on Figure 8 Along the lines of Figure 11 Schematic cross-sectional view taken along line FF'. Figure 13 It shows Figure 12 An enlarged schematic diagram of part G.

[0212] Reference Figure 9 , the substrate 110 of the display device 100 ′ according to other embodiments may include a hole area HLA surrounded by the display area DA and a hole peripheral area PHA disposed between the hole area HLA and the display area DA.

[0213] Reference Figure 10 , the display device 100 ′ according to other embodiments may further include light-transmitting holes TRH formed in the hole area HLA.

[0214] The light transmitting hole TRH may form a light path for light sensing of the optical device 500 disposed under the hole area HLA of the display device 100 ′.

[0215] The light transmission holes TRH may penetrate the substrate 110 , the circuit layer 120 , the element layer 130 , and the sealing layer 140 .

[0216] Reference Figure 11 , the circuit layer of the display device 100 ' according to other embodiments ( Figure 12 120) may include two or more auxiliary top portions ASRF and one or more separation grooves SPG, the two or more auxiliary top portions ASRF are disposed in the hole peripheral area PHA and sequentially surround the hole area HLA, and the one or more separation grooves SPG are positioned between the two or more auxiliary top portions ASRF.

[0217] As mentioned above Figure 6 As described, due to the component layer ( Figure 10 The second public layer (130) Figure 6 136 in the display area DA) is provided in the entire display area DA, so the second common layer 136 may also be provided in the hole peripheral area PHA surrounded by the display area DA.

[0218] Therefore, a permeation path for oxygen or moisture may be easily formed through the light transmission holes TRH in the hole area HLA and the second common layer 136 in the hole peripheral area PHA.

[0219] In order to prevent such a problem, according to other embodiments, when two or more auxiliary top portions ASRF and one or more separation grooves SPG are provided in the hole peripheral area PHA, the second common layer 136 in the hole peripheral area PHA may be separated. In this way, the passage of oxygen or moisture through the second common layer ( Figure 6 136) of penetration.

[0220] The display device 100 ′ according to other embodiments may further include one or more hole peripheral dams HPDM disposed between the two or more auxiliary top portions ASRF of the hole peripheral area PHA and the hole area HLA and surrounding the hole area HLA.

[0221] One or more hole peripheral dams HPDM may be a barrier sealing layer ( Figure 10 The second sealing layer (140) includes an organic material Figure 6 142) diffuses into the barrier in the hole area HLA.

[0222] Circuit layer ( Figure 10 120) may include light-emitting pixel drivers EPD arranged in the first direction DR1 and the second direction DR2 in the display area DA and transmitting data signals to the light-emitting pixel drivers EPD ( Figure 5 The data line DL includes a Vdata in the first direction and extends in the second direction DR2.

[0223] According to other embodiments, since the light emitting pixel driver EPD is also disposed in the display area DA adjacent to the hole peripheral area PHA, the data line DL may include a hole intersection data line HIDL intersecting the hole area HLA or the hole peripheral area PHA.

[0224] For example, the data lines DL may include a hole-intersecting data line HIDL intersecting the hole area HLA or the hole peripheral area PHA and a normal data line NDL except the hole-intersecting data line HIDL.

[0225] Each of the hole intersection data lines HIDL may include a first hole separation line HINL1 on one side facing the hole peripheral area PHA in the second direction DR2, a second hole separation line HINL2 on the other side facing the hole peripheral area PHA in the second direction DR2, and a hole bypass line HDE arranged in the hole peripheral area PHA and electrically connected between the first hole separation line HINL1 and the second hole separation line HINL2.

[0226] The hole detour line HDE may be disposed between the two or more auxiliary top portions ASRF and the display area DA, and may be in the form of a curved arc extending parallel to peripheries of the two or more auxiliary top portions ASRF.

[0227] Each of the normal data lines NDL may be provided in a form that does not intersect the hole area HLA and the hole peripheral area PHA and does not include a bent hole detour line HDE provided in the hole peripheral area PHA.

[0228] According to other embodiments, the circuit layer 120 may further include a dummy light-emitting pixel driver DEPD disposed closest to the hole peripheral area PHA.

[0229] Except for the dummy pixel driver DEPD, which is not electrically connected to the element layer ( Figure 10 130) of the light emitting element ( Figure 5 Except for the LE in , they can have the same structure as the light-emitting pixel driver EPD.

[0230] When the dummy light-emitting pixel driver DEPD is arranged around the hole peripheral area PHA, the light-transmitting hole ( Figure 10 Therefore, the physical or chemical impact generated during the process of setting the light-transmitting hole ( Figure 10 There is a possibility of damaging the light-emitting pixel driver EPD during the TRH process.

[0231] like Figure 12As shown in , according to other embodiments, two or more auxiliary top portions ASRF and one or more separation grooves SPG may be provided in the sealing auxiliary area ENAA of the hole peripheral area PHA spaced apart from each of the hole area HLA and the display area DA.

[0232] and the top portion of the display area DA ( Figure 8 Like the RF in FIG, the auxiliary top portion ASRF of the hole peripheral area PHA may also be set as a second source-drain conductive layer on the first planarization layer 127.

[0233] and the cathode connection hole of the display area DA ( Figure 8 The second hole of CTCH Figure 8 Like H2 in FIG, each of the one or more separation grooves SPG may penetrate the first planarization layer 127 .

[0234] In this way, the top portion of the display area DA ( Figure 8 RF) and cathode connection hole ( Figure 8 The CTCH in the display area DA can be provided together with the auxiliary top portion ASRF and the separation groove SPG of the hole peripheral area PHA. As a result, since the top portion ( Figure 8 RF) and cathode connection hole ( Figure 8 The CTCH in the top portion ( Figure 8 RF) and cathode connection hole ( Figure 8 The time and cost required for display device 100' of CTCH in FIG.

[0235] like Figure 13 As shown in , in the direction in which the two or more auxiliary top portions ASRF face each other (i.e., the direction between the hole area HLA and the display area DA), at least a portion of an edge of each of the two or more auxiliary top portions ASRF may protrude much further than the one or more separation grooves SPG.

[0236] For example, in a direction in which the two or more auxiliary top portions ASRF face each other, a width of a spaced region between the two or more auxiliary top portions ASRF may be smaller than a width of the one or more separation grooves SPG.

[0237] As a result, in a spaced region between the two or more auxiliary top portions ASRF, an undercut structure UC in which edges of the two or more auxiliary top portions ASRF protrude more than the one or more separation grooves SPG may be formed.

[0238] Since the second common layer 136 and the cathode electrode 134 of the element layer 130 are entirely disposed in the display area DA, the second common layer 136 and the cathode electrode 134 may also be disposed in the hole peripheral area PHA surrounded by the display area DA.

[0239] The second common layer 136 may be disposed on the light emitting layer 133 , the pixel defining layer 132 , and the spacer layer 132 ′ in the display area DA.

[0240] In the case where the second planarization layer 128 extends to the hole peripheral area PHA and covers two or more auxiliary top portions ASRF, the circuit layer 120 may further include an auxiliary separation groove ASSG overlapping the one or more separation grooves SPG and penetrating the second planarization layer 128 .

[0241] The pixel defining layer 132 may be disposed in the display area DA and may not extend to the hole peripheral area PHA. Therefore, the second common layer 136 may be disposed on the second planarization layer 128 in the hole peripheral area PHA.

[0242] In other embodiments, the second planarization layer 128 may not extend to the hole peripheral area PHA. In this case, the second common layer 136 may be disposed on the two or more auxiliary top portions ASRF in the sealing auxiliary area ENAA of the hole peripheral area PHA.

[0243] When the one or more separation grooves SPG are provided with a width greater than a gap between the two or more auxiliary top portions ASRF, an undercut structure UC may be formed between the two or more auxiliary top portions ASRF and the one or more separation grooves SPG.

[0244] Therefore, in the process of providing the second common layer 136, since the auxiliary top portion ASRF protrudes more than the separation groove SPG, it may be difficult for the organic material of the second common layer 136 to be connected from the side surface of the auxiliary top portion ASRF to the side surface of the separation groove SPG. For example, the portion of the second common layer 136 provided in the hole peripheral area PHA may be separated by the undercut structure UC.

[0245] In other words, the portion of the second common layer 136 disposed in the hole peripheral area PHA may include two or more third partition portions 1363 and one or more fourth partition portions 1364, the two or more third partition portions 1363 being overlapped with the two or more auxiliary top portions ASRF, and the one or more fourth partition portions 1364 being disposed in the one or more separation grooves SPG and spaced apart from the two or more third partition portions 1363.

[0246] The data line DL may be disposed in the second source-drain conductive layer on the first planarization layer 127 .

[0247] The data lines DL may include hole intersection data lines HIDL and normal data lines NDL. The hole intersection data lines HIDL may include first hole separation lines HINL1, second hole separation lines ( Figure 11 HINL2) and hole detour line HDE.

[0248] The hole detour line HDE of the hole intersection data line HIDL may be disposed in the detour area DETA between the display area DA and the sealing auxiliary area ENAA in the hole peripheral area PHA.

[0249] According to other embodiments, the display device 100 ′ may include one or more hole peripheral dams HPDM disposed between the two or more auxiliary top portions ASRF of the hole peripheral area PHA and the hole area HLA and surrounding the hole area HLA.

[0250] For example, one or more hole peripheral dams HPDM may be sequentially disposed in the hole peripheral dam area HDMA between the sealing auxiliary area ENAA and the hole area HLA in the hole peripheral area PHA.

[0251] Each of the one or more hole peripheral dams HPDM may include two or more dam layers.

[0252] Each of the two or more dam layers may be disposed at the same layer as one of the first planarization layer 127 , the second planarization layer 128 , the pixel defining layer 132 , and the spacer layer 132 ′.

[0253] As an example, the one or more hole peripheral dams HPDM may include a first hole peripheral dam HPDM1 adjacent to the sealing assisting area ENAA and a second hole peripheral dam HPDM2 disposed between the first hole peripheral dam HPDM1 and the hole area HLA.

[0254] The first hole peripheral dam HPDM1 may include a first dam layer DML11 on the same layer as the first planarization layer 127 , a second dam layer DML21 on the same layer as the second planarization layer 128 , a third dam layer DML31 on the same layer as the pixel defining layer 132 , and a fourth dam layer DML41 on the same layer as the spacer layer 132 ′.

[0255] The second hole peripheral dam HPDM2 may include a first dam layer DML12 at the same layer as the second planarization layer 128 , a second dam layer DML22 at the same layer as the pixel defining layer 132 , and a third dam layer DML32 at the same layer as the spacer layer 132 ′.

[0256] The sealing layer 140 may include a first sealing layer 141 disposed on the element layer 130 , a second sealing layer 142 disposed on the first sealing layer 141 and overlapping the display area DA, and a third sealing layer 143 disposed on the first sealing layer 141 and covering the second sealing layer 142 .

[0257] The second sealing layer 142 may extend to the one or more hole peripheral dams HPDM and include an organic insulating material spaced apart from the hole area HLA.

[0258] Each of the first sealing layer 141 and the third sealing layer 143 may include an inorganic insulating material.

[0259] Since the second sealing layer 142 extends to the one or more hole peripheral dams HPDM, the first sealing layer 141 and the third sealing layer 143 may contact each other in a junction area JNA between the hole area HLA and the one or more hole peripheral dams HPDM of the hole peripheral area PHA.

[0260] The circuit layer 120 may include a buffer layer ( Figure 6 121 in the buffer layer 121), a first gate insulating layer ( Figure 6 122 in), a second gate insulating layer ( Figure 6 123 in), provided in the second gate insulating layer ( Figure 6 123) on the additional interlayer insulating layer ( Figure 6 124) and provided in an additional interlayer insulating layer ( Figure 6 The third gate insulating layer (124) on Figure 6 An interlayer insulating layer 126 may be provided on the third gate insulating layer 125 .

[0261] Each of the buffer layer 121 , the first gate insulating layer 122 , the second gate insulating layer 123 , the additional interlayer insulating layer 124 , the third gate insulating layer 125 , and the interlayer insulating layer 126 may include an inorganic insulating material.

[0262] Each of the second common layer 136 and the cathode electrode 134 may be entirely disposed in the display area DA.

[0263] Each of the first sealing layer 141 and the third sealing layer 143 may include an inorganic insulating material and may be entirely disposed in the display area DA.

[0264] Therefore, the light-transmitting hole TRH of the hole area HLA can penetrate the third sealing layer 143, the first sealing layer 141, the cathode electrode 134, the second common layer 136, the interlayer insulating layer 126, the third gate insulating layer 125, the additional interlayer insulating layer 124, the second gate insulating layer 123, the first gate insulating layer 122, the buffer layer 121 and the substrate 110.

[0265] Figure 14 According to the embodiment of the invention Figure 7 Schematic cross-sectional view taken along line CC'.

[0266] Since, in addition to the undercut structure UC causing a gap in the second common layer 136, the undercut structure UC is formed between the sub-conductive layer SBL and the main conductive layer MNL of the top portion RF, according to Figure 14 The display device 100 of the embodiment shown in FIG. Figure 7 and Figure 8 The display devices 100 of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0267] like Figure 14 As shown in , the second source-drain conductive layer on the first planarization layer 127 may include a main conductive layer MNL and a sub-conductive layer SBL disposed on the main conductive layer MNL and including a metal material different from that of the main conductive layer MNL.

[0268] The main conductive layer MNL may include a low-resistance metal material such as aluminum (Al), copper (Cu), or silver (Ag).

[0269] The sub-conductive layer SBL may include a metal material that can block the metal material of the main conductive layer MNL from diffusing into the organic insulating material of the second planarization layer 128 and have a higher etching rate than the main conductive layer MNL. As an example, the sub-conductive layer SBL may include titanium (Ti).

[0270] The second source-drain conductive layer may further include a bottom layer BTL disposed under the main conductive layer MNL.

[0271] The bottom BTL may include a metal material that can block the metal material of the main conductive layer MNL from diffusing into the organic insulating material of the first planarization layer 127 and have a higher etching rate than the main conductive layer MNL. As an example, the bottom BTL may include titanium (Ti).

[0272] In this case, the cathode connection hole CTCH may include a first hole H1 penetrating the pixel defining layer 132 and the second planarization layer 128 and a second hole H2 penetrating the first planarization layer 127 .

[0273] The cathode connection hole CTCH may expose an edge of the top portion RF.

[0274] For example, the first hole H1 may contact the side surface of the sub-conductive layer SBL, and the second hole H2 may contact the side surface of the bottom layer BTL.

[0275] Because the sub-conductive layer SBL protrudes much more than the main conductive layer MNL, one side of the top portion RF exposed by the cathode connection hole CTCH may include an undercut structure UC.

[0276] A gap in the second common layer 136 (ie, between the first and second separation parts 1361 and 1362 ) may be formed in the undercut structure UC of the top portion RF.

[0277] For example, the second separation portion 1362 extending along the first hole H1 may not extend to the side surface of the main conductive layer MNL that is concave compared to the side surface of the sub-conductive layer SBL and may be provided only to the side surface of the sub-conductive layer SBL.

[0278] As an example, the undercut structure UC of the top portion RF can be formed by the following processes: forming a hole that penetrates the second planarization layer 128 and exposes one side of the top portion RF; and partially removing the main conductive layer MNL on one side of the top portion RF using an etching material for setting the anode electrode 131 before the process of setting the anode electrode 131.

[0279] Figure 15 is based on Figure 14 Along the lines of Figure 11 Schematic cross-sectional view taken along line FF'. Figure 16 It shows Figure 15 An enlarged schematic diagram of part H.

[0280] Since, except that a portion of an edge of each of the two or more auxiliary top portions ASRF exposed by the one or more separation grooves SPG includes an undercut structure UC in which the sub conductive layer SBL protrudes more than the main conductive layer MNL and a portion of the second common layer 136 disposed in the hole peripheral area PHA is separated from the undercut structure UC of the two or more auxiliary top portions ASRF, Figure 15 and Figure 16 The display device 100′ of another embodiment shown in FIG. Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 The display devices 100 ′ of other embodiments shown in FIG. 1 are substantially the same, and thus redundant descriptions will be omitted below.

[0281] according to Figure 15 and Figure 16In another embodiment, the two or more auxiliary top portions ASRF and the one or more separation grooves SPG disposed in the hole peripheral area PHA may be aligned with the top portion ( Figure 14 RF) and cathode connection hole ( Figure 14 As a result, the time and cost required to manufacture the display device 100' can be reduced.

[0282] according to Figure 15 and Figure 16 In another embodiment, a portion of the second common layer 136 disposed in the hole peripheral area PHA may include two or more third partition portions 1363 and one or more fourth partition portions 1364, the two or more third partition portions 1363 extending to the sub-conductive layers SBL of the two or more auxiliary top portions ASRF, and the one or more fourth partition portions 1364 disposed in the one or more separation grooves SPG and spaced apart from the two or more third partition portions 1363.

[0283] Figure 17 、 Figure 18 、 Figure 19 and Figure 20 Each is according to an embodiment along Figure 7 Schematic cross-sectional view taken along line CC'.

[0284] Since, except that the top portion RF is disposed on the second planarization layer 128 and is in the same layer as the anode electrode 131, the first hole H1 of the cathode connection hole CTCH penetrates the pixel defining layer 132, and the second hole H2 of the cathode connection hole CTCH penetrates the second planarization layer 128 and the first planarization layer 127, according to Figure 17 The display device 100 of the embodiment shown in FIG. Figure 7 and Figure 8 The display devices 100 of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0285] Since the cathode auxiliary electrode CASE is provided as the second source-drain conductive layer on the first planarization layer 127, according to Figure 18 The display device 100 of the embodiment shown in FIG. Figure 17 The display devices 100 of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0286] Since the circuit layer 120 further includes a power auxiliary electrode PASE provided as a first source-drain conductive layer on the interlayer insulating layer 126 and the cathode auxiliary electrode CASE is electrically connected to the power auxiliary electrode PASE through a hole penetrating the first planarization layer 127, according to Figure 19The display device 100 of the embodiment shown in FIG. Figure 18 The display devices 100 of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0287] The cathode auxiliary electrode CASE may be electrically connected to transmit the second power ( Figure 5 The second power line (ELVSS) Figure 5 As an example, the cathode auxiliary electrode CASE may be a second power line ( Figure 5 part of the VSL in the .

[0288] Since, in addition to the circuit layer 120, the circuit layer 120 also includes an auxiliary insulating layer 129 that is disposed on the interlayer insulating layer 126 and covers the first source-drain conductive layer including the cathode auxiliary electrode CASE, and an additional connection hole ADCH that penetrates the pixel defining layer 132, the second planarization layer 128, and the first planarization layer 127, the cathode connection hole CTCH is connected to the additional connection hole ADCH and penetrates the auxiliary insulating layer 129, and the top portion RF is disposed around the additional connection hole ADCH and is a portion of the first planarization layer 127 that protrudes much more than the auxiliary insulating layer 129, according to Figure 20 The display device 100 of the embodiment shown in FIG. Figure 7 and Figure 8 The display devices 100 of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0289] The top portion RF formed as a portion of the first planarization layer 127 may be more protruded than the auxiliary insulating layer 129 due to the cathode connection hole CTCH.

[0290] For example, the auxiliary insulating layer 129 may cover the edge of the cathode auxiliary electrode CASE. The portion of the auxiliary insulating layer 129 overlapping one side of the cathode auxiliary electrode CASE may be covered by the first planarization layer 127, and the other portion of the auxiliary insulating layer 129 overlapping the other side of the cathode auxiliary electrode CASE may be more recessed than a portion of the first planarization layer 127 (i.e., the top portion RF). Each of the interlayer insulating layer 126 and the auxiliary insulating layer 129 may include an inorganic insulating material. Each of the first planarization layer 127, the second planarization layer 128, and the pixel defining layer 132 may include an organic insulating material.

[0291] For example, when the top portion RF protrudes much more than the auxiliary insulating layer 129 , an undercut structure UC may be formed.

[0292] A gap in the second common layer 136 may be formed in the undercut structure UC between the top portion RF and the auxiliary insulating layer 129 .

[0293] Figure 21 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Schematic plan view of the cathode auxiliary electrode in part B.

[0294] Since the cathode auxiliary electrode CASE is adjacent to one side of the two or more third light emitting regions EA3 in the second direction DR2 and is also adjacent to one side of the third light emitting region EA3 in the first direction DR1, according to Figure 21 The display device 100 of the embodiment shown in FIG. Figures 7 to 20 The display devices 100 and 100 ′ of the embodiments are substantially the same, and thus redundant descriptions will be omitted below.

[0295] like Figure 21 As shown in FIG, in the case where the width of the third light emitting area EA3 in the first direction DR1 is reduced, the third spacing area GA3 disposed on one side of the third light emitting area EA3 may be disposed to have a width greater than that of the third light emitting area EA3. Figure 7 The third spacing area GA3' has a large width.

[0296] Since the third spacing area GA3 is provided with a sufficiently large width, the cathode auxiliary electrode CASE may be provided not only in the second spacing area GA2 but also in the third spacing area GA3.

[0297] The cathode auxiliary electrode CASE in the third spacing area GA3 may be adjacent to the first spacing area GA1 and a portion of each of two or more third light emitting areas EA31 and EA32 and EA33 and EA34 parallel to each other in the second direction DR2 and spaced apart by the first spacing area GA1.

[0298] Embodiments have been disclosed herein, and although terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly noted otherwise. Accordingly, it will be understood by one of ordinary skill in the art that various changes in form and detail may be made without departing from the spirit and scope of the disclosure.

Claims

1. A display device, comprising: a substrate including a display area in which a light emitting area is disposed; a circuit layer, disposed on the substrate; as well as A component layer is provided on the circuit layer, The circuit layer includes a cathode auxiliary electrode, and the cathode auxiliary electrode is arranged in a portion of the non-luminescent area between the luminescent areas in the display area. The element layer includes: an anode electrode, which is arranged in the light-emitting area; a pixel-defining layer, which is arranged in the non-light-emitting area and overlaps with the edge of each of the anode electrodes; a first common layer, which is arranged on the anode electrode; a light-emitting layer, which is arranged on the first common layer; a second common layer, which is arranged on the pixel-defining layer and the light-emitting layer; and a cathode electrode, which is arranged on the second common layer. A portion of each of the top portions overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode is exposed from the second common layer through a cathode connection hole, In the undercut structure formed by the top portion, a gap is formed in which the second common layer is separated, and The cathode electrode is electrically connected to the cathode auxiliary electrode through the cathode connection hole and the gap in the second common layer.

2. The display device according to claim 1, wherein The light-emitting area includes: a first light-emitting area emitting light of a first color; a second light-emitting area emitting light of a second color having a wavelength band lower than the wavelength band of the light of the first color; and a third light-emitting area emitting light of a third color having a wavelength band lower than the wavelength band of the light of the second color. The first light emitting regions are parallel to each other in a first direction, The second light emitting regions are parallel to each other in the first direction, Each of the third light emitting areas is adjacent to a portion of each of the first light emitting areas and a portion of each of the second light emitting areas in the first direction, In a second direction intersecting the first direction, the first light emitting areas and the second light emitting areas are alternately arranged. The third light emitting regions are parallel to each other in the second direction, and A first spacing region having a first width is arranged between two or more third light-emitting regions parallel in the second direction among the third light-emitting regions, and a second spacing region having a second width greater than the first width is arranged between the two or more third light-emitting regions and another two or more third light-emitting regions.

3. The display device according to claim 2, wherein: The cathode auxiliary electrode is disposed in the second spacing region.

4. The display device according to claim 2, wherein: The third spacing region is disposed on one side of the two or more third light emitting regions in the first direction, and The cathode auxiliary electrode is disposed in the first spacing region and the third spacing region.

5. The display device according to claim 2, wherein: The circuit layer includes: an interlayer insulating layer, disposed on the substrate; a first source and drain conductive layer, disposed on the interlayer insulating layer; a first planarization layer, overlapping the first source and drain conductive layer; a second source-drain conductive layer, disposed on the first planarization layer; and The second planarization layer is stacked with the second source-drain conductive layer.

6. The display device according to claim 5, wherein: The cathode auxiliary electrode is configured as the first source-drain conductive layer. The top portion is configured as the second source-drain conductive layer, The cathode connection hole includes: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion protrudes further than the second hole, and The gap in the second common layer is formed in an undercut structure between the top portion and the second hole.

7. The display device according to claim 6, wherein: The substrate further includes: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer further includes: two or more auxiliary top portions, which are provided as the second source-drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surround the hole region; and one or more separation grooves, which are located between the two or more auxiliary top portions and penetrate the first planarization layer. A portion of an edge of each of the two or more auxiliary top portions protrudes more than the one or more separation grooves, and A portion of the second common layer disposed in the hole peripheral region is separated from an undercut structure formed between the two or more auxiliary top portions and the one or more separation grooves.

8. The display device according to claim 5, wherein: The second source-drain conductive layer includes: a main conductive layer; and a sub-conductive layer, which is disposed on the main conductive layer and includes a metal material different from that of the main conductive layer. The cathode auxiliary electrode is configured as the first source-drain conductive layer. The top portion is configured as the second source-drain conductive layer, The cathode connection hole includes: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion exposed through the cathode connection hole includes an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer, and The gap in the second common layer is formed in the undercut structure of a portion of the top portion.

9. The display device according to claim 8, wherein: The substrate further includes: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer further includes: two or more auxiliary top portions, which are provided as the second source-drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surround the hole region; and one or more separation grooves, which are located between the two or more auxiliary top portions and penetrate the first planarization layer. a portion of an edge of each of the two or more auxiliary top portions exposed by the one or more separation grooves includes an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer; and A portion of the second common layer disposed in the hole peripheral region is separated from the undercut structures of the two or more auxiliary top portions.

10. The display device according to claim 5, wherein The cathode auxiliary electrode is configured as the first source-drain conductive layer. The top portion is disposed on the second planarization layer and is at the same layer as the anode electrode, The cathode connection hole includes: a first hole penetrating the pixel defining layer; and a second hole penetrating the second planarization layer and the first planarization layer. A portion of the top portion protrudes further than the second hole, and The gap in the second common layer is formed in an undercut structure between the top portion and the second hole.

11. The display device according to claim 5, wherein The cathode auxiliary electrode is configured as the second source-drain conductive layer. The top portion is disposed on the second planarization layer and is at the same layer as the anode electrode, The cathode connection hole includes: a first hole penetrating the pixel defining layer; and a second hole penetrating the second planarization layer. A portion of the top portion protrudes further than the second hole, and The gap in the second common layer is formed in an undercut structure between the top portion and the second hole.

12. The display device according to claim 11, wherein The circuit layer further includes a power auxiliary electrode, which is provided on the first source-drain conductive layer and electrically connected to the cathode auxiliary electrode.

13. The display device according to claim 5, wherein The circuit layer further includes an auxiliary insulating layer disposed on the interlayer insulating layer and overlapping the first source-drain conductive layer. Each of the interlayer insulating layer and the auxiliary insulating layer includes an inorganic insulating material, Each of the first planarization layer, the second planarization layer, and the pixel defining layer includes an organic insulating material, The cathode auxiliary electrode is configured as the first source-drain conductive layer. The cathode connection hole extends to an additional connection hole penetrating the pixel defining layer, the second planarization layer, and the first planarization layer, and penetrates the auxiliary insulating layer. The top portion is a portion of the first planarization layer disposed around the additional connection hole and protruding more than the auxiliary insulating layer, and The gap in the second common layer is formed in an undercut structure between the top portion and the auxiliary insulating layer.

14. A display device, comprising: a substrate including a display area in which a light emitting area is disposed; a circuit layer, disposed on the substrate; as well as The component layer is arranged on the circuit layer, wherein: The circuit layer includes: an interlayer insulating layer disposed on the substrate; a first source-drain conductive layer disposed on the interlayer insulating layer; a first planarizing layer overlapping the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarizing layer; a second planarizing layer overlapping the second source-drain conductive layer; and a cathode auxiliary electrode disposed on one of the first source-drain conductive layer and the second source-drain conductive layer in a portion of a non-luminescent region between the luminescent regions of the display region. The element layer includes: an anode electrode, which is arranged in the light-emitting area; a pixel-defining layer, which is arranged in the non-light-emitting area and overlaps with the edge of each of the anode electrodes; a first common layer, which is arranged on the anode electrode; a light-emitting layer, which is arranged on the first common layer; a second common layer, which is arranged on the pixel-defining layer and the light-emitting layer; and a cathode electrode, which is arranged on the second common layer. A portion of each of the top portions overlapping one side of the cathode auxiliary electrode and the cathode auxiliary electrode is exposed from the second common layer through a cathode connection hole, In the undercut structure formed by the top portion, a gap is formed in which the second common layer is separated, and The cathode electrode is electrically connected to the cathode auxiliary electrode through the cathode connection hole and the gap of the second common layer.

15. The display device according to claim 14, wherein The cathode auxiliary electrode is configured as the first source-drain conductive layer. The top portion is configured as the second source-drain conductive layer, The cathode connection hole includes: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion protrudes further than the second hole, and The gap in the second common layer is formed in an undercut structure between the top portion and the second hole.

16. The display device according to claim 15, wherein The substrate further includes: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer further includes: two or more auxiliary top portions, which are provided as the second source-drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surround the hole region; and one or more separation grooves, which are located between the two or more auxiliary top portions and penetrate the first planarization layer. A portion of an edge of each of the two or more auxiliary top portions protrudes more than the one or more separation grooves, and A portion of the second common layer disposed in the hole peripheral region is separated from an undercut structure formed between the two or more auxiliary top portions and the one or more separation grooves.

17. The display device according to claim 14, wherein: The second source-drain conductive layer includes: a main conductive layer; and a sub-conductive layer, which is disposed on the main conductive layer and includes a metal material different from that of the main conductive layer. The cathode auxiliary electrode is configured as the first source-drain conductive layer. The top portion is configured as the second source-drain conductive layer, The cathode connection hole includes: a first hole penetrating the pixel defining layer and the second planarization layer; and a second hole penetrating the first planarization layer. A portion of the top portion exposed through the cathode connection hole includes an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer, and The gap in the second common layer is formed in the undercut structure of a portion of the top portion.

18. The display device according to claim 17, wherein: The substrate further includes: a hole region surrounded by the display region; and a hole peripheral region disposed between the hole region and the display region. The circuit layer further includes: two or more auxiliary top portions, which are provided as the second source-drain conductive layer in the hole peripheral region on the first planarization layer and sequentially surround the hole region; and one or more separation grooves, which are located between the two or more auxiliary top portions and penetrate the first planarization layer. a portion of an edge of each of the two or more auxiliary top portions exposed by the one or more separation grooves includes an undercut structure in which the sub-conductive layer protrudes more than the main conductive layer; and A portion of the second common layer disposed in the hole peripheral region is separated from the undercut structures of the two or more auxiliary top portions.

19. The display device according to claim 14, wherein: The light-emitting area includes: a first light-emitting area emitting light of a first color; a second light-emitting area emitting light of a second color having a wavelength band lower than the wavelength band of the light of the first color; and a third light-emitting area emitting light of a third color having a wavelength band lower than the wavelength band of the light of the second color. The first light emitting regions are parallel to each other in a first direction, The second light emitting regions are parallel to each other in the first direction, Each of the third light emitting areas is adjacent to a portion of each of the first light emitting areas and a portion of each of the second light emitting areas in the first direction, In a second direction intersecting the first direction, the first light emitting areas and the second light emitting areas are alternately arranged. The third light emitting regions are parallel to each other in the second direction, A first spacing region having a first width is disposed between two or more third light-emitting regions parallel in the second direction among the third light-emitting regions, and a second spacing region having a second width greater than the first width is disposed between the two or more third light-emitting regions and another two or more third light-emitting regions, and The cathode auxiliary electrode is disposed in the second spacing region.

20. The display device according to claim 19, wherein The third spacing region is disposed on one side of the two or more third light emitting regions in the first direction, and The cathode auxiliary electrode is further disposed in the third spacing region.

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