Display device

Abstract

A display device is provided. The display device includes a display panel including a plurality of pixel groups, in which one pixel group among the plurality of pixel groups includes a normal pixel and a plurality of interpolated pixels around the normal pixel, the normal pixel includes a driving transistor, a normal light-emitting element, and a normal light-emitting transistor configured to supply a driving current provided through a first node connected to a drain electrode of the driving transistor to the normal light-emitting element in response to a normal light-emitting signal, and wherein, each of the plurality of interpolated pixels includes an interpolated light emitting element and a plurality of interpolated light emitting transistors configured to supply a portion of a driving current input from a first node of an adjacent normal pixel to the interpolated light emitting element in response to an interpolated light emitting signal.

Description

Technical Field

[0001] The present disclosure relates to a display device and a mobile electronic device including the display device. Background Art

[0002] Wearable devices in which the focus is formed at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. The wearable device provides the user with an augmented reality (hereinafter referred to as "AR") screen or a virtual reality (hereinafter referred to as "VR") screen.

[0003] Wearable devices such as head-mounted displays (HMDs) or augmented reality (AR) glasses typically require display specifications of approximately 3,500 pixels per inch (PPI) or higher to allow users to use them for extended periods without experiencing dizziness. To address this, organic light-emitting diode on silicon (OLEDoS) technology, which enables high-resolution, compact organic light-emitting displays, is gaining popularity. OLEDoS is a technology for displaying organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate with a complementary metal oxide semiconductor (CMOS) layer disposed thereon. Summary of the Invention

[0004] Aspects and features of embodiments of the present disclosure provide a display device capable of achieving up-scaling by arranging a plurality of interpolation pixels that emit light in response to an interpolation light emitting signal around normal pixels and capable of providing a high-resolution screen, and a mobile electronic device including the display device.

[0005] In one or more embodiments, a display device includes a display panel including a plurality of pixel groups, wherein one pixel group among the plurality of pixel groups includes a normal pixel and a plurality of interpolated pixels surrounding the normal pixel, wherein the normal pixel includes a driving transistor, a normal light-emitting element, and a normal light-emitting transistor configured to supply a driving current provided through a first node connected to a drain electrode of the driving transistor to the normal light-emitting element in response to a normal light-emitting signal, and wherein each of the plurality of interpolated pixels includes an interpolated light-emitting element and a plurality of interpolated light-emitting transistors configured to supply a portion of the driving current input from the first node of an adjacent normal pixel to the interpolated light-emitting element in response to the interpolated light-emitting signal.

[0006] In one or more embodiments, the normal pixel is at the center of a pixel group; the first interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a first plane direction; the second interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a second plane direction opposite to the first plane direction; the third interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a third plane direction perpendicular to the first plane direction; the fourth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a fourth plane direction opposite to the third plane direction; the fifth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a first oblique direction between the first plane direction and the third plane direction; the sixth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a second oblique direction between the second plane direction and the third plane direction; the seventh interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a third oblique direction opposite to the second oblique direction; and the eighth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a fourth oblique direction opposite to the first oblique direction.

[0007] In one or more embodiments, each of the first to fourth interpolated pixels includes a pair of interpolated light emitting transistors configured to receive a portion of the first driving current from the first normal pixel and configured to receive a portion of the second driving current from the second normal pixel.

[0008] In one or more embodiments, the first interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first drive current from a first normal pixel that is distant from the first interpolated pixel in a first plane direction and configured to receive a portion of the second drive current from a second normal pixel that is distant from the first interpolated pixel in a second plane direction, and wherein the second interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first drive current from the first normal pixel that is distant from the second interpolated pixel in the first plane direction and configured to receive a portion of the second drive current from the second normal pixel that is distant from the second interpolated pixel in the second plane direction.

[0009] In one or more embodiments, the third interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel located in a third plane direction from the third interpolated pixel and configured to receive a portion of the second driving current from a second normal pixel located in a fourth plane direction from the third interpolated pixel, and wherein the fourth interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel located in a third plane direction from the fourth interpolated pixel and configured to receive a portion of the second driving current from a second normal pixel located in a fourth plane direction from the fourth interpolated pixel.

[0010] In one or more embodiments, each of the fifth to eighth interpolated pixels includes two pairs of interpolated light emitting transistors configured to receive a portion of the first driving current from the first normal pixel, configured to receive a portion of the second driving current from the second normal pixel, configured to receive a portion of the third driving current from the third normal pixel, and configured to receive a portion of the fourth driving current from the fourth normal pixel.

[0011] In one or more embodiments, the fifth interpolated pixel includes two pairs of interpolated light-emitting transistors configured to receive drive currents from multiple normal pixels in various directions from the fifth interpolated pixel in the first oblique direction to the fourth oblique direction, wherein the sixth interpolated pixel includes two pairs of interpolated light-emitting transistors configured to receive drive currents from multiple normal pixels in various directions from the sixth interpolated pixel in the first oblique direction to the fourth oblique direction, wherein the seventh interpolated pixel includes two pairs of interpolated light-emitting transistors configured to receive drive currents from multiple normal pixels in various directions from the seventh interpolated pixel in the first oblique direction to the fourth oblique direction, and wherein the eighth interpolated pixel includes two pairs of interpolated light-emitting transistors configured to receive drive currents from multiple normal pixels in various directions from the eighth interpolated pixel in the first oblique direction to the fourth oblique direction.

[0012] In one or more embodiments, the interpolated light emitting transistor in the fifth interpolated pixel is configured to be turned on in response to the first emission control signal, the interpolated light emitting transistor in the third interpolated pixel is configured to be turned on in response to the second emission control signal, the interpolated light emitting transistor in the sixth interpolated pixel is configured to be turned on in response to the third emission control signal, the interpolated light emitting transistor in the first interpolated pixel is configured to be turned on in response to the fourth emission control signal, the normal light emitting transistor in the normal pixel is configured to be turned on in response to the fifth emission control signal, the interpolated light emitting transistor in the second interpolated pixel is configured to be turned on in response to the sixth emission control signal, the interpolated light emitting transistor in the seventh interpolated pixel is configured to be turned on in response to the seventh emission control signal, the interpolated light emitting transistor in the fourth interpolated pixel is configured to be turned on in response to the eighth emission control signal, and the interpolated light emitting transistor in the eighth interpolated pixel is configured to be turned on in response to the ninth emission control signal.

[0013] In one or more embodiments, the fifth emission control signal supplied to the normal pixel is a normal light emitting signal, and wherein each of the first to fourth emission control signals and the sixth to ninth emission control signals supplied to the first to eighth interpolated pixels is an interpolated light emitting signal.

[0014] In one or more embodiments, the first to ninth emission control signals are sequentially output during one frame period.

[0015] In one or more embodiments, the activation period of each of the first to ninth emission control signals does not overlap with each other.

[0016] In one or more embodiments, in a display area of a display panel, normal pixels and first to eighth interpolated pixels are arranged in a matrix form, wherein the normal pixels are positioned at specified intervals in odd pixel rows, and wherein the first interpolated pixel and the second interpolated pixel are alternately positioned between adjacent normal pixels in the odd pixel rows.

[0017] In one or more embodiments, the normal pixels are positioned at specified intervals in the even pixel columns, and wherein the third interpolated pixels and the fourth interpolated pixels are alternately positioned between adjacent normal pixels in the even pixel columns.

[0018] In one or more embodiments, in any pixel row in which the third interpolation pixel is located, the fifth interpolation pixel and the sixth interpolation pixel are alternately located with the third interpolation pixel therebetween.

[0019] In one or more embodiments, in any pixel row in which the fourth interpolation pixel is located, the seventh interpolation pixel and the eighth interpolation pixel are alternately located with the fourth interpolation pixel therebetween.

[0020] In one or more embodiments, a mobile electronic device includes a display panel including a plurality of pixel groups, wherein one pixel group among the plurality of pixel groups includes a normal pixel and a plurality of interpolated pixels surrounding the normal pixel, wherein the normal pixel includes a driving transistor, a normal light-emitting element, and a normal light-emitting transistor configured to supply a driving current to the normal light-emitting element through a first node connected to a drain electrode of the driving transistor in response to a normal light-emitting signal, and wherein each of the plurality of interpolated pixels includes an interpolated light-emitting element and a plurality of interpolated light-emitting transistors configured to supply a portion of the driving current input from a first node of an adjacent normal pixel to the interpolated light-emitting element in response to the interpolated light-emitting signal.

[0021] In one or more embodiments, the normal pixel is at the center of a pixel group; the first interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a first plane direction; the second interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a second plane direction opposite to the first plane direction; the third interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a third plane direction perpendicular to the first plane direction; the fourth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a fourth plane direction opposite to the third plane direction; the fifth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a first oblique direction between the first plane direction and the third plane direction; the sixth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a second oblique direction between the second plane direction and the third plane direction; the seventh interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a third oblique direction opposite to the second oblique direction; and the eighth interpolated pixel among the multiple interpolated pixels is away from the normal pixel in a fourth oblique direction opposite to the first oblique direction.

[0022] In one or more embodiments, each of the first to fourth interpolation pixels includes a pair of interpolation light emitting transistors configured to receive a portion of the first driving current from the first normal pixel and a portion of the second driving current from the second normal pixel.

[0023] In one or more embodiments, the first interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first drive current from a first normal pixel that is distant from the first interpolated pixel in a first plane direction and configured to receive a portion of the second drive current from a second normal pixel that is distant from the first interpolated pixel in a second plane direction, and wherein the second interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first drive current from the first normal pixel that is distant from the second interpolated pixel in the first plane direction and configured to receive a portion of the second drive current from the second normal pixel that is distant from the second interpolated pixel in the second plane direction.

[0024] In one or more embodiments, the third interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel located in a third plane direction from the third interpolated pixel and configured to receive a portion of the second driving current from a second normal pixel located in a fourth plane direction from the third interpolated pixel, and wherein the fourth interpolated pixel includes a pair of interpolated light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel located in a third plane direction from the fourth interpolated pixel and configured to receive a portion of the second driving current from a second normal pixel located in a fourth plane direction from the fourth interpolated pixel.

[0025] In the display device and the mobile electronic device including the display device according to one or more embodiments, up-scaling is achieved by arranging a plurality of interpolation pixels that emit light in response to an interpolation light emitting signal around normal pixels and a high-resolution screen can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features according to the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments;

[0028] Figure 2 is a block diagram illustrating a display device according to one or more embodiments;

[0029] Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments;

[0030] Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments;

[0031] Figure 5 and Figure 6 It shows Figure 4 A layout diagram of an embodiment of a display area;

[0032] Figure 7 is shown along Figure 5 A cross-sectional view of an example of a display panel taken along line I1-I1';

[0033] Figure 8 is a perspective view showing a head-mounted display according to one or more embodiments;

[0034] Figure 9 It shows Figure 8 An exploded perspective view of an example of a head-mounted display;

[0035] Figure 10 is a perspective view showing a head-mounted display according to one or more embodiments;

[0036] Figure 11 is a diagram schematically illustrating an arrangement of pixels of a display panel according to one or more embodiments;

[0037] Figure 12 is a diagram illustrating timing of emission control signals for driving pixels of a display panel according to one or more embodiments;

[0038] Figure 13is a circuit diagram illustrating a connection relationship between normal pixels and interpolation pixels according to one or more embodiments;

[0039] Figure 14 is a diagram illustrating timing of emission control signals for driving pixels of a display panel according to one or more embodiments; and

[0040] Figure 15 is an equivalent circuit diagram of a normal pixel according to one or more embodiments. DETAILED DESCRIPTION

[0041] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0042] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0043] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element can also be referred to as the first element.

[0044] The features of each of the various embodiments of the present disclosure may be combined with each other in part or in whole and may variously interact with each other technically, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0045] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms “comprises,” “comprising,” “has,” “have,” “having,” “includes,” and / or “including,” when used, may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0046] For the purposes of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or". For the purposes of its meaning and interpretation, in the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0047] In view of the entire content of this disclosure, it will be appreciated by those skilled in the art that, unless otherwise stated or implied, each appropriate feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various appropriate ways, and each embodiment may be implemented independently of each other or in combination with each other in any appropriate manner.

[0048] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0049] Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments. Figure 2 is a block diagram illustrating a display device according to one or more embodiments.

[0050] Reference Figure 1 and Figure 2 , the display device 10 according to one or more embodiments is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile PCs (UMPCs), and / or the like. For example, the display device 10 according to one or more embodiments can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, and / or an Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one or more embodiments can be applied to a smart watch, a watch phone, a head-mounted display (HMD) for realizing virtual reality and augmented reality, and / or the like.

[0051] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0052] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle at which the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be a right angle or rounded with an appropriate curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may be consistent with the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0053] like Figure 2 As shown in FIG, the display panel 100 includes a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0054] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0055] The plurality of pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0056] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0057] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 4 and FIG. 5 can be formed by a semiconductor process and arranged on a semiconductor substrate SSUB (see FIG. 4 ). Figure 7 For example, the plurality of pixel transistors of the plurality of sub-pixels SP1, SP2, and SP3 may be formed of a complementary metal oxide semiconductor (CMOS).

[0058] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of the plurality of write scan lines GWL (e.g., one write scan line GWL), any one of the plurality of control scan lines GCL (e.g., one control scan line GCL), any one of the plurality of bias scan lines EBL (e.g., one bias scan line EBL), any one of the plurality of first emission control lines EL1 (e.g., one first emission control line EL1), any one of the plurality of second emission control lines EL2 (e.g., one second emission control line EL2), and any one of the plurality of data lines DL (e.g., one data line DL). Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0059] The non-display area NDA includes a scan driver 610, an emission driver 620, and a data driver 700. The non-display area NDA may surround the display area DAA along an edge or periphery of the display area DAA.

[0060] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see Figure 7 ) on. For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed by CMOS. Although Figure 2 , the scan driver 610 is arranged on the left side of the display area DAA, and the emission driver 620 is arranged on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be arranged on either the left side or the right side of the display area DAA.

[0061] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals (also referred to herein as write control signals) in response to the scan timing control signal SCS and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and sequentially output them to the bias scan lines EBL.

[0062] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate first emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 can generate second emission control signals based on the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0063] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of data transistors may be formed of CMOS.

[0064] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0065] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be arranged on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as silver (Ag), copper (Cu), and / or aluminum (Al), and / or a layer including graphite, for example.

[0066] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 (see FIG. 1 ) by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. Figure 1 , the circuit board 300 is shown as being unfolded, but the circuit board 300 may be curved. In this case, one end of the circuit board 300 may be arranged on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be connected to the first pad portion PDA1 of the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ) at the opposite end of the other end of the circuit board 300.

[0067] The timing control circuit 400 may receive externally input digital video data DATA and timing signals. In response to the timing signals, the timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0068] The power supply circuit 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, a third driving voltage VINT and a reference voltage VREF, and supply them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0069] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0070] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be arranged in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on the semiconductor substrate SSUB by a semiconductor process (see Figure 7 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be arranged between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0071] Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments.

[0072] Reference Figure 3 The first subpixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first subpixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. In other words, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0073] The first subpixel SP1 includes a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0074] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE may be proportional to the driving current Ids. The light-emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer arranged between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0075] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (also referred to herein as a "driving current Ids") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0076] The second transistor T2 may be arranged between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0077] The third transistor T3 may be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal of the control scan line GCL to connect the first node N1 to the second node N2. For this reason, since the gate electrode and source electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode (for example, the first transistor T1 can be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0078] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current Ids of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0079] The fifth transistor T5 may be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line EBL to connect the third node N3 to the third drive voltage line VIL. Accordingly, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0080] The sixth transistor T6 may be arranged between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0081] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0082] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 (or the first node N1) and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0083] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0084] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0085] Although Figure 3 FIG. 4 shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to FIG. Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 As shown in .

[0086] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same as that described above. Therefore, descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are omitted in this specification.

[0087] Figure 4 is a layout diagram illustrating an example of a display panel according to one or more embodiments.

[0088] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0089] The scan driver 610 may be arranged on a first side of the display area DAA, and the emission driver 620 may be arranged on a second side of the display area DAA. For example, the scan driver 610 may be arranged on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be arranged on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be arranged on the left side of the display area DAA, and the emission driver 620 may be arranged on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be arranged on either the first side or the second side of the display area DAA.

[0090] The first pad portion PDA1 may include a portion connected to the circuit board 300 (eg, referring to FIG. 1 ) by a conductive adhesive member. Figure 1 ) of the plurality of first pads PD1 of the pads or bumps. The first pad portion PDA1 may be arranged on a third side of the display area DAA. For example, the first pad portion PDA1 may be arranged on one side of the display area DAA in the second direction DR2.

[0091] The first pad portion PDA1 may be arranged outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be arranged closer to the edge of the display panel 100 than the data driver 700.

[0092] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or a probe during the inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board (PCB) made of a rigid material or a flexible printed circuit board (FPCB) made of a flexible material.

[0093] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or greater), and as a result, the number of the plurality of first pads PD1 may be reduced. The first distribution circuit 710 may be arranged on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be arranged on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 may be arranged on the lower side of the display area DAA.

[0094] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 may be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 may be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be arranged on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 may be arranged on the upper side of the display area DAA.

[0095] Figure 5 and Figure 6 It shows Figure 4 Layout diagram of an implementation scheme of a display area.

[0096] Reference Figure 5 and Figure 6 , each of the pixels PX includes a first emission area EA1 which is an emission area of the first sub-pixel SP1, a second emission area EA2 which is an emission area of the second sub-pixel SP2, and a third emission area EA3 which is an emission area of the third sub-pixel SP3.

[0097] Each of the first, second, and third emission areas EA1, EA2, and EA3 may have a polygonal, circular, elliptical, and / or atypical shape in a plan view.

[0098] The maximum length of the third emission area EA3 in the first direction DR1 may be less than each of the maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1. The maximum length of the second emission area EA2 in the first direction DR1 and the maximum length of the first emission area EA1 in the first direction DR1 may be substantially the same.

[0099] The maximum length of the third emission area EA3 in the second direction DR2 may be greater than each of the maximum length of the second emission area EA2 in the second direction DR2 and the maximum length of the first emission area EA1 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 may be greater than the maximum length of the first emission area EA1 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum length of the second emission area EA2 in the second direction DR2.

[0100] like Figure 5 and Figure 6As shown in the figure, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in a plan view, but the present disclosure is not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a hexagon, a circular shape, an elliptical shape, and / or an atypical shape in a plan view.

[0101] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The area of the first emission area EA1, the area of the second emission area EA2, and the area of the third emission area EA3 may be different.

[0102] Alternatively, as Figure 6 As shown in , the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0103] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light of a blue wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0104] exist Figure 5 and Figure 6 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3 as an example, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four or more emission areas.

[0105] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to Figure 5 and Figure 6 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a structure in which the emission regions are arranged in a diamond shape, or a structure in which the emission regions are arranged in a stripe shape. Arrangement structure, or Figure 6 The hexagonal structure shown in FIG. 1 has hexagonal shaped emission regions arranged side by side in a plan view. is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0106] Figure 7 is shown along Figure 5 1 is a cross-sectional view of an example of a display panel taken along line I1-I1'.

[0107] Reference Figure 7 , the display panel 100 (for example, referring to Figure 4 ) includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizer POL.

[0108] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE each electrically connected to a corresponding one of the plurality of pixel transistors PTR. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0109] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be arranged on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities described above. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0110] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0111] The lower insulating layer BINS may be disposed between the gate electrode GE and the well area WA. The side insulating layer SINS may be disposed on the side surface of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0112] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be arranged on one side of the gate electrode GE, and the drain region DA may be arranged on the other side of the gate electrode GE.

[0113] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA may be increased. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby reducing or preventing breakdown and hot carrier phenomena that may be caused by a short channel.

[0114] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB and the pixel transistor PTR. The first semiconductor insulating layer SINS1 may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0115] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0116] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of a corresponding one of the pixel transistors PTR (e.g., one of the gate electrode GE, source area SA, and drain area DA) through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof.

[0117] The third semiconductor insulating layer SINS3 may be arranged on the side surface of each of the plurality of contact terminals CTE and on the second semiconductor insulating layer SINS2. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0118] The semiconductor substrate SSUB may be replaced with a glass substrate and / or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be arranged on the glass substrate and / or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent and / or folded.

[0119] The light emitting element back plate EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating layers INS1 to INS9. In addition, the light emitting element back plate EBP includes a plurality of insulating layers INS2 to INS8 disposed between the first to eighth conductive layers ML1 to ML8.

[0120] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 3 For example, the first to sixth transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 are connected to the first capacitor CP1 (for example, referring to FIG. Figure 3 ) and the second capacitor CP2 (eg, referring to Figure 3 ) are connected via the first to eighth conductive layers ML1 to ML8. In addition, connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also connected via the first to eighth conductive layers ML1 to ML8.

[0121] The first insulating layer INS1 may be disposed on the third semiconductor insulating layer SINS3 of the semiconductor backplane SBP. Each of the first via portions VA1 may penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating layer INS1 and may be connected to the first via portion VA1.

[0122] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second via portions VA2 may penetrate the second insulating layer INS2 and may be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second via portion VA2.

[0123] The third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third via portions VA3 may penetrate the third insulating layer INS3 and may be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third via portion VA3.

[0124] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth via portions VA4 may penetrate the fourth insulating layer INS4 and may be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may be connected to the fourth via portion VA4.

[0125] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth via portions VA5 may penetrate the fifth insulating layer INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may be connected to the fifth via portion VA5.

[0126] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth via portions VA6 may penetrate the sixth insulating layer INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may be connected to the sixth via portion VA6.

[0127] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh via portions VA7 may penetrate the seventh insulating layer INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and may be connected to the seventh via portion VA7.

[0128] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth via portions VA8 may penetrate the eighth insulating layer INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may be connected to the eighth via portion VA8.

[0129] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via portion VA1 to the eighth via portion VA8 may be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via portion VA1 to the eighth via portion VA8 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or an alloy including one or more thereof. The first via portion VA1 to the eighth via portion VA8 may be made of substantially the same material. The first insulating layer INS1 to the eighth insulating layer INS8 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0130] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thickness of the first via portion VA1, the second via portion VA2, the third via portion VA3, the fourth via portion VA4, the fifth via portion VA5, and the sixth via portion VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately And the thickness of each of the first via portion VA1, the second via portion VA2, the third via portion VA3, the fourth via portion VA4, the fifth via portion VA5, and the sixth via portion VA6 may be approximately However, in one or more embodiments, the thickness of one or more or each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be substantially the same as the thickness of the first conductive layer ML1.

[0131] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than each of the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via portion VA7 and the thickness of the eighth via portion VA8, respectively. The thickness of each of the seventh via portion VA7 and the eighth via portion VA8 may be greater than each of the thickness of the first via portion VA1, the thickness of the second via portion VA2, the thickness of the third via portion VA3, the thickness of the fourth via portion VA4, the thickness of the fifth via portion VA5, and the thickness of the sixth via portion VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh via portion VA7 and the eighth via portion VA8 may be approximately

[0132] The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0133] Each of the ninth via portions VA9 may penetrate the ninth insulating layer INS9 and may be connected to the exposed eighth conductive layer ML8. The ninth via portion VA9 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the ninth via portion VA9 may be approximately

[0134]

[0135] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include a reflective electrode layer RL, tenth and eleventh insulating layers INS10 and INS11, a tenth via portion VA10, and light emitting elements LE each including a first electrode AND, a light emitting stack IL, and a second electrode CAT. The display element layer EML may also include a pixel defining layer PDL and a plurality of trenches TRC.

[0136] The reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode (eg, at least one of the reflective electrodes RL1, RL2, RL3, and RL4). Figure 7As shown in , the reflective electrode layer RL may include a first reflective electrode RL1 , a second reflective electrode RL2 , a third reflective electrode RL3 , and a fourth reflective electrode RL4 .

[0137] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth via portion VA9. The first reflective electrode RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy and / or a metal compound including one or more thereof. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0138] Each of the second reflective electrodes RL2 may be arranged on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the second reflective electrode RL2 may include aluminum (Al).

[0139] Each of the third reflective electrodes RL3 may be arranged on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy and / or a metal compound including one or more of these. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0140] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0141] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE in one or more embodiments, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately And the thickness of the second reflective electrode RL2 may be approximately In one or more embodiments, Figure 7As shown in , the thickness of the second reflective electrode RL2 may be substantially the same as the thickness of one or more or each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0142] The tenth insulating layer INS10 may be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 may be disposed between the reflective electrode layers RL adjacent to each other in the lateral direction. In one or more embodiments, the tenth insulating layer INS10 may be disposed on the reflective electrode layer RL in the third sub-pixel SP3. The tenth insulating layer INS10 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0143] The eleventh insulating layer INS11 may be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 may be made of silicon oxide (SiO x The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL, among light emitted from the light emitting element LE, passes.

[0144] In order to match the resonance distance of light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, in one or more embodiments, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be arranged under the first electrode AND of the first sub-pixel SP1. In one or more embodiments, the first electrode AND of the first sub-pixel SP1 may be arranged directly on the reflective electrode layer RL. The eleventh insulating layer INS11 may be arranged under the first electrode AND of the second sub-pixel SP2. In one or more embodiments, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be arranged under the first electrode AND of the third sub-pixel SP3. However, in one or more other embodiments, as Figure 7 As shown in FIG, an eleventh insulating layer INS11 may be disposed under the first electrode AND of each of the first to third sub-pixels SP1 to SP3.

[0145] In summary, in one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7 ] It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 is greater than each of the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, but the present disclosure is not limited thereto.

[0146] In addition, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiment of the present disclosure, a twelfth insulating layer arranged under the first electrode AND of the first sub-pixel SP1 may be added. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be arranged under the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be arranged under the first electrode AND of the third sub-pixel SP3.

[0147] In one or more embodiments, each of the tenth via portions VA10 may penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second sub-pixel SP2 or the third sub-pixel SP3 and may be connected to the exposed reflective electrode layer RL. Figure 7 As shown in FIG, each of the tenth via portions VA10 may penetrate the eleventh insulating layer INS11 in the first sub-pixel SP1, the second sub-pixel SP2, or the third sub-pixel SP3 and may be connected to the exposed reflective electrode layer RL. The tenth via portion VA10 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or an alloy including one or more thereof. The thickness of the tenth via portion VA10 in the second sub-pixel SP2 may be less than that of the tenth via portion VA10 in the third sub-pixel SP3.

[0148] The first electrode AND of each light-emitting element LE may be arranged on the eleventh insulating layer INS11 and connected to the tenth via portion VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via portion VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via portions VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or metal compounds including one or more of these. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0149] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover the edge of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may be used to divide the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0150] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0151] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be arranged on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining layer PDL2 may be arranged on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be arranged on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the present disclosure is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 may each have an area of about thickness.

[0152] When the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) are formed into one pixel defining layer, the height of the one pixel defining layer is increased so that the first encapsulating inorganic layer (TFE1) can be cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the greater the possibility of the film being cut at the inclined portion.

[0153] Therefore, to prevent or reduce the first encapsulating inorganic layer TFE1 from being cut due to step coverage, the first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may have a cross-sectional structure including a stepped portion. For example, the width of the first pixel defining layer (PDL1) may be greater than each of the widths of the second pixel defining layer (PDL2) and the third pixel defining layer (PDL3), and the width of the second pixel defining layer (PDL2) may be greater than the width of the third pixel defining layer (PDL3). The width of the first pixel defining layer (PDL1) refers to the lateral length of the first pixel defining layer (PDL1) as defined in the first direction (DR1) or the second direction (DR2).

[0154] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Furthermore, each of the plurality of trenches TRC may penetrate the eleventh insulating layer INS11. In one or more embodiments, the tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0155] At least one trench TRC may be disposed between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3. Figure 7 It is shown that two trenches TRC are arranged between adjacent sub-pixels among the sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0156] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 The light emitting stack IL is shown to have a three-series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a two-series structure including two intermediate layers.

[0157] In the triple-series structure, the light emitting stack IL may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack IL may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of the second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be stacked sequentially.

[0158] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0159] A first charge generation layer for supplying charges to the second stack layer IL2 and supplying electrons to the first stack layer IL1 may be arranged between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0160] A second charge generation layer for supplying charges to the third stacked layer IL3 and supplying electrons to the second stacked layer IL2 may be arranged between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0161] The first stacked layer IL1 may be arranged on the first electrode AND and the pixel defining layer PDL and may be arranged on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 may be cut off between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 may be arranged on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be cut off between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space may be arranged between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 may be arranged on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and may be arranged to cover the second stacked layer IL2 in each trench TRC. That is, in the three-series structure, each of the multiple trenches TRC may be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML, and the first charge generation layer and the second charge generation layer between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3. In addition, in the two-series structure, each of the trenches TRC may be a structure for cutting off the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer, and the lower intermediate layer.

[0162] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels among the sub-pixels SP1, SP2, and SP3, another structure may be provided instead of the grooves TRC. For example, instead of the grooves TRC, an inverted tapered partition wall may be arranged on the pixel defining layer PDL.

[0163] The number of stacked layers emitting different light is not limited to Figure 7 . For example, the light emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be arranged between the two intermediate layers.

[0164] in addition, Figure 7 It is shown that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present disclosure is not limited to this. For example, in one or more embodiments, the first stacked layer IL1 may be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, in one or more embodiments, the second stacked layer IL2 may be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0165] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO) such as ITO and / or IZO, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, the microcavity effect may improve the luminous efficiency in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0166] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer (e.g., inorganic layers TFE1 and TFE2) to prevent oxygen and / or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0167] The first encapsulating inorganic layer TFE1 may be disposed on the second electrode CAT. The first encapsulating inorganic layer TFE1 may be formed in which silicon nitride (SiN x ), silicon oxynitride (SiON) and silicon oxide (SiO x ) in a multilayer of one or more inorganic layers. The first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0168] The second encapsulating inorganic layer TFE2 may be disposed on the first encapsulating inorganic layer TFE1. The second encapsulating inorganic layer TFE2 may be made of titanium oxide (TiO x ) and / or aluminum oxide (AlO x ) is formed, but the present disclosure is not limited thereto. The second encapsulation inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 may be less than the thickness of the first encapsulation inorganic layer TFE1.

[0169] The organic layer APL may be a layer for increasing interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0170] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged on the organic layer APL.

[0171] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color (i.e., light of the blue wavelength band). The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0172] The second color filter CF2 may overlap with the second emission area EA2 of the second subpixel SP2. The second color filter CF2 may transmit light of the second color (i.e., light of the green wavelength band). The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0173] The third color filter CF3 may overlap with the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color (i.e., light of a red wavelength band). The red wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0174] The plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a lens for increasing the amount of light directed to the display device 10 (eg, referring to FIG. 1 ). Figure 1 Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0175] A filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have an appropriate refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer including, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0176] The cover layer CVL can be arranged on the filler layer FIL. The cover layer CVL can be a glass substrate and / or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can serve as a packaging substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0177] The polarizing plate POL may be arranged on one surface of the cover layer CVL. The polarizing plate POL may be a structure for preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the present disclosure is not limited thereto. However, when the first color filter CF1, the second color filter CF2, and the third color filter CF3 sufficiently overcome visibility degradation caused by reflection of external light, the polarizing plate POL may be omitted.

[0178] Figure 8 is a perspective view illustrating a head-mounted display according to one or more embodiments. Figure 9 It shows Figure 8 An exploded perspective view of an example of a head-mounted display.

[0179] Reference Figure 8 and Figure 9 According to one or more embodiments, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0180] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0181] The first optical member 1510 may be arranged between the first display device 10_1 and the first eyepiece 1210 (e.g., in the Z-axis direction). The second optical member 1520 may be arranged between the second display device 10_2 and the second eyepiece 1220 (e.g., in the Z-axis direction). Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0182] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0183] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (e.g., referring to FIG. 1 ). Figure 2 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0184] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0185] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is arranged to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is arranged and a second eyepiece 1220 at which the user's right eye is arranged. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately arranged (eg, in the X-axis direction perpendicular to the Z-axis direction and the Y-axis direction), but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0186] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, a user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0187] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively arranged on the user's left eye and right eye. When the display device housing 1100 is implemented to be lightweight and compact, the head mounted display 1000 can be provided as Figure 10The eyeglass frame shown in FIG. 1 is used instead of the headband 1300.

[0188] In addition, the head-mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, and / or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0189] Figure 10 is a perspective view illustrating a head-mounted display according to one or more embodiments.

[0190] Reference Figure 10 The head-mounted display 1000_1 according to one or more embodiments may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0191] The display device housing 1200_1 may include a display device 10_3, an optical member 1060, and an optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user can observe, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined.

[0192] Figure 10 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user can observe the image displayed on the display device 10_3 with both the left eye and the right eye.

[0193] Figure 11 is a schematic diagram showing a display panel 100 according to one or more embodiments (eg, see Figure 1 ) is a diagram showing the arrangement of pixels.

[0194] Reference Figure 11 , in the display panel 100 according to one or more embodiments (for example, see Figure 1 ), one normal pixel (NOR) 1711 and a plurality of interpolation pixels (INT) 1712 to 1719 surrounding the one normal pixel 1711 form one pixel group PG. For example, one pixel group PG may include a total of nine pixels including the one normal pixel 1711.

[0195] The normal pixels 1711 of each pixel group PG may be connected to a data line (eg, Figure 15 of the data line DL), and according to the slave data line (eg, Figure 15 The data voltage provided by the data line DL) drives the normal light emitting element LE (for example, referring to Figure 15 ).

[0196] The interpolated pixels 1712 to 1719 of each pixel group PG are arranged around the normal pixel 1711 (eg, arranged to surround the normal pixel 1711), and receive light emitted by the normal light emitting transistor (eg, Figure 13 The normal light emitting transistor EM_TR5) supplies the normal light emitting element LE (for example, referring to Figure 13 ) of the driving current. Each of the interpolation pixels 1712 to 1719 may include an interpolation light emitting element LE driven based on the driving current supplied from the normal pixel 1711 (eg, referring to Figure 13 ) of an interposer light emitting transistor (e.g., Figure 13 interpolated light-emitting transistor EM_TR4).

[0197] Hereinafter, more specifically, the pixel group PG will be described.

[0198] According to one or more embodiments, a normal pixel 1711 includes a transistor 1711 that is responsive to a driving transistor (eg, Figure 13 The driving transistor DR), the normal light emitting element LE and the normal light emitting signal (eg, Figure 13 The fifth emission control signal EM5) is transmitted through the first node N1 (eg, Figure 13 The driving current provided by the first node N1 of the normal light emitting element LE is supplied to the normal light emitting transistor (for example, Figure 13 In the present disclosure, the driving transistor DR and the normal light emitting transistor (eg, Figure 13 The normal light emitting transistor EM_TR5) is exemplified as a P-type transistor, but the present disclosure is not limited thereto. For example, the driving transistor DR and the normal light emitting transistor (eg, Figure 13 The normal light emitting transistor EM_TR5) can be an N-type transistor.

[0199] The driving transistor can be referred to later Figure 13 The driving transistor DR is described.

[0200] Normal light emitting transistor can be referenced later Figure 13 Described is the normal light emitting transistor EM_TR5.

[0201] The normal light emitting signal for controlling the normal light emitting transistor can be referred to later. Figure 13 A fifth emission control signal EM5 is described.

[0202] Each of the interpolation pixels 1712 to 1719 includes a light emitting element LE in response to an interpolation light emitting signal (eg, Figure 12 The first emission control signal EM1 to the fourth emission control signal EM4 and the sixth emission control signal EM6 to the ninth emission control signal EM9 are used to supply a portion of the driving current input from the first node N1 of the adjacent normal pixel 1711 to the plurality of interpolated light-emitting transistors of the light-emitting element LE. In the present disclosure, the interpolated light-emitting transistors are exemplified as P-type transistors, but the present disclosure is not limited thereto. For example, the interpolated light-emitting transistors may be N-type transistors.

[0203] For reference, see the interposer light emitting transistor. Figure 13 Shown are interpolated light emitting transistors EM_TR2, EM_TR3, EM_TR4, and EM_TR6.

[0204] The interpolation light-emitting signal used to control the interpolation light-emitting transistor can refer to Figure 13 Shown are a second emission control signal EM2 , a third emission control signal EM3 , a fourth emission control signal EM4 , and a sixth emission control signal EM6 .

[0205] According to one or more embodiments, a pixel group PG includes a normal pixel 1711 arranged at the center of the pixel group PG, a first interpolated pixel 1712 arranged in a first plane direction PD1 from the normal pixel 1711, a second interpolated pixel 1713 arranged in a second plane direction PD2 opposite to the first plane direction PD1 from the normal pixel 1711, a third interpolated pixel 1714 arranged in a third plane direction PD3 perpendicular to the first plane direction PD1 from the normal pixel 1711, and a fourth interpolated pixel 1715 arranged in a fourth plane direction PD4 opposite to the third plane direction PD3 from the normal pixel 1711. The pixel 1715 is arranged on the first oblique direction PD5 between the first plane direction PD1 and the third plane direction PD3 away from the normal pixel 1711, the sixth interpolated pixel 1717 is arranged on the second oblique direction PD6 between the second plane direction PD2 and the third plane direction PD3 away from the normal pixel 1711, the seventh interpolated pixel 1718 is arranged on the third oblique direction PD7 opposite to the second oblique direction PD6 away from the normal pixel 1711, and the eighth interpolated pixel 1719 is arranged on the fourth oblique direction PD8 opposite to the first oblique direction PD5 away from the normal pixel 1711.

[0206] The interpolation light emitting transistor included in the fifth interpolation pixel 1716 is turned on in response to the first emission control signal EM1. When turned on, the interpolation light emitting transistor of the fifth interpolation pixel 1716 drives the interpolation light emitting element LE provided in the fifth interpolation pixel 1716 based on the driving current input from the peripheral normal pixel 1711.

[0207] The interpolation light emitting transistor (eg, Figure 13 The interpolation light emitting transistor EM_TR2 of the third interpolation pixel 1714 is turned on in response to the second emission control signal EM2. When turned on, the interpolation light emitting transistor of the third interpolation pixel 1714 (eg, Figure 13 The interpolation light emitting transistor EM_TR2) drives the interpolation light emitting element LE provided in the third interpolation pixel 1714 based on the driving current input from the peripheral normal pixel 1711.

[0208] The interpolation light emitting transistor (eg, Figure 13 The interpolation light emitting transistor EM_TR3 of the sixth interpolation pixel 1717 is turned on in response to the third emission control signal EM3. When turned on, the interpolation light emitting transistor of the sixth interpolation pixel 1717 (eg, Figure 13 The interpolation light emitting transistor EM_TR3) drives the interpolation light emitting element LE provided in the sixth interpolation pixel 1717 based on the driving current input from the peripheral normal pixel 1711.

[0209] The interpolation light emitting transistor (eg, Figure 13 The interpolation light emitting transistor EM_TR4 of the first interpolation pixel 1712 is turned on in response to the fourth emission control signal EM4. When turned on, the interpolation light emitting transistor (eg, Figure 13 The interpolation light emitting transistor EM_TR4) drives the interpolation light emitting element LE provided in the first interpolation pixel 1712 based on the driving current input from the peripheral normal pixel 1711.

[0210] A normal light emitting transistor (eg, Figure 13 The normal light emitting transistor EM_TR5 of the normal pixel 1711 is turned on in response to the fifth emission control signal EM5. Figure 13 The normal light emitting transistor EM_TR5 receives a driving current corresponding to the data voltage from the driving transistor DR. When turned on, the normal light emitting transistor (eg, Figure 13 The normal light emitting transistor EM_TR5) can drive the normal light emitting element LE based on the driving current input from the driving transistor DR. Figure 13 A first node N1 (e.g., a drain electrode of the drive transistor DR) between the normal emission transistor EM_TR5 and the normal emission transistor EM_TR5 of the normal pixel 1711 may be connected to the interpolated pixels 1712 to 1719 located at the periphery of the normal pixel 1711. Accordingly, a portion of the driving current output by the drive transistor DR of the normal pixel 1711 may be provided to the interpolated pixels 1712 to 1719 located at the periphery of the normal pixel 1711. For example, one normal pixel 1711 may provide a portion of the driving current to eight interpolated pixels 1712 to 1719 (i.e., the first to eighth interpolated pixels 1712 to 1719) around the one normal pixel 1711 (e.g., surrounding the one normal pixel 1711).

[0211] The interpolation light emitting transistor (eg, Figure 13 The interpolation light emitting transistor EM_TR6 of the second interpolation pixel 1713 is turned on in response to the sixth emission control signal EM6. When turned on, the interpolation light emitting transistor of the second interpolation pixel 1713 (eg, Figure 13 The interpolation light emitting transistor EM_TR6) drives the interpolation light emitting element LE provided in the second interpolation pixel 1713 based on the driving current input from the peripheral normal pixel 1711.

[0212] The interpolation light emitting transistor included in the seventh interpolation pixel 1718 is turned on in response to the seventh emission control signal EM7. When turned on, the interpolation light emitting transistor of the seventh interpolation pixel 1718 drives the interpolation light emitting element LE provided in the seventh interpolation pixel 1718 based on the driving current input from the peripheral normal pixel 1711.

[0213] The interpolation light emitting transistor included in the fourth interpolation pixel 1715 is turned on in response to the eighth emission control signal EM8. When turned on, the interpolation light emitting transistor of the fourth interpolation pixel 1715 drives the interpolation light emitting element LE provided in the fourth interpolation pixel 1715 based on the driving current input from the peripheral normal pixel 1711.

[0214] The interpolation light emitting transistor included in the eighth interpolation pixel 1719 is turned on in response to the ninth emission control signal EM9. When turned on, the interpolation light emitting transistor of the eighth interpolation pixel 1719 drives the interpolation light emitting element LE provided in the eighth interpolation pixel 1719 based on the driving current input from the peripheral normal pixel 1711.

[0215] Figure 12 is a diagram illustrating timings of emission control signals for driving pixels of a display panel according to one or more embodiments.

[0216] Reference Figure 12 , the emission control signal according to one or more embodiments includes first to ninth emission control signals EM1 to EM9.

[0217] The first to ninth emission control signals EM1 to EM9 are sequentially output during one frame period. In addition, activation periods of each of the first to ninth emission control signals EM1 to EM9 do not overlap with each other.

[0218] After the first to ninth emission control signals EM1 to EM9 are sequentially output, the first to ninth emission control signals EM1 to EM9 may be sequentially output again. For example, after the ninth emission control signal EM9 is output, the first to ninth emission control signals EM1 to EM9 may be sequentially output again.

[0219] Reference Figures 11 to 13 , the fifth emission control signal EM5 may be a “normal emission signal” for controlling the normal light emitting transistor of the normal pixel 1711 .

[0220] Reference Figure 11 and Figure 12, the first to fourth emission control signals EM1 to EM4 and the sixth to ninth emission control signals EM6 to EM9 may each be an “interpolation emission signal” for controlling an interpolation light emitting transistor of an interpolation pixel.

[0221] By sequentially outputting the first emission control signal EM1 to the ninth emission control signal EM9, the display device according to one or more embodiments can time-divide the light-emission time of the normal pixel 1711 and the interpolated pixels 1712 to 1719 within one frame. That is, the light-emission time of each of the normal pixel 1711 and the interpolated pixels 1712 to 1719 does not overlap with each other. If the light-emission time of each of the normal pixel 1711 and the interpolated pixels 1712 to 1719 overlaps with each other, a short circuit may occur on the current path between the normal pixel 1711 and the interpolated pixels 1712 to 1719, and image defects may occur.

[0222] Figure 13 is a diagram showing a normal pixel 1711 (eg, referring to Figure 11 ) and the circuit diagram showing the connection relationship between the interpolated pixels.

[0223] Figure 13 It is magnified Figure 11 A circuit diagram of area 1701.

[0224] exist Figure 13 In FIG, 1811 indicates a normal pixel 1711 (NOR(M,N)) arranged in the Nth row and the Mth column. Figure 13 In FIG, 1812 indicates the first interpolated pixel 1712 (INT(M+1,N)) arranged in the Nth row and the (M+1)th column. Figure 13 In FIG, 1813 indicates a normal pixel 1711 (NOR (M+2, N)) arranged in the Nth row and the (M+2)th column. Figure 13 In FIG, 1814 indicates the third interpolated pixel 1714 (INT(M,N+1)) arranged in the (N+1)th row and the Mth column. Figure 13 In FIG, 1815 indicates the sixth interpolated pixel 1717 (INT(M+1,N+1)) arranged in the (N+1)th row and the (M+1)th column. Figure 13 In FIG, 1816 indicates the third interpolated pixel 1714 (INT(M+2,N+1)) arranged in the (N+1)th row and the (M+2)th column. Figure 13 In FIG, 1817 indicates a normal pixel 1711 (NOR (M, N+2)) arranged in the (N+2)th row and the Mth column. Figure 13In FIG, 1818 indicates the second interpolated pixel 1713 (INT(M+1,N+2)) arranged in the (N+2)th row and the (M+1)th column. Figure 13 , 1819 indicates a normal pixel 1711 (INT(M+2,N+2)) arranged in the (N+2)th row and the (M+2)th column. As described above, Figure 13 Only the Figure 11 1712 , the second interpolated pixel 1713 , the third interpolated pixel 1714 , and the sixth interpolated pixel 1717 among the first interpolated pixel 1712 to the eighth interpolated pixel 1719 shown in FIG.

[0225] In the following, we will combine Figure 11 and Figure 13 The connection relationship between the normal pixels 1711 and the interpolation pixels according to one or more embodiments is described in detail.

[0226] Reference Figure 11 and Figure 13 , the first to eighth interpolated pixels 1712 to 1719 included in one pixel group PG may be divided into two groups as described below.

[0227] First, the first group includes interpolated pixels 1712 to 1715 located in each of the left, right, upper, and lower directions of the normal pixel 1711. For example, the first group includes the first to fourth interpolated pixels 1712 to 1715 located in each of the first to fourth planar directions PD1 to PD4 from the normal pixel 1711. Furthermore, the second group includes interpolated pixels 1716 to 1719 located in four oblique directions from the normal pixel 1711. For example, the second group includes the fifth to eighth interpolated pixels 1716 to 1719 located in each of the first to fourth oblique directions PD5 to PD8 from the normal pixel 1711.

[0228] Each of the first to fourth interpolated pixels 1712 to 1715 corresponding to the first group includes a pair of interpolated light emitting transistors receiving a portion of the first driving current from the first normal pixel 1711 and a portion of the second driving current from the second normal pixel 1711 .

[0229] The first interpolated pixel 1812 (eg, Figure 11A first interpolated pixel 1812 includes a pair of interpolated light emitting transistors EM_TR4 that receive a portion of the first driving current from a first normal pixel 1811 arranged in a first plane direction PD1 from the first interpolated pixel 1812 and receive a portion of the second driving current from a second normal pixel 1813 arranged in a second plane direction PD2 from the first interpolated pixel 1812. The pair of interpolated light emitting transistors EM_TR4 provided in the first interpolated pixel 1812 may be turned on in response to a fourth emission control signal EM4.

[0230] The second interpolated pixel 1818 (eg, Figure 11 The second interpolated pixel 1713 includes a pair of interpolated light emitting transistors EM_TR6 that receive a portion of the first driving current from a first normal pixel 1817 arranged in a first plane direction PD1 from the second interpolated pixel 1818 and receive a portion of the second driving current from a second normal pixel 1819 arranged in a second plane direction PD2 from the second interpolated pixel 1818. The pair of interpolated light emitting transistors EM_TR6 provided in the second interpolated pixel 1818 can be turned on in response to a sixth emission control signal EM6.

[0231] Each of the third interpolated pixels 1814 and 1816 (eg, Figure 11 A third interpolated pixel 1714 in the third interpolated pixel 1814 includes a pair of interpolated light emitting transistors EM_TR2 that receive a portion of the first driving current from a first normal pixel 1811 or 1813 arranged in a third plane direction PD3 from the third interpolated pixel 1814 or 1816, and receive a portion of the second driving current from a second normal pixel 1817 or 1819 arranged in a fourth plane direction PD4 from the third interpolated pixel 1814 or 1816. The pair of interpolated light emitting transistors EM_TR2 provided in each of the third interpolated pixels 1814 and 1816 can be turned on in response to a second emission control signal EM2.

[0232] The fourth interpolated pixel 1715 includes a pair of interpolated light emitting transistors that receive a portion of the first driving current from a first normal pixel 1711 arranged in a third plane direction PD3 from the fourth interpolated pixel 1715 and receive a portion of the second driving current from a second normal pixel 1711 arranged in a fourth plane direction PD4 from the fourth interpolated pixel 1715. The pair of interpolated light emitting transistors provided in the fourth interpolated pixel 1715 may be turned on in response to an eighth emission control signal EM8.

[0233] Each of the fifth to eighth interpolated pixels 1716 to 1719 corresponding to the second group includes two pairs of interpolated light-emitting transistors that receive a portion of the first driving current from the first normal pixel 1711, a portion of the second driving current from the second normal pixel 1711, a portion of the third driving current from the third normal pixel 1711, and a portion of the fourth driving current from the fourth normal pixel 1711.

[0234] The fifth interpolated pixel 1716 includes two pairs of interpolated light emitting transistors that receive drive currents from the normal pixels 1711 arranged in each of the first oblique direction PD5 to the fourth oblique direction PD8. The two pairs of interpolated light emitting transistors provided in the fifth interpolated pixel 1716 can be turned on in response to the first emission control signal EM1.

[0235] The sixth interpolated pixel 1815 (eg, Figure 11 The sixth interpolated pixel 1717 includes two pairs of interpolated light emitting transistors EM_TR3 that receive drive currents from normal pixels 1811, 1813, 1817, and 1819 arranged in respective directions from the first oblique direction PD5 to the fourth oblique direction PD8 from the sixth interpolated pixel 1815. The two pairs of interpolated light emitting transistors EM_TR3 provided in the sixth interpolated pixel 1815 can be turned on in response to the third emission control signal EM3.

[0236] The seventh interpolated pixel 1718 includes two pairs of interpolated light emitting transistors that receive drive currents from the normal pixels 1711 arranged in respective directions from the first oblique direction PD5 to the fourth oblique direction PD8 from the seventh interpolated pixel 1718. The two pairs of interpolated light emitting transistors provided in the seventh interpolated pixel 1718 can be turned on in response to the seventh emission control signal EM7.

[0237] The eighth interpolated pixel 1719 includes two pairs of interpolated light emitting transistors that receive drive currents from the normal pixels 1711 arranged in respective directions from the first oblique direction PD5 to the fourth oblique direction PD8 from the eighth interpolated pixel 1719. The two pairs of interpolated light emitting transistors provided in the eighth interpolated pixel 1719 may be turned on in response to the ninth emission control signal EM9.

[0238] According to one or more embodiments, in the display panel 100 (for example, referring to Figure 1 ) of the display area DAA (for example, referring to Figure 2 ), the normal pixel 1711 and the first interpolation pixel 1712 to the eighth interpolation pixel 1719 may be arranged in a matrix form and arranged according to the following rules. Figure 11 Arrangement of the normal pixel 1711 and the first to eighth interpolated pixels 1712 to 1719 is described in detail.

[0239] Normal pixels 1711 are arranged at specified intervals in odd pixel rows (e.g., odd pixel rows R1, R3, and R5), and first interpolated pixels 1712 and second interpolated pixels 1713 are alternately arranged in the odd pixel rows R1, R3, and R5 between adjacent normal pixels 1711. Normal pixels 1711 are not arranged in even pixel rows (e.g., even pixel rows R2 and R4).

[0240] The normal pixels 1711 are arranged at specified intervals in even-numbered pixel columns (e.g., even-numbered pixel columns C2 and C4), and the third interpolated pixels 1714 and the fourth interpolated pixels 1715 are alternately arranged in the even-numbered pixel columns C2 and C4 between adjacent normal pixels 1711. The normal pixels 1711 are not arranged in odd-numbered pixel columns (e.g., odd-numbered pixel columns C1, C3, and C5).

[0241] In any pixel row (for example, pixel row R2 ) in which the third interpolated pixel 1714 is arranged, the fifth interpolated pixel 1716 and the sixth interpolated pixel 1717 are alternately arranged with the third interpolated pixel 1714 interposed therebetween.

[0242] In any pixel row (for example, pixel row R4 ) in which the fourth interpolated pixel 1715 is arranged, the seventh interpolated pixel 1718 and the eighth interpolated pixel 1719 are alternately arranged with the fourth interpolated pixel 1715 interposed therebetween.

[0243] According to one or more embodiments, Figure 13 The current of each pixel shown in Table 1 can be organized as shown in Table 1. The current of each pixel described in Table 1 represents the brightness of the corresponding pixel. In one or more embodiments, the driving current (Iout=Iout) flowing through the driving transistor DR can be adjusted by setting the duty cycle of each light emitting signal differently within a frame. DS ). Accordingly, the brightness of each interpolated pixel can be adjusted, and the degree of the screen door effect can be controlled. The screen door effect may mean a phenomenon in which the boundary between adjacent pixels is visible to the user.

[0244] Table 1

[0245]

[0246] According to one or more embodiments, a display device may selectively perform an upscaling operation. For example, the display device may perform an upscaling off operation by turning off an "interpolation emission signal" that controls an interpolation emission transistor of an interpolation pixel.

[0247] Figure 14is a diagram illustrating timings of emission control signals for driving pixels of a display panel according to one or more embodiments.

[0248] Figure 14 The implementation method and Figure 12 The difference between the embodiment of FIG. 1 and FIG. 2 is that the first emission control signal EM1 to the ninth emission control signal EM9 are global signals output only once per frame.

[0249] Reference Figure 14 , one frame period may be divided into periods in which data voltages are sequentially applied to the display panels 100 (eg, see Figure 1 ) in a scanning period 1910 of the entire pixel and a light emitting period 1920 after the scanning period 1910.

[0250] The light-emitting period 1920 may include a first light-emitting period 1921 for outputting the first emission control signal EM1, a second light-emitting period 1922 for outputting the second emission control signal EM2, a third light-emitting period 1923 for outputting the third emission control signal EM3, a fourth light-emitting period 1924 for outputting the fourth emission control signal EM4, a fifth light-emitting period 1925 for outputting the fifth emission control signal EM5, a sixth light-emitting period 1926 for outputting the sixth emission control signal EM6, a seventh light-emitting period 1927 for outputting the seventh emission control signal EM7, an eighth light-emitting period 1928 for outputting the eighth emission control signal EM8, and a ninth light-emitting period 1929 for outputting the ninth emission control signal EM9.

[0251] In the first light emitting period 1921, the first emission control signal EM1 may be globally output, and accordingly, the fifth interpolation pixel 1716 (eg, referring to FIG. 1714 ) provided in the display panel 100 may be configured to emit a plurality of light emitting diodes. Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0252] In the second light emitting period 1922, the second emission control signal EM2 may be globally output, and accordingly, the third interpolated pixel 1714 (eg, referring to FIG. 1714 ) provided in the display panel 100 may be provided. Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0253] In the third light emitting period 1923, the third emission control signal EM3 may be globally output, and accordingly, the sixth interpolation pixel 1717 (eg, referring to FIG. 1717 ) provided in the display panel 100 may be Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0254] In the fourth light emitting period 1924, the fourth emission control signal EM4 may be globally output, and accordingly, the first interpolated pixel 1712 (eg, referring to FIG. 1714 ) provided in the display panel 100 is Figure 11) can emit light synchronously (e.g., simultaneously).

[0255] In the fifth light emitting period 1925, the fifth emission control signal EM5 may be globally output, and accordingly, the normal pixels 1711 (eg, referring to FIG. 1714 ) provided in the display panel 100 are Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0256] In the sixth light emitting period 1926, the sixth emission control signal EM6 may be globally output, and accordingly, the second interpolated pixel 1713 (eg, referring to FIG. 1714 ) provided in the display panel 100 is Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0257] In the seventh light emitting period 1927, the seventh emission control signal EM7 may be globally output, and accordingly, the seventh interpolation pixel 1718 (eg, referring to FIG. 1718 ) provided in the display panel 100 may be provided. Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0258] In the eighth light emitting period 1928, the eighth emission control signal EM8 may be globally output, and accordingly, the fourth interpolated pixel 1715 (eg, referring to FIG. 1714 ) provided in the display panel 100 is Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0259] In the ninth light emitting period 1929, the ninth emission control signal EM9 may be globally output, and accordingly, the eighth interpolation pixel 1719 (eg, referring to FIG. 1719 ) provided in the display panel 100 may be output. Figure 11 ) can emit light synchronously (e.g., simultaneously).

[0260] Figure 15 is an equivalent circuit diagram of a normal pixel (NOR) 1711 according to one or more embodiments. For example, Figure 15 Can Figure 11 and Figure 13 : An equivalent circuit diagram of a normal pixel 1711 is shown in FIG.

[0261] Reference Figure 15 , the normal pixel 1711 provides a scanning transistor S1 connected to the data line DL, a driving transistor S2 (eg, Figure 13 The normal light emitting transistor S3 (eg, the fifth emission control signal EM5) receives the driving current from the driving transistor S2 and supplies the driving current to the light emitting element LE according to the normal light emitting signal EM3 (eg, the fifth emission control signal EM5). Figure 13In addition, the normal pixel 1711 may further provide a gate electrode connected to the driving transistor DR (eg, the driving transistor S2) and a second driving voltage ( Figure 2 The node between the driving transistor S2 and the normal light emitting transistor S3 may be defined as a first node (eg, Figure 13 ), and the first node N1 can be connected to the interpolation pixel INT at the periphery of the normal pixel 1711.

[0262] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments of the present disclosure without departing substantially from the principles of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: a display panel comprising a plurality of pixel groups, wherein one pixel group among the plurality of pixel groups comprises a normal pixel and a plurality of interpolation pixels around the normal pixel; wherein the normal pixel includes a driving transistor, a normal light emitting element, and a normal light emitting transistor configured to supply a driving current provided through a first node connected to a drain electrode of the driving transistor to the normal light emitting element in response to a normal light emitting signal, and Each of the plurality of interpolation pixels includes an interpolation light emitting element and a plurality of interpolation light emitting transistors configured to supply a portion of the driving current input from the first node of the adjacent normal pixel to the interpolation light emitting element in response to an interpolation light emitting signal.

2. The display device according to claim 1, wherein The normal pixel is located at the center of the one pixel group; A first interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a first plane direction; A second interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a second plane direction opposite to the first plane direction; A third interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a third plane direction perpendicular to the first plane direction; A fourth interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a fourth plane direction opposite to the third plane direction; A fifth interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a first oblique direction between the first plane direction and the third plane direction; A sixth interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a second oblique direction between the second plane direction and the third plane direction; A seventh interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a third oblique direction opposite to the second oblique direction; and An eighth interpolation pixel among the plurality of interpolation pixels is located away from the normal pixel in a fourth oblique direction opposite to the first oblique direction.

3. The display device according to claim 2, wherein: Each of the first to fourth interpolation pixels includes a pair of interpolation light emitting transistors configured to receive a portion of a first driving current from a first normal pixel and configured to receive a portion of a second driving current from a second normal pixel.

4. The display device according to claim 2, wherein: The first interpolation pixel includes a pair of interpolation light emitting transistors configured to receive a portion of a first driving current from a first normal pixel located in the first plane direction from the first interpolation pixel and configured to receive a portion of a second driving current from a second normal pixel located in the second plane direction from the first interpolation pixel, and The second interpolation pixel includes a pair of interpolation light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel away from the second interpolation pixel in the first plane direction and configured to receive a portion of the second driving current from a second normal pixel away from the second interpolation pixel in the second plane direction.

5. The display device according to claim 2, wherein: The third interpolation pixel includes a pair of interpolation light emitting transistors configured to receive a portion of the first driving current from a first normal pixel distant from the third interpolation pixel in the third plane direction and configured to receive a portion of the second driving current from a second normal pixel distant from the third interpolation pixel in the fourth plane direction, and The fourth interpolation pixel includes a pair of interpolation light-emitting transistors configured to receive a portion of the first driving current from a first normal pixel away from the fourth interpolation pixel in the third plane direction and configured to receive a portion of the second driving current from a second normal pixel away from the fourth interpolation pixel in the fourth plane direction.

6. The display device according to claim 2, wherein: Each of the fifth to eighth interpolated pixels includes two pairs of interpolated light emitting transistors configured to receive a portion of the first driving current from the first normal pixel, configured to receive a portion of the second driving current from the second normal pixel, configured to receive a portion of the third driving current from the third normal pixel, and configured to receive a portion of the fourth driving current from the fourth normal pixel.

7. The display device according to claim 6, wherein: The fifth interpolation pixel includes two pairs of interpolation light emitting transistors configured to receive drive currents from a plurality of normal pixels located in respective directions from the first oblique direction to the fourth oblique direction away from the fifth interpolation pixel. The sixth interpolation pixel includes two pairs of interpolation light emitting transistors configured to receive driving currents from a plurality of normal pixels located in respective directions from the first oblique direction to the fourth oblique direction away from the sixth interpolation pixel. The seventh interpolation pixel includes two pairs of interpolation light emitting transistors configured to receive driving currents from a plurality of normal pixels in respective directions from the seventh interpolation pixel in the first oblique direction to the fourth oblique direction, and The eighth interpolation pixel includes two pairs of interpolation light emitting transistors configured to receive driving currents from a plurality of normal pixels located in respective directions from the eighth interpolation pixel in the first oblique direction to the fourth oblique direction.

8. The display device according to claim 7, wherein: The interpolation light emitting transistor in the fifth interpolation pixel is configured to be turned on in response to a first emission control signal, The interpolation light emitting transistor in the third interpolation pixel is configured to be turned on in response to a second emission control signal, The interpolation light emitting transistor in the sixth interpolation pixel is configured to be turned on in response to a third emission control signal, The interpolation light emitting transistor in the first interpolation pixel is configured to be turned on in response to a fourth emission control signal, The normal light emitting transistor in the normal pixel is configured to be turned on in response to a fifth emission control signal, The interpolation light emitting transistor in the second interpolation pixel is configured to be turned on in response to a sixth emission control signal, The interpolation light emitting transistor in the seventh interpolation pixel is configured to be turned on in response to a seventh emission control signal, The interpolation light emitting transistor in the fourth interpolation pixel is configured to be turned on in response to an eighth emission control signal, and The interpolation light emitting transistor in the eighth interpolation pixel is configured to be turned on in response to a ninth emission control signal.

9. The display device according to claim 8, wherein: The fifth emission control signal supplied to the normal pixel is the normal light emitting signal, and Here, each of the first to fourth emission control signals and the sixth to ninth emission control signals supplied to the first to eighth interpolation pixels is the interpolation light emitting signal.

10. The display device according to claim 9, wherein The first to ninth emission control signals are sequentially output during one frame period.

Images