Display panel, manufacturing method thereof and display device

Abstract

The embodiment of the invention discloses a display panel, a manufacturing method thereof and a display device, the display panel comprises a display area, and the display panel in the display area comprises a first substrate; the gate driving circuit is positioned on one side of the first substrate; the second substrate is positioned on one side, far away from the first substrate, of the gate driving circuit; and the pixel driving circuit is positioned on one side, far away from the first substrate, of the second substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] GOA (Gate On Array) technology in display products integrates gate drive circuitry directly onto an array substrate. The gate drive circuitry, comprised of various shift registers, drives the sub-pixel rows within the display area, thereby achieving the product's display functionality. With the continuous advancement of display technology and the desire for a better display experience, narrow-border and even borderless display products have been the goal of major device manufacturers and consumers alike. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device.

[0004] An embodiment of the present disclosure provides a display panel, including a display area, wherein the display panel includes in the display area:

[0005] a first substrate;

[0006] a gate driving circuit, located on one side of the first substrate;

[0007] a second substrate, located on a side of the gate driving circuit away from the first substrate;

[0008] The pixel driving circuit is located on a side of the second substrate away from the first substrate.

[0009] In a possible implementation, in the above-mentioned display panel provided by the embodiment of the present disclosure, the orthographic projection of the gate driving circuit on the first substrate and the orthographic projection of the pixel driving circuit on the first substrate at least partially overlap with each other.

[0010] In one possible implementation, in the display panel provided in an embodiment of the present disclosure, the display area is divided into a first display area, a second display area, and a third display area, which are sequentially arranged along a first direction and extend along a second direction, and the first direction intersects the second direction. The display panel further includes a first border area located on a side of the first display area away from the second display area, and a second border area located on a side of the third display area away from the second display area.

[0011] The gate driving circuit is provided on the first substrate corresponding to at least one of the first display area, the second display area, and the third display area.

[0012] In one possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the gate driving circuit includes a first gate driving circuit located in the first display area, the first gate driving circuit includes a plurality of first shift registers cascaded along the second direction, and the signal output end of each first shift register is electrically connected to the corresponding pixel driving circuit through a first via, and the first via is located in the first border area and arranged along the second direction.

[0013] In one possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the gate driving circuit includes a second gate driving circuit located in the third display area, the second gate driving circuit includes a plurality of second shift registers cascaded along the second direction, and the signal output end of each second shift register is electrically connected to the corresponding pixel driving circuit through a second via, and the second via is located in the second border area and arranged along the second direction.

[0014] In one possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, the gate driving circuit includes a third gate driving circuit located in the second display area, the third gate driving circuit includes a plurality of third shift registers cascaded along the second direction, and the signal output end of each of the third shift registers is electrically connected to the corresponding pixel driving circuit through a third via, and the third vias are located in the second display area and arranged along the second direction.

[0015] In a possible implementation, the display panel provided in the embodiment of the present disclosure further includes a first signal line electrically connected to the pixel driving circuit, and the first signal line is located on a side of the first substrate facing the second substrate.

[0016] In a possible implementation, in the display panel provided by an embodiment of the present disclosure, the first signal line includes an initialization signal line.

[0017] In a possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, the first signal line is electrically connected to the pixel driving circuit through a fourth via hole, and the fourth via hole is located in any area of the first border area, the second border area, and the second display area.

[0018] In a possible implementation, the display panel provided in the embodiment of the present disclosure further includes a plurality of gate drive circuit signal lines electrically connected to the gate drive circuit, and the gate drive circuit signal lines are located on a side of the first substrate facing the second substrate.

[0019] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, the gate drive circuit signal lines include a power line, a clock signal line, and a frame trigger signal line.

[0020] In a possible implementation, the above-mentioned display panel provided in the embodiment of the present disclosure further includes: a third border area connecting the first border area and the second border area, and a test signal line electrically connected to the signal output end of the gate drive circuit; the second substrate includes a first fan-out area corresponding to the third border area, and the first substrate includes at least one first area corresponding to the first fan-out area, and the gate drive circuit signal line, the first signal line and the test signal line are respectively electrically connected to the fan-out trace located in the first fan-out area through their respective corresponding fifth vias, and the orthographic projection of each of the fifth vias on the first substrate is located in the first area.

[0021] In a possible implementation, in the above-mentioned display panel provided in an embodiment of the present disclosure, the number of the first areas is 2, each of the first areas includes the gate drive circuit signal line, the first signal line and the fifth via corresponding to the test signal line, and the two first areas are located at both ends of the first fan-out area along the first direction.

[0022] In a possible implementation, in the display panel provided in an embodiment of the present disclosure, the second substrate further includes, corresponding to the third border area, a bending area, a second fan-out area, and a binding area, which are located on a side of the first fan-out area away from the display area and are sequentially arranged in a direction away from the display area;

[0023] Each of the fan-out traces located in the first fan-out area is electrically connected to the binding area through the bending area and the second fan-out area.

[0024] In one possible implementation, the display panel provided in the embodiment of the present disclosure further includes: a first buffer layer, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, and a first source-drain metal layer, which are located between the first substrate and the second substrate and stacked in sequence in a direction away from the first substrate; and a second buffer layer, a second active layer, a third gate insulating layer, a third gate metal layer, a fourth gate insulating layer, a fourth gate metal layer, a second interlayer insulating layer, and a second source-drain metal layer, which are located on a side of the second substrate away from the first substrate and stacked in sequence in a direction away from the second substrate.

[0025] The pixel driving circuit includes a transistor, the signal output end of the gate driving circuit is located at the first source-drain metal layer, and the signal output end of the gate driving circuit is electrically connected to the gate of the transistor through a first via hole that sequentially penetrates the second substrate, the second buffer layer and the third gate insulation layer.

[0026] In a possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, the first signal line is located in the first source-drain metal layer, and the first signal line is electrically connected to the source of the transistor through a fourth via hole that sequentially passes through the second substrate, the second buffer layer, the third gate insulation layer, the fourth gate insulation layer and the second interlayer insulation layer.

[0027] In a possible implementation, in the above-mentioned display panel provided by an embodiment of the present disclosure, the first signal line is located in the first source-drain metal layer, and the fourth via includes a first sub-via and a second sub-via stacked along the thickness direction of the display panel. The first signal line is electrically connected to the transition portion located in the third gate metal layer through the first sub-via that sequentially penetrates the second substrate, the second buffer layer and the third gate insulation layer, and the transition portion is electrically connected to the source of the transistor through the second sub-via that penetrates the fourth gate insulation layer and the second interlayer insulation layer.

[0028] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, the thickness of the second substrate is smaller than the thickness of the first substrate.

[0029] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, the thickness of the second substrate is 5-10 μm.

[0030] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, both the first substrate and the second substrate are flexible substrates.

[0031] In a possible implementation, in the display panel provided in the embodiment of the present disclosure, the first substrate is a rigid substrate, and the second substrate is a flexible substrate.

[0032] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0033] Accordingly, the embodiment of the present disclosure further provides a method for manufacturing a display panel, which is used to manufacture the above-mentioned display panel provided by the embodiment of the present disclosure. The manufacturing method includes:

[0034] forming a gate driving circuit on one side of the first substrate;

[0035] forming a second substrate on a side of the gate driving circuit away from the first substrate;

[0036] A pixel driving circuit is formed on a side of the second substrate away from the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a plan view of a display panel;

[0038] Figure 2 for Figure 1 A schematic cross-sectional view of a display panel shown;

[0039] Figure 3 for Figure 1 Another cross-sectional schematic diagram of the display panel shown;

[0040] Figure 4 A pixel driving circuit 4 having an 8T1C structure;

[0041] Figure 5 for Figure 1 A schematic diagram of the planar structure of the first substrate and the gate drive circuit thereon;

[0042] Figure 6 for Figure 5 A partial enlarged schematic diagram;

[0043] Figure 7 It is a shift register with 9T3C structure;

[0044] Figure 8 It is a shift register with 16T3C structure;

[0045] Figure 9 A schematic diagram of a layout and driving method of a gate driving circuit in a display panel provided by an embodiment of the present disclosure;

[0046] Figure 10 Indicate Figure 9 A partial enlarged schematic diagram of the display panel shown;

[0047] Figure 11 A schematic diagram of another layout and driving method of a gate driving circuit in a display panel provided by an embodiment of the present disclosure;

[0048] Figure 12 Indicate Figure 11 A partial enlarged schematic diagram of the display panel shown;

[0049] Figure 13 A schematic diagram of another layout and driving method of a gate driving circuit in a display panel provided by an embodiment of the present disclosure;

[0050] Figure 14 Indicate Figure 13 A partial enlarged schematic diagram of the display panel shown;

[0051] Figure 15 for Figure 1 Another cross-sectional schematic diagram of the display panel shown;

[0052] Figure 16 for Figure 1 Another cross-sectional schematic diagram of the display panel shown;

[0053] Figure 17 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure;

[0054] Figure 18 A schematic plan view of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0058] The present disclosure provides a display panel. Figure 1-Figure 3 As shown, Figure 1 is a plan view of the display panel. Figure 2 for Figure 1 A cross-sectional schematic diagram of a display panel shown in FIG. Figure 3 for Figure 1 Another cross-sectional schematic diagram of a display panel is shown, wherein the display panel includes a display area AA. The display panel includes in the display area AA:

[0059] a first substrate 1;

[0060] A gate drive circuit 2 (GOA), located on one side of the first substrate 1;

[0061] The second substrate 3 is located on a side of the gate driving circuit 2 away from the first substrate 1;

[0062] The pixel driving circuit 4 is located on a side of the second substrate 3 away from the first substrate 1 .

[0063] The above-mentioned display panel provided by the embodiment of the present disclosure arranges the gate driving circuit and the pixel driving circuit on different substrates, so that the entire first substrate can be used for the layout and production of the gate driving circuit, eliminating the space required for arranging the gate driving circuit at the left and right borders of the traditional display panel, thereby realizing a display panel with an ultra-narrow border or even a borderless design.

[0064] It should be noted that, in order to clearly illustrate that the gate driving circuit 2 is provided on the first substrate 1 and the pixel driving circuit 4 is provided on the second substrate 3, Figure 1 The display panel shown schematically illustrates that the first substrate 1 and the second substrate 3 are separated and staggered. In an actual display panel, the first substrate 1 and the second substrate 3 are stacked and overlapped.

[0065] In some embodiments, the display panel provided by the embodiments of the present disclosure may be an organic electroluminescent display panel (OLED), a stacked organic electroluminescent display panel (Tandom OLED), a quantum dot organic electroluminescent display panel (QLED), a light emitting diode (LED, Light Emitting Diode) display panel, a micro LED (including: mini-LED or micro-LED) display panel or an LCD display panel (Liquid Crystal Display).

[0066] The following describes the content of the present disclosure by taking the display panel provided in the embodiment of the present disclosure as an OLED as an example.

[0067] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1-Figure 3As shown, the display area AA of the second substrate 3 generally includes multiple gate lines (Gata Line, not shown) and multiple data lines (Data Line, not shown). The multiple gate lines and the multiple data lines are cross-set and define multiple pixel units. The pixel unit includes a connected pixel driving circuit 4 and a light-emitting device 5. The pixel driving circuit 4 is generally composed of transistors (T) and capacitors (C). For example, the pixel driving circuit 4 can be a 2T1C, 3T1C, 7T1C, 8T1C and other structures. The working principles of these pixel driving circuits 4 are the same or similar to those of the prior art and will not be described in detail here. For example, Figure 4 As shown, Figure 4 The pixel driving circuit 4 has an 8T1C structure, wherein the signal lines electrically connected to the gates of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 (e.g., the reset signal line Reset_P, the reset signal line Reset_N, the light-emitting control signal line EM, the gate line Gate_P, the gate line Gate_N) all need to be electrically connected to different gate driving circuits 2, and driving signals are provided to these signal lines by the gate driving circuit 2. The light-emitting device 5 generally includes an anode 51, a light-emitting layer 52, and a cathode 53 stacked in sequence in a direction away from the second substrate 3. For example, the anode 51 is electrically connected to the drain D of the transistor (T) in the pixel driving circuit 4, the data line is electrically connected to the source S of the transistor (T) in the pixel driving circuit 4, and the gate line is electrically connected to the gate G of the transistor (T) in the pixel driving circuit 4.

[0068] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, it also includes a pixel defining layer 6, which is produced after the anode 51 and before the light-emitting layer 52. The pixel defining layer 6 has a pixel opening that exposes part of the surface of the anode 51, and the light-emitting layer 52 is located in the pixel opening. It can also include a spacer 7 (PS) located between the pixel defining layer 6 and the cathode 53, and can also include an encapsulation layer (not shown) located on the side of the light-emitting device 5 away from the first substrate 1, and can also include a touch layer located on the side of the encapsulation layer away from the first substrate 1, and so on.

[0069] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1-Figure 3 、 Figure 5 and Figure 6 As shown, Figure 5 for Figure 1 Schematic diagram of the planar structure of the first substrate 1 and the gate drive circuit 2 thereon, Figure 6 for Figure 5As shown in the partial enlarged schematic diagram, each gate drive circuit 2 is generally composed of a plurality of cascaded shift registers (GOA1 to GOAn), each shift register includes a plurality of transistors (T) and capacitors (C), for example, the shift register can be a 9T3C, 16T3C or other structure. Figure 7 and Figure 8 As shown, Figure 7 It is a shift register with 9T3C structure. Figure 8 The shift register has a 16T3C structure. For example, the signal output terminals OUT of each shift register are electrically connected to the gate lines of the display area AA in a one-to-one correspondence. Thus, through the interaction of the transistors and capacitors of the shift register, the signal output terminals OUT of each shift register output the shift register signal to the gates of the corresponding transistors, thereby driving the pixel unit rows of the display area AA row by row. Furthermore, through the interaction of the transistors of the pixel driving circuit 4, the light-emitting devices 5 are driven to emit light.

[0070] In some embodiments, Figure 4 Taking the pixel driving circuit shown in FIG. 1 as an example, the gate driving circuit 2 may include five groups of GOAs, such as Reset_P GOA1 to GOAn, Reset_N GOA1 to GOAn, EM GOA1 to GOAn, Gate_P GOA1 to GOAn, and Gate_N GOA1 to GOAn. Of course, the type and number of GOAs may vary depending on the pixel driving circuit used, and should be designed based on actual needs.

[0071] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, since the pixel driving circuit 4 is manufactured in the display area AA, the present disclosure arranges the orthographic projection of the gate driving circuit 2 on the first substrate 1 to at least partially overlap with the orthographic projection of the pixel driving circuit 4 on the first substrate 1, that is, the gate driving circuit 2 is also manufactured in the display area AA, thereby eliminating the space for arranging the gate driving circuit at the left and right borders of the traditional display panel, thereby realizing a display panel with an ultra-narrow border or even a borderless design.

[0072] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1-Figure 3 As shown, the orthographic projections of some transistors of the gate driving circuit 2 and some transistors of the pixel driving circuit 4 on the first substrate 1 may overlap.

[0073] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, Figure 9A schematic diagram of a layout and driving method of a gate drive circuit in a display panel provided in an embodiment of the present disclosure shows that the display area AA can be divided into a first display area A1, a second display area A2, and a third display area A3, which are sequentially arranged along a first direction X (e.g., a horizontal direction) and extend along a second direction Y (e.g., a vertical direction). The first direction X and the second direction Y intersect. The display panel further includes a first border area B1 located on a side of the first display area A1 away from the second display area A2, and a second border area B2 located on a side of the third display area A3 away from the second display area A2.

[0074] The first substrate 1 is provided with a gate drive circuit 2 corresponding to at least one of the first display area A1, the second display area A2, and the third display area A3. Thus, the present disclosure fabricates the gate drive circuit 2 in at least one of the first display area A1, the second display area A2, and the third display area A3, thereby eliminating the space required for the gate drive circuit to be arranged within the first and second border areas B1 and B2 of a conventional display panel. This allows for a display panel with ultra-narrow borders in the first and second border areas B1 and B2, or even without the first and second border areas B1 and B2.

[0075] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, the gate drive circuit 2 may include a first gate drive circuit 21 located in the first display area A1. For example, the first gate drive circuit 21 may include the five groups of GOAs, namely, Reset_P GOA1 to GOAn, Reset_NGOA1 to GOAn, EM GOA1 to GOAn, Gate_P GOA1 to GOAn, and Gate_N GOA1 to GOAn, as described above. These five groups of GOAs located in the first display area A1 may be referred to as the first gate drive circuit 21. Each first gate drive circuit 21 includes a plurality of first shift registers (such as GOA1 to GOAn, not shown) cascaded along the second direction Y. The arrangement of these five groups of GOAs may refer to FIG. Figure 1 In the GOA arrangement, the signal output end OUT of each first shift register (GOA1~GOAn) is electrically connected to the corresponding pixel driving circuit 4 through the first via V1. For example, the signal output end OUT of each first shift register (GOA1~GOAn) is electrically connected to one end of the corresponding reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N through the first via V1, and the reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N are electrically connected to the gates of the transistors of the pixel driving circuit 4, so that the first gate driving circuit 21 drives the pixel driving circuit 4. The first via V1 is located in the first border area B1 and is arranged along the second direction Y.

[0076] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 and Figure 10 As shown, Figure 10 Indicate Figure 9 The partially enlarged schematic diagram of the display panel shown in the figure shows that the gate drive circuit 2 may include a second gate drive circuit 22 located in the third display area A3. For example, the second gate drive circuit 22 may include the five groups of GOAs, namely, Reset_P GOA1 to GOAn, Reset_N GOA1 to GOAn, EM GOA1 to GOAn, Gate_P GOA1 to GOAn, and Gate_N GOA1 to GOAn, as described above. These five groups of GOAs located in the third display area A3 may be referred to as the second gate drive circuit 22. Each second gate drive circuit 22 includes a plurality of second shift registers (such as GOA1 to GOAn, not shown) arranged in cascade along the second direction Y. The arrangement of these five groups of GOAs can be seen in FIG. Figure 1 In the GOA arrangement, the signal output end OUT of each second shift register (GOA1~GOAn) is electrically connected to the corresponding pixel driving circuit 4 through the second via V2. For example, the signal output end OUT of each second shift register (GOA1~GOAn) is electrically connected to the other end of the corresponding reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N through the second via V2. The reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N are electrically connected to the gates of the transistors of the pixel driving circuit 4, so that the second gate driving circuit 22 drives the pixel driving circuit 4, thereby realizing that the gate driving circuit 2 drives the pixel driving circuit 4 on both sides. The second vias V2 are located in the second border area B2 and are arranged along the second direction Y.

[0077] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, the first gate driving circuit 21 can be set in the area of the first display area A1 close to the first border area B1, and the second gate driving circuit 22 can be set in the area of the third display area A3 close to the second border area B2, that is, the gate driving circuit 2 is distributed on both the left and right sides of the display panel. In this way, the driving of the pixel driving circuit 4 is bilateral driving. Bilateral driving can reduce RC Loading during unilateral driving and improve the display effect. Figure 9 The double arrows in the figure indicate the driving direction of each gate driving circuit 2 on the pixel driving circuit 4 .

[0078] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, the first gate driving circuit 21 can be set only in the first display area A1, so that the pixel driving circuit 4 is driven from left to right (unilateral driving); the second gate driving circuit 22 can also be set only in the third display area A3, so that the pixel driving circuit 4 is driven from right to left (unilateral driving).

[0079] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 and Figure 10 As shown, the connection positions (first vias V1 and second vias V2) between the signal output terminals OUT of each first shift register (GOA1~GOAn) and each second shift register (GOA1~GOAn) and the pixel driving circuit 4 are distributed in the first border area B1 and the second border area B2 of the display panel, that is, the connection positions (first vias V1 and second vias V2) are distributed on the left and right sides of the display panel, close to the display area AA. The shapes of the first vias V1 and the second vias V2 can be rectangular or circular, and the specific shapes are determined by the process and capabilities.

[0080] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1 and Figure 9 As shown, it also includes a first signal line (not shown) electrically connected to the pixel driving circuit 4, and the first signal line is located on the side of the first substrate 1 facing the second substrate 3. Specifically, the first signal line may include an initialization signal line (such as Vinit1 / Vinit2 / Vinit3), for example, Vinit1 and Figure 4 The source of the first transistor T1 is electrically connected to Vinit2. Figure 4 The source of the seventh transistor T7 is electrically connected to Vinit3. Figure 4 The source of the eighth transistor T8 is electrically connected to Vinit1 / Vinit2 / Vinit3, which is used to drive the pixel driving circuit 4. In the present disclosure, Vinit1 / Vinit2 / Vinit3 are fabricated on the first substrate 1. On the one hand, this facilitates achieving an ultra-narrow bezel effect. On the other hand, due to the ample space on the first substrate 1, the DC signal traces of Vinit1 / Vinit2 / Vinit3 can be made wider, with smaller resistance and less DC signal attenuation.

[0081] It should be noted that the embodiment of the present disclosure takes the first signal line as the initialization signal line (Vinit1 / Vinit2 / Vinit3) as an example, but is certainly not limited thereto. For example, other signal lines electrically connected to the pixel driving circuit 4 may be fabricated on the first substrate 1, such as Figure 4 The high voltage power line (VDD) in the .

[0082] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 and Figure 10 As shown, the first signal line (e.g., Vinit1 / Vinit2 / Vinit3) is electrically connected to the pixel driving circuit through the fourth via hole V4. The fourth via hole V4 can be located in the first border area B1 and / or the second border area B2. Specifically, the first border area B1 may include multiple first via holes V1 and multiple fourth via holes V4. Figure 9 It is only shown that the first frame area B1 includes the first via hole V1 and the fourth via hole V4. The specific positions of the first via hole V1 and the fourth via hole V4 are determined by the process. The second frame area B2 may include multiple second via holes V2 and multiple fourth via holes V4. Figure 9 It is merely shown that the second frame area B2 includes the second via hole V2 and the fourth via hole V4 , and the specific positions of the second via hole V2 and the fourth via hole V4 are determined by the process.

[0083] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, in order to achieve the effect of a super narrow bezel, the embodiments of the present disclosure manufacture Vinit1 / Vinit2 / Vinit3 on the first substrate 1. In fact, if conditions permit, Vinit1 / Vinit2 / Vinit3 can also be manufactured on the second substrate 3. In this way, Vinit1 / Vinit2 / Vinit3 does not need to jump through holes to the first substrate 1 for routing, thereby reducing the difficulty of the process.

[0084] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1 and Figure 9 As shown, it also includes a plurality of gate drive circuit signal lines (not shown) electrically connected to the gate drive circuit 2. The gate drive circuit signal lines are used to drive the gate drive circuit 2. The gate drive circuit signal lines are located on the side of the first substrate 1 facing the second substrate 3. Specifically, the gate drive circuit signal lines may include power lines (e.g., high voltage power lines VGH1 / VGH2, low voltage power lines VGL1 / VGL2), clock signal lines (CLK), and frame trigger signal lines (STV). The present disclosure fabricates the gate drive circuit 2 and the gate drive circuit signal lines on the first substrate 1 with sufficient space, which is conducive to realizing a display panel with an ultra-narrow border or even a borderless design.

[0085] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1 、 Figure 9 and Figure 10As shown, it also includes: a third border area B3 connecting the first border area B1 and the second border area B2, and a test signal line (not shown) electrically connected to the signal output terminal OUT of the gate drive circuit 2; the second substrate 3 includes a first fan-out area 11 corresponding to the third border area B3, and the first substrate 1 includes at least one first area D1 corresponding to the first fan-out area 11, and the gate drive circuit signal line (VGH1 / VGH2 / VGL1 / VGL2 / CLK / STV), the first signal line (Vinit1 / Vinit2 / Vinit3) and the test signal line are respectively electrically connected to the fan-out trace located in the first fan-out area 11 through their respective corresponding fifth vias V5, and the orthographic projection of each fifth via V5 on the first substrate 1 is located in the first area D1. Specifically, the gate drive circuit signal lines (VGH1 / VGH2 / VGL1 / VGL2 / CLK / STV), the first signal lines (Vinit1 / Vinit2 / Vinit3) and the test signal lines are all made on the first substrate 1, and a first fan-out area 11 is set on the second substrate 2. The first fan-out area 11 includes multiple fan-out lines made on the second substrate 3. For example, the fan-out lines include a data fan-out line, a first power line and a second power line. The data fan-out line is located in the middle of the first fan-out area 11 and is connected to the data line of the display area AA in a fan-out (Fanout) routing manner. The first power line is configured to connect the high voltage power line (VDD) of the display area AA, and the second power line is a low voltage power line (VSS) located in the first border area B1 and the second border area B2. That is, the present disclosure manufactures the pixel driving circuit 4, fan-out wiring, VDD, and VSS signal lines on the second substrate 3, so that VGH1 / VGH2 / VGL1 / VGL2 / CLK / STV, Vinit1 / Vinit2 / Vinit3 and the test signal lines all need to jump through a hole (fifth via V5) to the second substrate 3 and be electrically connected to the fan-out wiring of the first fan-out area 11, and then be led out through the fan-out wiring.

[0086] In some embodiments, each group of gate drive circuits usually has a signal output terminal OUT electrically connected to one end of the test signal line, and the other end of the test signal line is electrically connected to the fan-out trace located on the second substrate 3 through the fifth via V5. The fan-out trace is then led to the IC and FPC for subsequent use of an oscilloscope to capture waveforms to confirm whether the output of each gate drive circuit 2 is normal.

[0087] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 and Figure 10As shown, since the gate drive circuit 2 adopts bilateral drive, the number of first areas D1 is 2, and each first area D1 includes a gate drive circuit signal line (VGH1 / VGH2 / VGL1 / VGL2 / CLK / STV), a first signal line (Vinit1 / Vinit2 / Vinit3) and a fifth via V5 corresponding to the test signal line. The two first areas D1 are located at both ends of the first fan-out area 11 along the first direction X, that is, the two first areas D1 are distributed on the lower left and lower right sides of the display panel, close to the display area AA. The shape of the fifth via V5 can be rectangular or circular, and the specific shape is determined by the process and capability.

[0088] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, the second substrate 3, corresponding to the third frame area B3, also includes a bending area 12, a second fan-out area 13, and a binding area 14, which are located on the side of the first fan-out area 11 away from the display area AA and are arranged in sequence along the direction away from the display area AA; each fan-out trace located in the first fan-out area 11 is electrically connected to the binding area 14 through the bending area 12 and the second fan-out area 13. Specifically, the binding area 14 may include a driver chip area 141, a third fan-out area 142, and a binding electrode area 143, which are arranged in sequence along the direction of the second fan-out area 13 away from the bending area 12. The bending area 12 may include a composite insulating layer provided with a groove, which is configured to bend the binding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines, etc. led out in the form of fan-out traces. The driver chip area 141 may be provided with an integrated circuit (IC) 10, which is configured to be connected to the multiple data connection lines of the second fan-out area 13. The binding electrode area 143 includes a plurality of binding pads (Bonding Pad), which are configured to be bound and connected to a flexible printed circuit (FPC). In some embodiments, the IC can be bound and connected to the driver chip area 141, and the FPC can be bound and connected to the binding electrode area 143. In some embodiments, the IC can generate a driving signal required to drive the pixel unit, and can provide the driving signal to the pixel unit located in the display area AA. For example, the driving signal can be a data signal that controls the brightness of the pixel unit. In some embodiments, the binding electrode area 143 can be provided with a pad (PAD) including a plurality of pins (PINs), and the FPC can be bound and connected to the pad.

[0089] It should be noted that the fan-out lines that are connected to the second substrate 3 through the fifth via V5 are routed together with the data fan-out lines into the bending area 12 .

[0090] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 9 As shown, a fourth border area B4 arranged opposite to the third border area B3 is also included. The fourth border area B4 is used for laying out VSS, VDD, ESD protection units, etc.

[0091] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 11 and Figure 12 As shown, Figure 11 A schematic diagram of another layout and driving method of a gate driving circuit in a display panel provided in an embodiment of the present disclosure is provided. Figure 12 Indicate Figure 11 The partially enlarged schematic diagram of the display panel shown is Figure 11 and Figure 9 One difference is that: Figure 11 The gate drive circuit 2 in the display panel shown further includes a third gate drive circuit 23 located in the second display area A2. For example, the third gate drive circuit 23 may include the five groups of GOAs, namely, Reset_P GOA1 to GOAn, Reset_N GOA1 to GOAn, EM GOA1 to GOAn, Gate_P GOA1 to GOAn, and Gate_N GOA1 to GOAn, as described above. These five groups of GOAs located in the second display area A2 may be referred to as the third gate drive circuit 23. Each third gate drive circuit 23 includes a plurality of third shift registers (such as GOA1 to GOAn, not shown) arranged in cascade along the second direction Y. The arrangement of these five groups of GOAs can be seen in FIG. Figure 1 In the GOA arrangement, the signal output end OUT of each third shift register (GOA1~GOAn) is electrically connected to the corresponding pixel driving circuit 4 through the third via V3. For example, the signal output end OUT of each third shift register (GOA1~GOAn) is electrically connected to one end of the corresponding reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N through the third via V3. The reset signal line Reset_P, reset signal line Reset_N, light-emitting control signal line EM, gate line Gate_P and gate line Gate_N are electrically connected to the gates of the transistors of the pixel driving circuit 4, so that the third gate driving circuit 23 drives the pixel driving circuit 4. The third vias V3 are located in the second display area A2 and are arranged along the second direction Y.

[0092] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 11As shown, the third gate driving circuit 23 can be arranged in the central area of the second display area A2, that is, the gate driving circuit 2 is arranged in the middle of the display area AA, so that the gate driving circuit 2 is distributed on the left and right sides and the middle position of the display panel. The first gate driving circuit 21 drives the pixel driving circuit 4 from left to right (unilateral drive), the second gate driving circuit 22 drives the pixel driving circuit 4 from right to left (unilateral drive), and the third gate driving circuit 23 drives the pixel driving circuit 4 from the middle to both sides. Figure 11 The double arrows in the figure indicate the driving direction of each gate driving circuit 2 on the pixel driving circuit 4 .

[0093] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 11 and Figure 12 As shown, the connection position (third via V3) between the signal output terminal OUT of each third shift register (GOA1~GOAn) and the pixel driving circuit 4 is distributed in the middle of the display area AA, that is, the connection position (third via V3) is distributed in the middle position of the display panel. The shape of the third via V3 can be rectangular or circular, and the specific shape is determined by the process and capability.

[0094] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 11 and Figure 12 As shown, Figure 11 and Figure 9 Another difference is that: Figure 11 The first signal lines (e.g., Vinit1 / Vinit2 / Vinit3) can also be electrically connected to the pixel driving circuit 4 through the fourth via V4 located in the second display area A2. The fourth via V4 and the third via V3 are located in the same column along the second direction. In this way, the first signal lines (e.g., Vinit1 / Vinit2 / Vinit3) are electrically connected to the pixel driving circuit 4 through the fourth via V4 located in the first border area B1, the second border area B2, and the second display area A2, which is more conducive to reducing the voltage attenuation of the Vinit signal group.

[0095] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 11 and Figure 12 As shown, the middle area of the second display area A2 may include a plurality of third via holes V3 and a plurality of fourth via holes V4. Figure 11 It is merely shown that the middle area of the second display area A2 includes the third via hole V3 and the fourth via hole V4 . The specific positions of the third via hole V3 and the fourth via hole V4 are determined by the manufacturing process.

[0096] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 13and Figure 14 As shown, Figure 13 A schematic diagram of another layout and driving method of a gate driving circuit in a display panel provided in an embodiment of the present disclosure is provided. Figure 14 Indicate Figure 13 The partially enlarged schematic diagram of the display panel shown is Figure 13 and Figure 11 The difference is: Figure 13 The display panel shown is provided with the third gate driving circuit 23 only in the second display area A2. The third gate driving circuit 23 drives the pixel driving circuit 4 from the middle to both sides. Figure 13 The double arrows in FIG. 5 represent the driving direction of the pixel driving circuit 4 by the third gate driving circuit 23 .

[0097] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, the present invention further includes: a first buffer layer 5, a first active layer 6, a first gate insulating layer 7, a first gate metal layer 8, a second gate insulating layer 9, a second gate metal layer 10, a first interlayer insulating layer 15, and a first source-drain metal layer 16, which are located between the first substrate 1 and the second substrate 3 and are stacked in sequence in a direction away from the first substrate 1; and a second buffer layer 17, a second active layer 18, a third gate insulating layer 19, a third gate metal layer 20, a fourth gate insulating layer 21, a fourth gate metal layer 22, a second interlayer insulating layer 23, and a second source-drain metal layer 24, which are located on a side of the second substrate 3 away from the first substrate 1 and are stacked in sequence in a direction away from the second substrate 3;

[0098] The pixel driving circuit 4 includes transistors (eg Figure 4 As shown), the signal output terminal OUT of the gate drive circuit 2 is located at the first source-drain metal layer 16, and the signal output terminal OUT of the gate drive circuit 2 passes through the first via hole V1 ( Figure 9 As shown) is electrically connected to the gate of the transistor of the pixel driving circuit 4. For example, the OUT of Reset_P GOA1 to GOAn provided on the first substrate 1 is electrically connected to the gate of the transistor of the pixel driving circuit 4. Figure 4 The gates of the seventh transistor T7 and the eighth transistor T8 are electrically connected, and the OUT of Reset_N GOA1 to GOAn on the first substrate 1 is connected to Figure 4 The gate of the first transistor T1 is electrically connected to the OUT of the EM GOA1 to GOAn on the first substrate 1. Figure 4 The gates of the fifth transistor T5 and the sixth transistor T6 are electrically connected, and the OUT terminals of Gate_P GOA1 to GOAn on the first substrate 1 are electrically connected. Figure 4The gate of the first transistor T1 is electrically connected to the OUT of Gate_N GOA1 to GOAn on the first substrate 1. Figure 4 The gate of the second transistor T2 is electrically connected.

[0099] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, it also includes a flat layer 25 located between the second source / drain metal layer 24 and the anode 51. The anode 51 is connected to the transistors (eg, Figure 4 The drain D of T7) is electrically connected.

[0100] In some embodiments, the material of the first buffer layer may be SiO2, the material of the first active layer may be P-Si, the material of the first gate insulating layer may be SiO2, the material of the first gate metal layer and the second gate metal layer may be Mo, the material of the second gate insulating layer may be SiNx, the material of the first interlayer insulating layer may be SiO2+SiNx, and the material of the first source / drain metal layer may be Ti / Al / Ti.

[0101] In some embodiments, the material of the second buffer layer may be SiO2, the material of the second active layer may be P-Si, the material of the third gate insulating layer may be SiO2, the material of the third gate metal layer and the fourth gate metal layer may be Mo, the material of the fourth gate insulating layer may be SiNx, the material of the second interlayer insulating layer may be SiO2+SiNx, the material of the second source / drain metal layer may be Ti / Al / Ti, the material of the planarizing layer may be PI glue, the material of the anode may be ITO / Ag / ITO, the material of the pixel defining layer may be PI glue, and the material of the spacer may be PI glue.

[0102] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2As shown, the first signal line (for example, Vinit1 / Vinit2 / Vinit3) is located in the first source-drain metal layer 16, and the first signal line (for example, Vinit1) is electrically connected to the source S of the transistor (for example, T1) of the pixel driving circuit 4 through the fourth via hole V4 that sequentially penetrates the second substrate 3, the second buffer layer 17, the third gate insulating layer 19, the fourth gate insulating layer 21 and the second interlayer insulating layer 23. The first signal line (for example, Vinit2) is electrically connected to the source S of the transistor (for example, T7) of the pixel driving circuit 4 through the fourth via hole V4 that sequentially penetrates the second substrate 3, the second buffer layer 17, the third gate insulating layer 19, the fourth gate insulating layer 21 and the second interlayer insulating layer 23. The first signal line (for example, Vinit3) is electrically connected to the source S of the transistor (for example, T8) of the pixel driving circuit 4 through the fourth via hole V4 that sequentially penetrates the second substrate 3, the second buffer layer 17, the third gate insulating layer 19, the fourth gate insulating layer 21 and the second interlayer insulating layer 23. Specifically, the pixel driving circuit 4 on the second substrate 3 is electrically interconnected with the gate driving circuit 2 / first signal line on the first substrate 1 through exposure, development, etching process or laser drilling process, and the first source and drain metal layer 16 on the first substrate 1 and the second source and drain metal layer 24 on the second substrate 3 can be directly interconnected.

[0103] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 3As shown, the first signal line (for example, Vinit1 / Vinit2 / Vinit3) is located in the first source-drain metal layer 16, and the fourth via hole V4 includes a first sub-via hole V41 and a second sub-via hole V42 stacked along the thickness direction of the display panel; the first signal line (for example, Vinit1) is electrically connected to the transition portion 26 located in the third gate metal layer 20 through the first sub-via hole V41 that sequentially penetrates the second substrate 3, the second buffer layer 17 and the third gate insulating layer 19, and the transition portion 26 is electrically connected to the source electrode S of the transistor (for example, T1) of the pixel driving circuit 4 through the second sub-via hole V42 that penetrates the fourth gate insulating layer 21 and the second interlayer insulating layer 23; the second signal line (for example, Vinit2) is electrically connected to the source electrode S of the transistor (for example, T1) of the pixel driving circuit 4 through the second sub-via hole V42 that sequentially penetrates the second substrate 3, the second buffer layer 17 and the third gate insulating layer 19. Another first sub-via V41 of the buffer layer 17 and the third gate insulating layer 19 is electrically connected to another transition portion 26 located in the third gate metal layer 20, and the transition portion 26 is electrically connected to the source S of the transistor (for example, T7) of the pixel driving circuit 4 through a second sub-via V42 that penetrates the fourth gate insulating layer 21 and the second interlayer insulating layer 23; the first signal line (for example, Vinit3) is electrically connected to another transition portion 26 located in the third gate metal layer 20 through another first sub-via V41 that penetrates the second substrate 3, the second buffer layer 17 and the third gate insulating layer 19 in sequence, and the transition portion 26 is electrically connected to the source S of the transistor (for example, T8) of the pixel driving circuit 4 through a second sub-via V42 that penetrates the fourth gate insulating layer 21 and the second interlayer insulating layer 23. Specifically, the pixel driving circuit 4 on the second substrate 3 is electrically interconnected with the gate driving circuit 2 / first signal line on the first substrate 1 through exposure, development, etching process or laser drilling process, and the first source and drain metal layer 16 on the first substrate 1 and the transition part 26 located in the third gate metal layer 20 can be interconnected through a jump hole, and the transition part 26 and the second source and drain metal layer 24 on the second substrate 3 are interconnected through a jump hole.

[0104] In some embodiments, Vinit1 / Vinit2 / Vinit3 may be a grid structure located in the first source / drain metal layer 16 .

[0105] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, since the entire first substrate 1 can be used for the layout and manufacture of the gate drive circuit 2 and there is sufficient space, only a single first source and drain metal layer needs to be provided on the first substrate 1 to reduce the increase in the manufacturing mask.

[0106] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 、 Figure 3 、 Figure 7 and Figure 8As shown, the gate drive circuit 2 on the first substrate 1 is based on the example of each transistor T being a PMOS type. If a CMOS type transistor T needs to be manufactured on the first substrate 1, Figure 2 and Figure 3 The stack diagram should also include some buffer layers, active layers (IGZO), gate insulation layers, gate metal layers and other film layers.

[0107] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, since exposure, development, etching process or laser drilling process is required to interconnect the gate drive circuit 2 / first signal line with the pixel drive circuit 4, the second substrate 3 can be made thinner according to actual process requirements. For example, the thickness of the second substrate 3 is less than the thickness of the first substrate 1. The minimum thickness standard of the second substrate 3 is that the second substrate 3 needs to completely cover the gate drive circuit 2 and play a flattening role to facilitate the subsequent production of the pixel drive circuit 4. For example, the thickness of the second substrate 3 can be 5-10μm.

[0108] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 2 and Figure 3 As shown, the schematic diagram of the stacking on the second substrate 3 is only a brief explanation of the main film layers included in the pixel driving circuit 4. If LTPO, high PPI and other technical products are to be applied, the pixel driving circuit 4 stacking is likely to also include some buffer layers, active layers (IGZO), gate insulation layers, gate metal layers, planar layers, source and drain metal layers, planar layers, source and drain metal layers and other film layers.

[0109] In some embodiments, in the above-mentioned display panel provided in the embodiments of the present disclosure, such as 1- Figure 3 As shown, the first substrate 1 and the second substrate 3 can both be flexible substrates, that is, the display panel provided in the embodiment of the present disclosure is a flexible display panel. Specifically, the flexible substrate can be made of polyimide (PI). PI substrates have high and low temperature resistance and good mechanical properties, which helps release stress and block the adverse effects of energy, static electricity, etc. on the upper film layer.

[0110] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as Figure 1 、 Figure 15 and Figure 16 As shown, Figure 15 and Figure 2 The difference and Figure 16 and Figure 3 The only difference is: Figure 1 、 Figure 15 and Figure 16The first substrate 1 is a rigid substrate, that is, the display panel provided by the embodiment of the present disclosure is a rigid display panel. Specifically, the material of the rigid substrate can be glass or the like.

[0111] It should be noted that the manufacturing process and layout of the gate driving circuit on the display panel using a rigid substrate are the same as the manufacturing process and layout of the gate driving circuit on the display panel using a flexible substrate described above, and will not be described in detail here.

[0112] It should be noted that other essential components of the display panel are well understood by those skilled in the art and are not described in detail here and should not be construed as limiting the present disclosure.

[0113] Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned display panel. Since the principle of solving the problem by the manufacturing method is similar to the principle of solving the problem by the above-mentioned display panel, the implementation of the manufacturing method provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned display panel provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0114] In some embodiments, the present disclosure provides a method for manufacturing a display panel, such as Figure 17 Shown, including:

[0115] S1701, forming a gate driving circuit on one side of a first substrate;

[0116] S1702, forming a second substrate on a side of the gate driving circuit away from the first substrate;

[0117] S1703 , forming a pixel driving circuit on a side of the second substrate away from the first substrate.

[0118] Below Figure 2 Taking the structure shown as an example, the manufacturing process of the display panel provided by the embodiment of the present disclosure is briefly described, which may specifically include the following steps:

[0119] (1) PI material is coated on a glass substrate to form the first substrate 1.

[0120] (2) The gate drive circuit 2, the gate drive circuit signal line and the first signal line are fabricated on the first substrate 1.

[0121] (3) PI material is coated on the gate drive circuit 2 to form the second substrate 3.

[0122] (4) Fabricate pixel driving circuit 4, Fanout wiring, etc. on the second substrate 3. In this process step, it is necessary to use exposure, development, etching process or laser drilling process to make connection holes to electrically interconnect the gate driving circuit 2 / first signal line and the pixel driving circuit 4.

[0123] (5) The anode 51 , the pixel defining layer 6 , the light emitting layer 52 , the spacer 7 and the cathode 53 are sequentially formed on the pixel driving circuit 4 .

[0124] (6) An encapsulation layer having a sandwich structure of inorganic layer / organic layer / inorganic layer is prepared on the cathode 53 based on a vacuum coating process to block the penetration of components such as water and oxygen to protect the light-emitting layer 52.

[0125] (7) The conventional LLO (laser lift-off technology) is used to separate the glass substrate from the first substrate 1 to remove the glass substrate.

[0126] (8) Cutting the completed large display panel into individual cells, and making the cells into OLED display panels.

[0127] Below Figure 15 Taking the structure shown as an example, the manufacturing process of the display panel provided by the embodiment of the present disclosure is briefly described, which may specifically include the following steps:

[0128] (1) A first buffer layer 5 is formed on a glass substrate.

[0129] (2) The gate drive circuit 2 , the gate drive circuit signal line, and the first signal line are fabricated on the first buffer layer 5 .

[0130] (3) PI material is coated on the gate drive circuit 2 to form the second substrate 3.

[0131] (4) Fabricate pixel driving circuit 4, Fanout wiring, etc. on the second substrate 3. In this process step, it is necessary to use exposure, development, etching process or laser drilling process to make connection holes to electrically interconnect the gate driving circuit 2 / first signal line and the pixel driving circuit 4.

[0132] (5) The anode 51 , the pixel defining layer 6 , the light emitting layer 52 , the spacer 7 and the cathode 53 are sequentially formed on the pixel driving circuit 4 .

[0133] (6) An encapsulation layer having a sandwich structure of inorganic layer / organic layer / inorganic layer is prepared on the cathode 53 based on a vacuum coating process to block the penetration of components such as water and oxygen to protect the light-emitting layer 52.

[0134] (7) Thinning the glass substrate, usually from a 0.5 mm thick glass substrate to a 0.2 mm thick glass substrate, to form a first substrate 1 made of glass.

[0135] (8) Cutting the completed large display panel into individual cells, and making the cells into OLED display panels.

[0136] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising the aforementioned display panel provided in embodiments of the present disclosure. Because the principles underlying the problems solved by the display device are similar to those of the aforementioned display panel, the implementation of the display device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated.

[0137] In specific implementations, the display panel provided in the embodiments of the present disclosure may be a liquid crystal display device, an OLED display device, etc. The display device may also include other necessary components and elements, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art may supplement these components accordingly based on the specific usage requirements of the display device. Detailed descriptions are omitted here and should not be construed as limiting the present disclosure.

[0138] In specific implementation, the display device provided by the embodiment of the present disclosure may be as follows: Figure 18 The full-screen mobile phone shown. Of course, the above-mentioned display device provided in the embodiment of the present disclosure can also be any product or component with a display function, such as a projector, a 3D printer, a virtual reality device, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be elaborated here, nor should they be used as limitations on the present disclosure. The display device includes but is not limited to components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it will be understood by those skilled in the art that the above-mentioned structure does not constitute a limitation on the above-mentioned display device provided in the embodiment of the present disclosure. In other words, the above-mentioned display device provided in the embodiment of the present disclosure may include more or fewer of the above-mentioned components, or a combination of certain components, or different component arrangements.

[0139] The embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device. By arranging a gate drive circuit and a pixel drive circuit on different substrates, the entire first substrate can be used for the layout and manufacturing of the gate drive circuit, eliminating the space required for arranging the gate drive circuit at the left and right borders of a traditional display panel, thereby realizing a display panel with an ultra-narrow border or even a borderless design.

[0140] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0141] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, wherein: The display panel includes a display area, wherein the display panel includes: a first substrate; a gate driving circuit, located on one side of the first substrate; a second substrate, located on a side of the gate driving circuit away from the first substrate; The pixel driving circuit is located on a side of the second substrate away from the first substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of the gate driving circuit on the first substrate and the orthographic projection of the pixel driving circuit on the first substrate at least partially overlap with each other.

3. The display panel according to claim 1, wherein: The display area is divided into a first display area, a second display area, and a third display area that are sequentially arranged along a first direction and extend along a second direction, wherein the first direction intersects the second direction, and the display panel further comprises a first frame area located on a side of the first display area away from the second display area, and a second frame area located on a side of the third display area away from the second display area; The gate driving circuit is provided on the first substrate corresponding to at least one of the first display area, the second display area, and the third display area.

4. The display panel according to claim 3, wherein: The gate driving circuit includes a first gate driving circuit located in the first display area, the first gate driving circuit includes a plurality of first shift registers cascaded along the second direction, the signal output end of each first shift register is electrically connected to the corresponding pixel driving circuit through a first via, and the first via is located in the first border area and arranged along the second direction.

5. The display panel according to claim 4, wherein: The gate drive circuit includes a second gate drive circuit located in the third display area, the second gate drive circuit includes a plurality of second shift registers cascaded along the second direction, the signal output end of each second shift register is electrically connected to the corresponding pixel drive circuit through a second via, and the second via is located in the second border area and arranged along the second direction.

6. The display panel according to any one of claims 3 to 5, wherein: The gate drive circuit includes a third gate drive circuit located in the second display area, and the third gate drive circuit includes a plurality of third shift registers cascaded along the second direction. The signal output end of each third shift register is electrically connected to the corresponding pixel drive circuit through a third via. The third vias are located in the second display area and arranged along the second direction.

7. The display panel according to claim 3, wherein: It also includes a first signal line electrically connected to the pixel driving circuit, and the first signal line is located on a side of the first substrate facing the second substrate.

8. The display panel according to claim 7, wherein: The first signal line includes an initialization signal line.

9. The display panel according to claim 8, wherein: The first signal line is electrically connected to the pixel driving circuit through a fourth via hole, and the fourth via hole is located in any area of the first frame area, the second frame area, and the second display area.

10. The display panel according to claim 7, wherein: It also includes a plurality of gate drive circuit signal lines electrically connected to the gate drive circuit, and the gate drive circuit signal lines are located on a side of the first substrate facing the second substrate.

11. The display panel according to claim 10, wherein: The gate drive circuit signal lines include a power line, a clock signal line, and a frame trigger signal line.

12. The display panel according to claim 11, wherein: Also includes: A third border area connecting the first border area and the second border area, and a test signal line electrically connected to the signal output end of the gate drive circuit; the second substrate includes a first fan-out area corresponding to the third border area, and the first substrate includes at least one first area corresponding to the first fan-out area, and the gate drive circuit signal line, the first signal line and the test signal line are respectively electrically connected to the fan-out trace located in the first fan-out area through their respective corresponding fifth vias, and the orthographic projection of each of the fifth vias on the first substrate is located in the first area.

13. The display panel according to claim 12, wherein: The number of the first areas is 2, each of the first areas includes the gate drive circuit signal line, the first signal line and the fifth via corresponding to the test signal line, and the two first areas are located at both ends of the first fan-out area along the first direction.

14. The display panel according to claim 12, wherein: The second substrate further includes, corresponding to the third border area, a bending area, a second fan-out area, and a binding area located on a side of the first fan-out area away from the display area and sequentially arranged in a direction away from the display area; Each of the fan-out traces located in the first fan-out area is electrically connected to the binding area through the bending area and the second fan-out area.

15. The display panel according to any one of claims 7 to 14, wherein: The device further comprises: a first buffer layer, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, and a first source-drain metal layer, which are located between the first substrate and the second substrate and are stacked in sequence in a direction away from the first substrate; and a second buffer layer, a second active layer, a third gate insulating layer, a third gate metal layer, a fourth gate insulating layer, a fourth gate metal layer, a second interlayer insulating layer, and a second source-drain metal layer, which are located on a side of the second substrate away from the first substrate and are stacked in sequence in a direction away from the second substrate; The pixel driving circuit includes a transistor, the signal output end of the gate driving circuit is located at the first source-drain metal layer, and the signal output end of the gate driving circuit is electrically connected to the gate of the transistor through a first via hole that sequentially penetrates the second substrate, the second buffer layer and the third gate insulation layer.

16. The display panel according to claim 15, wherein: The first signal line is located in the first source-drain metal layer, and is electrically connected to the source of the transistor through a fourth via hole that sequentially passes through the second substrate, the second buffer layer, the third gate insulation layer, the fourth gate insulation layer and the second interlayer insulation layer.

17. The display panel according to claim 15, wherein: The first signal line is located in the first source-drain metal layer, and the fourth via includes a first sub-via and a second sub-via stacked along the thickness direction of the display panel. The first signal line is electrically connected to the transition part located in the third gate metal layer through the first sub-via that sequentially penetrates the second substrate, the second buffer layer and the third gate insulation layer, and the transition part is electrically connected to the source of the transistor through the second sub-via that penetrates the fourth gate insulation layer and the second interlayer insulation layer.

18. The display panel according to claim 1, wherein: The thickness of the second substrate is smaller than that of the first substrate.

19. The display panel according to claim 18, wherein: The thickness of the second substrate is 5-10 μm.

20. The display panel according to claim 1, wherein Both the first substrate and the second substrate are flexible substrates.

21. The display panel according to claim 1, wherein: The first substrate is a rigid substrate, and the second substrate is a flexible substrate.

22. A display device, wherein: Comprising the display panel according to any one of claims 1-21.

23. A method for manufacturing a display panel, for manufacturing the display panel according to any one of claims 1 to 21, wherein: The production method comprises: forming a gate driving circuit on one side of the first substrate; forming a second substrate on a side of the gate driving circuit away from the first substrate; A pixel driving circuit is formed on a side of the second substrate away from the first substrate.

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