Display device

Abstract

The invention relates to a display device. The display device includes: a pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; an emission layer disposed on the pixel electrode; a common electrode disposed on the emission layer; a first bank disposed on the pixel defining layer; and a second bank disposed on the first bank and including a side surface that protrudes more than a side surface of the first bank, wherein the second bank contains a titanium zinc (TiZn) alloy.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0017938, filed on February 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, various demands for display devices are constantly increasing. For example, display devices are being used in various electronic devices (for example, smart phones, digital cameras, laptop computers, navigation devices and smart TVs). The display device may be a flat panel display device, for example, a liquid crystal display device, a field emission display device and an organic light emitting display device. In such a flat panel display device, the light emitting display device includes a light emitting element that can emit light by itself, so that each pixel of the display panel can emit light by itself. Accordingly, the light emitting display device can display an image without a backlight unit that supplies light to the display panel.

[0005] Recently, display devices are being used in eyeglass-type devices to provide virtual reality and augmented reality. In some cases where a display device is used in an eyeglass-type device, the display device may be very small in size, 2 inches or less, and have a high pixel integration to achieve high resolution. For example, the display device may have a high pixel integration of 400 PPI (pixels per inch) or more. Summary of the Invention

[0006] Aspects of the present disclosure provide a display device including separate light emitting elements formed in a small emission area without a mask process.

[0007] Aspects of the present disclosure also provide a display device having high luminous efficiency and no dark spots in pixels.

[0008] It should be noted that the objects of the present disclosure are not limited to the above-mentioned objects; and other objects of the present disclosure will be apparent to those skilled in the art through the following description.

[0009] According to an embodiment of the present disclosure, a display device includes: a pixel electrode arranged on a substrate; a pixel defining layer arranged on the substrate and exposing the pixel electrode; an emission layer arranged on the pixel electrode; a common electrode arranged on the emission layer; a first dam arranged on the pixel defining layer; and a second dam arranged on the first dam and including a side surface that protrudes much more than a side surface of the first dam, wherein the second dam contains a titanium zinc (TiZn) alloy.

[0010] The second bank may be amorphous.

[0011] The roughness of the second bank may be greater than 0 and equal to or less than 1 nm.

[0012] In an X-ray diffraction spectroscopy (XRD) spectrum, the peak width of the second bank may be 7° or greater.

[0013] The second bank may include a metal layer disposed on the first bank and containing a titanium zinc (TiZn) alloy; and a metal oxide layer disposed on the metal layer.

[0014] The metal oxide layer may include an oxide of a titanium zinc (TiZn) alloy.

[0015] The thickness of the metal oxide layer may be in the range of 1% to 10% of the total thickness of the second bank.

[0016] The thickness of the metal oxide layer of the second bank may be constant.

[0017] The thickness of the second dike can be to within the range.

[0018] A ratio of zinc (Zn) with respect to a total number of atoms in the metal layer of the second bank may be in a range of 20 at % to 60 at %.

[0019] The display device may further include a residual pattern disposed between the pixel electrode and the pixel defining layer.

[0020] The display device may further include a lower inorganic encapsulation layer disposed on the common electrode and the second bank and spaced apart from an upper surface of the second bank.

[0021] The display device may further include an organic encapsulating layer disposed between an upper surface of the second bank and the lower inorganic encapsulating layer.

[0022] One end portion of the common electrode contacts a side surface of the first bank, and the other end portion of the common electrode contacts the other side surface of the first bank.

[0023] According to an embodiment of the present disclosure, a display device includes: a pixel electrode arranged on a substrate; a pixel defining layer arranged on the substrate and exposing the pixel electrode; an emission layer arranged on the pixel electrode; a common electrode arranged on the emission layer; a first dam arranged on the pixel defining layer; and a second dam arranged on the first dam and including a side surface that protrudes much more than a side surface of the first dam, wherein in an X-ray diffraction spectroscopy (XRD) spectrum, the second dam has one peak or two peaks in the 2θ (2theta) range of 0° to 80°.

[0024] In an X-ray diffraction spectroscopy (XRD) spectrum, the peak width of the second bank is 7° or greater.

[0025] The roughness of the second bank is greater than 0 and equal to or less than 1 nm.

[0026] According to an embodiment of the present disclosure, a display device includes: a pixel electrode arranged on a substrate; a pixel defining layer arranged on the substrate and exposing the pixel electrode; an emission layer arranged on the pixel electrode; a common electrode arranged on the emission layer; a first dam arranged on the pixel defining layer; and a second dam arranged on the first dam and including a side surface that protrudes much more than a side surface of the first dam, wherein the second dam includes a metal layer arranged on the first dam and containing a titanium zinc (TiZn) alloy, and a metal oxide layer arranged on the metal layer and containing an oxide of the titanium zinc (TiZn) alloy, and wherein a thickness of the metal oxide layer is in a range of 1% to 10% of the total thickness of the second dam.

[0027] The total thickness of the second dike can be to within the range.

[0028] A ratio of zinc (Zn) with respect to a total number of atoms in the metal layer of the second bank may be in a range of 20 at % to 60 at %.

[0029] According to the embodiments of the present disclosure, dark spots in pixels in a display device can be eliminated, and mura in a display panel can be prevented.

[0030] It should be noted that the effects of the present disclosure are not limited to the effects described herein, and other effects of the present disclosure will be apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0032] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0033] Figure 2 Seen from the side Figure 1 sectional view of a display device.

[0034] Figure 3 A plan view illustrating arrangement of emission regions in a display region of a display device according to an embodiment.

[0035] Figure 4 A cross-sectional view illustrating a portion of a display device according to an embodiment of the present disclosure.

[0036] Figure 5 for Figure 4 Magnified view of area A1.

[0037] Figure 6 for Figure 5 Magnified view of area A2.

[0038] Figure 7 FIG. 4 is an enlarged cross-sectional view of a second bank containing crystalline titanium.

[0039] Figure 8 For illustration, a view of the second bank containing crystalline titanium observed using a scanning probe microscope (AFM).

[0040] Figure 9 A graph illustrating observation of a second bank containing crystalline titanium using X-ray diffraction spectroscopy (XRD) is provided.

[0041] Figure 10 For explanation, an image of a comparative example in which the second bank containing crystalline titanium was not removed from the emission region was observed using a scanning electron microscope (SEM).

[0042] Figure 11 For explanation, a view of the second bank according to an embodiment of the present disclosure observed using a scanning probe microscope (AFM) is shown.

[0043] Figure 12 A graph illustrating observation of a second bank of a display device according to an embodiment using X-ray diffraction spectroscopy (XRD) is provided. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate example embodiments of the invention. However, the aspects supported by the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example aspects of the disclosure to those skilled in the art.

[0045] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may also be present. Like reference numerals refer to like components throughout the specification.

[0046] It will be understood that although the terms "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element may also be referred to as the first element.

[0047] As used herein, the term "about" or "approximately" includes the stated value and includes an appropriate range of deviation for the particular quantity as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, the term "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of a display device 10 according to an embodiment of the present disclosure.

[0050] refer to Figure 1 The display device 10 according to the embodiment may be included in an electronic device and provide a display screen of the electronic device. The electronic device may refer to any electronic device that provides a display screen. For example, the electronic device may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, smart glasses, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook computer, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera or a video camera, etc.

[0051] The shape of the display device 10 can be modified in various ways. For example, the display device 10 can have a shape similar to a rectangle having a short side in the first direction DR1 and a long side in the second direction DR2. The corner where the short side in the first direction DR1 intersects the long side in the second direction DR2 can be rounded with a predetermined curvature. However, it should be understood that the embodiments of the present disclosure are not limited to this. The corner can be formed as a right angle. When viewed from the top, the shape of the display device 10 is not limited to a quadrilateral shape, but can be formed into a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0052] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see FIG. Figure 2 ).

[0053] The display panel 100 may include a main area MA and a sub-area SBA.

[0054] The main area MA may include a display area DA containing pixels for displaying an image and a non-display area NDA located around the display area DA. The display area DA may output light from multiple emission areas or multiple opening areas. For example, the display panel 100 may include a pixel circuit including: a switching element; a pixel defining layer defining an emission area or an opening area; and a self-luminous element.

[0055] For example, the self-luminous element may include but is not limited to at least one of the following: an organic light-emitting diode including an organic emission layer; a quantum dot light-emitting diode (quantum dot LED) including a quantum dot emission layer; an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor; and a micro light-emitting diode (micro LED).

[0056] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of voltage lines may be arranged in the display area DA. Each of the plurality of pixels may be defined as the minimum unit of light emission, and each of the self-luminous elements described above may function as a pixel. The plurality of scan lines may supply scan signals received from a scan driver to the plurality of pixels. The plurality of data lines may supply data voltages received from the display driver 200 to the plurality of pixels. The plurality of voltage lines may supply power supply voltages received from the display driver 200 to the plurality of pixels.

[0057] The non-display area NDA may be located outside the display area DA. The non-display area NDA may be defined as an edge of the main area MA of the display panel 100. The non-display area NDA may include a scan driver that supplies scan signals to scan lines, and fan-out lines that connect the display driver 200 to the display area DA.

[0058] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or rolled. In an example in which the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include pads connected to the display driver 200 and the circuit board 300. According to another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pads may be provided in the non-display area NDA.

[0059] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to the data lines. The display driver 200 can apply power voltages to the power lines and can supply scan control signals to the scan driver. The display driver 200 can be implemented as an integrated circuit (IC) and can be attached to the display panel 100 using chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 can be disposed in the sub-area SBA and can overlap with the main area MA in the thickness direction (third direction DR3) when the sub-area SBA is bent. In another example, the display driver 200 can be mounted on the circuit board 300.

[0060] The circuit board 300 may be attached to the pad area of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (RPCB), or a flexible film (for example, a chip on film (COF)).

[0061] Figure 2 Seen from the side Figure 1 sectional view of the display device 10. Specifically, Figure 2 Interpretation Figure 1 A cross section of the display device 10 in a folded state.

[0062] refer to Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, an emission material layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0063] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include, but is not limited to, a polymer resin, such as polyimide (PI). According to another embodiment, the substrate SUB may include a glass material or a metal material.

[0064] A thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors that form pixel circuits of pixels. The thin film transistor layer TFTL may further include scan lines, data lines, voltage lines, scan control lines, fan-out lines for connecting the display driver 200 to the data lines, leads for connecting the display driver 200 to pads, and other components. Each thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an example in which a scan driver is formed on one side of the non-display area (NDA) of the display panel 100, the scan driver may include a thin film transistor.

[0065] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. Thin film transistors in pixels, scan lines, data lines, and power lines in the thin film transistor layer TFTL may be disposed in the display area DA. Scan control lines and fan-out lines in the thin film transistor layer TFTL may be disposed in the non-display area NDA. Lead lines in the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0066] An emission material layer (EML) may be disposed on the thin film transistor layer TFTL. The emission material layer (EML) may include: a plurality of light-emitting elements that emit light, each including a first electrode, a second electrode, and an emission layer; and a pixel-defining layer for defining pixels. The plurality of light-emitting elements in the emission material layer (EML) may be disposed in the display area DA.

[0067] According to an embodiment of the present disclosure, the emission layer may be an organic emission layer containing an organic material. The emission layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. In an example in which the first electrode receives a voltage via a thin film transistor in the thin film transistor layer TFTL and the second electrode receives a cathode voltage via a thin film transistor in the thin film transistor layer TFTL, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, so that they recombine in the organic light-emitting layer to emit light.

[0068] According to another embodiment, the light emitting elements may include: quantum dot light emitting diodes each including a quantum dot emission layer; inorganic light emitting diodes each including an inorganic semiconductor; or micro light emitting diodes.

[0069] The thin film encapsulation layer TFEL may cover the upper surface and side surfaces of the emission material layer EML and may protect the emission material layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EML.

[0070] A color filter layer (CFL) may be disposed on the thin film encapsulation layer (TFEL). The CFL may include multiple color filters, each associated with a plurality of emission regions. Each color filter selectively transmits light of a specific wavelength and blocks or absorbs light of other wavelengths. The CFL may absorb some light introduced from outside the display device 10 to reduce reflection of external light. Accordingly, the CFL may prevent color distortion caused by reflection of external light.

[0071] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 can be implemented without a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively small.

[0072] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in the infrared, ultraviolet, and visible light ranges. For example, the optical device may be an optical sensor (e.g., a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, and an image sensor) that senses light incident on the display device 10.

[0073] Figure 3 A plan view illustrating a portion of a display device 10 according to an embodiment of the present disclosure. Figure 3 1 is a plan view illustrating the arrangement of the emission areas EA1 , EA2 , and EA3 in the display area DA of the display device 10 .

[0074] refer to Figure 3 , the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 arranged in the display area DA. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first to third emission areas EA1, EA2, and EA3 may emit red light, green light, and blue light, respectively. The color of the light emitted from the emission areas EA1, EA2, and EA3 may be based on the light emitting elements ED1, ED2, and ED3 (see FIG. 1 ), which will be described later. Figure 4 For example, the first emission area EA1 may output the first light, the second emission area EA2 may output the second light, and the third emission area EA3 may output the third light. However, it should be understood that the embodiments of the present disclosure are not limited thereto.

[0075] The emission areas EA1, EA2 and EA3 can be arranged as Matrix (e.g., diamond Matrix). For example, the first emission area EA1 and the third emission area EA3 are spaced apart from each other in the first direction DR1 and may be alternately arranged in the first direction DR1. The second emission area EA2 may be spaced apart from another adjacent second emission area EA2 in the first direction DR1 and the second direction DR2. The second emission area EA2 and the first emission area EA1, or the second emission area EA2 and the third emission area EA3, may be alternately arranged in any direction in a plane formed by the first direction DR1 and the second direction DR2.

[0076] Each of the first to third emission areas EA1, EA2, and EA3 may be formed by a pixel defining layer PDL (see FIG. Figure 4 )limited.

[0077] Figure 4 1 is a cross-sectional view illustrating a portion of a display device 10 according to an embodiment of the present disclosure. Specifically, Figure 4 To follow Figure 3 The cross-sectional view taken along line II' of FIG. 1 illustrates a cross section of the substrate SUB, the thin film transistor layer TFTL, the emission material layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL.

[0078] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer (not illustrated), a second buffer layer BF2, a thin film transistor TFT, a gate insulator GI, a first interlayer dielectric layer ILD1, a capacitor electrode CPE, a second interlayer dielectric layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0079] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked one after another.

[0080] A bottom metal layer (not illustrated) may be provided on the first buffer layer BF1. For example, the bottom metal layer may be made of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0081] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer. The second buffer layer BF2 may include an inorganic film that may prevent the penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked one after another.

[0082] A thin film transistor (TFT) may be disposed on the second buffer layer (BF2) and may form a pixel circuit for each of the plurality of pixels. For example, the thin film transistor (TFT) may be a driving transistor or a switching transistor for the pixel circuit. The thin film transistor (TFT) may include a semiconductor layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0083] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer and the gate electrode GE in the thickness direction (third direction DR3) and may be insulated from the gate electrode GE by a gate insulator GI. A portion of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0084] The gate electrode GE may be disposed on the gate insulator GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction (third direction DR3) with the gate insulator GI interposed therebetween.

[0085] The gate insulator GI may be disposed on the semiconductor layer ACT. For example, the gate insulator GI may cover the semiconductor layer ACT and the second buffer layer BF2 and insulate the semiconductor layer ACT from the gate electrode GE. The gate insulator GI may include a contact hole through which the first connection electrode CNE1 passes.

[0086] The first interlayer dielectric layer ILD1 may cover the gate electrode GE and the gate insulator GI. The first interlayer dielectric layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer ILD1 may be connected to the contact hole of the gate insulator GI and the contact hole of the second interlayer dielectric layer ILD2.

[0087] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer ILD1 , and may overlap the gate electrode GE in the thickness direction (third direction DR3 ). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0088] The second interlayer dielectric layer ILD2 may cover the capacitor electrode CPE and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer ILD2 may be connected to the contact hole of the first interlayer dielectric layer ILD1 and the contact hole of the gate insulator GI.

[0089] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the gate insulator GI to contact the drain electrode DE of the thin film transistor TFT.

[0090] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer dielectric layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0091] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0092] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0093] An emission material layer (EML) may be disposed on the thin film transistor layer (TFTL). The emission material layer (EML) may include light-emitting elements (ED), a pixel-defining layer (PDL), and a bank structure (BNS). The light-emitting elements (ED) may include pixel electrodes (AE1, AE2, and AE3), emission layers (EL1, EL2, and EL3), and common electrodes (CE1, CE2, and CE3).

[0094] Figure 5 To explain Figure 4 An enlarged view of the first emission area EA1 (specifically area A1).

[0095] Combine Figure 3 and Figure 4 refer to Figure 5 , the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 arranged in the display area DA. The emission areas EA1, EA2, and EA3 may be defined as areas in which the pixel electrodes AE1, AE2, and AE3, the emission layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 overlap with each other in the thickness direction (third direction DR3) of the substrate SUB. The emission areas EA1, EA2, and EA3 may include areas in which light is output from the light-emitting elements ED1, ED2, and ED3, respectively, and passes through the color filter layer CFL in the third direction DR3, wherein the pixel electrodes AE1, AE2, and AE3, the emission layers EL1, EL2, and EL3, and the common electrodes CE1, CE2, and CE3 are stacked one after another in sequence. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of the same color or different colors.

[0096] According to an embodiment of the present disclosure, the first to third emission areas EA1, EA2, and EA3 may have the same area or size. For example, the first emission area EA1, the second emission area EA2, and the third emission area EA3 of the display device 10 may have the same area. However, it should be understood that the embodiments of the present disclosure are not limited thereto. The first to third emission areas EA1, EA2, and EA3 of the display device 10 may have different areas or sizes. For example, the area of the second emission area EA2 may be larger than the areas of the first emission area EA1 and the third emission area EA3, and the area of the third emission area EA3 may be larger than the area of the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3, respectively, may change based on the size of the emission areas EA1, EA2, and EA3. The color of the image displayed on the display device 10 may be controlled by adjusting the size of the emission areas EA1, EA2, and EA3. Although according to Figure 4 In the embodiment, the emission areas EA1, EA2 and EA3 have the same area, but the embodiments of the present disclosure are not limited thereto.

[0097] In the display device 10, a first emission area EA1, a second emission area EA2, and a third emission area EA3 disposed adjacent to each other may form a single pixel group. A single pixel group may present a black and white or grayscale image by including emission areas EA1, EA2, and EA3 that emit light of different colors. However, it should be understood that the embodiments of the present disclosure are not limited thereto. The combination of emission areas EA1, EA2, and EA3 that form a single pixel group may vary based on the arrangement of the emission areas EA1, EA2, and EA3 and the color of the light emitted therefrom.

[0098] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0099] The light-emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, emission layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively. The light-emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3 may emit light of different colors based on the materials of the emission layers EL1, EL2, and EL3. For example, the first light-emitting element ED1 disposed in the first emission area EA1 may emit red light having a peak wavelength in the range of 610 nanometers (nm) to 650 nm, the second light-emitting element ED2 disposed in the second emission area EA2 may emit green light having a peak wavelength in the range of 510 nm to 550 nm, and the third light-emitting element ED3 disposed in the third emission area EA3 may emit blue light having a peak wavelength in the range of 440 nm to 480 nm. The first to third emission areas EA1, EA2, and EA3 forming a single pixel group may include light-emitting elements ED1, ED2, and ED3 that emit light of different colors to present a black and white or grayscale image. Alternatively, the emission layers EL1, EL2, and EL3 may include two or more materials that emit light of different colors, so that one emission layer can emit mixed light. For example, the emission layers EL1, EL2, and EL3 may contain a material that emits red light and a material that emits green light to emit yellow light, or may contain all of a material that emits red light, a material that emits green light, and a material that emits blue light to emit white light.

[0100] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third pixel electrode AE3 disposed in the third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2.

[0101] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. Edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other may be covered by the pixel defining layer PDL, and thus the first to third pixel electrodes AE1, AE2, and AE3 may be insulated from each other.

[0102] Pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and / or a conductive metal material, and may have a single-layer or multi-layer structure. The conductive metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material may be one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0103] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed entirely on the second passivation layer PAS2. The pixel defining layer PDL may cover the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the residual pattern RP, such that the pixel defining layer PDL exposes a portion of the top surfaces of the pixel electrodes AE1, AE2, and AE3. For example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first emission layer EL1 may be disposed directly on the first pixel electrode AE1.

[0104] The pixel defining layer (PDL) may include an inorganic insulating material and may include but is not limited to at least one of the following: a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer.

[0105] According to an embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3 and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may partially overlap with the upper surfaces of the pixel electrodes AE1, AE2, and AE3 in the thickness direction (third direction DR3) of the substrate SUB, but is not in direct contact with them. The residual pattern RP may be disposed between the lower surface of the pixel defining layer PDL and the upper surfaces of the pixel electrodes AE1, AE2, and AE3. It should be noted that the pixel defining layer PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3. The side surfaces of the pixel defining layer PDL may protrude toward the emission areas EA1, EA2, and EA3, rather than protruding toward the side surfaces of the second dam BN2.

[0106] The residual pattern RP may be arranged on the edge of each of the first to third pixel electrodes AE1, AE2 and AE3. Due to the presence of the residual pattern RP, the pixel defining layer PDL may not be in direct contact with the upper surface of the pixel electrodes AE1, AE2 and AE3. The residual pattern RP may include a metal or oxide semiconductor material. Although in the examples illustrated in the accompanying drawings, the side surface of the residual pattern RP facing the emission areas EA1, EA2 and EA3 is much more recessed than the side surface of the pixel defining layer PDL, the embodiments of the present disclosure are not limited thereto. The side surface of the residual pattern RP may protrude from the side surface of the pixel defining layer PDL toward the emission areas EA1, EA2 and EA3, or may be aligned with the side surface of the pixel defining layer PDL. The side surface of the pixel defining layer PDL may be a side surface located at the outermost position toward the emission areas EA1, EA2 and EA3.

[0107] The emission layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The emission layers EL1, EL2, and EL3 may be organic emission layers formed of an organic material and may be formed on the pixel electrodes AE1, AE2, and AE3 through a deposition process. The emission layers EL1, EL2, and EL3 may have a multilayer structure. The hole injection material, the hole transport material, the light emitting material, the electron transport material, and / or the electron injection material may each form a layer. In an example in which the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3, and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, and the holes and electrons may recombine in the emission layers EL1, EL2, and EL3 to emit light.

[0108] The emission layers EL1, EL2, and EL3 may include a first emission layer EL1, a second emission layer EL2, and a third emission layer EL3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The first emission layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second emission layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third emission layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. The emission layers EL1, EL2, and EL3 may emit light of different colors, or the emission layers EL1, EL2, or EL3 may emit mixed light. According to an embodiment of the present disclosure, the first emission layer EL1 may emit red light, the second emission layer EL2 may emit green light, and the third emission layer EL3 may emit blue light. According to another embodiment, the first emission layer EL1 may emit yellow light, which is a mixture of red and green light, and the second emission layer EL2 may emit blue light. According to yet another embodiment, the first emission layer EL1 may emit white light, which is a mixture of red, green, and blue light.

[0109] The emission layers EL1, EL2, and EL3 may be disposed on an upper surface of the pixel defining layer PDL. Depending on the embodiment, the emission layers EL1, EL2, and EL3 may be partially disposed in a space between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL. Depending on the embodiment, the emission layers EL1, EL2, and EL3 may be in contact with the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1, AE2, and AE3.

[0110] Common electrodes CE1, CE2, and CE3 may be disposed on the emission layers EL1, EL2, and EL3. The common electrodes CE1, CE2, and CE3 include a transparent conductive material to allow light generated in the emission layers EL1, EL2, and EL3 to be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-level voltage. In an example in which the pixel electrodes AE1, AE2, and AE3 receive a voltage equal to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low-level voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3, allowing the emission layers EL1, EL2, and EL3 to emit light.

[0111] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3, respectively, disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first emission layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second emission layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third emission layer EL3 in the third emission area EA3. The first to third common electrodes CE1, CE2, and CE3 may be spaced apart from each other.

[0112] A capping layer (not illustrated) may be provided on the common electrodes CE1, CE2, and CE3. The capping layer may include an organic insulating material or an inorganic insulating material and covers the patterns provided on the light-emitting elements ED1, ED2, and ED3. The capping layer may prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air. According to an embodiment, the capping layer may include an organic material (for example, a-NPD (2,2'-dimethyl-N,N'-di[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl-4,4'-diamine), NPB (N,N'-di(naphthalene-1-yl)-N,N'-diphenyl-benzidine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), m-MTDATA (4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine), Alq3 (8-hydroxyquinoline aluminum), LiF and / or CuPc) or an inorganic material (for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride).

[0113] The display device 10 may include a plurality of bank structures BNS disposed on a pixel defining layer (PDL). The bank structure BNS may have a structure in which banks BN1 and BN2 composed of different materials are stacked one after another. The bank structure BNS may include a plurality of openings containing emission areas EA1, EA2, and EA3, and may be arranged to overlap with a light-blocking region of a color filter layer (CFL), which will be described later. The light-emitting elements ED1, ED2, and ED3 of the display device 10 may overlap with the openings of the bank structure BNS.

[0114] The first bank BN1 may be provided on the pixel defining layer PDL. The side surface of the first bank BN1 may be more recessed than the side surface of the pixel defining layer PDL in a direction away from the emission areas EA1, EA2, and EA3. The side surface of the first bank BN1 may be more recessed than the side surface of the second bank BN2 in a direction away from the emission areas EA1, EA2, and EA3, which will be described later.

[0115] According to an embodiment, the first bank BN1 may include a conductive metal material. According to an embodiment, the first bank BN1 may include aluminum (Al), an oxide of aluminum (Al), or an alloy of aluminum (Al).

[0116] The common electrodes CE1, CE2, and CE3 may be in contact with and electrically connected to the first bank BN1. The common electrodes CE1, CE2, and CE3 spaced apart from each other may be electrically connected to each other through the first bank BN1.

[0117] The emission layers EL1, EL2, and EL3 may be in direct contact with the side surfaces of the first bank BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surfaces of the first bank BN1 may be greater than the contact area between the emission layers EL1, EL2, and EL3 and the side surfaces of the first bank BN1. The common electrodes CE1, CE2, and CE3 on the side surfaces of the first bank BN1 may have an area larger than the area of the emission layers EL1, EL2, and EL3 on the side surfaces of the first bank BN1, or may be positioned higher than the position at which the emission layers EL1, EL2, and EL3 are positioned on the side surfaces of the first bank BN1. The common electrodes CE1, CE2, and CE3 of different light-emitting elements ED1, ED2, and ED3 are electrically connected through the first bank BN1, and as described herein, embodiments of the present disclosure provide the advantage of increased contact area between the common electrodes CE1, CE2, and CE3 and the first bank BN1.

[0118] The first bank BN1 may have an upper surface higher than upper surfaces of the common electrodes CE1, CE2, and CE3. A height from the substrate SUB to the upper surface of the first bank BN1 may be greater than a height from the substrate SUB to the common electrodes CE1, CE2, and CE3.

[0119] The second embankment BN2 may be provided on the first embankment BN1. Figure 4 and Figure 5 The second bank BN2 may include openings that overlap with the emission areas EA1, EA2, and EA3, respectively, and each of the openings may include a side surface. The second bank BN2 may include a tip or eaves that protrudes from the first bank BN1. The side surface of the second bank BN2 may protrude more toward the emission areas EA1, EA2, and EA3 than the side surface of the first bank BN1.

[0120] Since the side surface of the second bank BN2 protrudes more toward the emission areas EA1, EA2, and EA3 than the side surface of the first bank BN1, an undercut structure of the first bank BN1 may be formed under the tip end TIP of the second bank BN2.

[0121] In the display device 10 according to an embodiment, the bank structure BNS includes a pointed tip TIP protruding toward the emission areas EA1, EA2, and EA3. This allows the emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 to be formed spaced apart from each other via a deposition and etching process rather than a masking process. In some aspects, embodiments of the present disclosure support the separate formation of different layers in the different emission areas EA1, EA2, and EA3 via a deposition process. For example, even if the emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 are formed via a deposition process without using a mask, the deposited material will not connect between the emission areas EA1, EA2, and EA3, but may be disconnected by the pointed tip TIP of the second bank BN2, with the bank structure BNS positioned therebetween. By forming material for forming a specific layer on the front surface of the display device 10 and then etching and removing the layer formed at an unwanted location, embodiments of the present disclosure support the separate formation of different layers in the different emission areas EA1, EA2, and EA3. In the display device 10 , the embodiments of the present disclosure support omitting unnecessary elements and reducing the area of the non-display area NDA.

[0122] The second bank BN2 may include a metal material different from that of the first bank BN1. According to an embodiment of the present disclosure, the second bank BN2 may include a titanium zinc (TiZn) alloy. The titanium zinc (TiZn) alloy may be an alloy and may be amorphous.

[0123] Figure 6 for Figure 5 FIG. 4 is an enlarged view of the area A2 of FIG. 4 , illustrating in detail the cross section of the second bank BN2 .

[0124] The second bank BN2 may include a metal layer BN201 disposed on the first bank BN1 and a metal oxide layer BN202 disposed on the metal layer BN201. According to an embodiment, the metal layer BN201 may include a titanium zinc (TiZn) alloy, and the metal oxide layer BN202 may include an oxide of the titanium zinc (TiZn) alloy.

[0125] Figure 7 This is an enlarged cross-sectional view of an example in which the second bank BN2' contains pure titanium (Ti) rather than an alloy as the metal material. In the example in which the second bank BN2' contains pure titanium (Ti), the thickness of the second bank BN2' increases, the titanium (Ti) crystallizes, and the size of the grains in the (111) direction of the crystal plane increases. Figure 8 To illustrate the observations made using scanning probe microscopy (AFM), Figure 7 1 , which is a view of the second bank BN2 ′ containing crystalline titanium illustrated in FIG. It can be seen that titanium (Ti) grains and grain boundaries are observed, and the surface roughness is high. Figure 9 To illustrate the graph of the second bank BN2' containing crystalline titanium (Ti) observed using X-ray diffraction spectroscopy (XRD). Figure 9 It can be seen that there are many narrow peaks, which means that the second bank BN2' of titanium (Ti) is crystalline. The growth of grains can lead to uneven thickness and high roughness of the titanium layer BN201', such as Figure 7 It should be understood that characteristics described herein with respect to relative degree terms (e.g., “high,” “low,” “large,” and “small,” etc.) refer to characteristics that meet (e.g., are higher than, lower than, greater than, or less than, etc.) a threshold value associated with the characteristic.

[0126] The titanium layer BN201' reacts with the atmosphere or oxygen in the chamber, so that a titanium (Ti) oxide layer BN202' is formed on the titanium layer BN201'. A portion of the titanium oxide layer BN202' may penetrate between the grains of titanium (Ti) and enter the grain boundaries, and therefore the thickness of the titanium oxide layer BN202' is uneven. The titanium oxide layer BN202' with an uneven thickness has an undesirable selectivity for the dry etching process and may act as a mask, interfering with the etching of the first dam BN1 below. If the titanium oxide layer BN202' in the grain boundaries is located in the emission areas EA1, EA2 and EA3, the dams BN1 and dams BN2' of the emission areas EA1, EA2 and EA3 may not be completely removed and may become dark spots. Figure 10 For illustration, a scanning electron microscope (SEM) image of a comparative example in which the second bank BN2' containing crystalline titanium was not removed from the emission areas EA1, EA2, and EA3 was observed. It can be seen that small remnants of the bank BN1 and bank BN2' are present in the emission areas EA1, EA2, and EA3. These may appear as dark spots when light is emitted.

[0127] In contrast, according to one or more embodiments of the present disclosure, when the second bank BN2 contains an amorphous titanium zinc (TiZn) alloy, there may be no grain boundaries. Figure 11 For explanation, the second bank BN2 of the display device 10 according to the embodiment is observed using a scanning probe microscope (AFM). It can be seen that the metal layer BN201 of the second bank BN2 including an amorphous titanium zinc (TiZn) alloy does not include a grain boundary and has low roughness.

[0128] Figure 12To illustrate the graph of the second bank BN2 of the display device 10 according to the embodiment, observed using X-ray diffraction spectroscopy (XRD). The X-ray diffraction spectroscopy (XRD) spectrum can be measured by scanning the sample in the θ / 2θ (theta-2theta) mode in an XRD instrument. A Philips X'Pert Pro diffractometer available from Malvern PANalytical Ltd. was used as the XRD instrument. The intensity was calculated using Bragg's law.

[0129] According to an embodiment of the present disclosure, the second bank BN2 and the metal layer BN201 may be amorphous. In an X-ray diffraction (XRD) spectrum, the second bank BN2 and the metal layer BN201 may have one or two peaks within a 2θ (2theta) range of 0° to 80°, and the width of the one or two peaks is relatively wide. In an XRD graph, the peak width may refer to the difference in 2θ values between points having corresponding peaks, where the corresponding peak is equal to the peak at the point where the intensity begins to surge immediately before the peak, or the peak at the point where the slope of the intensity changes from negative to positive immediately before the peak.

[0130] and Figure 9 Compared with the XRD spectra in Figure 12 The XRD spectrum in has a very large peak width w1 appearing around 40°. Figure 9 The peak width w1' in is about 5°, while Figure 12 The peak width w1 in may be 7° or greater or 9° or greater. In some aspects, Figure 9 In the XRD spectrum of Figure 12 In the XRD spectrum of the embodiment, no peak appears in the 2θ range of about 60° to 80°. It can be seen that the metal layer BN201 of the second bank BN2 containing amorphous titanium zinc (TiZn) alloy (see Figure 6 ) is amorphous.

[0131] refer to Figure 6 The thickness t21 of the amorphous metal layer BN201 can be constant. The metal oxide layer BN202 formed on the metal layer BN201 can also have a specific thickness t22. In this example, the metal oxide layer BN202 has a uniform thickness t22 and can have favorable selectivity for dry etching, and the banks BN1 and BN2 can be completely removed in the emission areas EA1, EA2, and EA3. As a result, no dark spots appear in the emission areas EA1, EA2, and EA3.

[0132] According to an embodiment of the present disclosure, the thickness t22 of the metal oxide layer BN202 of the second bank BN2 may be to or to The thickness t22 of the metal oxide layer BN202 of the second bank BN2 may be in the range of 1% to 10% or 1.5% to 6% of the total thickness t2 of the second bank BN2. In the above range of the thickness t22, the dry etching of the second bank BN2 may not be interfered with. According to an embodiment of the present disclosure, the thickness t2 of the second bank BN2 may be in the range of to Within the above range regarding the thickness t2, the tip of the second bank BN2 may have a small thickness without being bent.

[0133] According to an embodiment of the present disclosure, the ratio of zinc (Zn) relative to the total number of atoms included in the metal layer BN201 of the second bank BN2 may be in the range of 20 at % to 60 at % or 30 at % to 50 at %. Within the above ratio range, the embodiment of the present disclosure can prevent the crystallization of titanium (Ti), and the second bank BN2 can have amorphous characteristics. The element ratio or atomic ratio can be obtained through transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), or X-ray photoelectron spectroscopy (XPS) composition analysis.

[0134] According to an embodiment of the present disclosure, the roughness of the second bank BN2 may be greater than zero and equal to or less than 1 nm. Within the above range of roughness, the second bank BN2 can be removed during dry etching, and the etching of the first bank BN1 below may not be affected. The roughness of the second bank BN2 may be the roughness of the metal layer BN201 of the second bank BN2. The degree of roughness can be calculated using, for example, the roughness average value (Ra), the root mean square (RMS) roughness (Rq), the maximum height (Rs) and the ten-point height (Rz) of the profile, and other appropriate parameters. According to an embodiment of the present disclosure, the value using the root mean square (RMS) roughness (Rq) can be used as the roughness value. The roughness value can be measured in accordance with ISO 8503 and ASTM D4417.

[0135] Return Reference Figure 4, the tip TIP of the second bank BN2 may (for example, in a plan view) overlap with the common electrodes CE1, CE2, and CE3, the emission layers EL1, EL2, and EL3, and the pixel-defining layer PDL in a third direction DR3 perpendicular to the substrate SUB. For example, the tip TIP of the second bank BN2 may be located above the common electrodes CE1, CE2, and CE3, the emission layers EL1, EL2, and EL3, and the pixel-defining layer PDL in the third direction DR3 perpendicular to the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tip TIP of the second bank BN2. One end and the other end of each of the common electrodes CE1, CE2, and CE3 may overlap with the second bank BN2 in the thickness direction (third direction DR3) of the substrate.

[0136] The thin film encapsulation layer TFEL may be disposed on the light-emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light-emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the emission material layer EML. The thin film encapsulation layer TFEL may include at least one organic layer to protect the emission material layer EML from external foreign matter (e.g., dust, for example).

[0137] According to an embodiment of the present disclosure, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and an upper inorganic encapsulation layer TFE3 stacked one after another in the following order.

[0138] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the inorganic insulating material may be aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0139] The organic encapsulation layer TFE2 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, or polyethylene. For example, the organic encapsulation layer TFE2 may include an acrylic resin (e.g., polymethyl methacrylate and polyacrylic acid). The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0140] The lower inorganic encapsulation layer TFE1 may be disposed on the light-emitting elements ED1, ED2, and ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3, which are respectively disposed in different emission areas EA1, EA2, and EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material and respectively cover the light-emitting elements ED1, ED2, and ED3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light-emitting elements ED1, ED2, and ED3 from being damaged by external air.

[0141] Because the lower inorganic encapsulation layers TL1, TL2, and TL3 included in the lower inorganic encapsulation layer TFE1 can be formed by chemical vapor deposition (CVD), they can be formed along the steps of the layers on which they are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can even form a thin film below the undercut caused by the tip of the bank structure BNS. The lower inorganic encapsulation layers TL1, TL2, and TL3 can be arranged along the upper surface, side surface, and lower surface of the second bank BN2, the side surface of the first bank BN1, and the upper surface of the common electrodes CE1, CE2, and CE3. The lower inorganic encapsulation layers TL1, TL2, and TL3 are in contact with the lower surface of the second bank BN2 and can prevent the penetration of moisture from the outside air.

[0142] The first inorganic layer TL1 may be disposed (for example, only) on the first light-emitting element ED1 and the surrounding bank structure BNS without overlapping the second light-emitting element ED2 or the third light-emitting element ED3. The second inorganic layer TL2 may be disposed (for example, only) on the second light-emitting element ED2 and the surrounding bank structure BNS without overlapping the first light-emitting element ED1 or the third light-emitting element ED3. The third inorganic layer TL3 may be disposed (for example, only) on the third light-emitting element ED3 and the surrounding bank structure BNS without overlapping the first light-emitting element ED1 or the second light-emitting element ED2.

[0143] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from each other on the bank structure BNS.

[0144] The lower inorganic encapsulation layers TL1, TL2, and TL3 may be disposed on the upper and lower surfaces of the light-emitting elements ED1, ED2, and ED3 and the surrounding second bank BN2, and may be spaced apart from the upper surface of the second bank BN2. That is, the lower inorganic encapsulation layers TL1, TL2, and TL3 may have an undercut structure on the second bank BN2. Since the material of the emission layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 has been removed, a space may be created between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the second bank BN2.

[0145] The organic encapsulation layer TFE2 may be disposed on the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3. A portion of the organic encapsulation layer TFE2 may be disposed in the space between the lower inorganic encapsulation layers TL1, TL2, and TL3 and the upper surface of the second bank BN2. The second bank BN2, the organic encapsulation layer TFE2, and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially disposed in an area where the second bank BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 overlap with each other. In the tip area, the organic encapsulation layer TFE2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 may be sequentially disposed on the second bank BN2, and the organic encapsulation layer TFE2 may be disposed again on the lower inorganic encapsulation layers TL1, TL2, and TL3. In other words, some portions of the organic encapsulation layer TFE2 may be disposed between the upper surface of the second dam BN2 and the lower inorganic encapsulation layers TL1, TL2, and TL3 on the tip TIP of the second dam BN2, and other portions of the organic encapsulation layer TFE2 may be disposed above the lower inorganic encapsulation layers TL1, TL2, and TL3.

[0146] According to an embodiment of the present disclosure, the entire upper surface of the second bank BN2 may be in contact with the organic encapsulation layer TFE2. The first lower surfaces of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be surfaces facing the upper surface of the second bank BN2. The first lower surfaces of the lower inorganic encapsulation layers TL1, TL2, and TL3 may be in contact with the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may be in contact with the side surface of the second bank BN2.

[0147] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0148] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission areas EA1, EA2, and EA3. Each of the plurality of color filters CF1, CF2, and CF3 may include a filter pattern region and a light blocking region. The filter pattern region may be formed to overlap with the emission areas EA1, EA2, and EA3 or the opening of the bank structure BNS, and may form a light emission region through which light emitted from the emission areas EA1, EA2, and EA3 is emitted. In the light blocking region, the color filters CF1, CF2, and CF3 are stacked one after another, and thus light cannot pass through the light blocking region.

[0149] The color filters CF1, CF2 and CF3 include a first color filter CF1, a second color filter CF2 and a third color filter CF3 that are associated with different emission areas EA1, EA2 and EA3, respectively. The color filters CF1, CF2 and CF3 may include a colorant (for example, a dye and a pigment) that absorbs light within a wavelength range other than light within a specific wavelength range, and may be arranged in association with the light emitted from the emission areas EA1, EA2 and EA3. For example, the first color filter CF1 may be a red color filter that is arranged so that the first color filter CF1 overlaps with the first emission area EA1 and only transmits red first light. The second color filter CF2 may be a green color filter that is arranged so that the second color filter CF2 overlaps with the second emission area EA2 and only transmits green second light. The third color filter CF3 may be a blue color filter that is arranged so that the third color filter CF3 overlaps with the third emission area EA3 and only transmits blue third light.

[0150] In the display device 10, since the color filters CF1, CF2, and CF3 overlap each other, the intensity of the reflected light caused by external light can be reduced. In addition, when viewed from the top, the color of the reflected light caused by external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3.

[0151] An overcoat layer (OC) may be disposed on the color filters CF1, CF2, and CF3 and provide a flat upper surface for the color filters CF1, CF2, and CF3. The overcoat layer (OC) may be a colorless, light-transmitting layer having no color in the visible light band. For example, the overcoat layer (OC) may include a colorless, light-transmitting organic material, such as an acrylic resin.

[0152] Embodiments of the present disclosure support one or more processes (methods, flow charts) that support the features and embodiments described herein. According to the exemplary aspects described herein, descriptions of elements "configurable" and "formable" include processes (methods, flow charts) and techniques for making, configuring, forming, positioning, and modifying the elements, etc.

[0153] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications and changes may be made without departing from the technical ideas or essential features of the present disclosure. Therefore, it should be understood that the embodiments mentioned above are not restrictive in all aspects, but illustrative.

Claims

1. A display device comprising: A pixel electrode is provided on the substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; an emission layer disposed on the pixel electrode; a common electrode disposed on the emission layer; a first dam disposed on the pixel defining layer; and a second bank provided on the first bank and including a side surface that protrudes more than a side surface of the first bank, The second dam comprises a titanium-zinc alloy. The display device according to claim 1 , wherein the second bank is amorphous. 3 . The display device according to claim 1 , wherein a roughness of the second bank is greater than 0 nm and equal to or less than 1 nm. 4 . The display device according to claim 1 , wherein a peak width of the second bank is 7° or greater in an X-ray diffraction spectroscopy spectrum.

5. The display device according to claim 1 , wherein the second dam comprises: a metal layer disposed on the first dam and comprising a titanium-zinc alloy; and A metal oxide layer is disposed on the metal layer. The display device according to claim 5 , wherein the metal oxide layer comprises an oxide of a titanium zinc alloy. 7 . The display device of claim 5 , wherein a thickness of the metal oxide layer is in a range of 1% to 10% of a total thickness of the second bank. 8 . The display device according to claim 7 , wherein the thickness of the metal oxide layer of the second bank is constant.

9. The display device according to claim 1 , wherein the thickness of the second bank is to within the range. 10 . The display device according to claim 5 , wherein a ratio of zinc with respect to a total number of atoms in the metal layer of the second bank is in a range of 20 at % to 60 at %.

11. The display device according to claim 1 , further comprising: A residual pattern is disposed between the pixel electrode and the pixel defining layer.

12. The display device according to claim 1, further comprising: A lower inorganic encapsulation layer is disposed on the common electrode and the second bank and is spaced apart from an upper surface of the second bank.

13. The display device according to claim 12, further comprising: An organic encapsulating layer is disposed between the upper surface of the second bank and the lower inorganic encapsulating layer. 14 . The display device of claim 1 , wherein one end portion of the common electrode contacts the side surface of the first bank, and the other end portion of the common electrode contacts the other side surface of the first bank.

15. A display device comprising: A pixel electrode is provided on the substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; an emission layer disposed on the pixel electrode; a common electrode disposed on the emission layer; a first dam disposed on the pixel defining layer; and a second bank provided on the first bank and including a side surface that protrudes more than a side surface of the first bank, In an X-ray diffraction spectrum, the second bank has one peak or two peaks within a 2θ range of 0° to 80°. 16 . The display device according to claim 15 , wherein a peak width of the second bank is 7° or greater in an X-ray diffraction spectroscopy spectrum. The display device according to claim 15 , wherein a roughness of the second bank is greater than 0 nm and equal to or less than 1 nm.

18. A display device comprising: A pixel electrode is provided on the substrate; a pixel defining layer disposed on the substrate and exposing the pixel electrode; an emission layer disposed on the pixel electrode; a common electrode disposed on the emission layer; a first dam disposed on the pixel defining layer; and a second bank provided on the first bank and including a side surface that protrudes more than a side surface of the first bank, The second embankment comprises: a metal layer disposed on the first bank and comprising a titanium-zinc alloy, and A metal oxide layer is disposed on the metal layer and includes an oxide of a titanium zinc alloy, and wherein a thickness of the metal oxide layer is in a range of 1% to 10% of a total thickness of the second bank.

19. The display device according to claim 18, wherein the total thickness of the second bank is to within the range. 20 . The display device of claim 18 , wherein a ratio of zinc with respect to a total number of atoms in the metal layer of the second bank is in a range of 20 at % to 60 at %.

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