Display device

Abstract

The display device includes: a light emitting element for receiving a data voltage from a data line; a light receiving element for supplying the sensing current to the readout line; a first read-out connection line and a first data connection line; a second readout connection line; and a first electrode pattern. The read-out line, the first read-out connection line, and the second read-out connection line are connected to each other, and the data line and the first data connection line are connected to each other. The second readout connection line overlaps at least one of the data line and the first data connection line in the first region, and the first electrode pattern is located in the first region between the at least one of the data line and the first data connection line and the second readout connection line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0019099 filed in the Korean Intellectual Property Office on February 7, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0005] Display devices use pixels to display images. In addition, display devices can use multiple optical sensors to sense a user's fingerprint and perform user authentication functions. Recently, in-cell display panels are being manufactured in which pixels and optical sensors are formed in the same process.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] One or more embodiments of the present disclosure may relate to a display device that can minimize or reduce parasitic capacitance between a readout line of an optical sensor and other signal lines.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a pixel including a light-emitting element configured to receive a data voltage from a data line and emit light having a brightness based on the data voltage; an optical sensor including a light-receiving element and configured to provide a sensing current generated based on the amount of light received by the light-receiving element to a readout line; a plurality of first connection lines extending in a first direction and including a first readout connection line and a first data connection line; a plurality of second connection lines extending in a second direction different from the first direction and including a second readout connection line; and a first electrode pattern. The readout line, the first readout connection line, and the second readout connection line are connected to each other, and the data line and the first data connection line are connected to each other. The second readout connection line overlaps with at least one of the data line and the first data connection line in a first region, and the first electrode pattern is located between at least one of the data line and the first data connection line and the second readout connection line in the first region.

[0009] In an embodiment, the first electrode pattern may be configured to receive a first power voltage supplied to the pixel.

[0010] In an embodiment, the first electrode pattern may be integrated with a first power supply line connected to the pixel.

[0011] In embodiments, the first electrode pattern may not be connected to the optical sensor.

[0012] In an embodiment, the pixels and the optical sensor may be connected to the same scan line.

[0013] In an embodiment, the display device may further include a second electrode pattern, and the plurality of second connection lines may further include a second data connection line. The second data connection line may be connected to the data line and the first data connection line, and the second data connection line may overlap with at least one of the data line and the first data connection line in the second region. The second electrode pattern may be located in the second region between at least one of the data line and the first data connection line and the second data connection line.

[0014] In an embodiment, the second electrode pattern may have an island shape that may not be connected to other electrodes.

[0015] In an embodiment, no voltage may be supplied to the second electrode pattern.

[0016] In an embodiment, the first data link line may have a first interval from the data line closest thereto in the second direction; the first readout link line may have a second interval from the data line closest thereto in the second direction; and the second interval may be greater than the first interval.

[0017] In an embodiment, the first readout connection line may be located between two adjacent pixels arranged in a mirror-symmetrical layout.

[0018] According to one or more embodiments of the present disclosure, a display device includes: a pixel including a light-emitting element configured to receive a data voltage from a data line and emit light having a brightness based on the data voltage; an optical sensor including a light-receiving element and configured to provide a sensing current generated based on the amount of light received by the light-receiving element to a readout line; a plurality of first connection lines extending in a first direction and including a first readout connection line and a first data connection line; and a plurality of second connection lines extending in a second direction different from the first direction and including a second readout connection line. The readout line, the first readout connection line, and the second readout connection line are connected to each other, and the data line and the first data connection line are connected to each other. The first data connection line has a first spacing with the data line closest to it in the second direction, and the first readout connection line has a second spacing with the data line closest to it in the second direction, and the second spacing is greater than the first spacing.

[0019] In an embodiment, the first readout connection line may be located between two adjacent pixels arranged in a mirror-symmetrical layout.

[0020] In an embodiment, the display device may further include a first electrode pattern. The second readout link line may overlap with at least one of the data line and the first data link line in the first region, and the first electrode pattern may be located in the first region between at least one of the data line and the first data link line and the second readout link line.

[0021] In an embodiment, the first electrode pattern may be configured to receive a first power voltage supplied to the pixel.

[0022] In an embodiment, the first electrode pattern may be integrated with a first power supply line connected to the pixel.

[0023] In embodiments, the first electrode pattern may not be connected to the optical sensor.

[0024] In an embodiment, the pixels and the optical sensor may be connected to the same scan line.

[0025] In an embodiment, the display device may further include a second electrode pattern, and the plurality of second connection lines may further include a second data connection line. The second data connection line may be connected to the data line and the first data connection line, the second data connection line may overlap with at least one of the data line and the first data connection line in the second region, and the second electrode pattern may be located in the second region between at least one of the data line and the first data connection line and the second data connection line.

[0026] In an embodiment, the second electrode pattern may have an island shape that may not be connected to other electrodes.

[0027] In an embodiment, no voltage may be supplied to the second electrode pattern.

[0028] According to some embodiments of the present disclosure, a display device can minimize or reduce parasitic capacitance between a readout line of an optical sensor and other signal lines.

[0029] However, the present disclosure is not limited to the above-described aspects and features, and the above-described and other aspects and features will be described in part in the detailed description that follows with reference to the accompanying drawings, and in part may become apparent from them or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0031] Figure 1 and Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0033] Figure 4 is a diagram illustrating an optical sensor according to an embodiment of the present disclosure.

[0034] Figure 5 is a diagram illustrating a method of driving a pixel and an optical sensor according to an embodiment of the present disclosure.

[0035] Figure 6A and Figure 6B is a diagram illustrating a relationship among pads, connection lines, and signal lines according to one or more embodiments of the present disclosure.

[0036] Figure 7 is a diagram illustrating a stacked structure of a display area of a display panel.

[0037] Figures 8 to 17 is a diagram illustrating a planar layout of a first connection region according to one or more embodiments of the present disclosure.

[0038] Figure 18 The diagram follows Figure 16 A cross-sectional view taken along line II'.

[0039] Figure 19 is a diagram illustrating a planar layout of a second connection region according to an embodiment of the present disclosure.

[0040] Figure 20 The diagram follows Figure 19 A cross-sectional view taken along line II-II'.

[0041] Figure 21 is a diagram illustrating an example connection between a first data link line and a second data link line.

[0042] Figure 22 is a diagram illustrating an example connection between a first readout connection line and a second readout connection line.

[0043] Figure 23 A block diagram illustrating an electronic device according to one or more embodiments of the present disclosure is shown.

[0044] Figure 24 The picture shows Figure 23 The electronic device is implemented as an example of a smart phone.

[0045] Figure 25 The picture shows Figure 23 An example in which the electronic device is implemented as a tablet PC. DETAILED DESCRIPTION

[0046] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, the present disclosure can be embodied in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, throughout the drawings and written description, the same reference numerals indicate the same elements, and therefore, their redundant descriptions will not be repeated.

[0047] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0048] In addition, as understood by those skilled in the art, in view of the overall content of the present disclosure, each appropriate feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various appropriate manners, and each embodiment may be implemented independently of each other or in combination with each other in any appropriate manner, unless otherwise specified or implied.

[0049] As used in this disclosure, the expression "equal" or "same" may mean "substantially equal" or "substantially the same." In other words, they may be the same or equal to each other while taking into account various tolerances that indicate being the same or equal to each other as understood by those of ordinary skill in the art. In addition, other expressions used herein may be expressions from which "substantially" is omitted.

[0050] In the accompanying drawings, for the sake of clarity, the relative sizes, thicknesses and proportions of elements, layers and regions may be exaggerated and / or simplified. For ease of illustration, spatial relative terms such as "below", "below", "down", "beneath", "above" and "on" may be used herein to describe the relationship of an element or feature relative to another (some) element or feature as shown in the drawings. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the drawings. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0051] In each figure, the DR1 direction, the DR2 direction, and the DR3 direction are not limited to directions corresponding to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the DR1 direction, the DR2 direction, and the DR3 direction can be perpendicular to each other or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0052] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below could be termed a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure.

[0053] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, or it can be indirectly electrically connected to the other layer, region, or element via one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0054] The terms used herein are intended to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" and "an" are intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include," "comprise," and "have" and their variations indicate the presence of the stated features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. For example, the expression "A and / or B" means A, B, or A and B. Expressions such as "at least one of" when located after a list of elements modify the entire list of elements rather than modifying a single element in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0055] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0057] Figure 1 and Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0058] refer to Figure 1 The display device DD according to an embodiment of the present disclosure may include a display panel 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , a reset circuit 50 , a readout circuit 60 , and a timing controller 70 .

[0059] The timing controller 70 may receive grayscale (e.g., gray level) and timing signals for each frame period from a processor. The processor may correspond to (e.g., may include) at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP). The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal, among others.

[0060] Each cycle of the vertical synchronization signal may correspond to each frame period. Each cycle of the horizontal synchronization signal may correspond to each horizontal period. Grayscale may be supplied in units of horizontal lines in each horizontal period in response to a pulse of an enable level of a data enable signal. A horizontal line may refer to pixels (e.g., a pixel row) connected to the same scan line and emission line.

[0061] The timing controller 70 may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, a fourth control signal RCS, and a fifth control signal OCS based on the received grayscale and timing signal. The first control signal SCS may be supplied to the scan driver 30, the second control signal ECS may be supplied to the emission driver 40, the third control signal DCS may be supplied to the data driver 20, the fourth control signal RCS may be supplied to the reset circuit 50, and the fifth control signal OCS may be supplied to the readout circuit 60. The timing controller 70 may rearrange (e.g., render) and correct the grayscale and supply it to the data driver 20.

[0062] The display panel 10 may include pixels PX connected to data lines (e.g., DL1, ..., DLj, ..., DLm), scan lines (e.g., GWL1, ..., GWLi, ..., GWLn, GCL1, ..., GCLi, ..., GCLn, GIL1, ..., GILi, ..., GILn, GBL1, ..., GBLi, ..., GBLn), and emission lines (e.g., EML1, ..., EMLi, ..., EMLn). Each of the pixels PX may include a light-emitting element that receives a data voltage from a corresponding data line and emits light having a brightness based on the data voltage. In addition, the display panel 10 may include optical sensors FX connected to first scan lines (e.g., GWL1, ..., GWLi, ..., GWLn), reset lines RSL, and readout lines (e.g., ROL1, ..., ROLf, ..., ROLr). Each of the optical sensors FX may include a light-receiving element and may provide a sensing current generated based on the amount of light received by the light-receiving element to the corresponding readout line. Here, m, n, and r may be integers greater than 1.

[0063] The data driver 20 may receive a gray level and a third control signal DCS from the timing controller 70. For example, the third control signal DCS may include a source start signal and a clock signal, etc. For example, the data driver 20 may sample the gray level while shifting the source start signal based on the clock signal, and may apply a data voltage corresponding to the sampled gray level to the data lines DL1 to DLm in units of pixel rows.

[0064] The scan driver 30 may receive a first control signal SCS from the timing controller 70. The first control signal SCS may include a clock signal, a scan start signal, etc. The scan driver 30 may supply scan signals to the scan lines (e.g., GWL1, ..., GWLi, ..., GWLn, GCL1, ..., GCLi, ..., GCLn, GIL1, ..., GILi, ..., GILn, GBL1, ..., GBLi, ..., GBLn) in response to the first control signal SCS.

[0065] Figure 1 In the embodiment in which the scan lines (e.g., GWL1, ..., GWLi, ..., GWLn, GCL1, ..., GCLi, ..., GCLn, GIL1, ..., GILi, ..., GILn, GBL1, ..., GBLi, ..., GBLn) are connected to one scan driver 30, the present disclosure is not limited thereto. For example, the scan driver 30 may include a first sub-scan driver connected to the first scan lines (e.g., GWL1, ..., GWLi, ..., GWLn), a second sub-scan driver connected to the second scan lines (e.g., GCL1, ..., GCLi, ..., GCLn), a third sub-scan driver connected to the third scan lines (e.g., GIL1, ..., GILi, ..., GILn), and a fourth sub-scan driver connected to the fourth scan lines (e.g., GBL1, ..., GBLi, ..., GBLn). In another example, the scan driver 30 may include a first sub-scan driver connected to the scan lines (e.g., GWL1, ..., GWLi, ..., GWLn, GBL1, ..., GBLi, ..., GBLn) and a second sub-scan driver connected to the scan lines (e.g., GCL1, ..., GCLi, ..., GCLn, GIL1, ..., GILi, ..., GILn).

[0066] The scan driver 30 or each sub-scan driver can sequentially supply a scan signal having a pulse of an on-level to the corresponding scan line. The scan driver 30 or each sub-scan driver can include a scan stage configured in the form of a shift register. The scan driver 30 or each sub-scan driver can generate the scan signal by an appropriate method of sequentially transmitting a scan start signal in the form of a pulse of an on-level to the next scan stage under the control of a clock signal.

[0067] The emission driver 40 may receive a second control signal ECS from the timing controller 70. The second control signal ECS may include a clock signal and an emission stop signal, etc. The emission driver 40 may supply emission signals to the emission lines EML1 to EMLn in response to the second control signal ECS.

[0068] The emission driver 40 can sequentially supply emission signals of off-level pulses to the emission lines EML1 to EMLn. The emission driver 40 may include an emission stage configured in the form of a shift register. The emission driver 40 can generate emission signals by sequentially transmitting an emission stop signal in the form of an off-level pulse to the next emission stage according to the control of a clock signal.

[0069] Figure 1 An embodiment in which the scan driver 30 and the emission driver 40 are provided separately is illustrated, but the present disclosure is not limited thereto. For example, the scan driver 30 and the emission driver 40 may be integrated with each other into one driving circuit or one driving module.

[0070] The reset circuit 50 may receive a fourth control signal RCS from the timing controller 70. In response to the fourth control signal RCS, the reset circuit 50 may apply a reset signal to a reset line RSL. The reset line RSL may be commonly connected to all of the optical sensors FX of the display panel 10. In other words, a common reset signal may be transmitted to all of the optical sensors FX. In another embodiment, the reset circuit 50 may be connected to multiple optical sensors FX via multiple reset lines. In this case, multiple different reset signals may be transmitted to different optical sensors FX, respectively.

[0071] To perform sensing, at least some of the pixels PX disposed in the selected area may emit light in a sensing pattern. The sensing pattern may be a monochrome pattern (e.g., a red pattern or a green pattern). The optical sensor FX may generate a sensing signal corresponding to the amount of light received. Pixels PX disposed outside the selected area may continue to display an image (e.g., an existing image or a current image). Because the sensing pattern of the pixels PX disposed in the selected area covered by the finger is not visually recognized by the user, the user can continue to view the image (e.g., an existing image or a current image).

[0072] The readout circuit 60 may receive a fifth control signal OCS from the timing controller 70. In response to the fifth control signal OCS, the readout circuit 60 may provide sensing information based on the sensing signals received from the readout lines ROL1 to ROLr. The sensing information may be configured in various ways depending on the mode of the display device DD. For example, the sensing information may include (e.g., may be) fingerprint image information or photoplethysmography (PPG) information.

[0073] The processor or timing controller 70 may perform a user authentication function or the like using the sensing information provided from the readout circuit 60 .

[0074] refer to Figure 2 As an example, the connection relationship between the first scan lines GWL[p] to GWL[p+5], the data lines DL[q] to DL[q+7], the readout lines ROL[s] to ROL[s+3], the pixels PX and the optical sensors FX is illustrated in the display panel 10. Figure 3 Describe in more detail Figure 1 1 and 2. The connection relationship between the other scan lines GCL1 to GCLn, GIL1 to GILn and GBL1 to GBLn, the emission lines EML1 to EMLn, and the pixels PX shown in FIG.

[0075] The pixels PX may be connected to the first scan lines GWL[p] to GWL[p+5] and may include light-emitting elements R, G, and B. The first scan lines GWL[p] to GWL[p+5] may be arranged parallel or substantially parallel to each other in the first direction DR1. The first scan lines GWL[p] to GWL[p+5] may extend in the second direction DR2. Here, p may be an integer greater than zero and less than or equal to n. In addition, the pixels PX may be connected to the data lines DL[q] to DL[q+7]. The data lines DL[q] to DL[q+7] may extend in the first direction DR1 and may be arranged parallel or substantially parallel to each other in the second direction DR2. Here, q may be an integer greater than zero and less than or equal to m.

[0076] Each of the light-emitting elements R, G, and B of the pixel PX can emit one of a first color, a second color, and a third color. The first color, the second color, and the third color can be different colors from each other. For example, the first color can be one of red, green, and blue, the second color can be another color of red, green, and blue other than the first color, and the third color can be the remaining colors of red, green, and blue other than the first and second colors. In addition, magenta, cyan, and yellow can be used instead of red, green, and blue as the first to third colors. Hereinafter, for convenience, a case where the first color is red, the second color is green, and the third color is blue will be described in more detail as a representative example.

[0077] In this embodiment, as an example, the light emitting elements R, G, and B of the pixel PX are illustrated as being arranged in a diamond shape (eg, in a DIAMOND shape). structure or structure( is an officially registered trademark of Samsung Display Co., Ltd.)) setting. However, the present disclosure is not limited to the connection relationship of the first scan lines GWL[p] to GWL[p+5], the data lines DL[q] to DL[q+7] and the pixels PX shown in the figure, and various modifications can be made as needed or desired. For example, the pixels PX including the light-emitting elements R of the first color and the light-emitting elements B of the third color can be connected to the same data line DL[q], DL[q+2], DL[q+4] or DL[q+6], and the pixels PX including the light-emitting elements G of the second color can be connected to independent data lines DL[q+1], DL[q+3], DL[q+5] or DL[q+7]. The data lines DL[q], DL[q+2], DL[q+4] or DL[q+6] connected to the pixels PX including the first color light emitting elements R and the third color light emitting elements B and the data lines DL[q+1], DL[q+3], DL[q+5] or DL[q+7] connected to the pixels PX including the second color light emitting elements G can be alternately arranged along the second direction DR2.

[0078] The optical sensor FX including the light receiving element O may be connected to the first scan lines GWL[p] to GWL[p+5] and the readout lines ROL[s] to ROL[s+3]. The readout lines ROL[s] to ROL[s+3] may extend in the first direction DR1 and may be arranged parallel or substantially parallel to each other in the second direction DR2.

[0079] Figure 3 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0080] exist Figure 3, a pixel PX disposed in the i-th pixel row and the j-th pixel column among a plurality of pixels PX is illustrated as a representative example. A pixel row may represent pixels PX connected to the same scan line and emission line, and a pixel column may represent pixels PX connected to the same data line. Here, i is an integer greater than or equal to 1 and less than or equal to n, and j is an integer greater than or equal to 1 and less than or equal to m.

[0081] refer to Figure 3 The pixel PX may include a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC may include pixel transistors ST1 to ST8 and a storage capacitor Cst.

[0082] A gate electrode of the first pixel transistor ST1 (e.g., a driving transistor) may be connected to the first node N1, a first electrode of the first pixel transistor ST1 may be connected to the second node N2, and a second electrode of the first pixel transistor ST1 may be connected to the third node N3. The first pixel transistor ST1 may control a driving current flowing from the first power line to which the first power voltage VDD is applied via the light emitting element LD to the second power line to which the second power voltage VSS is applied, corresponding to (e.g., according to or based on) the voltage of the first node N1.

[0083] A first electrode of the second pixel transistor ST2 (e.g., a switching transistor) may be connected to the data line DLj, a second electrode of the second pixel transistor ST2 may be connected to the second node N2, and a gate electrode of the second pixel transistor ST2 may be connected to the first scan line GWLi. When a first scan signal at an on-level is supplied to the first scan line GWLi, the second pixel transistor ST2 may be turned on and may electrically connect the data line DLj and the second node N2 to each other.

[0084] A first electrode of the third pixel transistor ST3 (e.g., a diode-connected transistor) may be connected to the first node N1, a second electrode of the third pixel transistor ST3 may be connected to the third node N3, and a gate electrode of the third pixel transistor ST3 may be connected to the second scan line GCLi. When a second scan signal at an on-level is supplied to the second scan line GCLi, the third pixel transistor ST3 may be turned on and the gate electrode and the second electrode of the first pixel transistor ST1 may be electrically connected to each other. In other words, when the third pixel transistor ST3 is turned on, the first pixel transistor ST1 may be diode-connected.

[0085] A first electrode of the fourth pixel transistor ST4 (e.g., a gate initialization transistor) may be connected to the first node N1, a second electrode of the fourth pixel transistor ST4 may be connected to the first initialization line to which the first initialization voltage VINT is applied, and a gate electrode of the fourth pixel transistor ST4 may be connected to the third scan line GILi. When a third scan signal at an on-level is supplied to the third scan line GILi, the fourth pixel transistor ST4 may be turned on and may supply the first initialization voltage VINT to the first node N1.

[0086] A first electrode of the fifth pixel transistor ST5 (e.g., a first emission transistor) may be connected to a first power supply line to which a first power supply voltage VDD is applied, a second electrode of the fifth pixel transistor ST5 may be connected to a second node N2, and a gate electrode of the fifth pixel transistor ST5 may be connected to an emission line EMLi. When an off-level emission signal is supplied to the emission line EMLi, the fifth pixel transistor ST5 may be turned off, and may be turned on in other cases.

[0087] A first electrode of a sixth pixel transistor ST6 (e.g., a second emission transistor) may be connected to a third node N3, a second electrode of the sixth pixel transistor ST6 may be connected to a fourth node N4, and a gate electrode of the sixth pixel transistor ST6 may be connected to an emission line EMLi. When an off-level emission signal is supplied to the emission line EMLi, the sixth pixel transistor ST6 may be turned off, and may be turned on otherwise. The pixel PX may emit light in response to the emission signal received from the emission line EMLi. In other words, the emission timing of the pixel PX may be determined corresponding to the emission signal received from the emission line EMLi.

[0088] A first electrode of the seventh pixel transistor ST7 (e.g., an anode initialization transistor) may be connected to the fourth node N4, a second electrode of the seventh pixel transistor ST7 may be connected to the second initialization line to which the second initialization voltage AINT is applied, and a gate electrode of the seventh pixel transistor ST7 may be connected to the fourth scan line GBLi. When the fourth scan signal at an on level is supplied to the fourth scan line GBLi, the seventh pixel transistor ST7 may be turned on and may supply the second initialization voltage AINT to the fourth node N4. For example, the i-th fourth scan line GBLi may be the same as the i-1-th first scan line.

[0089] A first electrode of the eighth pixel transistor ST8 (e.g., a bias transistor) may receive a bias voltage VOBS, a second electrode of the eighth pixel transistor ST8 may be connected to the second node N2, and a gate electrode of the eighth pixel transistor ST8 may be connected to the fourth scan line GBLi. When the fourth scan signal at an on level is supplied to the fourth scan line GBLi, the eighth pixel transistor ST8 may be turned on and may supply the bias voltage VOBS to the second node N2.

[0090] Some of the pixel transistors ST1 to ST8, ST1, ST2, ST5, ST6, ST7, and ST8, may be P-type transistors and the other transistors ST3 and ST4 may be N-type transistors, but the present disclosure is not limited thereto. For example, each of the pixel transistors ST1 to ST8 may be a P-type transistor or an N-type transistor.

[0091] The P-type transistor may be a polysilicon semiconductor transistor. In a polysilicon semiconductor transistor, the channel of the semiconductor layer may include a polysilicon semiconductor. For example, the polysilicon semiconductor transistor may be a low-temperature polysilicon (LTPS) thin-film transistor. The polysilicon semiconductor transistor has high electron mobility and, therefore, fast driving characteristics.

[0092] The N-type transistor may be an oxide semiconductor transistor. In the oxide semiconductor transistor, the channel of the semiconductor layer may include an oxide semiconductor. For example, the oxide semiconductor transistor may be a low-temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor has a charge mobility lower than that of a polycrystalline silicon semiconductor transistor. Therefore, the amount of leakage current occurring in the off state of the oxide semiconductor transistor may be less than the amount of leakage current of the polycrystalline silicon semiconductor transistor.

[0093] A first electrode of the storage capacitor Cst may be connected to a first power line to which the first power voltage VDD is applied, and a second electrode of the storage capacitor Cst may be connected to the first node N1 .

[0094] The anode electrode of the light-emitting element LD can be connected to the fourth node N4, and the cathode electrode of the light-emitting element LD can be connected to the second power supply line to which the second power supply voltage VSS is applied. The light-emitting element LD can be a light-emitting diode. The light-emitting element LD can include an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot / quantum well light-emitting diode. The light-emitting element LD can emit light of one of a first color, a second color, and a third color. In addition, in this embodiment, only one light-emitting element LD is provided in each pixel, but in another embodiment, a plurality of light-emitting elements can be provided in each pixel. In this case, the plurality of light-emitting elements can be connected in series, in parallel, or in series / parallel with each other.

[0095] Figure 4 is a diagram illustrating an optical sensor according to an embodiment of the present disclosure.

[0096] refer to Figure 4 The optical sensor FX may include a sensor circuit FXC and a light receiving element PD. The sensor circuit FXC may include sensing transistors FT1 to FT3. The sensor circuit FXC may be connected to an anode electrode of the light receiving element PD and a first node FN1.

[0097] A first electrode of a first sensing transistor FT1 (e.g., an amplifying transistor) may be connected to a second initialization line to which a second initialization voltage AINT is applied, a second electrode of the first sensing transistor FT1 may be connected to a second node FN2, and a gate electrode of the first sensing transistor FT1 may be connected to a first node FN1. The first sensing transistor FT1 may control a sensing current flowing through the first sensing transistor FT1 in response to a voltage at the first node FN1. The sensing current may be supplied as a sensing signal to a readout line ROLf via the second sensing transistor FT2. The first node FN1 may be referred to as a sensing node.

[0098] A first electrode of a second sensing transistor FT2 (e.g., an output transistor) may be connected to a second node FN2, a second electrode of the second sensing transistor FT2 may be connected to a readout line ROLf, and a gate electrode of the second sensing transistor FT2 may be connected to a first scan line GWLi. In other words, the same scan line (e.g., the first scan line GWLi) may be connected to the gate electrode of the second sensing transistor FT2 and the gate electrode of the second pixel transistor ST2. When a first scan signal at an on-level is supplied to the first scan line GWLi, the second sensing transistor FT2 may be turned on to electrically connect the second electrode of the first sensing transistor FT1 and the readout line ROLf to each other.

[0099] A first electrode of the third sensing transistor FT3 (e.g., a reset transistor) can be connected to a reset voltage line to which a reset voltage VRST is applied, a second electrode of the third sensing transistor FT3 can be connected to the first node FN1, and a gate electrode of the third sensing transistor FT3 can be connected to the reset line RSL. The optical sensor FX can reset the voltage of the sensing node (e.g., the first node FN1) in response to a reset signal received from the reset line RSL. When a reset signal at an on level is supplied to the reset line RSL, the third sensing transistor FT3 can be turned on to supply the reset voltage VRST to the first node FN1. The first node FN1 (or, in other words, the gate electrode of the first sensing transistor FT1) can be reset by the reset voltage VRST. The reset voltage VRST can be lower than the second power supply voltage VSS.

[0100] Some of the sensing transistors FT1 to FT3 may be P-type transistors, and others may be N-type transistors, but the present disclosure is not limited thereto. For example, each of the sensing transistors FT1 to FT3 may be a P-type transistor or an N-type transistor.

[0101] A first electrode (e.g., an anode electrode) of the light receiving element PD may be connected to a first node FN1, and a second electrode (e.g., a cathode electrode) of the light receiving element PD may be connected to a second power supply line to which a second power supply voltage VSS is applied. The light receiving element PD may be a photodiode. In another embodiment, the light receiving element PD may be a phototransistor. When the light receiving element PD receives light, electrons are excited, which allows current to flow in the opposite direction from the cathode electrode to the anode electrode. Accordingly, when the light receiving element PD is exposed to light, the voltage of the first node FN1 may gradually increase after the reset time point. As the light reception time increases or the amount of light received increases, the amount of increase in the voltage of the first node FN1 after the reset time point may increase. Accordingly, the amount of sensing current flowing through the readout line ROLf may vary according to the light reception time and the amount of light received.

[0102] Figure 5 is a diagram illustrating a method of driving a pixel and an optical sensor according to an embodiment of the present disclosure.

[0103] Figure 5 The diagram shows Figure 3 The pixel PX and Figure 4 The process of the optical sensor FX running in any k-th frame period FRAME[k].

[0104] First, during the period before the k-th frame period FRAME[k] (e.g., time t1a to t2a), a reset signal RST at an on-level may be applied to the reset line RSL. Accordingly, the first node FN1 of the optical sensor FX may be reset by the reset voltage VRST. After time t2a, the voltage of the first node FN1 may gradually increase depending on the length of the light reception period EIT and the amount of received light.

[0105] At time point t3a, the emission signal EM[i] at the off level is supplied to the emission line EMLi. Accordingly, the fifth pixel transistor ST5 and the sixth pixel transistor ST6 are turned off, and the light emitting element LD is prevented or substantially prevented from emitting light.

[0106] At time point t4a, the third scan signal GI[i] at the on level is supplied to the third scan line GILi. Accordingly, the fourth pixel transistor ST4 is turned on, and the first node N1 is initialized to the first initialization voltage VINT.

[0107] At time point t5a, the second scan signal GC[i] at the on level is supplied to the second scan line GCLi. Accordingly, the third pixel transistor ST3 is turned on, and the first pixel transistor ST1 is diode-connected.

[0108] At time point t6a, the fourth scan signal GB[i] at the on level is supplied to the fourth scan line GBLi. Accordingly, the seventh pixel transistor ST7 is turned on, and the fourth node N4 is initialized to the second initialization voltage AINT. The second initialization voltage AINT can have (for example, can be set to) a voltage equal to or lower than the voltage of the second power supply voltage VSS to present a low gray level (for example, a low gray scale) of the light-emitting element LD. In addition, the eighth pixel transistor ST8 is turned on, and the second node N2 is initialized to the bias voltage VOBS.

[0109] At time point t7a, the first scan signal GW[i] at the on level is supplied to the first scan line GWLi. Accordingly, the second pixel transistor ST2 is turned on, and the data voltage is applied to the second node N2. In this case, the first node N1 may be in a state in which the first initialization voltage VINT is applied, and the first initialization voltage VINT may be a voltage sufficiently lower than the voltage of the data voltage. Accordingly, the first pixel transistor ST1 may be turned on, and a correction data voltage reflecting the reduction in the threshold voltage in the data voltage may be applied to the first node N1. The storage capacitor Cst maintains or substantially maintains a voltage corresponding to the difference between the first power supply voltage VDD and the compensated data voltage. This period may be referred to as a threshold voltage compensation period or a data write period.

[0110] In addition, at time point t7a, the second sensing transistor FT2 is turned on by the first scanning signal GW[i] at the on level. Accordingly, a sensing current corresponding to the light receiving period EIT and the amount of received light may flow through the readout line ROLf.

[0111] At time point t8a, the emission signal EM[i] at the on level is supplied to the emission line EMLi. Accordingly, the fifth pixel transistor ST5 and the sixth pixel transistor ST6 are turned on, and the light emitting element LD can be in a state capable of emitting light.

[0112] In this case, a drive current path is formed that connects the first power line, the fifth pixel transistor ST5, the first pixel transistor ST1, the sixth pixel transistor ST6, the light-emitting element LD, and the second power line. The amount of drive current flowing through the first electrode and the second electrode of the first pixel transistor ST1 is adjusted according to the voltage maintained in the storage capacitor Cst. The light-emitting element LD emits light with a brightness corresponding to the amount of drive current. The light-emitting element LD can emit light until the emission signal EM[i] at the off level is applied to the emission line EMLi.

[0113] Figure 6A and Figure 6B is a diagram illustrating a relationship among pads, connection lines, and signal lines according to one or more embodiments of the present disclosure.

[0114] refer to Figure 6A The substrate SUB of the display panel 10 may include a display area DA and a non-display area NDA. The display area DA may be an area in which the pixels PX are provided, and the non-display area NDA may be an area in which the pixels PX are not provided. In addition, the substrate SUB may include a sensing area SA and a non-sensing area NSA. The sensing area SA may be an area in which the optical sensor FX is provided, and the non-sensing area NSA may be an area in which the optical sensor FX is not provided.

[0115] For example, the size and shape of the display area DA may be the same or substantially the same as the size and shape of the sensing area SA. Furthermore, the size and shape of the non-display area NDA may be the same or substantially the same as the size and shape of the non-sensing area NSA. However, the present disclosure is not limited thereto, and in another embodiment, the sensing area SA may be larger or smaller than the display area DA. Depending on the size of the sensing area SA, the non-sensing area NSA may be smaller or larger than the non-display area NDA.

[0116] Hereinafter, the planar direction of the substrate SUB is defined based on a first direction DR1 and a second direction DR2 that intersects (e.g., is perpendicular or substantially perpendicular to) the first direction DR1. The vertical direction of the substrate SUB is defined based on a third direction DR3. However, the present disclosure is not limited thereto, and the substrate SUB may be curved. For example, a protruding portion of the substrate SUB in the first direction DR1 may include a pad area PADA, and the protruding portion may be bent to minimize or reduce the dead space. In addition, by bending the other side surfaces of the substrate SUB, a display device DD having a narrower frame including a minimized or reduced non-display area NDA may be realized.

[0117] The substrate SUB may include a first connection region BRSA1 and a second connection region BRSA2. The first connection region BRSA1 and the second connection region BRSA2 may jointly include signal lines SL1 and SL2, each extending in a first direction DR1, and first connection lines BRSV1 and BRSV2. The first connection region BRSA1 may include a second connection line BRSH1 extending in a second direction DR2. The second connection region BRSA2 may include a second connection line BRSH2 extending in the second direction DR2.

[0118] The signal lines SL1 and SL2 may include data lines DL1 to DLm and readout lines ROL1 to ROLr (eg, see Figure 1 The signal lines SL1 and SL2 may continuously extend in the first direction DR1 without being disconnected in the middle.

[0119] The first and second connection lines BRSV1 and BRSV2 and BRSH1 and BRSH2 are connected to corresponding pads in the pad area PADA, thereby transmitting signals to the signal lines SL1 and SL2.

[0120] The edge of the substrate SUB may have an angular shape, but the present disclosure is not limited thereto, and as Figure 6A As shown in FIG, the edge of the substrate SUB may have a curved shape. The curved edge may make it difficult to implement the existing fan-out wiring structure. The second connection area BRSA2 according to this embodiment may implement a non-fan-out structure.

[0121] The first connection area BRSA1 may be a readout connection area. For example, the second connection line BRSH1 of the first connection area BRSA1 may be connected to the optical sensor FX (eg, see Figure 1 ) of the readout lines ROL1 to ROLr. For example, the first signal line SL1 may be the readout lines ROL1 to ROLr. In this case, the first connection wire BRSV1 connected to the second connection wire BRSH1 in the first connection area BRSA1 may be the first readout connection wire. One of the readout lines, one of the first readout connection lines, and one of the second readout connection lines may be connected to each other. The order of connection is not particularly limited, and as used herein, the phrase "connected to each other" may mean "connected to the same electrical node with each other." The wirings connected to the same electrical node with each other may have the same voltage with each other. The first connection wire BRSV1 is connected to the corresponding pad so that the first connection wire BRSV1 can transmit the sensing current received from the optical sensor FX to the integrated chip (IC) connected to the pad.

[0122] In addition, the second connection area BRSA2 may be a data connection area. For example, the second connection line BRSH2 of the second connection area BRSA2 may be connected to the pixel PX (eg, see Figure 1 ) of the data lines DL1 to DLm. For example, the second signal line SL2 may be the data lines DL1 to DLm. In this case, the first connection line BRSV2 connected to the second connection line BRSH2 in the second connection area BRSA2 may be the first data connection line. One of the data lines, one of the first data connection lines, and one of the second data connection lines may be connected to each other. The order of connection is not particularly limited, and as used herein, the phrase "connected to each other" may mean "connected to the same electrical node with each other." The wirings connected to the same electrical node may have the same voltage with each other. The first connection line BRSV2 is connected to the corresponding pad so that the first connection line BRSV2 can transmit the data voltage received from the IC to the pixel PX.

[0123] exist Figure 6A , the second connection region BRSA2 is illustrated as being disposed from the first connection region BRSA1 in the first direction DR1. However, the present disclosure is not limited thereto. As another example, the first connection region BRSA1 may be disposed from the second connection region BRSA2 in the first direction DR1.

[0124] In some embodiments, the first connection region BRSA1 and the second connection region BRSA2 may not be spaced apart from each other in the first direction DR1. Figure 6B , the first connection region BRSA1 and the second connection region BRSA2 may be spaced apart from each other in the second direction DR2.

[0125] In another embodiment, there may be no distinction between the first connection area BRSA1 and the second connection area BRSA2. For example, because the second readout connection lines and the second data connection lines may be alternately arranged along the first direction DR1, the distinction between the readout connection area and the data connection area may be less obvious.

[0126] In some embodiments, the display device DD may further include an additional sensor layer on top of the layer in which the pixels PX and the optical sensors FX are formed (e.g., in the third direction DR3). The additional sensor layer may be a sensor layer for sensing a user's touch and / or an active pen, and may be configured in various suitable manners, such as resistive, capacitive, electromagnetic induction (EMI), electromagnetic resonance (EMR), and / or optical. In another embodiment, the additional sensor layer may be provided below the layer in which the pixels PX and the optical sensors FX are formed (e.g., in a direction opposite to the third direction DR3).

[0127] Figure 7 is a diagram illustrating a stacked structure of a display area of a display panel.

[0128] refer to Figure 7 , the display panel 10 may have a structure in which a substrate SUB, a first insulating layer INL1, a first active layer ACL1, a second insulating layer INL2, a first electrode layer CEL1, a third insulating layer INL3, a second electrode layer CEL2, a fourth insulating layer INL4, a second active layer ACL2, a fifth insulating layer INL5, a third electrode layer CEL3, a sixth insulating layer INL6, a fourth electrode layer CEL4, a seventh insulating layer INL7, a fifth electrode layer CEL5, an eighth insulating layer INL8 and a sixth electrode layer CEL6 are sequentially stacked one by one.

[0129] The following will refer to Figures 7 to 22 The stacked structure of the pixel circuit PXC and the sensor circuit FXC in the display area DA or the sensing area SA is described in more detail. Any suitable method known to those of ordinary skill in the art may be used to form the stacked structure of the light emitting element LD and the light receiving element PD.

[0130] The substrate SUB may include various suitable materials such as glass, polymer and / or metal (for example, may be made thereof). Depending on the desired product to which the substrate SUB is applied, the substrate SUB may be one of a rigid substrate and a flexible substrate. When the substrate SUB includes a polymer organic material, the substrate SUB may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate or cellulose acetate propionate. In some embodiments, the substrate SUB may include glass or fiberglass reinforced plastic (FRP) or the like (for example, may be made thereof).

[0131] The first active layer ACL1 and the second active layer ACL2 may be semiconductor layers. For example, the first active layer ACL1 may be formed of a polycrystalline silicon semiconductor, and the second active layer ACL2 may be formed of an oxide semiconductor. The first active layer ACL1 may include a channel CH1, a first electrode E11, and a second electrode E12 of a polycrystalline silicon semiconductor transistor TR1 (e.g., transistors ST1, ST2, ST5, ST6, ST7, ST8, FT1, and FT2). The second active layer ACL2 may include a channel CH2, a first electrode E21, and a second electrode E22 of an oxide semiconductor transistor TR2 (e.g., transistors ST3, ST4, and FT3). The first and second electrodes of each transistor may be doped with impurities to become conductors.

[0132] The gate electrode GE1 of the polycrystalline silicon semiconductor transistor TR1 may be disposed at (eg, in or on) the first electrode layer CEL1. In some embodiments, a sub-gate electrode (eg, a back gate electrode or a body electrode) of the polycrystalline silicon semiconductor transistor TR1 may be disposed between the substrate SUB and the first insulating layer INL1.

[0133] The gate electrode GE2 of the oxide semiconductor transistor TR2 may be disposed at (e.g., in or on) the third electrode layer CEL3. In some embodiments, the sub-gate electrode (e.g., back gate electrode or body electrode) of the oxide semiconductor transistor TR2 may be disposed at (e.g., in or on) the second electrode layer CEL2.

[0134] The first electrode layer CEL1, the second electrode layer CEL2, the third electrode layer CEL3, the fourth electrode layer CEL4, the fifth electrode layer CEL5, and the sixth electrode layer CEL6 may be conductive layers. Each electrode layer may be a single layer or multiple layers and may include (for example, may be made of) a conductive material such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or platinum (Pt).

[0135] A first insulating layer INL1, a second insulating layer INL2, a third insulating layer INL3, a fourth insulating layer INL4, a fifth insulating layer INL5, a sixth insulating layer INL6, a seventh insulating layer INL7, and an eighth insulating layer INL8 may be inserted to electrically separate the active layers ACL1 and ACL2 and the first to sixth electrode layers CEL1, CEL2, CEL3, CEL4, CEL5, and CEL6 from each other. The electrode patterns may be connected to each other through contact holes formed in the insulating layers INL1 to INL8. The insulating layers INL1 to INL8 may be formed of an organic insulating film, an inorganic insulating film, or an organic / inorganic insulating film, and may be formed of a single layer or a plurality of layers. For example, the insulating layers INL1 to INL8 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0136] Figures 8 to 17 is a diagram illustrating a planar layout of a first connection region according to one or more embodiments of the present disclosure. Figure 18 The diagram follows Figure 16 A cross-sectional view taken along line II'.

[0137] refer to Figure 8, the first active layer ACL1 is illustrated as an example. The first active layer ACL1 may include channels ST1c, ST2c, ST5c, ST6c, ST7c, ST8c, FT1c, and FT2c of transistors ST1, ST2, ST5, ST6, ST7, ST8, FT1, and FT2. Spaced-apart portions of the first active layer ACL1, with the channels therebetween, may constitute first and second electrodes of the transistors ST1, ST2, ST5, ST6, ST7, ST8, FT1, and FT2, respectively.

[0138] refer to Figure 9 , further illustrating an example pattern of the first electrode layer CEL1. The first electrode layer CEL1 may include gate electrodes ST1g, ST2g, ST5g, ST6g, ST7g, ST8g, FT1g, and FT2g of transistors ST1, ST2, ST5, ST6, ST7g, ST8g, FT1g, and FT2g. The gate electrodes ST1g, ST2g, ST5g, ST6g, ST7g, ST8g, FT1g, and FT2g may overlap with corresponding channels ST1c, ST2c, ST5c, ST6c, ST7c, ST8c, FT1c, and FT2c in the third direction DR3.

[0139] In addition, some patterns of the first electrode layer CEL1 may constitute the first scan line GWLi, the fourth scan line GBLi, the emission line EMLi, and the second electrode Cst2e of the storage capacitor Cst.

[0140] refer to Figure 10 , further illustrating an example pattern of the second electrode layer CEL2. The second electrode layer CEL2 may include sub-gate electrodes ST3ga, ST4ga, and FT3ga of the transistors ST3, ST4, and FT3.

[0141] In addition, some patterns of the second electrode layer CEL2 may constitute the sub reset line RSLa, the third sub scan line GILia, the second sub scan line GCLia, and the first electrode Cst1e of the storage capacitor Cst.

[0142] refer to Figure 11 , further illustrating an example pattern of the second active layer ACL2. The second active layer ACL2 may include channels ST3c, ST4c, and FT3c of the transistors ST3, ST4, and FT3. The channels ST3c, ST4c, and FT3c may overlap with the corresponding sub-gate electrodes ST3ga, ST4ga, and FT3ga in the third direction DR3. The spaced-apart portions of the second active layer ACL2, with the channels therebetween, may constitute the first and second electrodes of the transistors ST3, ST4, and FT3, respectively.

[0143] refer to Figure 12 , further illustrating an example pattern of the third electrode layer CEL3. The third electrode layer CEL3 may include gate electrodes ST3gb, ST4gb, and FT3gb of transistors ST3, ST4, and FT3. The gate electrodes ST3gb, ST4gb, and FT3gb may overlap with corresponding channels ST3c, ST4c, and FT3c in the third direction DR3.

[0144] In addition, some patterns of the third electrode layer CEL3 may constitute the reset line RSLb, the third scan line GILib, the second scan line GCLib, the 2-1st initialization line AINTL_R, and the 2-2nd initialization line AINTL_GB. The second initialization voltage AINT may be applied to the 2-1st initialization line AINTL_R and the 2-2nd initialization line AINTL_GB (for example, see Figure 3 and Figure 4 ). However, the 2-1st initialization line AINTL_R may be connected to a pixel including a light-emitting element R of the first color, and the 2-2nd initialization line AINTL_GB may be connected to a pixel including a light-emitting element G of the second color or a light-emitting element B of the third color. For example, the second initialization voltage AINT applied to the 2-1st initialization line AINTL_R and the second initialization voltage AINT applied to the 2-2nd initialization line AINTL_GB may be the same or substantially the same as each other, or may be different from each other. Whether the second initialization voltages AINT are the same or substantially the same as each other may be variously modified according to the characteristics of the light-emitting elements R, G, and B.

[0145] refer to Figure 13 , further illustrating example patterns of the fourth electrode layer CEL4. Some patterns of the fourth electrode layer CEL4 may include a reset voltage line VRSTL, a bias line VOBSL, a first initialization line VINTL, and a second connection line BRSH1.

[0146] The reset voltage VRST may be applied to a reset voltage line VRSTL (eg, see Figure 4 ). A bias voltage VOBS may be applied to a bias line VOBSL (eg, see Figure 3 ). The first initialization voltage VINT may be applied to the first initialization line VINTL (eg, see Figure 3 ). As mentioned above Figure 6A and Figure 6B As described above, the second connection line BRSH1 disposed in the first connection area BRSA1 may be a second readout connection line.

[0147] The first contact hole PCTH may be a hole etched to connect the pattern of the fourth electrode layer CEL4 to the electrode layer or the first active layer ACL1 thereunder. The second contact hole OCTH may be a hole etched to connect the pattern of the fourth electrode layer CEL4 to the electrode layer or the second active layer ACL2 thereunder.

[0148] refer to Figure 14 , illustrates an example pattern of the fifth electrode layer CEL5. Some patterns of the fifth electrode layer CEL5 may include a readout line pattern ROLfa, a first power line VDDL, and a first electrode pattern EPT1. The first power line VDDL and the first electrode pattern EPT1 may be integrally formed (e.g., integrally configured). A first power supply voltage VDD may be applied to the first power line VDDL. The first electrode pattern EPT1 may not be connected to the optical sensor FX.

[0149] The third contact hole VIAH1 may be a hole etched to connect the pattern of the fifth electrode layer CEL5 to an electrode layer or an active layer thereunder.

[0150] refer to Figure 15 , further illustrating example patterns of the sixth electrode layer CEL6. Some patterns of the sixth electrode layer CEL6 may include a readout line pattern ROLfb, data lines DL_RB and DL_G, first connection lines BRSV2_RB and BRSV2_G, and a second power line VSSL. A second power supply voltage VSS may be applied to the second power line VSSL.

[0151] The data line DL_RB may be connected to a pixel including a first color light emitting element R or a third color light emitting element B, and the data line DL_G may be connected to a pixel including a second color light emitting element G. Figure 6A and Figure 6B As described above, the first connection lines BRSV2_RB and BRSV2_G may be first data connection lines. For example, the first connection line BRSV2_RB may receive a data voltage corresponding to a pixel including a first color light-emitting element R or a third color light-emitting element B from a connected pad. The first connection line BRSV2_G may receive a data voltage corresponding to a pixel including a second color light-emitting element G from a connected pad.

[0152] The fourth contact hole VIAH2 may be a hole etched to connect the pattern of the sixth electrode layer CEL6 to an electrode layer or an active layer thereunder.

[0153] refer to Figure 16 , the patterns of the fourth electrode layer CEL4 , the fifth electrode layer CEL5 , and the sixth electrode layer CEL6 are illustrated as overlapping each other.

[0154] The readout line pattern ROLfb may be connected to the readout line pattern ROLfa to form a readout line ROLf extending in the first direction DR1 .

[0155] In addition, the readout line pattern ROLfa may be connected to the second link line BRSH1 through the third contact hole VIAH1_BRSH1. Accordingly, the second link line BRSH1 may serve as a second readout link line transmitting a sensing signal.

[0156] The second readout connection line may overlap with at least one of the data line and the first data connection line in the first region. For example, the second connection line BRSH1 may overlap with the data line DL_G and the first connection line BRSV2_G in the first region AR1. In this case, the second connection line BRSH1 may form an undesirable parasitic capacitance with the data line DL_G and the first connection line BRSV2_G. Accordingly, the voltage level of the sensing signal flowing through the second connection line BRSH1 may change according to the voltage changes of the data line DL_G and the first connection line BRSV2_G. When the sensing signal changes, the sensing information may become inaccurate.

[0157] According to one or more embodiments of the present disclosure, a first electrode pattern may be disposed in the first region between at least one of the data line and the first data connection line and the second readout connection line. For example, the first electrode pattern EPT1 may be disposed in the first region AR1 between the data line DL_G and the second connection line BRSH1. Alternatively, the first electrode pattern EPT1 may be disposed in the first region AR1 between the first connection line BRSV2_G and the second connection line BRSH1.

[0158] refer to Figure 18 , a cross-sectional view of the display panel 10 taken along line II' in the first area AR1 is illustrated as an example. In the third direction DR3, the first electrode pattern EPT1 can shield the second connection line BRSH1 from the data line DL_G and the first connection line BRSV2_G. The first electrode pattern EPT1, to which the first power supply voltage VDD is applied, can prevent or substantially prevent the formation of parasitic capacitance between the data line DL_G and the second connection line BRSH1. In addition, the first electrode pattern EPT1, to which the first power supply voltage VDD is applied, can prevent or substantially prevent the formation of parasitic capacitance between the first connection line BRSV2_G and the second connection line BRSH1. Accordingly, even if the voltages of the data line DL_G and the first connection line BRSV2_G change, the voltage level of the sensing signal flowing through the second connection line BRSH1 will not be affected.

[0159] exist Figure 17, a layout is shown in which the first active layer ACL1 , the first electrode layer CEL1 , the second electrode layer CEL2 , the second active layer ACL2 , the third electrode layer CEL3 , the fourth electrode layer CEL4 , the fifth electrode layer CEL5 , and the sixth electrode layer CEL6 overlap with each other.

[0160] Figure 19 is a diagram illustrating a planar layout of a second connection region according to an embodiment of the present disclosure. Figure 20 The diagram follows Figure 19 A cross-sectional view taken along line II-II'.

[0161] refer to Figure 19 and Figure 20 , the display panel 10 may further include a second electrode pattern EPT2 located in the second connection area BRSA2. Figure 6A and Figure 6B As described above, the second link line BRSH2 of the second connection area BRSA2 may serve as a second data link line to which the data voltage is applied.

[0162] The second data link line may overlap with at least one of the data line and the first data link line in the second area. For example, the second link line BRSH2 may overlap with the data line DL_G and the first link line BRSV2_G in the second area AR2. In this case, the second link line BRSH2 may form a parasitic capacitance with the data line DL_G and the first link line BRSV2_G. However, because the data voltage is applied to the second link line BRSH2, the data line DL_G, and the first link line BRSV2_G, the negative impact of the parasitic capacitance may be relatively small. For example, the signal levels in the second link line BRSH2, the data line DL_G, and the first link line BRSV2_G may change simultaneously or substantially simultaneously with each other, so that noise in the signal levels before and after the change can be minimized or reduced.

[0163] According to one or more embodiments of the present disclosure, the second electrode pattern may be disposed in the second region between at least one of the data line and the first data link line and the second data link line. For example, the second electrode pattern EPT2 may be disposed in the second region AR2 between the data line DL_G and the second link line BRSH2. The second electrode pattern EPT2 may be disposed in the second region AR2 between the first link line BRSV2_G and the second link line BRSH2.

[0164] As described above, because the negative impact of parasitic capacitance is relatively small, the second electrode pattern EPT2 can have an island shape that is not connected to other electrodes. In addition, no voltage may be supplied to the second electrode pattern EPT2. Therefore, the second electrode pattern EPT2 can be a dummy pattern.

[0165] Figure 21 is a diagram illustrating an example connection between a first data link line and a second data link line. The first link line BRSV2_G may serve as the first data link line, and the second link line BRSH2 may serve as the second data link line.

[0166] refer to Figure 21 The first connection line BRSV2_G may be connected to the second electrode pattern EPT2 through the fourth contact hole VIAH2_BRSV2_G. The second electrode pattern EPT2 may be connected to the second connection line BRSH2 through the third contact hole VIAH1_BRSH2.

[0167] Figure 21 The second electrode pattern EPT2 and Figure 20 The second electrode pattern EPT2 may be different in that the second electrode pattern EPT2 may function as a bridge pattern connecting the first connection wire BRSV2_G and the second connection wire BRSH2 to each other. As described above, the second electrode pattern EPT2 may function as a bridge pattern in a portion of the second connection area BRSA2 and may remain a dummy pattern in another portion of the second connection area BRSA2.

[0168] Figure 22 is a diagram illustrating an example connection between a first readout connection line and a second readout connection line. The first connection line BRSV1 may serve as a first readout connection line, and the second connection line BRSH1 may serve as a second readout connection line.

[0169] refer to Figure 22 ,exist Figure 16 The electrode pattern serving as the second power supply line VSSL is Figure 22 The first connection line BRSV1 may serve as a first connection line BRSV1. The first connection line BRSV1 may be a first readout connection line.

[0170] According to one or more embodiments of the present disclosure, the first data link line may have a first interval from the nearest data line in the second direction DR2. The first readout link line may have a second interval from the nearest data line in the second direction DR2. In this case, the second interval may be greater than the first interval.

[0171] For example, the first connection line BRSV2_G may have a first interval from the nearest data line DL_G in the second direction DR2. The first connection line BRSV1 may have a second interval from the nearest data line DL_G or DL_RB in the second direction DR2. In this case, the second interval may be greater than the first interval.

[0172] According to one or more embodiments of the present disclosure, the first readout connection line may be provided between two adjacent pixels arranged in a mirror-symmetrical layout. For example, the first connection line BRSV1 may be provided between two adjacent pixels PX_L and PX_R arranged in a mirror-symmetrical layout. Figure 16 The layout can minimize or reduce the dead space by supplying the second power supply voltage VSS shared by the pixels PX_L and PX_R from one line. In this embodiment, by making the electrode pattern previously serving as the second power supply line VSSL serve as the first connection line BRSV1, the horizontal spacing distance between the first connection line BRSV1 and the first connection lines BRSV2_G and BRSV2_RB, as well as the horizontal spacing distance between the first connection line BRSV1 and the data lines DL_G and DL_RB can be maximized.

[0173] According to this embodiment, the first connection line BRSV1 can be sufficiently spaced apart from the first connection lines BRSV2_G and BRSV2_RB in a plan view. Furthermore, the first connection line BRSV1 can be sufficiently spaced apart from the data lines DL_G and DL_RB in a plan view. Accordingly, the formation of parasitic capacitance between the first connection line BRSV1 and the first connection lines BRSV2_G and BRSV2_RB, as well as the formation of parasitic capacitance between the first connection line BRSV1 and the data lines DL_G and DL_RB, can be minimized or reduced.

[0174] The cathode electrodes of the light emitting elements LD of the pixels PX may be connected to each other. Therefore, even if a portion of the second power supply line VSSL serves as the first connection line BRSV1, no problem occurs.

[0175] Figure 23 A block diagram illustrating an electronic device according to one or more embodiments of the present disclosure is shown. Figure 24 The picture shows Figure 23 The electronic device is implemented as an example of a smart phone. Figure 25 The picture shows Figure 23 An example in which the electronic device is implemented as a tablet PC.

[0176] refer to Figures 23 to 25 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be the above reference Figure 1 In addition, the electronic device 1000 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or other systems. In an embodiment, as Figure 24 As shown in , the electronic device 1000 may be implemented as a smart phone. In another embodiment, as Figure 25 As shown in FIG, the electronic device 1000 may be implemented as a tablet PC. However, the present disclosure is not limited thereto, and the electronic device 1000 may be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a vehicle navigation device, a computer monitor, a laptop computer, or a head-mounted display device, etc.

[0177] The processor 1010 can perform specific calculations or tasks. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, or an application processor. The processor 1010 can be connected to other components via an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0178] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and / or a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and / or a mobile DRAM device.

[0179] The storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), and / or a CD-ROM, etc.

[0180] The input / output device 1040 may include an input device such as a keyboard, a keypad, a touchpad, a touch screen, and / or a mouse, and an output device such as a speaker and / or a printer. In some embodiments, a display device 1060 may be included in the input / output device 1040 .

[0181] The power supply 1050 may supply power for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0182] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but the present disclosure is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication links.

[0183] The foregoing is an illustration of some embodiments of the present disclosure and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments, unless otherwise expressly stated. Therefore, it is to be understood that the above is an illustration of various example embodiments and should not be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the claims and their equivalents.

Claims

1. A display device, comprising: a pixel including a light emitting element configured to receive a data voltage from a data line and emit light having a brightness based on the data voltage; an optical sensor including a light receiving element and configured to supply a sense current generated based on an amount of light received by the light receiving element to a readout line; a plurality of first connection lines extending in a first direction and including first readout connection lines and first data connection lines; a plurality of second connection lines extending in a second direction different from the first direction and including a second readout connection line; as well as a first electrode pattern, wherein the readout line, the first readout connection line and the second readout connection line are connected to each other, wherein the data line and the first data connection line are connected to each other, wherein the second readout connection line overlaps with at least one of the data line and the first data connection line in the first region, and The first electrode pattern is located in the first region, between at least one of the data line and the first data connection line and the second readout connection line.

2. The display device according to claim 1, wherein The first electrode pattern is configured to receive a first power supply voltage supplied to the pixel.

3. The display device according to claim 1, wherein The first electrode pattern is integrated with a first power supply line connected to the pixel.

4. The display device according to claim 3, wherein The first electrode pattern is not connected to the optical sensor.

5. The display device according to claim 4, wherein The pixels and the optical sensor are connected to the same scan line.

6. The display device according to claim 1, further comprising a second electrode pattern, in, The plurality of second connection lines further include a second data connection line, wherein the second data link line is connected to the data line and the first data link line, and the second data link line overlaps with at least one of the data line and the first data link line in the second region, and The second electrode pattern is located in the second area and between the second data connection line and at least one of the data line and the first data connection line.

7. The display device according to claim 6, wherein: The second electrode pattern has an island shape that is not connected to other electrodes.

8. The display device according to claim 7, wherein: No voltage is supplied to the second electrode pattern.

9. The display device according to claim 1, wherein: The first data link line has a first interval with a data line closest to the first data link line in the second direction; The first readout connection line has a second interval with the data line closest to the first readout connection line in the second direction; and The second interval is greater than the first interval.

10. The display device according to any one of claims 1 to 9, wherein: The first readout connection line is located between two adjacent pixels arranged in a mirror-symmetrical layout.

11. A display device comprising: a pixel including a light emitting element configured to receive a data voltage from a data line and emit light having a brightness based on the data voltage; an optical sensor including a light receiving element and configured to supply a sense current generated based on an amount of light received by the light receiving element to a readout line; a plurality of first connection lines extending in a first direction and including first readout connection lines and first data connection lines; as well as a plurality of second connection lines extending in a second direction different from the first direction and including a second readout connection line, wherein the readout line, the first readout connection line and the second readout connection line are connected to each other, wherein the data line and the first data connection line are connected to each other, The first data connection line has a first interval with the data line closest to the first data connection line in the second direction. wherein the first readout connection line has a second interval with the data line closest to the first readout connection line in the second direction, and The second interval is greater than the first interval.

12. The display device according to claim 11, wherein The first readout connection line is located between two adjacent pixels arranged in a mirror-symmetrical layout.

13. The display device according to claim 11, further comprising a first electrode pattern, in, The second readout connection line overlaps with at least one of the data line and the first data connection line in the first region, and The first electrode pattern is located in the first region, between at least one of the data line and the first data connection line and the second readout connection line.

14. The display device according to claim 13, wherein: The first electrode pattern is configured to receive a first power supply voltage supplied to the pixel.

15. The display device according to claim 13, wherein The first electrode pattern is integrated with a first power supply line connected to the pixel.

16. The display device according to claim 15, wherein The first electrode pattern is not connected to the optical sensor.

17. The display device according to claim 16, wherein: The pixels and the optical sensor are connected to the same scan line.

18. The display device according to claim 13, further comprising a second electrode pattern, in, The plurality of second connection lines further include a second data connection line, wherein the second data connection line is connected to the data line and the first data connection line, wherein the second data link line overlaps with at least one of the data line and the first data link line in the second region, and The second electrode pattern is located in the second area and between the second data connection line and at least one of the data line and the first data connection line.

19. The display device according to claim 18, wherein The second electrode pattern has an island shape that is not connected to other electrodes.

20. The display device according to claim 19, wherein No voltage is supplied to the second electrode pattern.

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