Display device

Abstract

The display device includes: a display area in which a plurality of pixels are disposed, the plurality of pixels each including a plurality of pixel electrodes spaced apart from each other; a first light blocking layer disposed in the display area and including a plurality of holes respectively overlapping the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer and respectively corresponding to the plurality of holes; and a second light blocking layer disposed on the color filter and corresponding to the pixel electrodes of some of the plurality of pixels. The second light blocking layer surrounds the pixel electrodes of the some of the plurality of pixels in a plan view and includes a plurality of light blocking patterns having different widths.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0019943 filed on February 8, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device including a light blocking layer. Background Art

[0004] With the development of information-oriented society, there is an increasing demand for display devices for displaying images. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display (LCD) device, a field emission display device, and an organic light emitting diode (OLED) display device. Among the flat panel display devices, in a light-emitting type display device, since each pixel of the display panel includes a light-emitting element that can emit light by itself, it is possible to display an image without a backlight unit that provides light to the display panel. Summary of the Invention

[0005] A display device includes: a display area in which a plurality of pixels are arranged, each of the plurality of pixels including a plurality of pixel electrodes spaced apart from each other; a first light-blocking layer arranged in the display area and including a plurality of holes respectively overlapping the plurality of pixel electrodes; a plurality of color filters arranged on the first light-blocking layer and corresponding to the plurality of holes respectively; and a second light-blocking layer arranged on the color filters and corresponding to the pixel electrodes of some of the plurality of pixels. The second light-blocking layer surrounds the pixel electrodes of some of the plurality of pixels in a plan view and includes a plurality of light-blocking patterns having different widths.

[0006] A display device includes: a substrate on which a first pixel and a second pixel are disposed, each of the first pixel and the second pixel including a plurality of pixel electrodes; an encapsulation layer disposed on the plurality of pixel electrodes; a first light-blocking layer disposed on the encapsulation layer and including a plurality of apertures corresponding to the plurality of pixel electrodes; a plurality of color filters disposed on the first light-blocking layer and corresponding to the plurality of pixel electrodes; a passivation layer disposed on the color filters and the first light-blocking layer; a second light-blocking layer disposed on the passivation layer in a second pixel and including a plurality of light-blocking patterns, the plurality of light-blocking patterns forming a plurality of transmissive portions that overlap the plurality of pixel electrodes of the second pixel; and an overcoat layer disposed on the second light-blocking layer. The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode, the first pixel electrode being disposed in each of the first pixel and the second pixel, and a second pixel electrode being disposed in each of the first pixel and the second pixel and having a radius smaller than a radius of the first pixel electrode. The width of the first light-blocking pattern overlapping the first pixel electrode disposed in the second pixel is smaller than the width of the second light-blocking pattern overlapping the second pixel electrode disposed in the second pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0008] Figure 1 is a schematic perspective view of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 2 is a perspective view showing a display device included in an electronic device according to an embodiment of the present disclosure;

[0010] Figure 3 yes Figure 2 a cross-sectional view of a display device viewed from the side;

[0011] Figure 4 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment of the present disclosure;

[0012] Figure 5 is a plan view illustrating the arrangement of a pixel electrode, a first light blocking layer, and a color filter in a display area of a display device according to an embodiment of the present disclosure;

[0013] Figure 6 is a plan view illustrating the arrangement of a pixel electrode and a second light blocking layer in a display area of a display device according to an embodiment of the present disclosure;

[0014] Figure 7 is a schematic diagram illustrating a light-emitting pixel according to an emission mode of a display device according to an embodiment of the present disclosure;

[0015] Figure 8 It is along Figure 5 and Figure 6 A cross-sectional view taken along line X1-X1';

[0016] Figure 9 It is along Figure 5 and Figure 6 A cross-sectional view taken along line X2-X2';

[0017] Figure 10 It is along Figure 6 A cross-sectional view taken along lines X3-X3' and X4-X4';

[0018] Figure 11 is a diagram illustrating relative arrangements of pixel electrodes and a first light-blocking layer provided in two pixels of a display device according to an embodiment of the present disclosure;

[0019] Figure 12 is a diagram illustrating relative arrangements of a pixel electrode and a second light-blocking layer provided in a second-type pixel of a display device according to an embodiment of the present disclosure;

[0020] Figure 13 is an exemplary diagram illustrating relative arrangement of a second light blocking layer and an emission direction of light emitted from a pixel electrode of a display device;

[0021] Figure 14 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment of the present disclosure;

[0022] Figure 15 It shows Figure 14 A plan view of an arrangement of a pixel electrode, a first light blocking layer, and a color filter in a display area of a display device;

[0023] Figure 16 It shows Figure 14 A plan view of an arrangement of a pixel electrode and a second light blocking layer in a display area of a display device;

[0024] Figure 17 It shows Figures 14 to 16 A diagram showing relative arrangement of a pixel electrode and a second light blocking layer in a display device; and

[0025] Figure 18 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the invention are shown. However, the present invention can be embodied in different forms and should not necessarily be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0027] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or intervening layers can also be present. Throughout the specification and drawings, like reference numerals may represent like components. In the drawings, although some elements may be drawn to scale so that relative lengths, thicknesses, and angles can be inferred, it should be understood that the present invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values may be varied within the spirit and scope of the present disclosure, for example, to allow for manufacturing limitations, etc.

[0028] Although the terms "first", "second" etc. can be used to describe various elements in this article, these elements do not necessarily need to be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element discussed below can be named as the second element. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second" etc. can also be used to distinguish between different categories or different groups of elements in this article. For simplicity, the terms "first", "second" etc. can respectively represent "first category (or first group)", "second category (or second group)" etc.

[0029] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0030] Figure 1 is a schematic perspective view of an electronic device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , electronic device 1 displays a dynamic image or a still image. Electronic device 1 may refer to any electronic device that provides a display screen. Examples of electronic device 1 may include televisions that provide a display screen, laptop computers, computer monitors, digital billboards, IoT devices, mobile phones, smartphones, tablet computers, electronic watches, smart watches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, portable game consoles, digital cameras, and video cameras.

[0032] The electronic device 1 may include Figure 2A display device 10 is provided for providing a display screen. Examples of the display device 10 may include an inorganic light-emitting diode (LED) display device, an organic light-emitting diode display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. In the following description, an organic light-emitting diode (OLED) display device is used as an example of a display device, but the present disclosure is not necessarily limited thereto, and other display devices may be applied within the scope of the same technical spirit.

[0033] The shape of the electronic device 1 may be modified in various ways. For example, in a plan view, the electronic device 1 may have a horizontally elongated rectangular shape, a vertically elongated rectangular shape, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 The electronic device 1 is shown having a rectangular shape elongated in the second direction DR2 in a plan view.

[0034] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where images can be displayed, and the non-display area NDA is an area where images are not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0035] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas in which components for adding various functions to the electronic device 1 are provided, and the second display area DA2 and the third display area DA3 may correspond to component areas.

[0036] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an embodiment of the present disclosure.

[0037] Reference Figure 2 , according to the electronic device 1 of the embodiment of the present disclosure (see Figure 1) may include a display device 10. The display device 10 may provide an image displayed by the electronic device 1. The display device 10 may have a planar shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangular shape having a pair of short sides extending in the first direction DR1 and a pair of long sides extending in the second direction DR2. The edges where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a desired degree of curvature, but are not necessarily limited thereto and may be formed at right angles. The planar shape of the display device 10 is not necessarily limited to a quadrilateral shape and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0038] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0039] The display panel 100 may include a main area MA and a sub-area SBA.

[0040] The main area MA may include a display area DA and a non-display area NDA. The display area DA includes pixels PX1, PX2, PX3, and PX4 (see FIG. Figure 4 ), and the non-display area NDA is arranged around the display area DA. The display area DA can be arranged at the center of the main area MA, and the non-display area NDA can surround the display area DA. The display area DA can include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA can emit light from multiple emission areas or multiple opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer that defines the emission area or the opening area, and a self-luminous element.

[0041] For example, the self-luminous element may include an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and / or a micro LED, but is not necessarily limited thereto.

[0042] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies gate signals to gate lines and a fan-out line that connects the display driver 200 to the display area DA.

[0043] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled to a significant degree without breaking or otherwise suffering damage. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In an embodiment of the present disclosure, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0044] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can supply power voltages to power lines and can supply gate control signals to gate drivers. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be disposed in a sub-area SBA and can overlap with the main area MA in the thickness direction by bending the sub-area SBA. For example, the display driver 200 can be mounted on a circuit board 300.

[0045] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0046] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the multiple touch electrodes of the touch sensing unit and may sense the change in capacitance between the multiple touch electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate whether an input has been made and the input coordinates based on the change in capacitance between the multiple touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0047] Figure 3 yes Figure 2 sectional view of a display device viewed from the side. Figure 3 Shown Figure 2 The sub-area SBA of the display panel 100 in the folded state in the display device 10 is shown.

[0048] Reference Figure 3The display panel 100 may include a display layer DU, a touch sensing layer TSU, a color filter layer CFL, and a light blocking member layer PML. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0049] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled to a significant degree without breaking or otherwise being damaged. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not necessarily limited thereto. In embodiments of the present disclosure, the substrate SUB may include glass or metal.

[0050] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors that constitute pixel circuits of the pixels. The thin film transistor layer TFTL may also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portion. Each thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0051] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines for each pixel in the thin film transistor layer TFTL may be disposed in the display area DA. Gate control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. Lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0052] The light-emitting element layer (EML) may be disposed on the thin film transistor layer TFTL. The light-emitting element layer (EML) may include a plurality of light-emitting elements, each including a first electrode, a second electrode, and a light-emitting layer for emitting light, and a pixel-defining layer that defines pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be disposed in the display area DA.

[0053] In an embodiment of the present disclosure, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be transferred to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other to emit light in the organic light-emitting layer.

[0054] In an embodiment of the present disclosure, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0055] The encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0056] The touch sensing layer TSU may be provided on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes for capacitively sensing a user's touch, and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense a user's touch using a mutual capacitance method or a self-capacitance method.

[0057] In an embodiment of the present disclosure, the touch sensing layer TSU may be provided on a separate substrate provided on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

[0058] The plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor area overlapping the display area DA, and the touch wires of the touch sensing layer TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0059] A color filter layer (CFL) may be provided on the touch sensing layer (TSU). The color filter layer (CFL) may include multiple color filters corresponding to the multiple emission regions. Each color filter selectively transmits light of a specific wavelength and blocks or absorbs light of a different wavelength. The color filter layer (CFL) may absorb a portion of light from outside the display device 10 to reduce reflected light caused by external light. Thus, the color filter layer (CFL) may prevent color distortion caused by reflection of external light.

[0060] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0061] The light blocking member layer PML may be disposed on the color filter layer CFL. The light blocking member layer PML may include light blocking patterns corresponding to specific pixels of the display layer DU. The display device 10 may further include the light blocking member layer PML to control visibility at a specific viewing angle and provide a privacy protection mode for the user.

[0062] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may transmit or receive light in the infrared band, the ultraviolet band, and the visible light band. For example, the optical device 500 may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, or an image sensor.

[0063] Figure 4 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment of the present disclosure. Figure 5 is a plan view illustrating the arrangement of a pixel electrode, a first light blocking layer, and a color filter in a display area of a display device according to an embodiment of the present disclosure.

[0064] Reference Figure 4 and Figure 5 , the display device 10 (see Figure 2 ) may include a display area DA (see Figure 2 ) in a plurality of pixels PX1, PX2, PX3 and PX4. The plurality of pixels PX1, PX2, PX3 and PX4 may be arranged in a fourth direction DR4 and a fifth direction DR5, the fourth direction DR4 being an oblique direction between the first direction DR1 and the second direction DR2, and the fifth direction DR5 being an oblique direction between the opposite direction of the first direction DR1 and the second direction DR2. The first pixel PX1 and the second pixel PX2 may be arranged to be adjacent to each other in the fifth direction DR5, and the second pixel PX2 and the third pixel PX3 may be arranged to be adjacent to each other in the fourth direction DR4. The third pixel PX3 and the fourth pixel PX4 may be arranged to be adjacent to each other in the fifth direction DR5. The first pixel PX1 and the fourth pixel PX4 may be arranged to be adjacent to each other in the fourth direction DR4. The plurality of pixels PX1, PX2, PX3 and PX4 may be arranged to be adjacent to each other in the fourth direction DR4 throughout the entire display area DA. Figure 4 The arrangement is repeated.

[0065] Each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a plurality of pixel electrodes AE1, AE2, and AE3. For example, each of the plurality of pixels PX1, PX2, PX3, and PX4 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3. One pixel PX1, PX2, PX3, or PX4 may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3. However, the present disclosure is not necessarily limited thereto. The number of pixel electrodes AE1, AE2, and AE3 provided in the pixels PX1, PX2, PX3, and PX4 may vary.

[0066] Each of the pixel electrodes AE1, AE2, and AE3 may be an anode electrode of a light emitting element included in each of the pixels PX1, PX2, PX3, and PX4. One pixel PX1, PX2, PX3, or PX4 may include one or more light emitting elements ED (see Figure 8 ), and the light-emitting element ED can emit light of different colors. For example, the light-emitting element including the first pixel electrode AE1 can emit light of a first color, which is red. The light-emitting element including the second pixel electrode AE2 can emit light of a second color, which is green, and the light-emitting element including the third pixel electrode AE3 can emit light of a third color, which is blue. However, the present disclosure is not necessarily limited to this. One first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3 can form a pixel PX1, PX2, PX3, or PX4, emitting light of different colors and representing a white grayscale. However, the present disclosure is not necessarily limited to this, and the combination of pixel electrodes AE1, AE2, and AE3 forming one pixel PX1, PX2, PX3, or PX4 can vary depending on the arrangement of the pixel electrodes AE1, AE2, and AE3, the color of the light emitted by the pixel electrodes AE1, AE2, and AE3, and the like.

[0067] Each of the pixel electrodes AE1, AE2, and AE3 may form an emission region in each of the pixels PX1, PX2, PX3, and PX4. For example, the first pixel electrode AE1 may form a first emission region that emits light of a first color, the second pixel electrode AE2 may form a second emission region that emits light of a second color, and the third pixel electrode AE3 may form a third emission region that emits light of a third color. In some embodiments, the emission region of the display device 10 may be a region overlapping with the pixel electrodes AE1, AE2, and AE3, and for example, Figure 8 The opening of the pixel defining layer PDL shown in FIG. 1 may correspond to the emission region. For example, the emission region may be formed by the pixel defining layer PDL (see FIG. 1 ) formed on the light emitting element layer EML to be described later. Figure 8 ). The first emission region may be defined by a first opening of the pixel defining layer PDL overlapping with the first pixel electrode AE1, the second emission region may be defined by a second opening of the pixel defining layer PDL overlapping with the second pixel electrode AE2, and the third emission region may be defined by a third opening of the pixel defining layer PDL overlapping with the third pixel electrode AE3.

[0068] The plurality of pixel electrodes AE1, AE2 and AE3 may be Type settings, where PENTILE is an arrangement of light emitting areas (e.g., diamond) manufactured by SAMSUNG Type). For example, the first pixel electrode AE1 and the third pixel electrode AE3 may be spaced apart from each other in the second direction DR2, and the first pixel electrode AE1 and the third pixel electrode AE3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second pixel electrode AE2 may be spaced apart from another adjacent second pixel electrode AE2 in the first direction DR1 and the second direction DR2, and may be spaced apart from the adjacent first pixel electrode AE1 and the adjacent third pixel electrode AE3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second pixel electrodes AE2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second pixel electrode AE2 and the first pixel electrode AE1 or the second pixel electrode AE2 and the third pixel electrode AE3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0069] In some embodiments, the areas or sizes of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be different from each other. Figure 4 In the embodiment of the present invention, the area of the third pixel electrode AE3 may be larger than the area of the first pixel electrode AE1 and the area of the second pixel electrode AE2, and the area of the first pixel electrode AE1 may be larger than the area of the second pixel electrode AE2. The intensity of the emitted light may vary depending on the size of the emission area overlapping with the pixel electrodes AE1, AE2 and AE3, and in the display device 10 or the electronic device 1 (see Figure 1 ) can be controlled by adjusting the size of the emission area. Figure 4 In the embodiment of FIG. 1 , the third pixel electrode AE3 has the largest area, but the present invention is not limited thereto. The sizes of the pixel electrodes AE1, AE2, and AE3 and the size of the emission area can be freely adjusted according to the color of the image required in the display device 10 or electronic device 1. In addition, the areas of the pixel electrodes AE1, AE2, and AE3 may be related to the light efficiency and lifespan of the light-emitting element ED, and may have a trade-off relationship with the reflection of external light. The areas of the pixel electrodes AE1, AE2, and AE3 may be adjusted in consideration of the above factors.

[0070] The display device 10 may include a first light blocking layer BM1 and a plurality of color filters CF1 , CF2 , and CF3 disposed on the pixel electrodes AE1 , AE2 , and AE3 .

[0071] The first light blocking layer BM1 may be provided throughout the entire display area DA. The first light blocking layer BM1 may include a plurality of holes OPT1, OPT2, and OPT3 corresponding to the plurality of pixel electrodes AE1, AE2, and AE3, respectively. Alternatively, the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may correspond to the pixel defining layers PDL (see FIG. Figure 8 ). The first light blocking layer BM1 may cover the display area DA at locations other than the area in the display area DA where the holes OPT1, OPT2, and OPT3 are provided. The holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be areas through which light emitted from the light-emitting element including the pixel electrodes AE1, AE2, and AE3 is emitted. The plurality of holes OPT1, OPT2, and OPT3 may include a first hole OPT1 overlapping with the first pixel electrode AE1, a second hole OPT2 overlapping with the second pixel electrode AE2, and a third hole OPT3 overlapping with the third pixel electrode AE3. Within the area occupied by one pixel PX1, PX2, PX3, or PX4, one first hole OPT1, two second holes OPT2, and one third hole OPT3 may be formed in the first light blocking layer BM1.

[0072] The areas (or sizes) of the plurality of apertures OPT1, OPT2, and OPT3 in a plan view may be larger than the areas (or sizes) of the pixel electrodes AE1, AE2, and AE3, respectively, in a plan view. For example, in a plan view, the area of the first aperture OPT1 may be larger than the area of the first pixel electrode AE1. In a plan view, the areas of the second aperture OPT2 and the third aperture OPT3 may also be larger than the areas of the second pixel electrode AE2 and the third pixel electrode AE3, respectively. Furthermore, in a plan view, the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may have different areas. As described above, the areas of the plurality of pixel electrodes AE1, AE2, and AE3 may differ from one another, and therefore, the sizes of the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 may also differ from one another. For example, the radius or size of the third aperture OPT3 may be larger than the radius or size of the first aperture OPT1 and the second aperture OPT2, and the radius or size of the first aperture OPT1 may be larger than the radius or size of the second aperture OPT2. However, the present disclosure is not necessarily limited to this.

[0073] In an embodiment of the present disclosure, the radius difference between the pixel electrodes AE1, AE2, and AE3 and the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, or the separation distance between the outer sides of the pixel electrodes AE1, AE2, and AE3 and the inner sides of the apertures OPT1, OPT2, and OPT3, in pixels PX1 and PX2 of the same type, can be uniform, regardless of the type of pixel electrodes AE1, AE2, and AE3 or the apertures OPT1, OPT2, and OPT3. For example, the separation distance between the first pixel electrode AE1 and the first aperture OPT1, or the radius difference between the first pixel electrode AE1 and the first aperture OPT1, can be the same as the separation distance between the second pixel electrode AE2 and the second aperture OPT2, or the radius difference between the second pixel electrode AE2 and the second aperture OPT2. The separation distance between the first pixel electrode AE1 and the first aperture OPT1, or the radius difference between the first pixel electrode AE1 and the first aperture OPT1, can also be the same as the separation distance between the third pixel electrode AE3 and the third aperture OPT3, or the radius difference between the third pixel electrode AE3 and the third aperture OPT3. However, the present disclosure is not necessarily limited thereto, and separation distances between the pixel electrodes AE1 , AE2 , and AE3 and the holes OPT1 , OPT2 , and OPT3 of the first light blocking layer BM1 may differ depending on types of the pixel electrodes AE1 , AE2 , and AE3 .

[0074] According to an embodiment of the present disclosure, the display device 10 may include pixels PX1, PX2, PX3, and PX4 having different pixel electrodes AE1, AE2, and AE3 and holes OPT1, OPT2, and OPT3 and holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1 (see FIG. Figure 9 ). For example, the first pixel PX1 and the third pixel PX3 may have the same separation distance between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1. The second pixel PX2 and the fourth pixel PX4 may also have the same separation distance between the pixel electrodes AE1, AE2, and AE3 and the holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1 (see Figure 9). However, in the first pixel PX1 and the second pixel PX2, the separation distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1 to OPT3 and the holes OPT4 to OPT6 of the first light blocking layer BM1 may be different from each other. In an embodiment of the present disclosure, the separation distances between the pixel electrodes AE1, AE2, and AE3 in the first pixel PX1 and the third pixel PX3 and the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be greater than the separation distances between the pixel electrodes AE1, AE2, and AE3 in the second pixel PX2 and the fourth pixel PX4 and the holes OPT4, OPT5, and OPT6 of the first light blocking layer BM1. In the second pixel PX2 and the fourth pixel PX4, the radius difference between the pixel electrodes AE1, AE2 and AE3 and the holes OPT4, OPT5 and OPT6 of the first light blocking layer BM1 can be small, and the outer sides of the pixel electrodes AE1, AE2 and AE3 and the inner sides of the holes OPT1, OPT2 and OPT3 can be positioned adjacent to each other in a plan view.

[0075] The display device 10 may include first-type pixels (such as first and third pixels PX1 and PX3) and second-type pixels (such as second and fourth pixels PX2 and PX4). The first-type pixels and the second-type pixels may be distinguished not only by the separation distances between the pixel electrodes AE1, AE2, and AE3 and the holes OPT1 to OPT3 and the holes OPT4 to OPT6 of the first light blocking layer BM1, but also by the presence / absence of the pixels to be referred to later. Figure 6 For example, the second light blocking layer BM2 may not be provided in the first pixel PX1 and the third pixel PX3, and the second light blocking layer BM2 may be provided in the second pixel PX2 and the fourth pixel PX4. The second light blocking layer BM2 will be described later with reference to other drawings.

[0076] The plurality of color filters CF1, CF2, and CF3 may correspond to the pixel electrodes AE1, AE2, and AE3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on the first light blocking layer BM1 and may correspond to the plurality of holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1. The holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may be aligned with the pixel defining layer PDL (see FIG. Figure 8) overlap with the opening of the first light blocking layer BM1 and can form a light exit area through which light emitted from the emission area is emitted. The color filters CF1, CF2, and CF3 can have an area larger than the area of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, respectively, and the color filters CF1, CF2, and CF3 can respectively completely cover the light exit area formed by the holes OPT1, OPT2, and OPT3. The color filters CF1, CF2, and CF3 can respectively completely cover the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, and a portion of the color filters CF1, CF2, and CF3 can be directly disposed on the first light blocking layer BM1. However, in some embodiments, the color filters CF1, CF2, and CF3 can be omitted.

[0077] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to different pixel electrodes AE1, AE2, and AE3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or pigment that absorbs light in a wavelength band other than a specific wavelength band, and may correspond to the color of light emitted by the light-emitting element including the pixel electrodes AE1, AE2, and AE3. For example, the first color filter CF1 may be a red color filter that overlaps with the first pixel electrode AE1 and transmits only red first light. The second color filter CF2 may be a green color filter that overlaps with the second pixel electrode AE2 and transmits only green second light, and the third color filter CF3 may be a blue color filter that overlaps with the third pixel electrode AE3 and transmits only blue third light.

[0078] Similar to the arrangement of the pixel electrodes AE1, AE2 and AE3, the color filters CF1, CF2 and CF3 may be arranged in a manner similar to the arrangement of the pixel electrodes AE1, AE2 and AE3. Type (e.g., diamond Type) arrangement. For example, the first color filter CF1 and the third color filter CF3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second color filter CF2 and another adjacent second color filter CF2 may be arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2 and the adjacent first color filter CF1 and the adjacent third color filter CF3 may be arranged in the fourth direction DR4 or the fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1 or the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0079] According to an embodiment of the present disclosure, the multiple color filters CF1, CF2, and CF3 may have different areas in a plan view. As described above, the areas of the multiple pixel electrodes AE1, AE2, and AE3 may differ from one another, and therefore, the plan view areas of the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, as well as the plan view areas of the color filters CF1, CF2, and CF3, may also differ from one another. For example, the area of the first color filter CF1, which is a red color filter, may be larger than the area of the second color filter CF2, which is a green color filter, and the area of the third color filter CF3, which is a blue color filter. Furthermore, the area of the third color filter CF3 may be larger than the area of the second color filter CF2. Similar to the shapes of the pixel electrodes AE1, AE2, and AE3, the color filters CF1, CF2, and CF3 may have a circular shape in a plan view. However, the present disclosure is not necessarily limited to this, and the color filters CF1, CF2, and CF3 may have a rectangular or diamond shape in a plan view. The display device 10 according to an embodiment of the present disclosure may be designed such that the planar shapes and areas of the color filters CF1 , CF2 , and CF3 allow external light of the display device 10 to have a specific color.

[0080] The display device 10 may include a display layer DU (see FIG. Figure 3 ) on the color filters CF1, CF2, and CF3 to reduce the intensity of reflected light caused by external light. In addition, the color of the reflected light due to external light can be controlled by adjusting the arrangement, shape, and area of the color filters CF1, CF2, and CF3 in a plan view. A detailed description will be given below with reference to other drawings.

[0081] The touch electrode TL may be disposed between the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be aligned with the pixel defining layer PDL (see FIG. Figure 8 ) overlaps the first light blocking layer BM1. Although the touch electrode TL is simply shown in the drawings, the touch electrode TL may include a touch driving electrode and a sensing electrode.

[0082] Figure 6 is a plan view illustrating the arrangement of a pixel electrode and a second light blocking layer in a display area of a display device according to an embodiment of the present disclosure. Figure 7 is a schematic diagram illustrating a light-emitting pixel according to an emission mode of a display device according to an embodiment of the present disclosure. Figure 7 A light-emitting pixel in an emissive mode with partially restricted side visibility among the emissive modes of the display device 10 is schematically illustrated.

[0083] Reference Figure 6 and Figure 7 , according to the display device 10 of the embodiment of the present disclosure (see Figure 2 ) may include a second light blocking layer BM2. The second light blocking layer BM2 may be provided only in the display area DA (see Figure 2 ) in some of the plurality of pixels in the first light blocking layer BM1. For example, the second light blocking layer BM2 may be provided in the second type pixels (e.g., the second pixel PX2 and the fourth pixel PX4) in the plurality of pixels. As described above, the plurality of pixels may include holes OPT1, OPT2, and OPT3 (see FIG. 1 ) having the pixel electrodes AE1, AE2, and AE3 and the first light blocking layer BM1. Figure 8 ), and the second light blocking layer BM2 may be provided only in the second type pixel.

[0084] The second light blocking layer BM2 may include a plurality of light blocking patterns BMP1, BMP2, and BMP3 (see Figure 12 ), and the light-blocking patterns BMP1, BMP2, and BMP3 may correspond to the plurality of pixel electrodes AE1, AE2, and AE3, respectively. For example, the light-blocking patterns BMP1, BMP2, and BMP3 may each have a uniform width and may surround the pixel electrodes AE1, AE2, and AE3, respectively, in a plan view without overlapping the pixel electrodes AE1, AE2, and AE3. The light-blocking patterns BMP1, BMP2, and BMP3 may have a ring shape that surrounds the pixel electrodes AE1, AE2, and AE3, respectively, in a plan view without overlapping the pixel electrodes AE1, AE2, and AE3. Similar to the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, the inner sides of the light-blocking patterns BMP1, BMP2, and BMP3 may be spaced apart from the outer sides of the pixel electrodes AE1, AE2, and AE3, respectively, in a plan view.

[0085] In the display device 10 according to an embodiment of the present disclosure, a plurality of pixels may include first-type pixels in which the second light-blocking layer BM2 is not provided and second-type pixels in which the second light-blocking layer BM2 is provided, so that side visibility can be adjusted according to the emission mode. Depending on the viewing angle of the display device 10, the light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 may partially cover the pixel electrodes AE1, AE2, and AE3, respectively, and may block the emission of light at a specific viewing angle.

[0086] For example, in the first emission mode of the display device 10, when side visibility is not restricted, both the first type pixel and the second type pixel can emit light. Figure 6As shown in , when the first pixel PX1, the second pixel PX2, the third pixel PX3 and the fourth pixel PX4 all emit light in the first emission mode, the light emitted from at least the first pixel PX1 and the third pixel PX3 can be visually recognized by the user regardless of the direction in which the user views the display device 10.

[0087] In the second emission mode of the display device 10, when it is desired to limit side visibility, only the second type of pixels may emit light. Figure 7 As shown in FIG, when only the second pixel PX2 and the fourth pixel PX4 emit light in the second emission mode, at a specific viewing angle, the light emitted from the holes OPT1, OPT2, and OPT3 of the first light-blocking layer BM1 can be blocked by the second light-blocking layer BM2. Since the first pixel PX1 and the third pixel PX3 do not emit light, the screen of the display device 10 in the second emission mode can be visually recognized only by users viewing from the front of the display area DA, and may not be visually recognized by users viewing from a specific viewing angle (such as from the side). The display device 10 can provide a privacy protection mode for users viewing from the front.

[0088] In the second emission mode of the display device 10, depending on the extent to which the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the fourth pixel PX4 are covered by the second light-blocking layer BM2, light leakage of light emitted from the pixel electrodes AE1, AE2, and AE3 of the second pixel PX2 and the fourth pixel PX4 may occur. However, in the display device 10 according to an embodiment of the present disclosure, the light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 may surround the pixel electrodes AE1, AE2, and AE3, respectively, corresponding to the shapes of the pixel electrodes AE1, AE2, and AE3. In the display device 10, in the second emission mode, the extent to which the pixel electrodes AE1, AE2, and AE3 of the second-type pixels are covered may be uniform at all viewing angles of the display device 10, and it is possible to prevent light leakage of light emitted from the light-emitting elements including the specific pixel electrodes AE1, AE2, and AE3.

[0089] In addition, in the display device 10, since the light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 correspond to the pixel electrodes AE1, AE2, and AE3 of the second type pixels, respectively, they may not extend into other adjacent pixels (e.g., first type pixels), and therefore may not cover the pixel electrodes AE1, AE2, and AE3 of the first type pixels in the first emission mode. For example, in the display device 10, even in the implementation of a high-resolution display device, the arrangement of the pixel structure can be freely designed.

[0090] Figure 8 It is along Figure 5 and Figure 6 A cross-sectional view taken along line X1-X1'. Figure 9 It is along Figure 5 and Figure 6 A cross-sectional view taken along line X2-X2'. Figure 10 It is along Figure 6 Cross-sectional views taken along lines X3-X3' and X4-X4'.

[0091] Figure 8 A cross section across the first pixel electrode AE1 , the second pixel electrode AE2 , and the third pixel electrode AE3 in the first pixel PX1 , which is a first-type pixel, is shown. Figure 9 A cross section across the first pixel electrode AE1 , the second pixel electrode AE2 , and the third pixel electrode AE3 in the second pixel PX2 , which is a second type pixel, is shown. Figure 10 A cross section spanning the first pixel electrode AE1 of a first type pixel and the first pixel electrode AE1 of a second type pixel is shown.

[0092] Will refer to Figures 8 to 10 The display device 10 (see Figure 3 ) is described with reference to the cross-sectional structure of the display panel 100 of the display device 10 (see Figure 3 ) may include a display layer DU, a touch sensing layer TSU, a first light blocking layer BM1, a color filter layer CFL, passivation layers PSV1 and PSV2, a second light blocking layer BM2, and an overcoat layer OC. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL. The first light blocking layer BM1 may be disposed on the touch sensing layer TSU of the display panel 100, and the color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light blocking layer BM1. The second light blocking layer BM2 may be disposed on the passivation layers PSV1 and PSV2 disposed on the color filter layer CFL, and the overcoat layer OC may be disposed on the second light blocking layer BM2.

[0093] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not necessarily limited thereto. For example, the substrate SUB may include glass or metal.

[0094] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0095] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0096] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu), and / or alloys thereof.

[0097] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0098] A thin film transistor (TFT) may be disposed on the second buffer layer (BF2) and may constitute a pixel circuit for each of the plurality of pixels. For example, the thin film transistor (TFT) may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor (TFT) may include a semiconductor layer (ACT), a source electrode (SE), a drain electrode (DE), and a gate electrode (GE).

[0099] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap with the lower metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the semiconductor layer ACT may be made of a conductor material to form a source electrode SE and a drain electrode DE.

[0100] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0101] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0102] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0103] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1 , overlap the gate electrode GE in the thickness direction, and form a capacitor with the gate electrode GE.

[0104] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0105] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0106] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0107] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrode AE of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0108] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS 1. The second passivation layer PAS2 may include a contact hole through which the pixel electrode AE of the light emitting element ED passes.

[0109] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, a light emitting layer EL, and a common electrode CE.

[0110] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. Different pixel electrodes AE1, AE2, and AE3 may each overlap any one of the different openings of the pixel defining layer PDL. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT via a first connection electrode CNE1 and a second connection electrode CNE2.

[0111] The light-emitting layer EL may be provided on the pixel electrodes AE1, AE2, and AE3. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. When an organic light-emitting layer is used as the light-emitting layer EL, the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting element ED. When the common electrode CE of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer and recombine to generate light to be emitted by the light-emitting layer EL.

[0112] In some embodiments, the light-emitting layers EL provided on different pixel electrodes AE1, AE2, and AE3 may emit light of different colors. For example, the light-emitting layer provided on the first pixel electrode AE1 may emit red light of a first color, the light-emitting layer provided on the second pixel electrode AE2 may emit green light of a second color, and the light-emitting layer provided on the third pixel electrode AE3 may emit blue light of a third color. However, the present disclosure is not necessarily limited to this. In an embodiment of the present disclosure, the light-emitting layer EL may be provided as a single common layer on different pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, and the light-emitting layers EL provided on different pixel electrodes AE1, AE2, and AE3 may emit light of the same color. In this case, the display device 10 may further include a color adjustment layer provided on the light-emitting element ED.

[0113] A common electrode CE may be provided on the light-emitting layer EL. For example, the common electrode CE may be formed as an electrode common to all pixels rather than an electrode specific to each pixel. The common electrode CE may be provided on the light-emitting layer EL in a region overlapping with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and may be provided on the pixel defining layer PDL in a region other than the region overlapping with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3.

[0114] The common electrode CE can receive a common voltage or a low potential voltage. When the pixel electrode AE receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2 and AE3 and the common electrode CE, so that the light emitting layer EL can emit light.

[0115] The pixel defining layer PDL may include a plurality of openings and may be disposed on a portion of the pixel electrodes AE1, AE2, and AE3 and the second passivation layer PAS2. Each opening of the pixel defining layer PDL may expose a portion of the pixel electrodes AE1, AE2, and AE3. As described above, the corresponding openings of the pixel defining layer PDL may define the first emission area to the third emission area, and the areas or sizes of the corresponding openings of the pixel defining layer PDL may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrodes AE1, AE2, and AE3 of each of the plurality of light-emitting elements ED. The pixel defining layer PDL may include a light-absorbing material to prevent light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based adhesive and a pigment in which red, green, and blue are mixed. Alternatively, the pixel defining layer PDL may include a Cardo-based adhesive resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the pixel defining layer PDL may include carbon black.

[0116] The encapsulation layer TFEL may be disposed on the common electrode CE and may cover the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0117] In some embodiments, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0118] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0119] The second encapsulation layer TFE2 may include a polymer material. Examples of polymer materials include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the second encapsulation layer TFE2 may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0120] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL, and may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, touch electrodes TL, and a third touch insulating layer SIL3.

[0121] The first touch insulating layer SIL1 may be disposed on the encapsulation layer TFEL. The first touch insulating layer SIL1 may have an insulating function and an optical function. The first touch insulating layer SIL1 may include at least one inorganic layer. Optionally, the first touch insulating layer SIL1 may be omitted.

[0122] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. In some embodiments, another layer of touch electrodes may be further provided on the first touch insulating layer SIL1. In this case, the second touch insulating layer SIL2 may cover the touch electrodes provided on the first touch insulating layer SIL1. The second touch insulating layer SIL2 may have both insulating and optical functions. For example, the second touch insulating layer SIL2 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0123] A portion of the touch electrode TL may be disposed on the second touch insulating layer SIL2. The touch electrode TL may not overlap with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The touch electrode TL may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0124] The touch electrode TL of the touch sensing layer TSU can have a constant line width and can overlap with the first light-blocking layer BM1, which will be described below. The first light-blocking layer BM1 can have a width sufficient to completely cover the touch electrode TL, and a gap can be defined between the edge of the first light-blocking layer BM1 and the touch electrode TL. In some embodiments, the line width of the touch electrode TL can be in a range of 4 μm to 6 μm, and the gap between the touch electrode TL and the edge of the first light-blocking layer BM1 can be in a range of 5 μm to 7 μm. The touch electrode TL can be arranged so that the center of the touch electrode TL is substantially aligned with the center of the first light-blocking layer BM1, and the gap from both sides of the touch electrode TL to the edge of the first light-blocking layer BM1 can be substantially constant.

[0125] The third touch insulating layer SIL3 may cover the touch electrode TL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have an insulating function and an optical function. The third touch insulating layer SIL3 may be made of the materials exemplified in association with the second touch insulating layer SIL2.

[0126] The first light-blocking layer BM1 may be disposed on the third touch insulating layer SIL3 of the touch sensing layer TSU. The first light-blocking layer BM1 may cover the conductive lines of the touch electrodes TL and include a plurality of apertures OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 that overlap with the pixel electrodes AE1, AE2, and AE3. For example, the first aperture OPT1 may overlap with the first pixel electrode AE1 of the first pixel PX1 / the third pixel PX3. The second aperture OPT2 may overlap with the second pixel electrode AE2 of the first pixel PX1, and the third aperture OPT3 may overlap with the third pixel electrode AE3 of the first pixel PX1. The fourth aperture OPT4 may overlap with the first pixel electrode AE1 of the second pixel PX2 / the fourth pixel PX4. The fifth aperture OPT5 may overlap with the second pixel electrode AE2 of the second pixel PX2, and the sixth aperture OPT6 may overlap with the third pixel electrode AE3 of the second pixel PX2. The area or size of each of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 may be larger than the area or size of the corresponding pixel electrodes AE1, AE2, and AE3. In addition, the area or size of each of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the corresponding opening of the pixel defining layer PDL, and the light emitted from the light-emitting element ED may be visually recognized by the user not only from the front of the display device 10 but also from the side of the display device 10. However, whether the first pixel PX1 and the second pixel PX2 emit light may depend on the emission mode of the display device 10, and the shape of the first light blocking layer BM1 may be designed so that the light of the second pixel PX2 is not visually recognized at a specific viewing angle in an emission mode with limited side visibility.

[0127] Figure 11 is a diagram illustrating relative arrangements of pixel electrodes and a first light-blocking layer provided in two pixels of a display device according to an embodiment of the present disclosure.

[0128] Reference Figure 11 Combined with Figure 8 and Figure 9 , in the display device 10 according to the embodiment of the present disclosure (see Figure 3 ), the sizes of the first hole OPT1, the second hole OPT2, and the third hole OPT3 provided in the first pixel PX1 may be larger than the sizes of the fourth hole OPT4, the fifth hole OPT5, and the sixth hole OPT6 provided in the second pixel PX2. For example, the size or radius RT1 of the first hole OPT1 in the first pixel PX1 overlapping with the first pixel electrode AE1 may be larger than the size or radius RT2 of the fourth hole OPT4 in the second pixel PX2 overlapping with the first pixel electrode AE1.

[0129] In the second emission mode of the display device 10, only the second-type pixels can emit light, while the first-type pixels can not emit light. When the second-type pixels emit light, the size of the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 in the second pixel PX2 can be relatively small to facilitate blocking light emission at a specific viewing angle. In addition, because the second light-blocking layer BM2 is provided in the second-type pixels, the second emission mode of the display device 10 can control the side visibility of the light emitted from the second-type pixels.

[0130] In the first emission mode, both the first pixel PX1 and the second pixel PX2 can emit light and can be visually recognized from both the front and side. Therefore, in the first pixel PX1, the radii of the pixel electrodes AE1, AE2, and AE3 and the first, second, and third apertures OPT1, OPT2, and OPT3 can be equal to or greater than a certain level to ensure visibility from the side. In the second emission mode, only the second pixel PX2 can emit light, while the first pixel PX1 may not emit light, and side visibility may be limited. In the second emission mode, light from the second pixel PX2 may not be visually recognized at side viewing angles other than near-front viewing angles. The radii of the fourth, fifth, and sixth apertures OPT4, OPT5, and OPT6 provided in the second pixel PX2 can be almost identical to those of the pixel electrodes AE1, AE2, and AE3, limiting visibility even at small side viewing angles. In addition, a second light-blocking layer BM2, described below, may be provided in the second pixel PX2 to further limit side visibility.

[0131] In the display device 10, the radius of the same type of pixel electrodes AE1, AE2, and AE3 provided in each of the first pixel PX1 and the second pixel PX2 (for example, the radius of the first pixel electrode AE1 of the first pixel PX1) may be equal to the radius of the first pixel electrode AE1 of the second pixel PX2, and the first hole OPT1 provided in the first pixel PX1 may have a radius larger than the radius of the fourth hole OPT4 provided in the second pixel PX2. In some embodiments, the radius difference between the holes OPT4, OPT5, and OPT6 in the second pixel PX2 and the pixel electrodes AE1, AE2, and AE3 may be adjusted based on the patterning process capability of the first light blocking layer BM1, and in addition to the above-mentioned patterning process capability, the radius difference between the holes OPT1, OPT2, and OPT3 in the first pixel PX1 and the pixel electrodes AE1, AE2, and AE3 may also be adjusted based on the optical distance from the pixel electrodes AE1, AE2, and AE3. In an embodiment of the present disclosure, the radius difference between the holes OPT4, OPT5 and OPT6 in the second pixel PX2 and the pixel electrodes AE1, AE2 and AE3 may be 1.0 μm to 1.5 μm or about 1.2 μm, and the radius difference between the holes OPT1, OPT2 and OPT3 in the first pixel PX1 and the pixel electrodes AE1, AE2 and AE3 may be 4.5 μm to 6.5 μm or about 5 μm. The radius difference between the holes OPT1, OPT2 and OPT3 in the first pixel PX1 and the holes OPT4, OPT5 and OPT6 in the second pixel PX2 may be a value designed in consideration of the above-mentioned optical distance (for example, the distance between the pixel electrodes AE1, AE2 and AE3 and the top surface of the second encapsulation layer TFE2). However, the present disclosure is not necessarily limited thereto, and the radius difference between the holes set in the first pixel PX1 and the second pixel PX2 may be determined according to the electronic device 1 (see Figure 1 )The optical property conditions required or desired are designed and modified in various ways.

[0132] The first light-blocking layer BM1 may include a light-absorbing material. For example, the first light-blocking layer BM1 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not necessarily limited thereto. The first light-blocking layer BM1 may prevent visible light from penetrating and color mixing between the holes OPT1, OPT2, and OPT3, thereby improving the color reproducibility of the display device 10. In some embodiments, the first light-blocking layer BM1 may have a thickness of 1 μm to 3 μm, or approximately 1.5 μm.

[0133] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the first light-blocking layer BM1. Different color filters CF1, CF2, and CF3 may correspond to different pixel electrodes AE1, AE2, and AE3 and apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, respectively. For example, the first color filter CF1 may correspond to the first pixel electrode AE1, the second color filter CF2 may correspond to the second pixel electrode AE2, and the third color filter CF3 may correspond to the third pixel electrode AE3. The first color filter CF1 may be disposed in the first aperture OPT1 of the first light-blocking layer BM1, the second color filter CF2 may be disposed in the second aperture OPT2 of the first light-blocking layer BM1, and the third color filter CF3 may be disposed in the third aperture OPT3 of the first light-blocking layer BM1. Each of the color filters CF1, CF2, and CF3 may have a larger area in plan view than the apertures OPT1, OPT2, and OPT3 of the first light-blocking layer BM1, and some color filters may be disposed directly on the first light-blocking layer BM1.

[0134] The areas of the plurality of color filters CF1, CF2, and CF3 may vary depending on the sizes of the holes OPT1, OPT2, OPT3, OPT4, OPT5, and OPT6 of the first light blocking layer BM1. For example, in a plan view, the area of the first color filter CF1 may be larger than the area of the second color filter CF2, but smaller than the area of the third color filter CF3. In some embodiments, the area of the first color filter CF1 disposed in the first pixel PX1 in a plan view may be the same as the area of the first color filter CF1 disposed in the second pixel PX2 in a plan view. However, the present disclosure is not necessarily limited thereto. In some embodiments, the area of the first color filter CF1 disposed in the first pixel PX1 in a plan view may be larger than the area of the first color filter CF1 disposed in the second pixel PX2 in a plan view.

[0135] The passivation layers PSV1 and PSV2 may be disposed on the first light blocking layer BM1 and the color filter layer CFL. The passivation layers PSV1 and PSV2 may extend over the entire display area DA (see FIG. Figure 2 ) is provided to flatten the top surface of the display panel 100. The passivation layers PSV1 and PSV2 may include a first passivation layer PSV1 provided on the color filter layer CFL and the first light blocking layer BM1, and a second passivation layer PSV2 provided on the first passivation layer PSV1. The passivation layers PSV1 and PSV2 may be formed of a plurality of layers to flatten a stepped portion caused by the color filter layer CFL and the first light blocking layer BM1.

[0136] The passivation layers PSV1 and PSV2 may be colorless light-transmitting layers having no color in the visible light band. For example, the passivation layers PSV1 and PSV2 may include a colorless light-transmitting organic material such as acrylic resin.

[0137] The second light-blocking layer BM2 may be disposed on the passivation layers PSV1 and PSV2. The second light-blocking layer BM2 may not be disposed in the first-type pixel (or first pixel PX1), but may be disposed only in the second-type pixel (or second pixel PX2). The second light-blocking layer BM2 may correspond to the periphery of the pixel electrodes AE1, AE2, and AE3 of the second-type pixel and may form transmissive portions OPB1, OPB2, and OPB3 that overlap with the pixel electrodes AE1, AE2, and AE3. For example, the second light-blocking layer BM2 may include a first transmissive portion OPB1 that overlaps with the first pixel electrode AE1, a second transmissive portion OPB2 that overlaps with the second pixel electrode AE2, and a third transmissive portion OPB3 that overlaps with the third pixel electrode AE3. The transmissive portions OPB1, OPB2, and OPB3 may also overlap with the apertures OPT4, OPT5, and OPT6, respectively, of the first light-blocking layer BM1.

[0138] In an embodiment of the present disclosure, the radius or area of the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2 in a plan view may be larger than the radius or area of the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 and the pixel electrodes AE1, AE2, and AE3 in a plan view. Light emitted from the light-emitting element ED including the pixel electrodes AE1, AE2, and AE3 may be emitted through the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1 and the transmissive portions OPB1, OPB2, and OPB3 of the second light-blocking layer BM2. Light emitted from the second-type pixels is ultimately emitted after passing through the transmissive portions OPB1, OPB2, and OPB3, and a large amount of light may be visually recognized at least when the display device 10 is viewed from the front.

[0139] However, when the display device 10 is viewed from the side, even if light emitted from the second-type pixel passes through the holes OPT4, OPT5, and OPT6 of the first light-blocking layer BM1, the light may be blocked by the second light-blocking layer BM2. For example, the display device 10 may allow only the second pixel PX2 or the second-type pixel in which the second light-blocking layer BM2 is disposed to emit light in the second emission mode, thereby controlling visibility at a specific viewing angle and providing a privacy protection mode for the user.

[0140] The second light-blocking layer BM2 may include a light-absorbing material. For example, the second light-blocking layer BM2 may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not necessarily limited thereto. In some embodiments, the second light-blocking layer BM2 may have a thickness of 1 μm to 3 μm, or approximately 1.5 μm.

[0141] An overcoat layer (OC) may be provided on the second light-blocking layer BM2 and the passivation layers PSV1 and PSV2. The overcoat layer (OC) may be provided throughout the entire display area (DA) to flatten the top surface of the display panel 100. The overcoat layer (OC) may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer (OC) may include a colorless light-transmitting organic material such as an acrylic resin.

[0142] Hereinafter, the second light blocking layer BM2 and the pixel electrodes AE1 , AE2 , and AE3 of the display device 10 will be described in more detail with reference to other drawings.

[0143] Figure 12 is a diagram illustrating relative arrangement of a pixel electrode and a second light blocking layer provided in a second type pixel of a display device according to an embodiment of the present disclosure. Figure 13 is an exemplary diagram illustrating relative arrangement of a second light blocking layer and an emission direction of light emitted from a pixel electrode of a display device. Figure 12 An example of a second pixel PX2 or a second type pixel in which a second light blocking layer BM2 is provided is shown. Figure 13 A size variation of the light-blocking patterns BMP2 and BMP3 according to the pixel electrodes AE2 and AE3 having different radii is shown.

[0144] Reference Figure 12 and Figure 13 Combined with Figure 8 and Figure 9 , in the display device 10 (see Figure 3 ), the radii PR1, PR2, and PR3 of different pixel electrodes AE1, AE2, and AE3 may be different from each other. For example, the radius PR3 of the third pixel electrode AE3 may be larger than the radius PR1 of the first pixel electrode AE1 and the radius PR2 of the second pixel electrode AE2. The radius PR1 of the first pixel electrode AE1 may be larger than the radius PR2 of the second pixel electrode AE2. This may mean that the areas of the pixel electrodes AE1, AE2, and AE3 are designed taking into account the wavelength of light emitted from the light-emitting element ED including each of the pixel electrodes AE1, AE2, and AE3 and the lifespan of the light-emitting element ED.

[0145] As described above, in the display device 10, the same type of pixel electrodes AE1, AE2, and AE3 provided in each of the first pixel PX1 and the second pixel PX2 may have the same radius. For example, the first pixel electrode AE1 provided in the first pixel PX1 may have the same radius as the first pixel electrode AE1 provided in the second pixel PX2.

[0146] In the second pixel PX2, the second light-blocking layer BM2 may include light-blocking patterns BMP1, BMP2, and BMP3 corresponding to the pixel electrodes AE1, AE2, and AE3, respectively, and surrounding the pixel electrodes AE1, AE2, and AE3 in a plan view. For example, the second light-blocking layer BM2 may include a first light-blocking pattern BMP1 surrounding the first pixel electrode AE1, a second light-blocking pattern BMP2 surrounding the second pixel electrode AE2, and a third light-blocking pattern BMP3 surrounding the third pixel electrode AE3. One second pixel PX2 may include one first light-blocking pattern BMP1, two second light-blocking patterns BMP2, and one third light-blocking pattern BMP3 in the same manner as the number and arrangement of the pixel electrodes AE1, AE2, and AE3 included in one second pixel PX2. The one first light-blocking pattern BMP1, two second light-blocking patterns BMP2, and one third light-blocking pattern BMP3 may be spaced apart from each other in an oblique direction. However, the present disclosure is not necessarily limited to this.

[0147] The plurality of light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 may form transmissive portions OPB1, OPB2, and OPB3 overlapping the pixel electrodes AE1, AE2, and AE3 (see FIG. Figure 9 ), and may have a circular ring shape having inner radii IR1, IR2, and IR3 and outer radii OR1, OR2, and OR3 measured from the center of the pixel electrodes AE1, AE2, and AE3, as well as the width of the light-blocking patterns BMP1, BMP2, and BMP3 themselves. The inner radii IR1, IR2, and IR3 of the light-blocking patterns BMP1, BMP2, and BMP3 may be understood as the distance between the center of the pixel electrodes AE1, AE2, and AE3 and the inner side of the light-blocking patterns BMP1, BMP2, and BMP3. The outer radii OR1, OR2, and OR3 of the light-blocking patterns BMP1, BMP2, and BMP3 may be understood as the distance between the center of the pixel electrodes AE1, AE2, and AE3 and the outer side of the light-blocking patterns BMP1, BMP2, and BMP3.

[0148] According to an embodiment of the present disclosure, the plurality of light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 may have the same inner radius IR1, IR2, and IR3, and the separation distances between the light-blocking patterns BMP1, BMP2, and BMP3 and the pixel electrodes AE1, AE2, and AE3 may be different from each other. The separation distance between the light-blocking patterns BMP1, BMP2, and BMP3 and the pixel electrodes AE1, AE2, and AE3 refers to the difference between the inner radius IR1, IR2, and IR3 of the light-blocking patterns BMP1, BMP2, and BMP3 and the radius PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3. For example, the inner radius IR1, IR2, and IR3 of the first light-blocking pattern BMP1, the second light-blocking pattern BMP2, and the third light-blocking pattern BMP3 may be the same. The difference between the inner radius IR3 of the third light-blocking pattern BMP3 and the radius PR3 of the third pixel electrode AE3 may be smaller than the difference between the inner radius IR1 of the first light-blocking pattern BMP1 and the radius PR1 of the first pixel electrode AE1, and the difference between the inner radius IR2 of the second light-blocking pattern BMP2 and the radius PR2 of the second pixel electrode AE2. The difference between the inner radius IR1 of the first light-blocking pattern BMP1 and the radius PR1 of the first pixel electrode AE1 may be smaller than the difference between the inner radius IR2 of the second light-blocking pattern BMP2 and the radius PR2 of the second pixel electrode AE2. The order of the separation distances between the pixel electrodes AE1, AE2, and AE3 and the light-blocking patterns BMP1, BMP2, and BMP3 may be opposite to the order of the radii PR1, PR2, and PR3 of the pixel electrodes AE1, AE2, and AE3. In some embodiments, inner radii IR1, IR2, and IR3 of the light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 may each have a size of about 9 μm, and a separation distance between the light blocking patterns BMP1, BMP2, and BMP3 and the pixel electrodes AE1, AE2, and AE3 may be in the range of about 1 μm to about 3 μm.

[0149] According to an embodiment of the present disclosure, the light-blocking patterns BMP1, BMP2, and BMP3 of the second light-blocking layer BM2 may have the same inner radius IR1, IR2, and IR3, but may have different outer radii OR1, OR2, and OR3, as well as different widths. The widths of the light-blocking patterns BMP1, BMP2, and BMP3 may be correlated with the radius of the pixel electrodes AE1, AE2, and AE3. In some embodiments, in the display device 10, the dimensional relationship of the widths of the light-blocking patterns BMP1, BMP2, and BMP3 may be opposite to the dimensional relationship of the radius of the pixel electrodes AE1, AE2, and AE3. For example, the radius of the third pixel electrode AE3 may be greater than the radius of the first and second pixel electrodes AE1, AE2, but the width of the third light-blocking pattern BMP3 may be smaller than the widths of the first and second light-blocking patterns BMP1 and BMP2. The radius of the second pixel electrode AE2 may be smaller than the radius of the first pixel electrode AE1, but the width of the second light-blocking pattern BMP2 may be greater than the width of the first light-blocking pattern BMP1. The radii of the pixel electrodes AE1, AE2, and AE3 may decrease in the order of the third pixel electrode AE3, the first pixel electrode AE1, and the second pixel electrode AE2, but the widths of the light blocking patterns BMP1, BMP2, and BMP3 may increase in the order of the third light blocking pattern BMP3, the first light blocking pattern BMP1, and the second light blocking pattern BMP2.

[0150] The light-blocking patterns BMP1, BMP2, and BMP3 may have the same inner radii IR1, IR2, and IR3, but different widths, and therefore the outer radii OR1, OR2, and OR3 may also differ in size from one another. The outer radius OR3 of the third light-blocking pattern BMP3 may be smaller than the outer radius OR1 of the first light-blocking pattern BMP1 and the outer radius OR2 of the second light-blocking pattern BMP2, and the outer radius OR1 of the first light-blocking pattern BMP1 may be smaller than the outer radius OR2 of the second light-blocking pattern BMP2. The widths and outer radii of the light-blocking patterns BMP1, BMP2, and BMP3 may be arranged in the opposite order to the radii of the pixel electrodes AE1, AE2, and AE3.

[0151] The extent to which pixel electrodes AE1, AE2, and AE3 are covered by light-blocking patterns BMP1, BMP2, and BMP3 at a specific viewing angle of display device 10 may be related to the separation distance between pixel electrodes AE1, AE2, and AE3 and light-blocking patterns BMP1, BMP2, and BMP3. To prevent light from being visually discernible when display device 10 in the second emission mode is viewed from a specific viewing angle, all pixel electrodes AE1, AE2, and AE3 need to be covered at the corresponding viewing angle, regardless of the type of pixel electrodes AE1, AE2, and AE3. When the radii of pixel electrodes AE1, AE2, and AE3 are different but the separation distance between pixel electrodes AE1, AE2, and AE3 and light-blocking patterns BMP1, BMP2, and BMP3 is uniform, at a specific viewing angle, any one of pixel electrodes AE1, AE2, and AE3 may be completely covered, while the other pixel electrodes AE1, AE2, and AE3 may not be covered, thereby making it possible for light to be visually discernible.

[0152] For example, at a certain viewing angle, the second pixel electrode AE2, which has a relatively small radius compared to other pixel electrodes, may be covered to a relatively large extent by the light-blocking patterns BMP1, BMP2, and BMP3. In this case, at the corresponding viewing angle, a relatively small amount of light emitted from the light-emitting layer disposed on the second pixel electrode AE2 of the second pixel PX2 may be visually recognized. When the light-emitting layer disposed on the second pixel electrode AE2 emits green light, due to the lack of green light, an overall purple-magenta phenomenon may occur in the displayed image at the corresponding viewing angle.

[0153] Furthermore, at a specific viewing angle, the second pixel electrode AE2 having a relatively small radius may not be covered by the light-blocking patterns BMP1, BMP2, and BMP3, while the other pixel electrodes AE1 and AE3 may be covered by the light-blocking patterns BMP1, BMP2, and BMP3. In this case, at the corresponding viewing angle, light emitted from the light-emitting layer disposed on the second pixel electrode AE2 of the second pixel PX2 may be visually recognized. When the light-emitting layer disposed on the second pixel electrode AE2 emits green light, a green phenomenon may occur in which the display screen has an overall green color at the corresponding viewing angle.

[0154] With this in mind, in the display device 10, at a viewing angle where pixel electrodes with larger radii can be covered by the light-blocking pattern, the separation distance between the pixel electrodes and the light-blocking pattern can be adjusted to ensure that pixel electrodes with smaller radii are also covered by the light-blocking pattern at a similar ratio. In the display device 10, the difference between the radius of the pixel electrodes AE1, AE2, and AE3 and the inner radius IR1, IR2, and IR3 of the light-blocking patterns BMP1, BMP2, and BMP3, or the separation distance between the pixel electrodes AE1, AE2, and AE3 and the light-blocking patterns BMP1, BMP2, and BMP3, can be different from one another. As described above, as the radius of the pixel electrodes AE1, AE2, and AE3 increases, the separation distance can decrease. In an embodiment of the present disclosure, the separation distances between the pixel electrodes AE1, AE2, and AE3 and the light-blocking patterns BMP1, BMP2, and BMP3 can be different from one another, and the relationship of the difference in separation distances can be opposite to the relationship of the difference in radius of the pixel electrodes AE1, AE2, and AE3.

[0155] Furthermore, the relationship between the widths of the light-blocking patterns BMP1, BMP2, and BMP3 can also be opposite to the relationship between the radii of the pixel electrodes AE1, AE2, and AE3. For example, when the widths of the light-blocking patterns BMP1, BMP2, and BMP3 are the same, the second pixel electrode AE2, which has a smaller radius, may be closer to the outside of the light-blocking patterns BMP1, BMP2, and BMP3 than the third pixel electrode AE3, which has a larger radius. In this case, light emitted from the light-emitting layer disposed on the second pixel electrode AE2, which has a smaller radius, may be more easily emitted at high viewing angles. To account for this, the widths of the light-blocking patterns BMP1, BMP2, and BMP3 corresponding to the pixel electrodes AE1, AE2, and AE3, which have smaller radii, can be designed to be larger to prevent light leakage at high viewing angles.

[0156] like Figure 13As shown in FIG, the position at which light L emitted from one side of pixel electrodes AE1, AE2, and AE3 at a specific emission angle reaches light-blocking patterns BMP1, BMP2, and BMP3 may be spaced a certain distance from the other side of pixel electrodes AE1, AE2, and AE3. Here, light L emitted from pixel electrodes AE1, AE2, and AE3 with a smaller radius (e.g., second pixel electrode AE2) at a specific emission angle reaches light-blocking patterns BMP1, BMP2, and BMP3 may be positioned farther away than light L emitted from pixel electrodes AE1, AE2, and AE3 with a larger radius (e.g., third pixel electrode AE3). As described above, in contrast to the size of pixel electrodes AE1, AE2, and AE3, the separation distance between pixel electrodes AE1, AE2, and AE3 and light-blocking patterns BMP1, BMP2, and BMP3 may be smaller for third light-blocking pattern BMP3, making it more likely that light L emitted from second pixel electrode AE2 will be emitted beyond light-blocking patterns BMP1, BMP2, and BMP3. Considering this, the width WB2 of the second light-blocking pattern BMP2 corresponding to the second pixel electrode AE2 having a smaller radius may be greater than the width WB3 of the third light-blocking pattern BMP3. Therefore, the separation distance DB3 between one side of the third pixel electrode AE3 and the outer side of the third light-blocking pattern BMP3 may be smaller than the separation distance DB2 between one side of the second pixel electrode AE2 and the outer side of the second light-blocking pattern BMP2. The relationship of the difference in width of the light-blocking patterns BMP1, BMP2, and BMP3 may be opposite to the relationship of the difference in radius of the pixel electrodes AE1, AE2, and AE3.

[0157] The display device 10 according to an embodiment of the present disclosure may include a first light-blocking layer BM1 and a second light-blocking layer BM2 to control the visibility of an image at a specific viewing angle, depending on the emission mode of the display device 10. In the display device 10, by designing the separation distances between the pixel electrodes AE1, AE2, and AE3 and the first and second light-blocking layers BM1 and BM2, and the widths of the light-blocking patterns BMP1, BMP2, and BMP3, it is possible to prevent the image displayed to the user from not having a specific color and light leakage that may occur at specific viewing angles. The display device 10 can provide a privacy protection mode for the user by preventing visibility at specific viewing angles.

[0158] Figure 14 is a plan view of an arrangement of pixel electrodes in a display area of a display device according to an embodiment of the present disclosure. Figure 15 It shows Figure 14 A plan view of an arrangement of a pixel electrode, a first light blocking layer, and a color filter in a display area of a display device. Figure 16 It shows Figure 14A plan view of an arrangement of a pixel electrode and a second light-blocking layer in a display area of a display device.

[0159] Reference Figures 14 to 16 , in the display device 10 according to the embodiment of the present disclosure (see Figure 3 ), the pixel electrodes AE1, AE2, and AE3 may have an approximately quadrilateral shape, and therefore, the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 and the light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 may also have a shape close to a quadrilateral shape. Except for the differences in the shapes of the pixel electrodes AE1, AE2, and AE3, the shapes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1, and the shapes of the light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2, the display device 10 according to the present embodiment is different from the display device 10 according to the present embodiment. Figures 4 to 6 The display device 10 of the embodiment is the same.

[0160] The length of the first pixel electrode AE1 and the third pixel electrode AE3 measured in one direction may be the same as the length of the first pixel electrode AE1 and the third pixel electrode AE3 measured in another direction. For example, the length of the first pixel electrode AE1 and the third pixel electrode AE3 in the fourth direction DR4 having a linear side and the length in the fifth direction DR5 perpendicular to the fourth direction DR4 may be the same. The first pixel electrode AE1 and the third pixel electrode AE3 may have a substantially square or regular octagonal shape. However, as described above, in plan view, the size or area of the third pixel electrode AE3 may be larger than the size or area of the first pixel electrode AE1.

[0161] The length of the second pixel electrode AE2 measured in one direction may be different from the length of the second pixel electrode AE2 measured in another direction. For example, one of the second pixel electrodes AE2 may have a length in the fourth direction DR4 that is greater than its length in the fifth direction DR5, and the other second pixel electrode AE2 may have a length in the fourth direction DR4 that is less than its length in the fifth direction DR5. Two different second pixel electrodes AE2 in one pixel PX1, PX2 may have different major axis directions.

[0162] In some embodiments, the length of the first pixel electrode AE1 measured in one direction may be the same as the length of the second pixel electrode AE2 measured in the short axis direction, and the length of the third pixel electrode AE3 measured in one direction may be the same as the length of the second pixel electrode AE2 measured in the long axis direction. Unlike the above-described embodiments of the present disclosure, in a plan view, the size or area of the second pixel electrode AE2 may be larger than the size or area of the first pixel electrode AE1. However, in a plan view, the size or area of the second pixel electrode AE2 may be smaller than the size or area of the third pixel electrode AE3.

[0163] The shapes and sizes of the holes OPT1, OPT2 and OPT3 of the first light blocking layer BM1 may also correspond to the shapes and sizes of the pixel electrodes AE1, AE2 and AE3. Figures 4 to 6 The shapes and sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 of the embodiment are different. The holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 may also be substantially quadrilateral. However, as in the above-mentioned embodiment, the sizes of the holes OPT1, OPT2, and OPT3 of the first light blocking layer BM1 provided in the first pixel PX1 may be respectively larger than the sizes of the plurality of holes of the second light blocking layer BM2 provided in the second pixel PX2.

[0164] The light blocking patterns BMP1, BMP2, and BMP3 of the second light blocking layer BM2 may surround the pixel electrodes AE1, AE2, and AE3, respectively, while being spaced apart from the pixel electrodes AE1, AE2, and AE3. As described above, the separation distances between the light blocking patterns BMP1, BMP2, and BMP3 and the pixel electrodes AE1, AE2, and AE3 may vary depending on the sizes of the pixel electrodes AE1, AE2, and AE3.

[0165] In addition, in the display device 10, the widths of the light-blocking patterns BMP1, BMP2, and BMP3 may also vary depending on the sizes of the pixel electrodes AE1, AE2, and AE3. According to an embodiment of the present disclosure, the display device 10 may include pixel electrodes AE (e.g., the second pixel electrode AE2) having different lengths measured in different directions, and the second light-blocking pattern BMP2 surrounding the pixel electrode AE may have different widths depending on the position.

[0166] Figure 17 It shows Figures 14 to 16 FIG. 1 is a diagram showing the relative arrangement of a pixel electrode and a second light blocking layer in a display device. Figure 17 Schematically shows Figures 14 to 16 The sizes of the second pixel electrode AE2 and the second light-blocking pattern BMP2 are shown in FIG.

[0167] Reference Figure 17 , in the display device 10 (see Figure 3 ), the pixel electrode AE (or Figures 14 to 16 The first length WA1 of the second pixel electrode AE2 in the fifth direction DR5 may be greater than that of the pixel electrode AE (or Figures 14 to 16 The second length WA2 of the second pixel electrode AE2 in the light blocking pattern BMP (or Figure 16 The second light blocking pattern BMP2 in the pixel electrode AE may be spaced apart from the pixel electrode AE by a certain distance while surrounding the pixel electrode AE, and the area surrounded by the light blocking pattern BMP may be the opening OPB. Figure 13 To prevent light leakage at high viewing angles, the width of the light-blocking pattern BMP surrounding the pixel electrode AE may increase as the radius of the pixel electrode AE decreases. The light-blocking pattern BMP may have, similar to the pixel electrode AE, one side (also referred to as a first side) extending in the fourth direction DR4 and another side (also referred to as a second side) extending in the fifth direction DR5. The first width WB1 of the one side extending in the fourth direction DR4 may be smaller than the second width WB2 of the other side extending in the fifth direction DR5. A first length WA1 of the pixel electrode AE measured in the fifth direction DR5 may be greater than a second length WA2 of the pixel electrode AE measured in the fourth direction DR4. Furthermore, a first width WB1 of the first side of the light-blocking pattern BMP, located at a location extending along the long side of the pixel electrode AE, may be smaller than a second width WB2 of the second side of the light-blocking pattern BMP, located at a location extending along the short side of the pixel electrode AE. The display device 10 can provide a privacy protection mode for the user by designing the shape and width of the light-blocking pattern BMP in various ways to correspond to the shape and size of the pixel electrode AE.

[0168] Figure 18 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0169] Reference Figure 18 , in the display device 10 according to the embodiment of the present disclosure (see Figure 3 ), the color filters CF1, CF2 and CF3 can be omitted (see Figure 9 ). The display device 10 according to the present embodiment is similar to the display device 10 of the embodiment except that the color filters CF1, CF2 and CF3 are omitted. Figures 7 to 9 The display device 10 of the embodiment is the same.

[0170] Although some exemplary embodiments of the present disclosure have been described above, these exemplary embodiments are examples and do not necessarily limit the present disclosure. In addition, without departing from the features of the present disclosure, those skilled in the art may change and modify the present disclosure in various ways. For example, the components described in the exemplary embodiments of the present disclosure may be modified. Differences associated with these modifications and applications should be interpreted as being within the scope of the present disclosure.

Claims

1. A display device, wherein: The display device includes: a display area, a plurality of pixels being arranged in the display area, each of the plurality of pixels including a plurality of pixel electrodes spaced apart from each other; a first light blocking layer disposed in the display area and comprising a plurality of holes respectively overlapping the plurality of pixel electrodes; a plurality of color filters disposed on the first light blocking layer and corresponding to the plurality of holes, respectively; and a second light blocking layer disposed on the color filter and corresponding to the pixel electrodes of some of the plurality of pixels, wherein the second light blocking layer surrounds the pixel electrodes of the some pixels among the plurality of pixels in a plan view, and The second light blocking layer includes a plurality of light blocking patterns having different widths.

2. The display device according to claim 1, wherein Each of the plurality of pixels includes a first pixel electrode and a second pixel electrode, the second pixel electrode having a radius smaller than that of the first pixel electrode, The second light blocking layer includes a first light blocking pattern corresponding to the first pixel electrode and a second light blocking pattern corresponding to the second pixel electrode, and A separation distance between the first pixel electrode and the first light-blocking pattern is different from a separation distance between the second pixel electrode and the second light-blocking pattern.

3. The display device according to claim 2, wherein: A width of the first light-blocking pattern is smaller than a width of the second light-blocking pattern.

4. The display device according to claim 2, wherein The separation distance between the first pixel electrode and the first light-blocking pattern is smaller than the separation distance between the second pixel electrode and the second light-blocking pattern.

5. The display device according to claim 2, wherein The separation distance between the first pixel electrode and the first light-blocking pattern is in the range of 1 μm to 3 μm, inclusive. The display device according to claim 2 , wherein: A distance between a center of the first pixel electrode and the inner side of the first light-blocking pattern is equal to a distance between a center of the second pixel electrode and the inner side of the second light-blocking pattern.

7. The display device according to claim 2, wherein: A distance between a center of the first pixel electrode and an outer side of the first light-blocking pattern is smaller than a distance between a center of the second pixel electrode and an outer side of the second light-blocking pattern.

8. The display device according to claim 2, wherein: each of the plurality of pixels includes a third pixel electrode having a radius larger than the radius of the first pixel electrode, The second light blocking layer includes a third light blocking pattern corresponding to the third pixel electrode, and A separation distance between the third pixel electrode and the third light-blocking pattern is smaller than a separation distance between the first pixel electrode and the first light-blocking pattern.

9. The display device according to claim 8, wherein A width of the third light-blocking pattern is smaller than a width of the first light-blocking pattern.

10. The display device according to claim 2, wherein: In the first pixel electrode, the length in the first direction is equal to the length in the second direction perpendicular to the first direction, and In the second pixel electrode, a length in the first direction is greater than a length in the second direction. The display device according to claim 10 , wherein: In the second light-blocking pattern, a length in the first direction is greater than a length in the second direction.

12. The display device according to claim 10, wherein: In the second light-blocking pattern, a width of a side extending in the first direction is greater than a width of a side extending in the second direction.

13. The display device according to claim 1, wherein The plurality of pixels comprises: a first pixel, the second light blocking layer not being provided in the first pixel; and A second pixel, in which the plurality of light-blocking patterns respectively correspond to the plurality of pixel electrodes.

14. The display device according to claim 13, wherein: A radius of the hole of the first light blocking layer in the first pixel is greater than a radius of the hole of the first light blocking layer in the second pixel.

15. The display device according to claim 14, wherein A difference between a radius of the pixel electrode in the first pixel and a radius of the hole of the first light blocking layer is greater than a difference between a radius of the pixel electrode in the second pixel and the radius of the hole of the first light blocking layer.

16. A display device, wherein: The display device includes: a substrate, on which a first pixel and a second pixel are arranged, wherein each of the first pixel and the second pixel includes a plurality of pixel electrodes; an encapsulation layer, disposed on the plurality of pixel electrodes; a first light blocking layer disposed on the encapsulation layer and comprising a plurality of holes corresponding to the plurality of pixel electrodes, respectively; a plurality of color filters disposed on the first light blocking layer and corresponding to the plurality of pixel electrodes respectively; a passivation layer disposed on the plurality of color filters and the first light blocking layer; a second light blocking layer disposed on the passivation layer in the second pixel and including a plurality of light blocking patterns forming a plurality of transmissive portions respectively overlapping the plurality of pixel electrodes of the second pixel; and an outer coating layer disposed on the second light blocking layer, wherein the plurality of pixel electrodes include a first pixel electrode and a second pixel electrode, the first pixel electrode being disposed in each of the first pixel and the second pixel, the second pixel electrode being disposed in each of the first pixel and the second pixel and having a radius smaller than that of the first pixel electrode, and The width of the first light-blocking pattern overlapping the first pixel electrode disposed in the second pixel is smaller than the width of the second light-blocking pattern overlapping the second pixel electrode disposed in the second pixel.

17. The display device according to claim 16, wherein: A separation distance between a first side of the first pixel electrode of the second pixel and an outer side of the first light-blocking pattern is smaller than a separation distance between a first side of the second pixel electrode of the second pixel and an outer side of the second light-blocking pattern.

18. The display device according to claim 17, wherein: A separation distance between the first side of the first pixel electrode of the second pixel and an inner side of the first light-blocking pattern is smaller than a separation distance between the first side of the second pixel electrode of the second pixel and an inner side of the second light-blocking pattern.

19. The display device according to claim 16, wherein: The first light blocking layer includes a first hole provided in the first pixel and overlapping with the first pixel electrode, and a second hole provided in the second pixel and overlapping with the first pixel electrode. The radius of the first pixel electrode of the first pixel is equal to the radius of the first pixel electrode of the second pixel, and The radius of the first hole is greater than the radius of the second hole.

20. The display device according to claim 19, wherein The first light blocking layer includes a third hole overlapping the second pixel electrode of the first pixel, and a radius of the first hole is equal to a radius of the third hole.

Images