Display device and method of measuring resistance of display device

Abstract

A display device and a method of measuring resistance of the display device are provided. The display device includes: a substrate including a display area in which a plurality of pixels are positioned and a non-display area in contact with the display area; an external wiring on the substrate in the non-display area; a 1-1 substrate pad on the substrate in the non-display area and connected to the external wiring; a first chip on film attached to one side of the substrate and including a 1-1 output pad connected to the 1-1 substrate pad and a 1-1 input pad connected to the 1-1 output pad through a 1-1 line; and a circuit board attached to one side of the first chip on film and including a 1-1 circuit board pad connected to the 1-1 input pad and a 1-1 test pad connected to the 1-1 circuit board pad through a 1-1 test line.

Description

Technical Field

[0001] Aspects of some embodiments relate to a display device and a method of measuring resistance of a display device. Background Art

[0002] A display device is a device that displays an image for providing visual information to a user. Among display devices, organic light emitting diode display devices have recently attracted attention.

[0003] The display device may include a substrate having a plurality of pixels arranged thereon, a chip-on-film positioned on one side of the substrate, and a circuit board attached to one side of the chip-on-film. The substrate and the chip-on-film may be attached to each other in a bonding region. The resistance of the bonding region may be measured using a test pad included in the circuit board.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0005] Aspects of some embodiments include a display device having relatively improved quality.

[0006] Aspects of some embodiments include a method of measuring resistance of a display device.

[0007] According to some embodiments, the display device includes: a substrate, including a display area and a non-display area contacting the display area, and a plurality of pixels are positioned in the display area; external wiring, on the substrate in the non-display area; a 1-1 substrate pad, on the substrate in the non-display area, and connected to the external wiring; a first film-on-chip, attached to one side of the substrate, and including a 1-1 output pad and a 1-1 input pad, the 1-1 output pad is connected to the 1-1 substrate pad, and the 1-1 input pad is connected to the 1-1 output pad through a 1-1 line; and a circuit board, attached to one side of the first film-on-chip, and including a 1-1 circuit board pad and a 1-1 test pad, the 1-1 circuit board pad is connected to the 1-1 input pad, and the 1-1 test pad is connected to the 1-1 circuit board pad through a 1-1 test line.

[0008] According to some embodiments, the external wiring may be antistatic wiring.

[0009] According to some embodiments, the display device may further include: a 1-2 substrate pad, on the substrate in a non-display area, and adjacent to the 1-1 substrate pad; a 1-2 output pad, included in the first chip on film, connected to the 1-2 substrate pad, and adjacent to the 1-1 output pad; a 1-2 input pad, included in the first chip on film, connected to the 1-2 output pad through a 1-2 line, and adjacent to the 1-1 input pad; a 1-2 circuit board pad, included in the circuit board, connected to the 1-2 input pad, and adjacent to the 1-1 circuit board pad; and a 1-2 test pad, included in the circuit board, connected to the 1-2 circuit board pad through a 1-2 test line, and adjacent to the 1-1 test pad.

[0010] According to some embodiments, the display device may further include: a 1-3 input pad included in the first chip-on-film and adjacent to the 1-2 input pad.

[0011] According to some embodiments, the 1-3 input pad may be connected to the 1-2 line via the 1-3 line.

[0012] According to some embodiments, the display device may further include: a 1-3 substrate pad, on the substrate in a non-display area, and adjacent to the 1-2 substrate pad; a 1-3 output pad, included in the first chip on the film, connected to the 1-3 substrate pad, and adjacent to the 1-2 output pad; a 1-3 circuit board pad, included in the circuit board, connected to the 1-3 input pad, and adjacent to the 1-2 circuit board pad; and a 1-3 test pad, included in the circuit board, connected to the 1-3 circuit board pad via a 1-3 test line, and adjacent to the 1-2 test pad.

[0013] According to some embodiments, the display device may further include: 1-4 substrate pads, on the substrate in the non-display area, and adjacent to the 1-3 substrate pads; 1-4 output pads, included in the first film-on-chip, connected to the 1-4 substrate pads, and adjacent to the 1-3 output pads; 1-4 input pads, included in the first film-on-chip, connected to the 1-4 output pads through 1-4 lines, and adjacent to the 1-3 input pads; 1-4 circuit board pads, included in the circuit board, connected to the 1-4 input pads, and adjacent to the 1-3 circuit board pads; and 1-4 test pads, included in the circuit board, connected to the 1-4 circuit board pads through 1-4 test lines, and adjacent to the 1-3 test pads.

[0014] According to some embodiments, the 1-2 base pad and the 1-4 base pad may be connected to each other through a 1-1 bridge line.

[0015] According to some embodiments, external wiring may be connected to the 1-1 bridge wire.

[0016] According to some embodiments, in a method of measuring the resistance of a display device, the method includes: connecting a first output pad included in a chip on film to a first substrate pad in a non-display area of a substrate; connecting a first input pad included in the chip on film to a first circuit board pad included in a circuit board; and connecting a first terminal of an ammeter to a first test pad included in the circuit board.

[0017] According to some embodiments, the first substrate pad may be connected to an external wiring.

[0018] According to some embodiments, the first input pad may be connected to the first output pad through a first line.

[0019] According to some embodiments, the first test pad may be connected to the first circuit board pad via a first test line.

[0020] According to some embodiments, the method may further include: connecting a second output pad included in the chip on film to a second substrate pad in a non-display area of the substrate; connecting a second input pad connected to the second output pad through a second line to a second circuit board pad included in the circuit board; connecting a second terminal of the ammeter to a second test pad included in the circuit board and connected to the second circuit board pad through a second test line; connecting a first terminal of the voltmeter to a third test pad included in the circuit board; and connecting a second terminal of the voltmeter to a fourth test pad included in the circuit board.

[0021] According to some embodiments, the second base pad may be adjacent to the first base pad.

[0022] According to some embodiments, the second circuit board pad may be adjacent to the first circuit board pad.

[0023] According to some embodiments, the second test line may be adjacent to the first test line.

[0024] According to some embodiments, the third test pad may be adjacent to the second test pad.

[0025] According to some embodiments, the fourth test pad may be adjacent to the third test pad.

[0026] According to some embodiments, a display device may include: a substrate, including a display area and a non-display area contacting the display area, a plurality of pixels being positioned in the display area; external wiring on the substrate in the non-display area; a 1-1 substrate pad on the substrate in the non-display area and connected to the external wiring; a first film-on-chip, attached to one side of the substrate, and including a 1-1 output pad and a 1-1 input pad, the 1-1 output pad being connected to the 1-1 substrate pad, and the 1-1 input pad being connected to the 1-1 output pad through a 1-1 line; and a circuit board, attached to one side of the first film-on-chip, and including a 1-1 circuit board pad and a 1-1 test pad, the 1-1 circuit board pad being connected to the 1-1 input pad, and the 1-1 test pad being connected to the 1-1 circuit board pad through a 1-1 test line.

[0027] Therefore, the number of substrate pads, the number of input pads, the number of output pads, and the number of circuit board pads can each be relatively reduced. Consequently, the width of the substrate pads, the width of the input pads, the width of the output pads, and the width of the circuit board pads can each be relatively increased. Furthermore, sufficient space can be secured between the substrate, the chip-on-film, and the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view illustrating a display device according to some embodiments.

[0030] Figure 2 It is shown that the Figure 1 A circuit diagram of a pixel in a display device.

[0031] Figure 3 It is shown that the Figure 1 A cross-sectional view of a pixel in a display device.

[0032] Figure 4 It is shown that the Figure 3 A plan view of a substrate, multiple chip-on-film (COMs), and a circuit board in a display device.

[0033] Figure 5 yes Figure 4 An enlarged plan view of portion A.

[0034] Figure 6 yes Figure 4 An enlarged plan view of portion B.

[0035] Figure 7 It shows Figure 1 A plan view of a display device.

[0036] Figure 8 yes Figure 7An enlarged plan view of section X.

[0037] Figure 9 yes Figure 7 An enlarged plan view of portion Y. DETAILED DESCRIPTION

[0038] Hereinafter, a display device according to some embodiments will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and some redundant descriptions of the same components may be omitted.

[0039] Figure 1 is a plan view illustrating a display device according to some embodiments.

[0040] Reference Figure 1 , a display device DD according to some embodiments may include a substrate 10 , a plurality of chip-on-films (C2Fs), and a circuit board PCB.

[0041] The substrate 10 may include a display area DA and a non-display area NDA. The display area DA may be defined as an area that emits light. The non-display area NDA may be defined as an area in which components for transmitting signals to the display area DA are located. According to some embodiments, the non-display area NDA may be located in the periphery of the display area DA (e.g., outside the footprint of the display area DA).

[0042] A plurality of pixels PX may be positioned in the display area DA. For example, the pixels PX may be positioned in the display area DA. Each of the plurality of pixels PX may emit light based on a signal applied from the non-display area NDA. For example, the plurality of pixels PX may be repeatedly arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Thus, the display area DA may emit light throughout the entire area and display an image.

[0043] The non-display area NDA may contact the display area DA. For example, the non-display area NDA may be arranged around the display area DA. For example, the non-display area NDA may surround at least a portion of the display area DA.

[0044] The non-display area NDA may include a driver for driving the plurality of pixels PX. For example, the non-display area NDA may include a gate driver, a light emitting driver, a power voltage generator, a timing controller, and the like.

[0045] According to some embodiments, the anti-static wiring ESD may be positioned in the non-display area NDA. For example, the anti-static wiring ESD may be arranged to surround at least a portion of the display area DA.

[0046] The anti-static wiring ESD may protect the display area DA from static electricity introduced from the outside. For example, the anti-static wiring ESD may protect the display area DA from static electricity applied to the display area DA when the display device DD is driven. Figure 2 For example, the anti-static wiring ESD can protect the first transistor (eg, Figure 2 The first transistor TR1 is protected from static electricity introduced from the data line.

[0047] According to some embodiments, the anti-static wiring ESD may include an anti-static transistor. The anti-static transistor may receive a gate voltage from a power line and a signal line, etc. For example, a first power voltage (eg, Figure 2 The first power voltage ELVSS) may be applied to the anti-static transistor, but the embodiments of the present disclosure are not limited thereto. For example, the anti-static wiring ESD may be referred to as an external wiring.

[0048] A plurality of chips on film may be attached to one side of the substrate 10. For example, the plurality of chips on film may be positioned on one side of the non-display area NDA of the substrate 10. For example, the plurality of chips on film may be spaced apart from the display area DA in the second direction DR2.

[0049] The plurality of film chips may include a first film chip COF1, a second film chip COF2 and an nth film chip COFn. The first film chip COF1 may be connected to one end of the antistatic wiring ESD. The second film chip COF2 may be connected to the other end of the antistatic wiring ESD. The nth film chip COFn may be positioned between the first film chip COF1 and the second film chip COF2. For example, the nth film chip COFn may be spaced apart from the first film chip COF1 in the first direction DR1. For example, the second film chip COF2 may be spaced apart from the nth film chip COFn in the first direction DR1.

[0050] In this specification, when it is mentioned that a component is “connected” to another component, it means that the component can be electrically connected to another component.

[0051] According to some embodiments, the number of the plurality of film chips may be 12. However, embodiments of the present disclosure are not limited thereto, and the number of the plurality of film chips may vary. For example, the number of the plurality of film chips may be equal to or greater than 1 and equal to or less than 11. For example, the number of the plurality of film chips may be equal to or greater than 13.

[0052] For example, each of the plurality of film chips may include a flexible material. For example, each of the plurality of film chips may include polyethylene terephthalate ("PET") or polyimide ("PI"), etc. These materials may be used alone or in combination with each other. However, the embodiments of the present disclosure are not limited thereto, and each of the plurality of film chips may include a different type of material.

[0053] The driver chips can be positioned on multiple chip-on-film (COF) chips. For example, a first driver chip IC1 can be positioned on a first chip-on-film (COF) chip. Furthermore, a second driver chip IC2 can be positioned on a second chip-on-film (COF) chip. Furthermore, an nth driver chip ICn can be positioned on an nth chip-on-film (COF) chip. Each of the first driver chip IC1, the second driver chip IC2, and the nth driver chip ICn can convert a digital data signal among the drive signals into an analog data signal. Furthermore, each of the first driver chip IC1, the second driver chip IC2, and the nth driver chip ICn can provide the analog data signal to a plurality of pixels PX.

[0054] For example, the first driver chip IC1 can provide analog data signals to multiple pixels PX via signal lines located on the first chip-on-film COF1. Furthermore, the second driver chip IC2 can provide analog data signals to multiple pixels PX via signal lines located on the second chip-on-film COF2. Furthermore, the nth driver chip ICn can provide analog data signals to multiple pixels PX via signal lines located on the nth chip-on-film COFn.

[0055] The circuit board PCB can be attached to one side of the plurality of chip-on-film chips. For example, the circuit board PCB can be attached to one side of the first chip-on-film COF1, the second chip-on-film COF2, and the nth chip-on-film COFn. For example, the circuit board PCB can be spaced apart from the substrate 10 in the second direction DR2. The circuit board PCB can apply driving signals and driving voltages to the first driver chip IC1, the second driver chip IC2, the nth driver chip ICn, and the plurality of pixels PX.

[0056] According to some embodiments, the number of circuit boards PCB may be one. However, embodiments of the present disclosure are not limited thereto, and the number of circuit boards PCB may vary. For example, the number of circuit boards PCB may be two. For example, the number of circuit boards PCB may be equal to or greater than three.

[0057] In this specification, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. For example, the second direction DR2 may be perpendicular to the first direction DR1. However, embodiments according to the present disclosure are not limited thereto, and the second direction DR2 may form an acute angle or an obtuse angle with the first direction DR1. In addition, a third direction DR3 intersecting (e.g., perpendicular to) a plane formed by the first direction DR1 and the second direction DR2 may be defined. For example, the third direction DR3 may be perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, embodiments according to the present disclosure are not limited thereto, and the third direction DR3 may form an acute angle or an obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.

[0058] Figure 2 It is shown that the Figure 1 A circuit diagram of a pixel in a display device.

[0059] Reference Figure 2 , the pixel PX may include a pixel circuit PXC and a light emitting element EE. The pixel circuit PXC may include a first transistor TR1, a second transistor TR2 and a capacitor CST. Figure 2 Various components in the pixel PX are shown, but embodiments according to the present disclosure are not limited thereto, and according to some embodiments, the pixel PX may include additional components without departing from the spirit and scope of embodiments according to the present disclosure.

[0060] The first transistor TR1 may apply a driving current to the light-emitting element EE. The first transistor TR1 may include a first electrode, a second electrode, and a gate electrode. The second power voltage ELVDD may be applied to the first electrode of the first transistor TR1. The gate electrode of the first transistor TR1 may be connected to the first node N1. The second electrode of the first transistor TR1 may be connected to the light-emitting element EE. In other words, the first transistor TR1 may be a driving transistor.

[0061] The second transistor TR2 may include a first electrode, a second electrode, and a gate electrode. A data voltage DT may be applied to the first electrode of the second transistor TR2. A gate signal GS may be applied to the gate electrode of the second transistor TR2. The second electrode of the second transistor TR2 may be connected to the first node N1. That is, the second transistor TR2 may be a switching transistor.

[0062] The capacitor CST may include a first electrode and a second electrode. The second power voltage ELVDD may be applied to the first electrode of the capacitor CST. The second electrode of the capacitor CST may be connected to the first node N1. The capacitor CST may maintain the voltage level of the gate electrode of the first transistor TR1 during the inactive period of the gate signal GS.

[0063] The light emitting element EE may include a first electrode and a second electrode. The first electrode of the light emitting element EE may be connected to the second electrode of the first transistor TR1. The first power voltage ELVSS may be applied to the second electrode of the light emitting element EE.

[0064] According to some embodiments, the pixel circuit PXC may include two transistors and one capacitor. For example, the pixel circuit PXC may include a first transistor TR1, a second transistor TR2, and a capacitor CST. However, the embodiments of the present disclosure are not limited thereto, and the pixel circuit PXC may include three or more transistors and two or more capacitors.

[0065] Figure 3 It is shown that the Figure 1 A cross-sectional view of a pixel in a display device.

[0066] Reference Figure 3 The pixel PX may include a substrate 10, a lower metal layer BML, a buffer layer BUF, a gate insulating layer GI, an interlayer insulating layer ILD, a via insulating layer VIA, an active layer ACT, a source electrode SE, a gate electrode GE, a drain electrode DE, a pixel electrode PE, a pixel defining layer PDL, a light emitting layer EML, a common electrode CE and an encapsulation layer TFE.

[0067] The transistor TR may include an active layer ACT, a source electrode SE, a gate electrode GE, and a drain electrode DE. For example, Figure 3 The transistor TR can have Figure 2 The first transistor TR1 has the same (or substantially the same) configuration.

[0068] The substrate 10 may include a transparent material or an opaque material. The substrate 10 may be formed of a transparent resin substrate. Examples of transparent resin substrates may include polyimide substrates. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, and a second organic layer.

[0069] Alternatively, the substrate 10 may include a quartz substrate (eg, a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, or an alkali-free glass substrate, etc. These materials may be used alone or in combination with each other.

[0070] The lower metal layer BML may be positioned on the substrate 10. For example, the lower metal layer BML may at least partially overlap the gate electrode GE in a plan view. For example, the lower metal layer BML may at least partially overlap the active layer ACT in a plan view.

[0071] For example, the lower metal layer BML may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. Examples of metals may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), or scandium ("Sc"), etc. These materials may be used alone or in combination with one another. Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide, etc. These materials may be used alone or in combination with one another. In addition, examples of metal nitrides may include aluminum nitride ("AlN"). x ”), tungsten nitride (“WN x ”) or chromium nitride (“CrN x ”), etc. These materials can be used alone or in combination with each other.

[0072] The buffer layer BUF may be positioned on the substrate 10. The buffer layer BUF may prevent or reduce contaminants such as metal atoms or other impurities from diffusing from the substrate 10 to the transistor TR. In addition, when the surface of the substrate 10 is uneven, the buffer layer BUF may improve the flatness of the surface of the substrate 10.

[0073] For example, the buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other.

[0074] The active layer ACT may be positioned on the buffer layer BUF. The active layer ACT may include an inorganic semiconductor (e.g., amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor) or an organic semiconductor. These materials may be used alone or in combination. The active layer ACT may include a source region, a drain region, and a channel region positioned between the source and drain regions.

[0075] The metal oxide semiconductor may include a binary compound ("AB x ”), ternary compounds (“AB x C y ”) or a quaternary compound (“AB x C y D z ”), etc. These materials can be used alone or in combination with each other.

[0076] For example, the metal oxide semiconductor may include zinc oxide ("ZnO x ”), gallium oxide (“GaO x ”), tin oxide (“SnOx ”), indium oxide (“InO x ”), indium gallium oxide (“IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), indium zinc tin oxide (“IZTO”), and indium gallium zinc oxide (“IGZO”). These materials can be used alone or in combination with each other.

[0077] The gate insulating layer GI may be positioned on the buffer layer BUF. The gate insulating layer GI may fully cover the active layer ACT. For example, the gate insulating layer GI may cover the active layer ACT and may be arranged along the contour of the active layer ACT.

[0078] For example, the gate insulating layer GI may include silicon oxide ("SiO x ”), silicon nitride (“SiN x ”), Silicon Carbide (“SiC x ”), silicon oxynitride (“SiO x N y ”) or silicon oxycarbide (“SiO x C y ”) and the like. These materials may be used alone or in combination with each other.

[0079] The gate electrode GE may be positioned on the gate insulating layer GI. The gate electrode GE may overlap the channel region of the active layer ACT in a plan view.

[0080] The gate electrode GE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. Examples of the metal may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), or scandium ("Sc"), etc. These materials may be used alone or in combination with each other.

[0081] Examples of conductive metal oxides may include indium tin oxide or indium zinc oxide, etc. In addition, examples of metal nitrides may include aluminum nitride ("AlN x ”), tungsten nitride (“WN x ”) or chromium nitride (“CrN x ”), etc. These materials can be used alone or in combination with each other.

[0082] The interlayer insulating layer ILD may be positioned on the gate insulating layer GI. The interlayer insulating layer ILD may sufficiently cover the gate electrode GE. For example, the interlayer insulating layer ILD may cover the gate electrode GE and may be arranged along the outline of the gate electrode GE.

[0083] For example, the interlayer insulating layer ILD may include an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. These materials may be used alone or in combination with each other.

[0084] The source electrode SE may be positioned on the interlayer insulating layer ILD. The source electrode SE may be connected to the source region of the active layer ACT through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0085] The drain electrode DE may be positioned on the interlayer insulating layer ILD and may be connected to a drain region of the active layer ACT through a contact hole penetrating the gate insulating layer GI and the interlayer insulating layer ILD.

[0086] For example, the source electrode SE may include metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc. These materials may be used alone or in combination with each other. The drain electrode DE and the source electrode SE may be formed by the same process and may include the same material.

[0087] The via insulating layer VIA may be positioned on the interlayer insulating layer ILD. The via insulating layer VIA may sufficiently cover the source electrode SE and the drain electrode DE. The via insulating layer VIA may include an organic material. For example, the via insulating layer VIA may include an organic material such as a phenolic resin, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. These materials may be used alone or in combination.

[0088] The pixel electrode PE may be positioned on the via insulating layer VIA and connected to the drain electrode DE through a contact hole penetrating the via insulating layer VIA.

[0089] The pixel electrode PE may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials may be used alone or in combination. According to some embodiments, the pixel electrode PE may have a stacked structure including ITO / Ag / ITO. For example, the pixel electrode PE may operate as an anode.

[0090] The pixel defining layer PDL may be positioned on the via insulating layer VIA. The pixel defining layer PDL may cover the side of the pixel electrode PE. In addition, an opening exposing a portion of the upper surface of the pixel electrode PE may be defined in the pixel defining layer PDL.

[0091] For example, the pixel defining layer (PDL) may include an inorganic material or an organic material. According to some embodiments, the pixel defining layer (PDL) may include an organic material such as an epoxy resin or a silicone resin. These materials may be used alone or in combination. According to some embodiments, the pixel defining layer (PDL) may also include a light-blocking material including a black pigment or a black dye.

[0092] The light-emitting layer (EML) may be positioned on the pixel electrode PE. The light-emitting layer (EML) may include an organic material that emits light of a color (e.g., a set color or a predetermined color). For example, the light-emitting layer (EML) may include an organic material that emits red light. However, embodiments of the present disclosure are not limited thereto, and the light-emitting layer (EML) may emit light of a color other than red.

[0093] The common electrode CE can be positioned on the light-emitting layer EML and the pixel-defining layer PDL. The common electrode CE can include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. These materials can be used alone or in combination. The common electrode CE can operate as a cathode.

[0094] The encapsulation layer TFE may be positioned on the common electrode CE. The encapsulation layer TFE may prevent or reduce the penetration of pollutants, impurities, and / or moisture from the outside into the pixel electrode PE, the light-emitting layer EML, and the common electrode CE. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer.

[0095] For example, the inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic layer may include a cured product of a polymer such as polyacrylate.

[0096] Although reference has been Figure 3 The pixel PX according to some embodiments is described, but the pixel PX is not limited to Figure 3 That is, the pixel PX may include all structures that receive an electrical signal and emit light having a brightness corresponding to the intensity of the electrical signal.

[0097] Figure 4 It is shown that the Figure 3 A plan view of a substrate, multiple chip-on-film (COMs), and a circuit board in a display device. Figure 5 yes Figure 4 An enlarged plan view of portion A. Figure 6 yes Figure 4 An enlarged plan view of part B. For example, Figure 4 is a plan view showing a case where a substrate is not bonded to a plurality of chips on film and a plurality of chips on film are not bonded to a circuit board.

[0098] Reference Figure 4A plurality of substrate pads (also referred to as "pads" or "solder pads") 100 may be positioned on the substrate 10. For example, the plurality of substrate pads 100 may be positioned in the non-display area NDA. For example, the plurality of substrate pads 100 may be positioned on one side of the non-display area NDA. The plurality of substrate pads 100 may be repeatedly arranged along the first direction DR1.

[0099] The first chip on film COF1 may include a plurality of first output pads 210 and a plurality of first input pads 310. For example, the plurality of first output pads 210 may be positioned on one side of the first chip on film COF1. The plurality of first output pads 210 may be repeatedly arranged along the first direction DR1.

[0100] For example, the plurality of first input pads 310 may be positioned on the other side of the first chip-on-film COF1. For example, the plurality of first input pads 310 may be spaced apart from the plurality of first output pads 210, with the first driver chip IC1 positioned between the first input pads 310 and the first output pads 210. In other words, the plurality of first input pads 310 may be spaced apart from the plurality of first output pads 210 in the second direction DR2. The plurality of first input pads 310 may be repeatedly arranged along the first direction DR1.

[0101] The second chip on film COF2 may include a plurality of second output pads 220 and a plurality of second input pads 320. For example, the plurality of second output pads 220 may be positioned on one side of the second chip on film COF2. The plurality of second output pads 220 may be repeatedly arranged along the first direction DR1.

[0102] For example, the plurality of second input pads 320 may be positioned on the other side of the second chip-on-film COF2. For example, the plurality of second input pads 320 may be spaced apart from the plurality of second output pads 220, with the second driver chip IC2 positioned between the second input pads 320 and the second output pads 220. In other words, the plurality of second input pads 320 may be spaced apart from the plurality of second output pads 220 in the second direction DR2. The plurality of second input pads 320 may be repeatedly arranged along the first direction DR1.

[0103] The nth chip-on-film COFn may include a plurality of third output pads 230 and a plurality of third input pads 330. For example, the plurality of third output pads 230 may be positioned on one side of the nth chip-on-film COFn. The plurality of third output pads 230 may be repeatedly arranged along the first direction DR1.

[0104] For example, the plurality of third input pads 330 may be positioned on the other side of the nth chip-on-film COFn. For example, the plurality of third input pads 330 may be spaced apart from the plurality of third output pads 230, with the nth driver chip ICn positioned between the third input pads 330 and the third output pads 230. In other words, the plurality of third input pads 330 may be spaced apart from the plurality of third output pads 230 in the second direction DR2. The plurality of third input pads 330 may be repeatedly arranged along the first direction DR1.

[0105] The circuit board PCB may include a plurality of circuit board pads 400. For example, the plurality of circuit board pads 400 may be positioned on one side of the circuit board PCB. The plurality of circuit board pads 400 may be repeatedly arranged along the first direction DR1.

[0106] According to some embodiments, the circuit board PCB may further include a plurality of test pads, for example, a first test pad 510 , a second test pad 520 , a third test pad 530 , a fourth test pad 540 , a fifth test pad 550 , and a sixth test pad 560 .

[0107] The second test pad 520 may be spaced apart from the first test pad 510 in the first direction DR1. The fourth test pad 540 may be spaced apart from the third test pad 530 in the first direction DR1. The sixth test pad 560 may be spaced apart from the fifth test pad 550 in the first direction DR1.

[0108] Further references Figure 5 For example, the plurality of first base pads 110 may include a 1-1 base pad PP1-1, a 1-2 base pad PP1-2, a 1-3 base pad PP1-3, a 1-4 base pad PP1-4, a 1-5 base pad PP1-5, a 1-6 base pad PP1-6, a 1-7 base pad PP1-7, a 1-8 base pad PP1-8, a 1-9 base pad PP1-9, a 1-10 base pad PP1-10, a 1-11 base pad PP1-11 and a 1-12 base pad PP1-12.

[0109] The 1-2 base pad PP1-2 may be adjacent to the 1-1 base pad PP1-1 in the first direction DR1. The 1-3 base pad PP1-3 may be adjacent to the 1-2 base pad PP1-2 in the first direction DR1. The 1-4 base pad PP1-4 may be adjacent to the 1-3 base pad PP1-3 in the first direction DR1. The 1-5 base pad PP1-5 may be adjacent to the 1-4 base pad PP1-4 in the first direction DR1. The 1-6 base pad PP1-6 may be adjacent to the 1-5 base pad PP1-5 in the first direction DR1.

[0110] The 1-7 base pad PP1-7 may be adjacent to the 1-8 base pad PP1-8 in a direction opposite to the first direction DR1. The 1-8 base pad PP1-8 may be adjacent to the 1-9 base pad PP1-9 in a direction opposite to the first direction DR1. The 1-9 base pad PP1-9 may be adjacent to the 1-10 base pad PP1-10 in a direction opposite to the first direction DR1. The 1-10 base pad PP1-10 may be adjacent to the 1-11 base pad PP1-11 in a direction opposite to the first direction DR1. The 1-11 base pad PP1-11 may be adjacent to the 1-12 base pad PP1-12 in a direction opposite to the first direction DR1.

[0111] According to some embodiments, the 1-1 substrate pad PP1-1 may be connected to the anti-static wiring ESD. For example, the 1-1 substrate pad PP1-1 may be connected to one end of the anti-static wiring ESD.

[0112] According to some embodiments, the 1-2 substrate pad PP1-2 and the 1-4 substrate pad PP1-4 may be connected to each other through the 1-1 bridge line BR1-1. For example, the 1-2 substrate pad PP1-2 may be connected to the 1-1 bridge line BR1-1, and the 1-4 substrate pad PP1-4 may be connected to the 1-1 bridge line BR1-1.

[0113] According to some embodiments, the 1-1 bridge line BR1-1 may be positioned on the same layer as the 1-2 substrate pad PP1-2 and the 1-4 substrate pad PP1-4. For example, the 1-2 substrate pad PP1-2 and the 1-4 substrate pad PP1-4 may be positioned on the same layer as the source electrode (eg, Figure 3 The source electrode SE) is positioned on the same layer, and the 1-1 bridge wire BR1-1 may also be positioned on the same layer as the source electrode.

[0114] However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the 1-1 bridge line BR1-1 may be positioned at a different layer from the 1-2 substrate pad PP1-2 and the 1-4 substrate pad PP1-4. In this case, the 1-1 bridge line BR1-1 may be connected to the 1-2 substrate pad PP1-2 through a first contact hole, and may be connected to the 1-4 substrate pad PP1-4 through a second contact hole.

[0115] According to some embodiments, the 1-1 bridge wire BR1-1 may be connected to the anti-static wiring ESD. According to some embodiments, the 1-1 bridge wire BR1-1 may be positioned on a different layer from the anti-static wiring ESD. For example, the anti-static wiring ESD may be positioned on a lower metal layer (e.g., Figure 3 The lower metal layer BML) is positioned at the same layer, and the 1-1 bridge line BR1-1 can be positioned at the same layer as the source electrode. In this case, the 1-1 bridge line BR1-1 can be connected to the anti-static wiring ESD through the third contact hole.

[0116] However, embodiments according to the present disclosure are not limited thereto, and according to some embodiments, the 1-1 bridge wire BR1 - 1 and the anti-static wiring ESD may be positioned on the same layer.

[0117] According to some embodiments, the 1-9 substrate pad PP1-9, the 1-11 substrate pad PP1-11, and the 1-12 substrate pad PP1-12 may be connected to each other via the 1-2 bridge line BR1-2. For example, the 1-9 substrate pad PP1-9 may be connected to the 1-2 bridge line BR1-2, the 1-11 substrate pad PP1-11 may be connected to the 1-2 bridge line BR1-2, and the 1-12 substrate pad PP1-12 may be connected to the 1-2 bridge line BR1-2.

[0118] According to some embodiments, the 1-2 bridging wire BR1-2 may be positioned on the same layer as the 1-9 substrate pad PP1-9, the 1-11 substrate pad PP1-11, and the 1-12 substrate pad PP1-12. For example, the 1-9 substrate pad PP1-9, the 1-11 substrate pad PP1-11, and the 1-12 substrate pad PP1-12 may be positioned on the same layer as the source electrode, and the 1-2 bridging wire BR1-2 may also be positioned on the same layer as the source electrode.

[0119] However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the 1-2 bridging wire BR1-2 may be positioned at a different layer from the 1-9 substrate pad PP1-9, the 1-11 substrate pad PP1-11, and the 1-12 substrate pad PP1-12. In this case, the 1-2 bridging wire BR1-2 may be connected to the 1-9 substrate pad PP1-9 via the fourth contact hole, may be connected to the 1-11 substrate pad PP1-11 via the fifth contact hole, and may be connected to the 1-12 substrate pad PP1-12 via the sixth contact hole.

[0120] For example, the plurality of first output pads 210 may include a 1-1 output pad OP1-1, a 1-2 output pad OP1-2, a 1-3 output pad OP1-3, a 1-4 output pad OP1-4, a 1-5 output pad OP1-5, a 1-6 output pad OP1-6, a 1-7 output pad OP1-7, a 1-8 output pad OP1-8, a 1-9 output pad OP1-9, a 1-10 output pad OP1-10, a 1-11 output pad OP1-11, and a 1-12 output pad OP1-12.

[0121] The 1-2 output pad OP1-2 may be adjacent to the 1-1 output pad OP1-1 in the first direction DR1. The 1-3 output pad OP1-3 may be adjacent to the 1-2 output pad OP1-2 in the first direction DR1. The 1-4 output pad OP1-4 may be adjacent to the 1-3 output pad OP1-3 in the first direction DR1. The 1-5 output pad OP1-5 may be adjacent to the 1-4 output pad OP1-4 in the first direction DR1. The 1-6 output pad OP1-6 may be adjacent to the 1-5 output pad OP1-5 in the first direction DR1.

[0122] The 1-7 output pad OP1-7 may be adjacent to the 1-8 output pad OP1-8 in a direction opposite to the first direction DR1. The 1-8 output pad OP1-8 may be adjacent to the 1-9 output pad OP1-9 in a direction opposite to the first direction DR1. The 1-9 output pad OP1-9 may be adjacent to the 1-10 output pad OP1-10 in a direction opposite to the first direction DR1. The 1-10 output pad OP1-10 may be adjacent to the 1-11 output pad OP1-11 in a direction opposite to the first direction DR1. The 1-11 output pad OP1-11 may be adjacent to the 1-12 output pad OP1-12 in a direction opposite to the first direction DR1.

[0123] For example, the plurality of first input pads 310 may include a 1-1 input pad IP1-1, a 1-2 input pad IP1-2, a 1-3 input pad IP1-3, a 1-4 input pad IP1-4, a 1-5 input pad IP1-5, a 1-6 input pad IP1-6, a 1-7 input pad IP1-7, a 1-8 input pad IP1-8, a 1-9 input pad IP1-9, a 1-10 input pad IP1-10, a 1-11 input pad IP1-11, and a 1-12 input pad IP1-12.

[0124] The 1-2 input pad IP1-2 may be adjacent to the 1-1 input pad IP1-1 in the first direction DR1. The 1-3 input pad IP1-3 may be adjacent to the 1-2 input pad IP1-2 in the first direction DR1. The 1-4 input pad IP1-4 may be adjacent to the 1-3 input pad IP1-3 in the first direction DR1. The 1-5 input pad IP1-5 may be adjacent to the 1-4 input pad IP1-4 in the first direction DR1. The 1-6 input pad IP1-6 may be adjacent to the 1-5 input pad IP1-5 in the first direction DR1.

[0125] The 1-7 input pad IP1-7 may be adjacent to the 1-8 input pad IP1-8 in a direction opposite to the first direction DR1. The 1-8 input pad IP1-8 may be adjacent to the 1-9 input pad IP1-9 in a direction opposite to the first direction DR1. The 1-9 input pad IP1-9 may be adjacent to the 1-10 input pad IP1-10 in a direction opposite to the first direction DR1. The 1-10 input pad IP1-10 may be adjacent to the 1-11 input pad IP1-11 in a direction opposite to the first direction DR1. The 1-11 input pad IP1-11 may be adjacent to the 1-12 input pad IP1-12 in a direction opposite to the first direction DR1.

[0126] The 1-6 output pad OP1-6, the 1-7 output pad OP1-7, the 1-6 input pad IP1-6, and the 1-7 input pad IP1-7 may be connected to the first driving chip IC1.

[0127] The 1-1 output pad OP1-1 and the 1-1 input pad IP1-1 may be connected to each other through an 1-1 line L1-1. For example, the 1-1 line L1-1 may extend in the second direction DR2.

[0128] The 1-2 output pad OP1-2 and the 1-2 input pad IP1-2 may be connected to each other through a 1-2 line L1-2. For example, the 1-2 line L1-2 may extend in the second direction DR2.

[0129] The 1-3 input pad IP1-3 can be connected to the 1-3 line L1-3. In addition, the 1-3 line L1-3 can be connected to the 1-2 line L1-2. That is, the 1-3 input pad IP1-3 can be connected to the 1-2 line L1-2 through the 1-3 line L1-3. For example, the 1-3 line L1-3 may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2.

[0130] The 1-4 output pads OP1-4 and the 1-4 input pads IP1-4 may be connected to each other through 1-4 lines L1-4. For example, the 1-4 lines L1-4 may extend in the second direction DR2.

[0131] The 1-9 output pad OP1-9 and the 1-9 input pad IP1-9 may be connected to each other through a 1-5 line L1-5. For example, the 1-5 line L1-5 may extend in the second direction DR2.

[0132] The 1-10 input pad IP1-10 can be connected to the 1-6 line L1-6. In addition, the 1-6 line L1-6 can be connected to the 1-7 line L1-7. That is, the 1-10 input pad IP1-10 can be connected to the 1-7 line L1-7 through the 1-6 line L1-6. For example, the 1-6 line L1-6 may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2.

[0133] The 1-11 output pad OP1-11 and the 1-11 input pad IP1-11 may be connected to the 1-7 line L1-7. For example, the 1-7 line L1-7 may extend in the second direction DR2.

[0134] The 1-12 output pads OP1-12 and the 1-12 input pads IP1-12 may be connected by an 1-8 line L1-8. For example, the 1-8 line L1-8 may extend in the second direction DR2.

[0135] For example, the plurality of first circuit board pads 410 may include a 1-1 circuit board pad FP1-1, a 1-2 circuit board pad FP1-2, a 1-3 circuit board pad FP1-3, a 1-4 circuit board pad FP1-4, a 1-5 circuit board pad FP1-5, a 1-6 circuit board pad FP1-6, a 1-7 circuit board pad FP1-7, a 1-8 circuit board pad FP1-8, a 1-9 circuit board pad FP1-9, a 1-10 circuit board pad FP1-10, a 1-11 circuit board pad FP1-11, and a 1-12 circuit board pad FP1-12.

[0136] The 1-2 circuit board pad FP1-2 may be adjacent to the 1-1 circuit board pad FP1-1 in the first direction DR1. The 1-3 circuit board pad FP1-3 may be adjacent to the 1-2 circuit board pad FP1-2 in the first direction DR1. The 1-4 circuit board pad FP1-4 may be adjacent to the 1-3 circuit board pad FP1-3 in the first direction DR1. The 1-5 circuit board pad FP1-5 may be adjacent to the 1-4 circuit board pad FP1-4 in the first direction DR1. The 1-6 circuit board pad FP1-6 may be adjacent to the 1-5 circuit board pad FP1-5 in the first direction DR1.

[0137] The 1-7 circuit board pad FP1-7 may be adjacent to the 1-8 circuit board pad FP1-8 in a direction opposite to the first direction DR1. The 1-8 circuit board pad FP1-8 may be adjacent to the 1-9 circuit board pad FP1-9 in a direction opposite to the first direction DR1. The 1-9 circuit board pad FP1-9 may be adjacent to the 1-10 circuit board pad FP1-10 in a direction opposite to the first direction DR1. The 1-10 circuit board pad FP1-10 may be adjacent to the 1-11 circuit board pad FP1-11 in a direction opposite to the first direction DR1. The 1-11 circuit board pad FP1-11 may be adjacent to the 1-12 circuit board pad FP1-12 in a direction opposite to the first direction DR1.

[0138] Reference Figure 4 , for example, the first test pads 510 may include a 1-1 test pad TP1-1, a 1-2 test pad TP1-2, a 1-3 test pad TP1-3, and a 1-4 test pad TP1-4.

[0139] For example, the second test pads 520 may include a 1-5 test pad TP1-5, a 1-6 test pad TP1-6, a 1-7 test pad TP1-7, and a 1-8 test pad TP1-8.

[0140] The 1-1 circuit board pad FP1-1 and the 1-1 test pad TP1-1 may be connected by a 1-1 test line TL1-1. For example, the 1-1 test line TL1-1 may extend in the second direction DR2.

[0141] The 1-2 circuit board pad FP1-2 and the 1-2 test pad TP1-2 may be connected by a 1-2 test line TL1-2. For example, the 1-2 test line TL1-2 may extend in the second direction DR2.

[0142] The 1-3 circuit board pad FP1-3 and the 1-3 test pad TP1-3 may be connected by a 1-3 test line TL1-3. For example, the 1-3 test line TL1-3 may extend in the second direction DR2.

[0143] The 1-4 circuit board pads FP1-4 and the 1-4 test pads TP1-4 may be connected by 1-4 test lines TL1-4. For example, the 1-4 test lines TL1-4 may extend in the second direction DR2.

[0144] The 1-9 circuit board pads FP1-9 and the 1-5 test pads TP1-5 may be connected by a 1-5 test line TL1-5. For example, the 1-5 test line TL1-5 may extend in the second direction DR2.

[0145] The 1-10 circuit board pad FP1-10 and the 1-6 test pad TP1-6 may be connected by a 1-6 test line TL1-6. For example, the 1-6 test line TL1-6 may extend in the second direction DR2.

[0146] The 1-11 circuit board pad FP1-11 and the 1-7 test pad TP1-7 may be connected by a 1-7 test line TL1-7. For example, the 1-7 test line TL1-7 may extend in the second direction DR2.

[0147] The 1-12 circuit board pads FP1-12 and the 1-8 test pads TP1-8 may be connected by 1-8 test lines TL1-8. For example, the 1-8 test lines TL1-8 may extend in the second direction DR2.

[0148] Reference Figure 4 and Figure 6 For example, the plurality of second base pads 120 may include a 2-1 base pad PP2-1, a 2-2 base pad PP2-2, a 2-3 base pad PP2-3, a 2-4 base pad PP2-4, a 2-5 base pad PP2-5, a 2-6 base pad PP2-6, a 2-7 base pad PP2-7, a 2-8 base pad PP2-8, a 2-9 base pad PP2-9, a 2-10 base pad PP2-10, a 2-11 base pad PP2-11 and a 2-12 base pad PP2-12.

[0149] The 2-2 base pad PP2-2 may be adjacent to the 2-1 base pad PP2-1 in the first direction DR1. The 2-3 base pad PP2-3 may be adjacent to the 2-2 base pad PP2-2 in the first direction DR1. The 2-4 base pad PP2-4 may be adjacent to the 2-3 base pad PP2-3 in the first direction DR1. The 2-5 base pad PP2-5 may be adjacent to the 2-4 base pad PP2-4 in the first direction DR1. The 2-6 base pad PP2-6 may be adjacent to the 2-5 base pad PP2-5 in the first direction DR1.

[0150] The 2-7 base pad PP2-7 may be adjacent to the 2-8 base pad PP2-8 in a direction opposite to the first direction DR1. The 2-8 base pad PP2-8 may be adjacent to the 2-9 base pad PP2-9 in a direction opposite to the first direction DR1. The 2-9 base pad PP2-9 may be adjacent to the 2-10 base pad PP2-10 in a direction opposite to the first direction DR1. The 2-10 base pad PP2-10 may be adjacent to the 2-11 base pad PP2-11 in a direction opposite to the first direction DR1. The 2-11 base pad PP2-11 may be adjacent to the 2-12 base pad PP2-12 in a direction opposite to the first direction DR1.

[0151] According to some embodiments, the 2-12 substrate pad PP2-12 may be connected to the anti-static wiring ESD. For example, the 2-12 substrate pad PP2-12 may be connected to the other end of the anti-static wiring ESD.

[0152] As described above, 1-1 base pad (e.g., Figure 5 The 1-1 substrate pad PP1-1 can be connected to one end of the anti-static wiring ESD. Furthermore, the 2-12 substrate pad PP2-12 can be connected to the other end of the anti-static wiring ESD. Thus, a constant voltage can be applied from the first chip-on-film COF1, the second chip-on-film COF2, and the circuit board PCB to the anti-static wiring ESD. For example, a direct current (DC) voltage can be applied from the first chip-on-film COF1, the second chip-on-film COF2, and the circuit board PCB to the anti-static wiring ESD.

[0153] According to some embodiments, the 2-1 substrate pad PP2-1 and the 2-2 substrate pad PP2-2 can be connected to each other via the 2-1 bridge line BR2-1. In addition, the 2-2 substrate pad PP2-2 and the 2-4 substrate pad PP2-4 can be connected to each other via the 2-1 bridge line BR2-1. For example, the 2-1 substrate pad PP2-1 can be connected to the 2-1 bridge line BR2-1, the 2-2 substrate pad PP2-2 can be connected to the 2-1 bridge line BR2-1, and the 2-4 substrate pad PP2-4 can be connected to the 2-1 bridge line BR2-1.

[0154] According to some embodiments, the 2-1 bridge line BR2-1 may be positioned on the same layer as the 2-1 base pad PP2-1, the 2-2 base pad PP2-2, and the 2-4 base pad PP2-4. For example, the 2-1 base pad PP2-1, the 2-2 base pad PP2-2, and the 2-4 base pad PP2-4 may be positioned on the same layer as the source electrode (e.g., Figure 3 The source electrode SE) is positioned on the same layer, and the 2-1 bridge wire BR2-1 may also be positioned on the same layer as the source electrode.

[0155] However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the 2-1 bridging line BR2-1 may be positioned at a different layer from the 2-1 base pad PP2-1, the 2-2 base pad PP2-2, and the 2-4 base pad PP2-4. In this case, the 2-1 bridging line BR2-1 may be connected to the 2-1 base pad PP2-1 through the seventh contact hole, may be connected to the 2-2 base pad PP2-2 through the eighth contact hole, and may be connected to the 2-4 base pad PP2-4 through the ninth contact hole.

[0156] According to some embodiments, the 2-9 substrate pad PP2-9 and the 2-11 substrate pad PP2-11 may be connected to each other via the 2-2 bridge line BR2-2. For example, the 2-9 substrate pad PP2-9 may be connected to the 2-2 bridge line BR2-2, and the 2-11 substrate pad PP2-11 may be connected to the 2-2 bridge line BR2-2.

[0157] According to some embodiments, the 2-2 bridging wire BR2-2 may be positioned on the same layer as the 2-9 substrate pad PP2-9 and the 2-11 substrate pad PP2-11. For example, the 2-9 substrate pad PP2-9 and the 2-11 substrate pad PP2-11 may be positioned on the same layer as the source electrode, and the 2-2 bridging wire BR2-2 may also be positioned on the same layer as the source electrode.

[0158] However, the embodiments of the present disclosure are not limited thereto, and according to some embodiments, the 2-2 bridging wire BR2-2 may be positioned at a different layer from the 2-9 substrate pad PP2-9 and the 2-11 substrate pad PP2-11. In this case, the 2-2 bridging wire BR2-2 may be connected to the 2-9 substrate pad PP2-9 through the tenth contact hole, and may be connected to the 2-11 substrate pad PP2-11 through the eleventh contact hole.

[0159] According to some embodiments, the 2-2 bridge wire BR2-2 may be connected to the anti-static wiring ESD. According to some embodiments, the 2-2 bridge wire BR2-2 may be positioned on a different layer from the anti-static wiring ESD. For example, the anti-static wiring ESD may be positioned on a lower metal layer (e.g., Figure 3 The lower metal layer BML) is positioned at the same layer, and the 2-2 bridge wire BR2-2 can be positioned at the same layer as the source electrode. In this case, the 2-2 bridge wire BR2-2 can be connected to the anti-static wiring ESD through the twelfth contact hole.

[0160] However, embodiments according to the present disclosure are not limited thereto, and according to some embodiments, the 2-2 bridge wire BR2-2 may be positioned on the same layer as the anti-static wiring ESD.

[0161] For example, the plurality of second output pads 220 may include a 2-1 output pad OP2-1, a 2-2 output pad OP2-2, a 2-3 output pad OP2-3, a 2-4 output pad OP2-4, a 2-5 output pad OP2-5, a 2-6 output pad OP2-6, a 2-7 output pad OP2-7, a 2-8 output pad OP2-8, a 2-9 output pad OP2-9, a 2-10 output pad OP2-10, a 2-11 output pad OP2-11, and a 2-12 output pad OP2-12.

[0162] The 2-2 output pad OP2-2 may be adjacent to the 2-1 output pad OP2-1 in the first direction DR1. The 2-3 output pad OP2-3 may be adjacent to the 2-2 output pad OP2-2 in the first direction DR1. The 2-4 output pad OP2-4 may be adjacent to the 2-3 output pad OP2-3 in the first direction DR1. The 2-5 output pad OP2-5 may be adjacent to the 2-4 output pad OP2-4 in the first direction DR1. The 2-6 output pad OP2-6 may be adjacent to the 2-5 output pad OP2-5 in the first direction DR1.

[0163] The 2-7 output pad OP2-7 may be adjacent to the 2-8 output pad OP2-8 in a direction opposite to the first direction DR1. The 2-8 output pad OP2-8 may be adjacent to the 2-9 output pad OP2-9 in a direction opposite to the first direction DR1. The 2-9 output pad OP2-9 may be adjacent to the 2-10 output pad OP2-10 in a direction opposite to the first direction DR1. The 2-10 output pad OP2-10 may be adjacent to the 2-11 output pad OP2-11 in a direction opposite to the first direction DR1. The 2-11 output pad OP2-11 may be adjacent to the 2-12 output pad OP2-12 in a direction opposite to the first direction DR1.

[0164] For example, the plurality of second input pads 320 may include a 2-1 input pad IP2-1, a 2-2 input pad IP2-2, a 2-3 input pad IP2-3, a 2-4 input pad IP2-4, a 2-5 input pad IP2-5, a 2-6 input pad IP2-6, a 2-7 input pad IP2-7, a 2-8 input pad IP2-8, a 2-9 input pad IP2-9, a 2-10 input pad IP2-10, a 2-11 input pad IP2-11, and a 2-12 input pad IP2-12.

[0165] The 2-2 input pad IP2-2 may be adjacent to the 2-1 input pad IP2-1 in the first direction DR1. The 2-3 input pad IP2-3 may be adjacent to the 2-2 input pad IP2-2 in the first direction DR1. The 2-4 input pad IP2-4 may be adjacent to the 2-3 input pad IP2-3 in the first direction DR1. The 2-5 input pad IP2-5 may be adjacent to the 2-4 input pad IP2-4 in the first direction DR1. The 2-6 input pad IP2-6 may be adjacent to the 2-5 input pad IP2-5 in the first direction DR1.

[0166] The 2-7 input pad IP2-7 may be adjacent to the 2-8 input pad IP2-8 in a direction opposite to the first direction DR1. The 2-8 input pad IP2-8 may be adjacent to the 2-9 input pad IP2-9 in a direction opposite to the first direction DR1. The 2-9 input pad IP2-9 may be adjacent to the 2-10 input pad IP2-10 in a direction opposite to the first direction DR1. The 2-10 input pad IP2-10 may be adjacent to the 2-11 input pad IP2-11 in a direction opposite to the first direction DR1. The 2-11 input pad IP2-11 may be adjacent to the 2-12 input pad IP2-12 in a direction opposite to the first direction DR1.

[0167] The 2-6 output pad OP2-6, the 2-7 output pad OP2-7, the 2-6 input pad IP2-6, and the 2-7 input pad IP2-7 may be connected to the second driving chip IC2.

[0168] The 2-1 output pad OP2-1 and the 2-1 input pad IP2-1 may be connected to each other through a 2-1 line L2-1. For example, the 2-1 line L2-1 may extend in the second direction DR2.

[0169] The 2-2 output pad OP2-2 and the 2-2 input pad IP2-2 may be connected to each other through a 2-2 line L2-2. For example, the 2-2 line L2-2 may extend in the second direction DR2.

[0170] The 2-3 input pad IP2-3 may be connected to the 2-3 line L2-3. Furthermore, the 2-3 line L2-3 may be connected to the 2-2 line L2-2. That is, the 2-3 input pad IP2-3 may be connected to the 2-2 line L2-2 via the 2-3 line L2-3. For example, the 2-3 line L2-3 may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2.

[0171] The 2-4 output pad OP2-4 and the 2-4 input pad IP2-4 may be connected to each other through a 2-4 line L2-4. For example, the 2-4 line L2-4 may extend in the second direction DR2.

[0172] The 2-9 output pad OP2-9 and the 2-9 input pad IP2-9 may be connected to each other through a 2-5 line L2-5. For example, the 2-5 line L2-5 may extend in the second direction DR2.

[0173] The 2-10 input pad IP2-10 can be connected to the 2-6 line L2-6. In addition, the 2-6 line L2-6 can be connected to the 2-7 line L2-7. That is, the 2-10 input pad IP2-10 can be connected to the 2-7 line L2-7 through the 2-6 line L2-6. For example, the 2-6 line L2-6 may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2.

[0174] The 2-11 output pad OP2-11 and the 2-11 input pad IP2-11 may be connected to each other through a 2-7 line L2-7. For example, the 2-7 line L2-7 may extend in the second direction DR2.

[0175] The 2-12 output pad OP2-12 and the 2-12 input pad IP2-12 may be connected to each other through a 2-8 line L2-8. For example, the 2-8 line L2-8 may extend in the second direction DR2.

[0176] For example, the plurality of second circuit board pads 420 may include a 2-1 circuit board pad FP2-1, a 2-2 circuit board pad FP2-2, a 2-3 circuit board pad FP2-3, a 2-4 circuit board pad FP2-4, a 2-5 circuit board pad FP2-5, a 2-6 circuit board pad FP2-6, a 2-7 circuit board pad FP2-7, a 2-8 circuit board pad FP2-8, a 2-9 circuit board pad FP2-9, a 2-10 circuit board pad FP2-10, a 2-11 circuit board pad FP2-11, and a 2-12 circuit board pad FP2-12.

[0177] The 2-2 circuit board pad FP2-2 may be adjacent to the 2-1 circuit board pad FP2-1 in the first direction DR1. The 2-3 circuit board pad FP2-3 may be adjacent to the 2-2 circuit board pad FP2-2 in the first direction DR1. The 2-4 circuit board pad FP2-4 may be adjacent to the 2-3 circuit board pad FP2-3 in the first direction DR1. The 2-5 circuit board pad FP2-5 may be adjacent to the 2-4 circuit board pad FP2-4 in the first direction DR1. The 2-6 circuit board pad FP2-6 may be adjacent to the 2-5 circuit board pad FP2-5 in the first direction DR1.

[0178] The 2-7 circuit board pad FP2-7 may be adjacent to the 2-8 circuit board pad FP2-8 in a direction opposite to the first direction DR1. The 2-8 circuit board pad FP2-8 may be adjacent to the 2-9 circuit board pad FP2-9 in a direction opposite to the first direction DR1. The 2-9 circuit board pad FP2-9 may be adjacent to the 2-10 circuit board pad FP2-10 in a direction opposite to the first direction DR1. The 2-10 circuit board pad FP2-10 may be adjacent to the 2-11 circuit board pad FP2-11 in a direction opposite to the first direction DR1. The 2-11 circuit board pad FP2-11 may be adjacent to the 2-12 circuit board pad FP2-12 in a direction opposite to the first direction DR1.

[0179] For example, the third test pads 530 may include a 2-1 test pad TP2-1, a 2-2 test pad TP2-2, a 2-3 test pad TP2-3, and a 2-4 test pad TP2-4.

[0180] For example, the fourth test pads 540 may include a 2-5 test pad TP2-5, a 2-6 test pad TP2-6, a 2-7 test pad TP2-7, and a 2-8 test pad TP2-8.

[0181] The 2-1 circuit board pad FP2-1 and the 2-1 test pad TP2-1 may be connected to each other through a 2-1 test line TL2-1. For example, the 2-1 test line TL2-1 may extend in the second direction DR2.

[0182] The 2-2 circuit board pad FP2-2 and the 2-2 test pad TP2-2 may be connected to each other through a 2-2 test line TL2-2. For example, the 2-2 test line TL2-2 may extend in the second direction DR2.

[0183] The 2-3 circuit board pad FP2-3 and the 2-3 test pad TP2-3 may be connected to each other through a 2-3 test line TL2-3. For example, the 2-3 test line TL2-3 may extend in the second direction DR2.

[0184] The 2-4 circuit board pad FP2-4 and the 2-4 test pad TP2-4 may be connected to each other through a 2-4 test line TL2-4. For example, the 2-4 test line TL2-4 may extend in the second direction DR2.

[0185] The 2-9 circuit board pad FP2-9 and the 2-5 test pad TP2-5 may be connected to each other through a 2-5 test line TL2-5. For example, the 2-5 test line TL2-5 may extend in the second direction DR2.

[0186] The 2-10 circuit board pad FP2-10 and the 2-6 test pad TP2-6 may be connected to each other through a 2-6 test line TL2-6. For example, the 2-6 test line TL2-6 may extend in the second direction DR2.

[0187] The 2-11 circuit board pad FP2-11 and the 2-7 test pad TP2-7 may be connected to each other through a 2-7 test line TL2-7. For example, the 2-7 test line TL2-7 may extend in the second direction DR2.

[0188] The 2-12 circuit board pad FP2-12 and the 2-8 test pad TP2-8 may be connected to each other through a 2-8 test line TL2-8. For example, the 2-8 test line TL2-8 may extend in the second direction DR2.

[0189] Figure 7 It shows Figure 1 A plan view of a display device. Figure 8 yes Figure 7 An enlarged plan view of section X. Figure 9 yes Figure 7 An enlarged plan view of part Y. For example, Figure 7 It shows Figure 4 A plan view of a substrate bonded to a plurality of chip-on-film chips and the plurality of chip-on-film chips bonded to a circuit board.

[0190] Reference Figure 4 and Figure 7 , the substrate 10 and the first chip-on-film COF1 can be bonded to each other. For example, a plurality of first substrate pads (eg, Figure 5 The plurality of first substrate pads 110 and the plurality of first output pads 210 can be stacked in plan view, allowing the substrate 10 and the first chip-on-film COF1 to be bonded to each other. For example, the plurality of first substrate pads and the plurality of first output pads 210 can be bonded to each other via an anisotropic conductive film (ACF). For example, a first output bonding area OBA1 can be defined in which the plurality of first substrate pads and the plurality of first output pads 210 overlap in plan view.

[0191] The substrate 10 and the second chip-on-film COF2 may be bonded to each other. For example, a plurality of second substrate pads (eg, Figure 6 The plurality of second substrate pads 120 and the plurality of second output pads 220 can overlap in plan view, allowing the substrate 10 and the second chip-on-film COF2 to be bonded to each other. For example, the plurality of second substrate pads and the plurality of second output pads 220 can be bonded to each other via an anisotropic conductive film (ACF). For example, a second output bonding area OBA2 can be defined in which the plurality of second substrate pads and the plurality of second output pads 220 overlap in plan view.

[0192] The substrate 10 and the nth chip-on-film COFn may be bonded to each other in substantially the same manner as the substrate 10 and the first chip-on-film COF1 are bonded to each other.

[0193] The first chip on film COF1 and the circuit board PCB may be bonded to each other. For example, a plurality of first input pads 310 and a plurality of first circuit board pads (eg, Figure 5 The plurality of first circuit board pads 410 are stacked in plan view, allowing the first chip-on-film COF1 and the circuit board PCB to be bonded to each other. For example, the plurality of first input pads 310 and the plurality of first circuit board pads can be bonded to each other via an anisotropic conductive film. For example, a first input bonding area IBA1 can be defined in which the plurality of first input pads 310 and the plurality of first circuit board pads are stacked in plan view.

[0194] The second chip on film COF2 and the circuit board PCB can be bonded to each other. For example, a plurality of second input pads 320 and a plurality of second circuit board pads (eg, Figure 6 The plurality of second circuit board pads 420 are stacked in plan view, allowing the second chip-on-film COF2 and the circuit board PCB to bond with each other. For example, the plurality of second input pads 320 and the plurality of second circuit board pads can be bonded with each other via an anisotropic conductive film. For example, a second input bonding area IBA2 can be defined in which the plurality of second input pads 320 and the plurality of second circuit board pads are stacked in plan view.

[0195] The nth chip-on-film COFn and the circuit board PCB may be bonded to each other in substantially the same manner as the first chip-on-film COF1 and the circuit board PCB are bonded to each other.

[0196] Reference Figure 5 and Figure 8 The first output bonding area OBA1 may include 1-1 output bonding part OB1-1, 1-2 output bonding part OB1-2, 1-3 output bonding part OB1-3, 1-4 output bonding part OB1-4, 1-5 output bonding part OB1-5, 1-6 output bonding part OB1-6, 1-7 output bonding part OB1-7, 1-8 output bonding part OB1-8, 1-9 output bonding part OB1-9, 1-10 output bonding part OB1-10, 1-11 output bonding part OB1-11 and 1-12 output bonding part OB1-12.

[0197] The 1-1 output joint portion OB1-1 can be defined by overlapping the 1-1 base pad PP1-1 and the 1-1 output pad OP1-1 in a plan view. For example, the 1-1 output joint portion OB1-1 can include the 1-1 base pad PP1-1, the 1-1 output pad OP1-1, and the 1-1 anisotropic conductive film positioned between the 1-1 base pad PP1-1 and the 1-1 output pad OP1-1. For example, the 1-1 base pad PP1-1 can be connected to the 1-1 output pad OP1-1 via the 1-1 anisotropic conductive film.

[0198] The 1-2 output joint portion OB1-2 can be defined by overlapping the 1-2 base pad PP1-2 and the 1-2 output pad OP1-2 in a plan view. For example, the 1-2 output joint portion OB1-2 can include the 1-2 base pad PP1-2, the 1-2 output pad OP1-2, and the 1-2 anisotropic conductive film positioned between the 1-2 base pad PP1-2 and the 1-2 output pad OP1-2. For example, the 1-2 base pad PP1-2 can be connected to the 1-2 output pad OP1-2 via the 1-2 anisotropic conductive film.

[0199] The 1-3 output joint OB1-3 can be defined by overlapping the 1-3 base pad PP1-3 and the 1-3 output pad OP1-3 in a plan view. For example, the 1-3 output joint OB1-3 can include the 1-3 base pad PP1-3, the 1-3 output pad OP1-3, and the 1-3 anisotropic conductive film positioned between the 1-3 base pad PP1-3 and the 1-3 output pad OP1-3. For example, the 1-3 base pad PP1-3 can be connected to the 1-3 output pad OP1-3 via the 1-3 anisotropic conductive film.

[0200] The 1-4 output joint OB1-4 can be defined by overlapping the 1-4 base pad PP1-4 and the 1-4 output pad OP1-4 in a plan view. For example, the 1-4 output joint OB1-4 can include the 1-4 base pad PP1-4, the 1-4 output pad OP1-4, and the 1-4 anisotropic conductive film positioned between the 1-4 base pad PP1-4 and the 1-4 output pad OP1-4. For example, the 1-4 base pad PP1-4 can be connected to the 1-4 output pad OP1-4 via the 1-4 anisotropic conductive film.

[0201] The 1-5 output joint OB1-5 can be defined by overlapping the 1-5 base pad PP1-5 and the 1-5 output pad OP1-5 in a plan view. For example, the 1-5 output joint OB1-5 can include the 1-5 base pad PP1-5, the 1-5 output pad OP1-5, and the 1-5 anisotropic conductive film positioned between the 1-5 base pad PP1-5 and the 1-5 output pad OP1-5. For example, the 1-5 base pad PP1-5 can be connected to the 1-5 output pad OP1-5 via the 1-5 anisotropic conductive film.

[0202] The 1-6 output junction OB1-6 can be defined by overlapping the 1-6 base pad PP1-6 and the 1-6 output pad OP1-6 in a plan view. For example, the 1-6 output junction OB1-6 can include the 1-6 base pad PP1-6, the 1-6 output pad OP1-6, and the 1-6 anisotropic conductive film positioned between the 1-6 base pad PP1-6 and the 1-6 output pad OP1-6. For example, the 1-6 base pad PP1-6 can be connected to the 1-6 output pad OP1-6 via the 1-6 anisotropic conductive film.

[0203] The 1-7 output junction OB1-7 can be defined by overlapping the 1-7 base pad PP1-7 and the 1-7 output pad OP1-7 in a plan view. For example, the 1-7 output junction OB1-7 can include the 1-7 base pad PP1-7, the 1-7 output pad OP1-7, and the 1-7 anisotropic conductive film positioned between the 1-7 base pad PP1-7 and the 1-7 output pad OP1-7. For example, the 1-7 base pad PP1-7 can be connected to the 1-7 output pad OP1-7 via the 1-7 anisotropic conductive film.

[0204] The 1-8 output joint OB1-8 can be defined by overlapping the 1-8 base pad PP1-8 and the 1-8 output pad OP1-8 in a plan view. For example, the 1-8 output joint OB1-8 can include the 1-8 base pad PP1-8, the 1-8 output pad OP1-8, and the 1-8 anisotropic conductive film positioned between the 1-8 base pad PP1-8 and the 1-8 output pad OP1-8. For example, the 1-8 base pad PP1-8 can be connected to the 1-8 output pad OP1-8 via the 1-8 anisotropic conductive film.

[0205] The 1-9 output joint OB1-9 can be defined by overlapping the 1-9 base pad PP1-9 and the 1-9 output pad OP1-9 in a plan view. For example, the 1-9 output joint OB1-9 can include the 1-9 base pad PP1-9, the 1-9 output pad OP1-9, and the 1-9 anisotropic conductive film positioned between the 1-9 base pad PP1-9 and the 1-9 output pad OP1-9. For example, the 1-9 base pad PP1-9 can be connected to the 1-9 output pad OP1-9 via the 1-9 anisotropic conductive film.

[0206] The I-10 output joint OB1-10 can be defined by stacking the I-10 base pad PP1-10 and the I-10 output pad OP1-10 in a plan view. For example, the I-10 output joint OB1-10 can include the I-10 base pad PP1-10, the I-10 output pad OP1-10, and the I-10 anisotropic conductive film positioned between the I-10 base pad PP1-10 and the I-10 output pad OP1-10. For example, the I-10 base pad PP1-10 can be connected to the I-10 output pad OP1-10 via the I-10 anisotropic conductive film.

[0207] The 1-11 output joint OB1-11 can be defined by overlapping the 1-11 base pad PP1-11 and the 1-11 output pad OP1-11 in a plan view. For example, the 1-11 output joint OB1-11 can include the 1-11 base pad PP1-11, the 1-11 output pad OP1-11, and the 1-11 anisotropic conductive film positioned between the 1-11 base pad PP1-11 and the 1-11 output pad OP1-11. For example, the 1-11 base pad PP1-11 can be connected to the 1-11 output pad OP1-11 via the 1-11 anisotropic conductive film.

[0208] The 1-12 output joint OB1-12 can be defined by stacking the 1-12 base pad PP1-12 and the 1-12 output pad OP1-12 in a plan view. For example, the 1-12 output joint OB1-12 can include the 1-12 base pad PP1-12, the 1-12 output pad OP1-12, and a 1-12 anisotropic conductive film positioned between the 1-12 base pad PP1-12 and the 1-12 output pad OP1-12. For example, the 1-12 base pad PP1-12 can be connected to the 1-12 output pad OP1-12 via the 1-12 anisotropic conductive film.

[0209] The first input bonding area IBA1 may include a 1-1 input bonding portion IB1-1, a 1-2 input bonding portion IB1-2, a 1-3 input bonding portion IB1-3, a 1-4 input bonding portion IB1-4, a 1-5 input bonding portion IB1-5, a 1-6 input bonding portion IB1-6, a 1-7 input bonding portion IB1-7, a 1-8 input bonding portion IB1-8, a 1-9 input bonding portion IB1-9, a 1-10 input bonding portion IB1-10, a 1-11 input bonding portion IB1-11 and a 1-12 input bonding portion IB1-12.

[0210] The 1-1 input bonding portion IB1-1 can be defined by stacking the 1-1 input pad IP1-1 and the 1-1 circuit board pad FP1-1 in a plan view. For example, the 1-1 input bonding portion IB1-1 can include the 1-1 input pad IP1-1, the 1-1 circuit board pad FP1-1, and the 1-13 anisotropic conductive film positioned between the 1-1 input pad IP1-1 and the 1-1 circuit board pad FP1-1. For example, the 1-1 circuit board pad FP1-1 can be connected to the 1-1 input pad IP1-1 via the 1-13 anisotropic conductive film.

[0211] The 1-2 input bonding portion IB1-2 can be defined by overlapping the 1-2 input pad IP1-2 and the 1-2 circuit board pad FP1-2 in a plan view. For example, the 1-2 input bonding portion IB1-2 can include the 1-2 input pad IP1-2, the 1-2 circuit board pad FP1-2, and the 1-14 anisotropic conductive film positioned between the 1-2 input pad IP1-2 and the 1-2 circuit board pad FP1-2. For example, the 1-2 circuit board pad FP1-2 can be connected to the 1-2 input pad IP1-2 via the 1-14 anisotropic conductive film.

[0212] The 1-3 input bonding portion IB1-3 can be defined by overlapping the 1-3 input pad IP1-3 and the 1-3 circuit board pad FP1-3 in a plan view. For example, the 1-3 input bonding portion IB1-3 can include the 1-3 input pad IP1-3, the 1-3 circuit board pad FP1-3, and the 1-15 anisotropic conductive film positioned between the 1-3 input pad IP1-3 and the 1-3 circuit board pad FP1-3. For example, the 1-3 circuit board pad FP1-3 can be connected to the 1-3 input pad IP1-3 via the 1-15 anisotropic conductive film.

[0213] The 1-4 input bond IB1-4 can be defined by overlapping the 1-4 input pad IP1-4 and the 1-4 circuit board pad FP1-4 in a plan view. For example, the 1-4 input bond IB1-4 can include the 1-4 input pad IP1-4, the 1-4 circuit board pad FP1-4, and the 1-16 anisotropic conductive film positioned between the 1-4 input pad IP1-4 and the 1-4 circuit board pad FP1-4. For example, the 1-4 circuit board pad FP1-4 can be connected to the 1-4 input pad IP1-4 via the 1-16 anisotropic conductive film.

[0214] The 1-5 input bonding portion IB1-5 can be defined by overlapping the 1-5 input pad IP1-5 and the 1-5 circuit board pad FP1-5 in a plan view. For example, the 1-5 input bonding portion IB1-5 can include the 1-5 input pad IP1-5, the 1-5 circuit board pad FP1-5, and the 1-17 anisotropic conductive film positioned between the 1-5 input pad IP1-5 and the 1-5 circuit board pad FP1-5. For example, the 1-5 circuit board pad FP1-5 can be connected to the 1-5 input pad IP1-5 via the 1-17 anisotropic conductive film.

[0215] The 1-6 input bond IB1-6 can be defined by stacking the 1-6 input pad IP1-6 and the 1-6 circuit board pad FP1-6 in a plan view. For example, the 1-6 input bond IB1-6 can include the 1-6 input pad IP1-6, the 1-6 circuit board pad FP1-6, and the 1-18 anisotropic conductive film positioned between the 1-6 input pad IP1-6 and the 1-6 circuit board pad FP1-6. For example, the 1-6 circuit board pad FP1-6 can be connected to the 1-6 input pad IP1-6 via the 1-18 anisotropic conductive film.

[0216] The 1-7 input bond IB1-7 can be defined by overlapping the 1-7 input pad IP1-7 and the 1-7 circuit board pad FP1-7 in a plan view. For example, the 1-7 input bond IB1-7 can include the 1-7 input pad IP1-7, the 1-7 circuit board pad FP1-7, and the 1-19 anisotropic conductive film positioned between the 1-7 input pad IP1-7 and the 1-7 circuit board pad FP1-7. For example, the 1-7 circuit board pad FP1-7 can be connected to the 1-7 input pad IP1-7 via the 1-19 anisotropic conductive film.

[0217] The 1-8 input bond IB1-8 can be defined by overlapping the 1-8 input pad IP1-8 and the 1-8 circuit board pad FP1-8 in a plan view. For example, the 1-8 input bond IB1-8 can include the 1-8 input pad IP1-8, the 1-8 circuit board pad FP1-8, and the 1-20 anisotropic conductive film positioned between the 1-8 input pad IP1-8 and the 1-8 circuit board pad FP1-8. For example, the 1-8 circuit board pad FP1-8 can be connected to the 1-8 input pad IP1-8 via the 1-20 anisotropic conductive film.

[0218] The 1-9 input bond IB1-9 can be defined by overlapping the 1-9 input pad IP1-9 and the 1-9 circuit board pad FP1-9 in a plan view. For example, the 1-9 input bond IB1-9 can include the 1-9 input pad IP1-9, the 1-9 circuit board pad FP1-9, and the 1-21 anisotropic conductive film positioned between the 1-9 input pad IP1-9 and the 1-9 circuit board pad FP1-9. For example, the 1-9 circuit board pad FP1-9 can be connected to the 1-9 input pad IP1-9 via the 1-21 anisotropic conductive film.

[0219] The I-10 input bond IB1-10 can be defined by stacking the I-10 input pad IP1-10 and the I-10 circuit board pad FP1-10 in a plan view. For example, the I-10 input bond IB1-10 can include the I-10 input pad IP1-10, the I-10 circuit board pad FP1-10, and the I-22 anisotropic conductive film positioned between the I-10 input pad IP1-10 and the I-10 circuit board pad FP1-10. For example, the I-10 circuit board pad FP1-10 can be connected to the I-10 input pad IP1-10 via the I-22 anisotropic conductive film.

[0220] The 1-11 input bond IB1-11 can be defined by stacking the 1-11 input pad IP1-11 and the 1-11 circuit board pad FP1-11 in a plan view. For example, the 1-11 input bond IB1-11 can include the 1-11 input pad IP1-11, the 1-11 circuit board pad FP1-11, and the 1-23 anisotropic conductive film positioned between the 1-11 input pad IP1-11 and the 1-11 circuit board pad FP1-11. For example, the 1-11 circuit board pad FP1-11 can be connected to the 1-11 input pad IP1-11 via the 1-23 anisotropic conductive film.

[0221] The 1-12 input bond IB1-12 can be defined by stacking the 1-12 input pad IP1-12 and the 1-12 circuit board pad FP1-12 in a plan view. For example, the 1-12 input bond IB1-12 can include the 1-12 input pad IP1-12, the 1-12 circuit board pad FP1-12, and the 1-24 anisotropic conductive film positioned between the 1-12 input pad IP1-12 and the 1-12 circuit board pad FP1-12. For example, the 1-12 circuit board pad FP1-12 can be connected to the 1-12 input pad IP1-12 via the 1-24 anisotropic conductive film.

[0222] According to some embodiments, the 1-3 output junction OB1-3 can be omitted. That is, the 1-3 base pad PP1-3 and the 1-3 output pad OP1-3 can be omitted. In addition, the 1-10 output junction OB1-10 can be omitted. That is, the 1-10 base pad PP1-10 and the 1-10 output pad OP1-10 can be omitted.

[0223] Hereinafter, a measurement display device (eg, Figure 7 The method of displaying the resistance of the device DD).

[0224] A method of measuring resistance of a display device according to some embodiments may include measuring resistance of the 1-2 output bonding portion OB1-2 and the 1-11 output bonding portion OB1-11 using a resistance tester including an ammeter and a voltmeter.

[0225] For example, the resistance tester may include an ammeter including a first terminal and a second terminal and a voltmeter including a first terminal and a second terminal.

[0226] According to some embodiments, a first terminal of the ammeter may be connected to test pad TP1-1. Furthermore, a second terminal of the ammeter may be connected to test pad TP1-2. Furthermore, a first terminal of the voltmeter may be connected to test pad TP1-3. Furthermore, a second terminal of the voltmeter may be connected to test pad TP1-4.

[0227] When a constant current flows through the ammeter, a circuit including the 1-1 test line TL1-1, the 1-1 input junction IB1-1, the 1-1 line L1-1, the 1-1 output junction OB1-1, the 1-1 bridge line BR1-1, the 1-2 line L1-2, the 1-2 input junction IB1-2, and the 1-2 test line TL1-2 can be formed. In this case, the resistance applied to the 1-2 output junction OB1-2 can be measured by the first terminal of the voltmeter connected to the 1-3 test pad TP1-3 and the second terminal of the voltmeter connected to the 1-4 test pad TP1-4.

[0228] According to some embodiments, a first terminal of the ammeter may be connected to the 1-8 test pad TP1-8. Furthermore, a second terminal of the ammeter may be connected to the 1-7 test pad TP1-7. Furthermore, a first terminal of the voltmeter may be connected to the 1-6 test pad TP1-6. Furthermore, a second terminal of the voltmeter may be connected to the 1-5 test pad TP1-5.

[0229] When a constant current flows through the ammeter, a circuit including the 1-8 test line TL1-8, the 1-12 input junction IB1-12, the 1-8 line L1-8, the 1-12 output junction OB1-12, the 1-2 bridge line BR1-2, the 1-7 line L1-7, the 1-11 input junction IB1-11, and the 1-7 test line TL1-7 can be formed. In this case, the resistance applied to the 1-11 output junction OB1-11 can be measured by the first terminal of the voltmeter connected to the 1-6 test pad TP1-6 and the second terminal of the voltmeter connected to the 1-5 test pad TP1-5.

[0230] Reference Figure 6 and Figure 9 The second output bonding area OBA2 may include 2-1 output bonding part OB2-1, 2-2 output bonding part OB2-2, 2-3 output bonding part OB2-3, 2-4 output bonding part OB2-4, 2-5 output bonding part OB2-5, 2-6 output bonding part OB2-6, 2-7 output bonding part OB2-7, 2-8 output bonding part OB2-8, 2-9 output bonding part OB2-9, 2-10 output bonding part OB2-10, 2-11 output bonding part OB2-11 and 2-12 output bonding part OB2-12.

[0231] The 2-1 output junction OB2-1 can be defined by overlapping the 2-1 base pad PP2-1 and the 2-1 output pad OP2-1 in a plan view. For example, the 2-1 output junction OB2-1 can include the 2-1 base pad PP2-1, the 2-1 output pad OP2-1, and the 2-1 anisotropic conductive film positioned between the 2-1 base pad PP2-1 and the 2-1 output pad OP2-1. For example, the 2-1 base pad PP2-1 can be connected to the 2-1 output pad OP2-1 via the 2-1 anisotropic conductive film.

[0232] The 2-2 output joint portion OB2-2 can be defined by overlapping the 2-2 base pad PP2-2 and the 2-2 output pad OP2-2 in a plan view. For example, the 2-2 output joint portion OB2-2 can include the 2-2 base pad PP2-2, the 2-2 output pad OP2-2, and a 2-2 anisotropic conductive film positioned between the 2-2 base pad PP2-2 and the 2-2 output pad OP2-2. For example, the 2-2 base pad PP2-2 can be connected to the 2-2 output pad OP2-2 via the 2-2 anisotropic conductive film.

[0233] The 2-3 output joint OB2-3 can be defined by overlapping the 2-3 base pad PP2-3 and the 2-3 output pad OP2-3 in a plan view. For example, the 2-3 output joint OB2-3 can include the 2-3 base pad PP2-3, the 2-3 output pad OP2-3, and a 2-3 anisotropic conductive film positioned between the 2-3 base pad PP2-3 and the 2-3 output pad OP2-3. For example, the 2-3 base pad PP2-3 can be connected to the 2-3 output pad OP2-3 via the 2-3 anisotropic conductive film.

[0234] The 2-4 output joint OB2-4 can be defined by overlapping the 2-4 base pad PP2-4 and the 2-4 output pad OP2-4 in a plan view. For example, the 2-4 output joint OB2-4 can include the 2-4 base pad PP2-4, the 2-4 output pad OP2-4, and the 2-4 anisotropic conductive film positioned between the 2-4 base pad PP2-4 and the 2-4 output pad OP2-4. For example, the 2-4 base pad PP2-4 can be connected to the 2-4 output pad OP2-4 via the 2-4 anisotropic conductive film.

[0235] The 2-5 output joint OB2-5 can be defined by overlapping the 2-5 base pad PP2-5 and the 2-5 output pad OP2-5 in a plan view. For example, the 2-5 output joint OB2-5 can include the 2-5 base pad PP2-5, the 2-5 output pad OP2-5, and a 2-5 anisotropic conductive film positioned between the 2-5 base pad PP2-5 and the 2-5 output pad OP2-5. For example, the 2-5 base pad PP2-5 can be connected to the 2-5 output pad OP2-5 via the 2-5 anisotropic conductive film.

[0236] The 2-6 output junction OB2-6 can be defined by overlapping the 2-6 base pad PP2-6 and the 2-6 output pad OP2-6 in a plan view. For example, the 2-6 output junction OB2-6 can include the 2-6 base pad PP2-6, the 2-6 output pad OP2-6, and the 2-6 anisotropic conductive film positioned between the 2-6 base pad PP2-6 and the 2-6 output pad OP2-6. For example, the 2-6 base pad PP2-6 can be connected to the 2-6 output pad OP2-6 via the 2-6 anisotropic conductive film.

[0237] The 2-7 output junction OB2-7 can be defined by overlapping the 2-7 base pad PP2-7 and the 2-7 output pad OP2-7 in a plan view. For example, the 2-7 output junction OB2-7 can include the 2-7 base pad PP2-7, the 2-7 output pad OP2-7, and the 2-7 anisotropic conductive film positioned between the 2-7 base pad PP2-7 and the 2-7 output pad OP2-7. For example, the 2-7 base pad PP2-7 can be connected to the 2-7 output pad OP2-7 via the 2-7 anisotropic conductive film.

[0238] The 2-8 output joint OB2-8 can be defined by overlapping the 2-8 base pad PP2-8 and the 2-8 output pad OP2-8 in a plan view. For example, the 2-8 output joint OB2-8 can include the 2-8 base pad PP2-8, the 2-8 output pad OP2-8, and the 2-8 anisotropic conductive film positioned between the 2-8 base pad PP2-8 and the 2-8 output pad OP2-8. For example, the 2-8 base pad PP2-8 can be connected to the 2-8 output pad OP2-8 via the 2-8 anisotropic conductive film.

[0239] The 2-9 output junction OB2-9 can be defined by overlapping the 2-9 base pad PP2-9 and the 2-9 output pad OP2-9 in a plan view. For example, the 2-9 output junction OB2-9 can include the 2-9 base pad PP2-9, the 2-9 output pad OP2-9, and the 2-9 anisotropic conductive film positioned between the 2-9 base pad PP2-9 and the 2-9 output pad OP2-9. For example, the 2-9 base pad PP2-9 can be connected to the 2-9 output pad OP2-9 via the 2-9 anisotropic conductive film.

[0240] The 2-10 output joint OB2-10 can be defined by stacking the 2-10 base pad PP2-10 and the 2-10 output pad OP2-10 in a plan view. For example, the 2-10 output joint OB2-10 can include the 2-10 base pad PP2-10, the 2-10 output pad OP2-10, and the 2-10 anisotropic conductive film positioned between the 2-10 base pad PP2-10 and the 2-10 output pad OP2-10. For example, the 2-10 base pad PP2-10 can be connected to the 2-10 output pad OP2-10 via the 2-10 anisotropic conductive film.

[0241] The 2-11 output junction OB2-11 can be defined by connecting the 2-11 base pad PP2-11 and the 2-11 output pad OP2-11 in a plan view. For example, the 2-11 output junction OB2-11 can include the 2-11 base pad PP2-11, the 2-11 output pad OP2-11, and the 2-11 anisotropic conductive film positioned between the 2-11 base pad PP2-11 and the 2-11 output pad OP2-11. For example, the 2-11 base pad PP2-11 can be connected to the 2-11 output pad OP2-11 via the 2-11 anisotropic conductive film.

[0242] The 2-12 output joint OB2-12 can be defined by stacking the 2-12 base pad PP2-12 and the 2-12 output pad OP2-12 in a plan view. For example, the 2-12 output joint OB2-12 can include the 2-12 base pad PP2-12, the 2-12 output pad OP2-12, and a 2-12 anisotropic conductive film positioned between the 2-12 base pad PP2-12 and the 2-12 output pad OP2-12. For example, the 2-12 base pad PP2-12 can be connected to the 2-12 output pad OP2-12 via the 2-12 anisotropic conductive film.

[0243] The second input bonding area IBA2 may include a 2-1 input bonding portion IB2-1, a 2-2 input bonding portion IB2-2, a 2-3 input bonding portion IB2-3, a 2-4 input bonding portion IB2-4, a 2-5 input bonding portion IB2-5, a 2-6 input bonding portion IB2-6, a 2-7 input bonding portion IB2-7, a 2-8 input bonding portion IB2-8, a 2-9 input bonding portion IB2-9, a 2-10 input bonding portion IB2-10, a 2-11 input bonding portion IB2-11 and a 2-12 input bonding portion IB2-12.

[0244] The 2-1 input bonding portion IB2-1 can be defined by stacking the 2-1 input pad IP2-1 and the 2-1 circuit board pad FP2-1 in a plan view. For example, the 2-1 input bonding portion IB2-1 can include the 2-1 input pad IP2-1, the 2-1 circuit board pad FP2-1, and the 2-13 anisotropic conductive film positioned between the 2-1 input pad IP2-1 and the 2-1 circuit board pad FP2-1. For example, the 2-1 circuit board pad FP2-1 can be connected to the 2-1 input pad IP2-1 via the 2-13 anisotropic conductive film.

[0245] The 2-2 input bonding portion IB2-2 can be defined by overlapping the 2-2 input pad IP2-2 and the 2-2 circuit board pad FP2-2 in a plan view. For example, the 2-2 input bonding portion IB2-2 can include the 2-2 input pad IP2-2, the 2-2 circuit board pad FP2-2, and the 2-14 anisotropic conductive film positioned between the 2-2 input pad IP2-2 and the 2-2 circuit board pad FP2-2. For example, the 2-2 circuit board pad FP2-2 can be connected to the 2-2 input pad IP2-2 via the 2-14 anisotropic conductive film.

[0246] The 2-3 input bonding portion IB2-3 can be defined by overlapping the 2-3 input pad IP2-3 and the 2-3 circuit board pad FP2-3 in a plan view. For example, the 2-3 input bonding portion IB2-3 can include the 2-3 input pad IP2-3, the 2-3 circuit board pad FP2-3, and the 2-15 anisotropic conductive film positioned between the 2-3 input pad IP2-3 and the 2-3 circuit board pad FP2-3. For example, the 2-3 circuit board pad FP2-3 can be connected to the 2-3 input pad IP2-3 via the 2-15 anisotropic conductive film.

[0247] The 2-4 input bond portion IB2-4 can be defined by overlapping the 2-4 input pad IP2-4 and the 2-4 circuit board pad FP2-4 in a plan view. For example, the 2-4 input bond portion IB2-4 can include the 2-4 input pad IP2-4, the 2-4 circuit board pad FP2-4, and a 2-16 anisotropic conductive film positioned between the 2-4 input pad IP2-4 and the 2-4 circuit board pad FP2-4. For example, the 2-4 circuit board pad FP2-4 can be connected to the 2-4 input pad IP2-4 via the 2-16 anisotropic conductive film.

[0248] The 2-5 input bonding portion IB2-5 can be defined by overlapping the 2-5 input pad IP2-5 and the 2-5 circuit board pad FP2-5 in a plan view. For example, the 2-5 input bonding portion IB2-5 can include the 2-5 input pad IP2-5, the 2-5 circuit board pad FP2-5, and the 2-17 anisotropic conductive film positioned between the 2-5 input pad IP2-5 and the 2-5 circuit board pad FP2-5. For example, the 2-5 circuit board pad FP2-5 can be connected to the 2-5 input pad IP2-5 via the 2-17 anisotropic conductive film.

[0249] The 2-6 input bond portion IB2-6 can be defined by stacking the 2-6 input pad IP2-6 and the 2-6 circuit board pad FP2-6 in a plan view. For example, the 2-6 input bond portion IB2-6 can include the 2-6 input pad IP2-6, the 2-6 circuit board pad FP2-6, and the 2-18 anisotropic conductive film positioned between the 2-6 input pad IP2-6 and the 2-6 circuit board pad FP2-6. For example, the 2-6 circuit board pad FP2-6 can be connected to the 2-6 input pad IP2-6 via the 2-18 anisotropic conductive film.

[0250] The 2-7 input bond portion IB2-7 can be defined by overlapping the 2-7 input pad IP2-7 and the 2-7 circuit board pad FP2-7 in a plan view. For example, the 2-7 input bond portion IB2-7 can include the 2-7 input pad IP2-7, the 2-7 circuit board pad FP2-7, and the 2-19 anisotropic conductive film positioned between the 2-7 input pad IP2-7 and the 2-7 circuit board pad FP2-7. For example, the 2-7 circuit board pad FP2-7 can be connected to the 2-7 input pad IP2-7 via the 2-19 anisotropic conductive film.

[0251] The 2-8 input bond portion IB2-8 can be defined by overlapping the 2-8 input pad IP2-8 and the 2-8 circuit board pad FP2-8 in a plan view. For example, the 2-8 input bond portion IB2-8 can include the 2-8 input pad IP2-8, the 2-8 circuit board pad FP2-8, and the 2-20 anisotropic conductive film positioned between the 2-8 input pad IP2-8 and the 2-8 circuit board pad FP2-8. For example, the 2-8 circuit board pad FP2-8 can be connected to the 2-8 input pad IP2-8 via the 2-20 anisotropic conductive film.

[0252] The 2-9 input bond portion IB2-9 can be defined by overlapping the 2-9 input pad IP2-9 and the 2-9 circuit board pad FP2-9 in a plan view. For example, the 2-9 input bond portion IB2-9 can include the 2-9 input pad IP2-9, the 2-9 circuit board pad FP2-9, and the 2-21 anisotropic conductive film positioned between the 2-9 input pad IP2-9 and the 2-9 circuit board pad FP2-9. For example, the 2-9 circuit board pad FP2-9 can be connected to the 2-9 input pad IP2-9 via the 2-21 anisotropic conductive film.

[0253] The 2-10 input bond portion IB2-10 can be defined by stacking the 2-10 input pad IP2-10 and the 2-10 circuit board pad FP2-10 in a plan view. For example, the 2-10 input bond portion IB2-10 can include the 2-10 input pad IP2-10, the 2-10 circuit board pad FP2-10, and the 2-22 anisotropic conductive film positioned between the 2-10 input pad IP2-10 and the 2-10 circuit board pad FP2-10. For example, the 2-10 circuit board pad FP2-10 can be connected to the 2-10 input pad IP2-10 via the 2-22 anisotropic conductive film.

[0254] The 2-11 input bond portion IB2-11 can be defined by stacking the 2-11 input pad IP2-11 and the 2-11 circuit board pad FP2-11 in a plan view. For example, the 2-11 input bond portion IB2-11 can include the 2-11 input pad IP2-11, the 2-11 circuit board pad FP2-11, and the 2-23 anisotropic conductive film positioned between the 2-11 input pad IP2-11 and the 2-11 circuit board pad FP2-11. For example, the 2-11 circuit board pad FP2-11 can be connected to the 2-11 input pad IP2-11 via the 2-23 anisotropic conductive film.

[0255] The 2-12 input bond portion IB2-12 can be defined by stacking the 2-12 input pad IP2-12 and the 2-12 circuit board pad FP2-12 in a plan view. For example, the 2-12 input bond portion IB2-12 can include the 2-12 input pad IP2-12, the 2-12 circuit board pad FP2-12, and the 2-24 anisotropic conductive film positioned between the 2-12 input pad IP2-12 and the 2-12 circuit board pad FP2-12. For example, the 2-12 circuit board pad FP2-12 can be connected to the 2-12 input pad IP2-12 via the 2-24 anisotropic conductive film.

[0256] According to some embodiments, the 2-3 output junction OB2-3 can be omitted. That is, the 2-3 base pad PP2-3 and the 2-3 output pad OP2-3 can be omitted. In addition, the 2-10 output junction OB2-10 can be omitted. That is, the 2-10 base pad PP2-10 and the 2-10 output pad OP2-10 can be omitted.

[0257] The method of measuring the resistance of a display device according to some embodiments may further include measuring the resistance of the 2-2 output bonding portion OB2-2 and the 2-11 output bonding portion OB2-11 using a resistance tester.

[0258] According to some embodiments, a first terminal of the ammeter may be connected to test pad TP2-1 (2-1). Furthermore, a second terminal of the ammeter may be connected to test pad TP2-2 (2-2). Furthermore, a first terminal of the voltmeter may be connected to test pad TP2-3 (2-3). Furthermore, a second terminal of the voltmeter may be connected to test pad TP2-4 (2-4).

[0259] When a constant current flows through the ammeter, a circuit including the 2-1 test line TL2-1, the 2-1 input junction IB2-1, the 2-1 line L2-1, the 2-1 output junction OB2-1, the 2-1 bridge line BR2-1, the 2-2 line L2-2, the 2-2 input junction IB2-2, and the 2-2 test line TL2-2 can be formed. In this case, the resistance applied to the 2-2 output junction OB2-2 can be measured by the first terminal of the voltmeter connected to the 2-3 test pad TP2-3 and the second terminal of the voltmeter connected to the 2-4 test pad TP2-4.

[0260] According to some embodiments, a first terminal of the ammeter can be connected to the 2-8 test pad TP2-8. In addition, a second terminal of the ammeter can be connected to the 2-7 test pad TP2-7. In addition, a first terminal of the voltmeter can be connected to the 2-6 test pad TP2-6. In addition, a second terminal of the voltmeter can be connected to the 2-5 test pad TP2-5.

[0261] When a constant current flows through the ammeter, a circuit including the 2-8 test line TL2-8, the 2-12 input junction IB2-12, the 2-8 line L2-8, the 2-12 output junction OB2-12, the 2-2 bridge line BR2-2, the 2-7 line L2-7, the 2-11 input junction IB2-11, and the 2-7 test line TL2-7 can be formed. In this case, the resistance applied to the 2-11 output junction OB2-11 can be measured by the first terminal of the voltmeter connected to the 2-6 test pad TP2-6 and the second terminal of the voltmeter connected to the 2-5 test pad TP2-5.

[0262] Reference Figure 8 and Figure 9 , a voltage may be applied to the substrate (e.g., Figure 7 substrate 10).

[0263] A state in which a voltage is applied to the substrate through the anti-static wiring ESD may be defined as a driving state. In addition, a state in which a voltage is not applied to the substrate through the anti-static wiring ESD may be defined as a non-driving state.

[0264] According to some embodiments, the operation of connecting the first terminal of the ammeter to the 1-1 test pad TP1-1 may be performed in a non-driving state. That is, the operation of measuring the resistance of the 1-2 output junction OB1-2 may be performed in a non-driving state.

[0265] In the non-driving state, the 1-1 input joint IB1-1, the 1-1 line L1-1, and the 1-1 output joint OB1-1 may not apply a signal to the anti-static wiring ESD. According to some embodiments, in the non-driving state, the 1-1 input joint IB1-1, the 1-1 line L1-1, and the 1-1 output joint OB1-1 can be used to measure the resistance of the 1-2 output joint OB1-2. That is, in order to measure the resistance of the 1-2 output joint OB1-2, no additional input joint, line, and output joint may be required. Therefore, each of the number of substrate pads, the number of input pads, the number of output pads, and the number of circuit board pads can be relatively reduced. Therefore, each of the width of the substrate pad, the width of the input pad, the width of the output pad, and the width of the circuit board pad can be increased. In addition, sufficient space can be ensured in the substrate, the first chip on film COF1, and the circuit board PCB.

[0266] According to some embodiments, the operation of connecting the first terminal of the ammeter to the 2-8 test pad TP2-8 may be performed in a non-driving state. That is, the operation of measuring the resistance of the 2-11 output junction OB2-11 may be performed in a non-driving state.

[0267] In the non-driving state, the 2-12 input joint IB2-12, the 2-8 line L2-8 and the 2-12 output joint OB2-12 may not apply a signal to the antistatic wiring ESD. According to some embodiments, in the non-driving state, the 2-12 input joint IB2-12, the 2-8 line L2-8 and the 2-12 output joint OB2-12 may be used to measure the resistance of the 2-11 output joint OB2-11. In other words, in order to measure the resistance of the 2-11 output joint OB2-11, additional input joints, lines and output joints may not be needed. Therefore, each of the number of substrate pads, the number of input pads, the number of output pads and the number of circuit board pads can be relatively reduced. Therefore, each of the width of the substrate pad, the width of the input pad, the width of the output pad and the width of the circuit board pad can be increased. In addition, sufficient space can be ensured in the substrate, the second chip on film COF2 and the circuit board PCB.

[0268] Embodiments of the present disclosure can be applied to various display devices. For example, the present disclosure is applicable to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for display or information transmission, and medical display devices.

[0269] The foregoing is an illustration of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, it will be readily understood by those skilled in the art that many modifications can be made in the embodiments without substantially departing from the novel teachings and features of the embodiments according to the present disclosure. Therefore, all such modifications are intended to be included within the scope of the embodiments according to the present disclosure as defined in the appended claims and their equivalents. Therefore, it will be understood that the foregoing is an illustration of various embodiments and is not to be construed as being limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate comprising a display area and a non-display area in contact with the display area, wherein a plurality of pixels are positioned in the display area; external wiring, on the substrate in the non-display area; 1-1 substrate pad, on the substrate in the non-display area and connected to the external wiring; a first chip-on-film attached to one side of the substrate and comprising a 1-1 output pad and a 1-1 input pad, the 1-1 output pad being connected to the 1-1 substrate pad, the 1-1 input pad being connected to the 1-1 output pad via a 1-1 line; as well as A circuit board is attached to one side of the chip on the first film and includes a 1-1 circuit board pad and a 1-1 test pad, wherein the 1-1 circuit board pad is connected to the 1-1 input pad and the 1-1 test pad is connected to the 1-1 circuit board pad through a 1-1 test line.

2. The display device according to claim 1, wherein The external wiring is an antistatic wiring.

3. The display device according to claim 1 , further comprising: 1-2 base pad, on the base in the non-display area and adjacent to the 1-1 base pad; a 1-2 output pad, in the first chip-on-film, connected to the 1-2 base pad and adjacent to the 1-1 output pad; a 1-2 input pad, in the first chip-on-film, connected to the 1-2 output pad through a 1-2 line and adjacent to the 1-1 input pad; a 1-2 circuit board pad, connected to the 1-2 input pad and adjacent to the 1-1 circuit board pad, in the circuit board; as well as A 1-2 test pad is connected to the 1-2 circuit board pad through a 1-2 test line in the circuit board and is adjacent to the 1-1 test pad.

4. The display device according to claim 3, further comprising: 1-3 input pad, in the first chip-on-film, and adjacent to the 1-2 input pad, and The 1-3 input pad is connected to the 1-2 line via the 1-3 line.

5. The display device according to claim 4, further comprising: 1-3 base pad, on the base in the non-display area and adjacent to the 1-2 base pad; 1-3 output pad, in the first chip-on-film, connected to the 1-3 base pad and adjacent to the 1-2 output pad; 1-3 circuit board pad, in the circuit board, connected to the 1-3 input pad and adjacent to the 1-2 circuit board pad; as well as The 1-3 test pad is connected to the 1-3 circuit board pad through the 1-3 test line in the circuit board and is adjacent to the 1-2 test pad.

6. The display device according to claim 5, further comprising: 1-4 base pads, on the base in the non-display area and adjacent to the 1-3 base pads; 1-4 output pad, in the first chip-on-film, connected to the 1-4 base pad and adjacent to the 1-3 output pad; A 1-4 input pad, in the first chip-on-film, connected to the 1-4 output pad through a 1-4 line and adjacent to the 1-3 input pad; 1-4 circuit board pad, connected to the 1-4 input pad and adjacent to the 1-3 circuit board pad in the circuit board; as well as The 1-4 test pad is connected to the 1-4 circuit board pad through the 1-4 test line in the circuit board and is adjacent to the 1-3 test pad.

7. The display device according to claim 6, wherein: The 1-2 base pad and the 1-4 base pad are connected to each other through a 1-1 bridge line.

8. The display device according to claim 7, wherein: The external wiring is connected to the 1-1 bridge wire.

9. A method for measuring resistance of a display device, the method comprising: connecting a first output pad in the chip-on-film to a first substrate pad in a non-display area of the substrate, wherein the first substrate pad is connected to an external wiring; connecting a first input pad in the chip on film to a first circuit board pad included in a circuit board, wherein the first input pad is connected to the first output pad through a first line; and A first terminal of an ammeter is connected to a first test pad included in the circuit board, wherein the first test pad is connected to the first circuit board pad through a first test line.

10. The method according to claim 9, further comprising: connecting a second output pad in the chip-on-film to a second substrate pad in the non-display area of the substrate, wherein the second substrate pad is adjacent to the first substrate pad; connecting a second input pad connected to the second output pad via a second line to a second circuit board pad in the circuit board, wherein the second circuit board pad is adjacent to the first circuit board pad; connecting a second terminal of the ammeter to a second test pad in the circuit board and connected to the second circuit board pad through a second test line, wherein the second test line is adjacent to the first test line; connecting a first terminal of a voltmeter to a third test pad in the circuit board, wherein the third test pad is adjacent to the second test pad; and Connecting a second terminal of the voltmeter to a fourth test pad in the circuit board, wherein the fourth test pad is adjacent to the third test pad.

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