Overlay correction for advanced integrated circuit devices

Abstract

Various examples described herein include correction for layer-to-layer or substrate-to-substrate overlay alignment based on feedback from critical dimension (CD) measurements of locations of various features to be formed on a subsequently formed layer of a substrate relative to locations of similar features on a previously formed layer. Layer-to-layer or substrate-to-substrate overlay alignment feedback may be enhanced by determining a position of a plurality of the features on each of the formed layers relative to a first layer in the stack. In addition, layer-to-layer or substrate-to-substrate overlay alignment feedback may be enhanced by determining a position of a plurality of the features on each of the formed layers relative to a previously formed layer. The overlay alignment error may be sent back to the lithographic exposure tool. And accumulated overlay errors can be marked. Other techniques and methods are also disclosed.

Description

[0001] Claim priority

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 63 / 477,694, filed on December 29, 2022, entitled “OVERLAY CORRECTION FOR ADVANCED INTEGRATED-CIRCUIT DEVICES,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The disclosed subject matter generally relates to the field of semiconductors and related industries (e.g., flat panel display and solar cell production facilities). More specifically, in various embodiments, the disclosed subject matter relates to aligning subsequent layers formed on a substrate used to manufacture, for example, integrated circuit devices. Background Art

[0004] Current process flows for advanced integrated circuit device production consist of, for example, up to twelve redistribution layers (RDLs) and twelve via layers. In various process flows, a via layer is a layer that is drilled, etched, or otherwise formed through a corresponding layer to electrically couple one layer to a subsequently formed layer. In this example, the twelve RDLs and twelve via layers may be repeated on both sides of the substrate on which the IC device is formed. However, as the number of process layers increases, the x-coordinate position and the y-coordinate position (e.g., with reference to the plane of the substrate on which the device is formed) may distort (incorrectly positioned) from one layer on the substrate to a subsequent layer. This distortion may be caused, for example, by heating cycles during curing operations in processes such as, for example, an Ajinomoto built-up film (ABF) layer. Summary of the Invention

[0005] This document describes, among other things, various types of techniques, methods, and mechanisms for tracking and correcting alignment errors of integrated circuits formed on a substrate. For example, in various embodiments, the disclosed subject matter is a method for measuring and tracking the dx displacement error and dy displacement error of a selected subset or each of redistribution layer (RDL) and via features on a substrate relative to an exposure position on a first layer. In an alternative embodiment, the disclosed subject matter compares the dx displacement error and dy displacement error to an original planned layout of the substrate, which has defined x- and y-coordinates for each feature to be formed on each layer (e.g., redistribution layer (RDL) and via feature).

[0006] In various embodiments described herein, a method for correcting overlay error in a multi-layer process is disclosed. The method includes exposing a first plurality of features on a first layer of a substrate. The exposure is performed by a photolithography exposure tool. For at least one additional layer of a plurality of additional layers formed above the first layer, x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on the subsequent layer are measured with reference to the same position of at least one of the various positions of the first plurality of features and the defined x-coordinates and y-coordinates of the first plurality of features on the substrate. The method also includes feeding back corrections for the x-coordinate offsets and y-coordinate offsets of the subsequent plurality of features to the photolithography exposure tool before exposing the additional subsequent layer.

[0007] In various embodiments described herein, a system for correcting overlay error in a multi-layer process is disclosed. The system includes a lithographic exposure tool for exposing a first plurality of features on a first layer of a substrate. For at least one additional layer of a plurality of additional layers formed above the first layer, a metrology-based measurement tool measures x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on the subsequent layer with reference to a common location of at least one of the various locations of the first plurality of features and defined x- and y-coordinates of the first plurality of features on the substrate. At least one computational module is configured to feed back corrections for the x- and y-coordinate offsets of the subsequent plurality of features to the lithographic exposure tool before exposing the additional subsequent layer.

[0008] BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The figures in the drawings merely illustrate example implementations of the disclosure and are not to be considered limiting of its scope.

[0010] Figure 1A A cross-sectional view showing a portion of an integrated circuit device structure having features aligned with each other;

[0011] Figure 1B showing a cross-sectional view of a portion of an integrated circuit device structure having progressively misaligned features at each layer indicating accumulation of misalignment in the structure;

[0012] Figure 1C Shown Figure 1B The integrated circuit device structure has the following features: Figure 1B a plan view of a portion of a feature with progressive layer-to-layer misalignment as shown in a cross-sectional view;

[0013] Figure 2A A plan view of a portion of an integrated circuit device structure is shown having misaligned overlay occurring from a first layer to a second layer;

[0014] Figure 2B Shown Figure 2A The integrated circuit device structure has Figure 2AA plan view of the misaligned overlay portion appearing from the second layer to the third layer;

[0015] Figure 2C Shown Figure 2B The integrated circuit device structure has Figure 2B A plan view of the misaligned overlay portion appearing from the third to the fourth layer;

[0016] Figure 2D Shown Figures 2A to 2C The integrated circuit device structure has Figure 2A The first floor to Figure 2C The fourth layer shows a plan view of the gradually misaligned overlay portion;

[0017] Figure 3 An example of a method incorporated into a manufacturing environment to reduce or eliminate misaligned overlay of features according to various embodiments of the disclosed subject matter is shown;

[0018] Figure 4 is an exemplary flow chart of a method for aligning overlay features on subsequent layers; and

[0019] Figure 5 A block diagram is shown that includes an example of a machine on which any one or more of the techniques discussed herein (eg, methods, calculations, etc.) may be performed. DETAILED DESCRIPTION

[0020] The disclosed subject matter relates to providing alignment of features formed on subsequent layers of a substrate used to form, for example, integrated circuit (IC) devices within a fabrication facility (e.g., a semiconductor fabrication facility). In various embodiments, various mechanisms, techniques, and methods are disclosed for providing overlay correction from layer to layer and from substrate to substrate for IC devices.

[0021] In the disclosed subject matter, corrections for layer-to-layer overlay alignment can be improved based on feedback from critical dimension (CD) measurements of the positions of various features to be formed on subsequently formed layers of a substrate relative to the positions of similar features on previously formed layers. However, the layer-to-layer overlay alignment feedback can be enhanced by determining the positions of multiple features on each of the formed layers relative to the first layer in the stack (e.g., comparing the positions of features on each of layers 2 to 12 with the positions of similar or related features on layer 1). Furthermore, the layer-to-layer overlay alignment feedback can be enhanced by determining the positions of multiple features on each of the formed layers relative to the previously formed layers (e.g., comparing the positions of features on layer 8 with the positions of similar features on layer 7).

[0022] Thus, for each formed layer, the position of features on the subsequent layer can be determined relative to CD measurements of either: (1) the position of similar or related features on the first layer; and / or (2) the position of features on the subsequent layer relative to the defined (e.g., planned) x- and y-coordinates of the first plurality of features on the substrate (the planned xy position of each of the plurality of features on the first layer).

[0023] Maintaining a vertically stacked RDL and via structure helps minimize or reduce the interconnect resistance between contacts on subsequent layers (e.g., the resistance value between interconnected vias or RDL contacts). For example, on twelve layers of RDL and vias, even if the performance from one layer to the next (e.g., layer-to-layer performance) may be acceptable, the total overlay error (e.g., the dx coordinate offset and the dy coordinate offset (e.g., displacement error) compared to the first layer) may be quite large. In a typical IC device in this example, the total overlay error can be up to twelve times the layer-to-layer overlay error because offset errors are generally cumulative because position errors tend to occur in the same general direction from layer to layer. However, even if the position errors are not in the same direction from layer to layer, the disclosed subject matter can help minimize or reduce, for example, the interconnect resistance between contacts.

[0024] In various embodiments, the disclosed subject matter includes a method for measuring and tracking dx and dy displacement errors for each layer of a selected subset of, or each RDL and via features on a substrate relative to a location on a first layer. In alternative embodiments, the disclosed subject matter compares the dx and dy displacement errors to an original planned layout of the substrate, which has defined x and y coordinates for each feature to be formed on each layer.

[0025] Based on this data collected from metrology measurements and / or planned positioning positions, a cumulative total overlay error can be calculated. The cumulative total overlay error can be compared to a predefined threshold (e.g., a predefined threshold error value), and when the predefined threshold is exceeded, the user is notified and the affected area of the substrate is identified. Thus, before etching exposed features (or before etching unexposed features, depending on whether a positive photoresist process or a negative photoresist process is used), the measured error can be compared to a predetermined threshold for possible rework, or used as an addition to the offset sent to the lithography tool for manufacturing subsequent substrates with the same type of IC devices formed thereon. These calculated dx offset values and dy offset values can be used to compensate for displacement errors and bring the RDL / via total stack overlay within specifications for rework or subsequent substrate manufacturing.

[0026] As used herein, a substrate may include, for example, various substrate types used in semiconductor and related fields (e.g., flat panel displays, solar cell panels, etc.), as well as other technical fields (e.g., quartz photomask production, production of ceramic windows for radiation monitoring, etc.). In the semiconductor field, a substrate may include an elemental (e.g., silicon or germanium) semiconductor, a compound semiconductor (e.g., silicon carbide, gallium arsenide, or indium gallium arsenide), or various types of polymer resins (e.g., polyethylene terephthalate (PET) on which a film is deposited or a semiconductor layer is otherwise formed), or many other types of substrates independently known in the art.

[0027] Now refer to Figure 1A , shows a cross-sectional view of an aligned version of an overlay structure 100 having features aligned with each other from layer to layer. The overlay structure 100 may be part of an IC device. Figure 1A The features are shown only from a two-dimensional perspective, and thus the overlay structure 100 may be considered as viewed from front to back or from side to side with reference to a cross section of the layers (layers L1 to L3) formed on the substrate. Figure 1A The difference (e.g., with the Figure 1C In contrast, features are aligned in two directions (the x-direction and the y-direction). Thus, the features are aligned in two directions relative to a plane parallel to the surface of the substrate on which the layer is formed (the xy plane).

[0028] Figure 1A 1 is shown as including a first formed feature 101 within a first layer 1 (L1). The first formed feature 101 can be considered, for example, a via or a via formed and subsequently filled with a conductive substance, such as tungsten (W). A second formed feature 103 (e.g., a second filled via) is formed within a second layer (L2) vertically aligned with the first formed feature 101. A third formed feature 105 (e.g., a third filled via) is formed within a third layer (L3) vertically aligned with both the immediately adjacent second formed feature 103 and the lower first formed feature 101. Because each of the subsequently formed features is vertically aligned with each of the corresponding features below, the overall level of contact resistance is reduced or minimized.

[0029] and Figure 1A In contrast to the overlay structure 100, Figure 1B A cross-sectional view of a portion of an integrated circuit device structure 110 is shown with each layer having progressively misaligned features, indicating accumulation of misalignment in the structure 110. The accumulated misalignment of features in the structure 110 results in misalignment from layer to layer and from layer to the substrate on which the structure 110 is formed to the top layers of the structure 110 (e.g., layers 12, Figure 1B The level of contact resistance (eg, interconnect resistance) of the substrate is increased.

[0030] Figure 1B is shown as including a first formed feature 111 within a first layer 1 (L1). The first formed feature 111 may be Figure 1A 1. The first formed feature 101 (e.g., a filled via) is similar or identical to the first formed feature 101 (e.g., a filled via). A second formed feature 113 (e.g., a second filled via) is formed in the second layer (L2), but is positionally misaligned relative to the first formed feature 111. A third formed feature 115 (e.g., a third filled via) is formed in the third layer (L3). The third formed feature 115 is positionally misaligned relative to both the immediately adjacent second formed feature 113 and the lower first formed feature 111. However, in an example not shown, the third formed feature 115 may be positionally misaligned relative to the immediately adjacent second formed feature 113, but positionally aligned relative to the first formed feature 111.

[0031] As the position of each of the subsequently formed features (e.g., second formed feature 113 and third formed feature 115) is misaligned, both the layer-to-layer contact resistance and the overall level of contact resistance increase. Due to the misalignment of each feature within the subsequently formed layer relative to the adjacent features in the previously formed layer, the overall level of contact resistance continues to increase. At least a portion of the increased contact resistance can be the result of, for example, a reduced contact area of the subsequently formed features. Although the shifting of features is shown in a single direction (lower left to upper right), the shifting can occur in any direction or in multiple directions.

[0032] Figure 1C Shown Figure 1B The integrated circuit device structure has the following features: Figure 1B The cross-sectional view 130 shows a plan view of a portion of the layer-to-layer progressive misalignment feature. Figure 1C is shown as including a portion of a first layer (L1) 131, a portion of a second layer (L2) 133, and a portion of a third layer (L3) 135. The third layer 135 shows a feature 137 formed within the third layer 135. The feature 137 can be considered to be Figure 1B Each of the following layers (first layer 131 and second layer 133) also has features formed therein (e.g., such as Figure 1B first forming feature 111 and second forming feature 113).

[0033] Figure 2A A plan view 200 of a portion of an integrated circuit device structure is shown having misaligned overlay occurring from a first layer (L1) 201 to a second layer (L2) 203. Based on the design rules for a given IC device, critical dimension (CD) measurements may be performed to determine whether the degree of overlay misalignment is within predetermined tolerances.

[0034] For example, considering that the predetermined tolerance level threshold for overlay misalignment in the x-direction is less than or equal to 10 μm and the predetermined tolerance level threshold for overlay misalignment in the y-direction is less than or equal to 10 μm, giving a total overlay misalignment of up to 14.0 μm, if the first misalignment 207 is found to be 5 μm from the center position of the second layer feature 205 in the +x direction and 5 μm from the center position in the +y direction, then the misalignment is considered to be within the predetermined tolerances shown above for a total amount of the first misalignment 207 of approximately 7.1 μm.

[0035] Figure 2B Shown Figure 2A The integrated circuit device structure has Figure 2A A plan view 210 of a portion of the misaligned overlay from the second layer (L2) 203 to the third layer 211 (L3). Figure 2A For the first two layers of the portion of the device structure shown in FIG, and following the same or similar design rules for a given IC device between the second layer 203 and the third layer 211, a second CD measurement can be performed to determine whether the degree of misalignment is within predetermined tolerances for the second and third layers. For example, if the second misalignment 215 is found to be 3 μm from the center position of the third layer feature 213 in the +x direction and 3 μm from the center position in the +y direction, then for a total amount of the second misalignment 215 of approximately 4.2 μm, the misalignment is still considered to be within the predetermined tolerance example of x ≤ 10 μm and y ≤ 10 μm.

[0036] However, one must also consider Figure 2A 2. The first misalignment 207 is approximately 7.1 μm. Thus, in this example, the amount of the first misalignment 207 and the second misalignment 215 are in the same direction (e.g., equal amounts in both the x-direction and the y-direction when measured layer by layer). Thus, the total amount of misalignment from the first layer (L1) 201 to the third layer (L3) is 8 μm in the +x direction and 8 μm in the +y direction, for a total of 11.3 μm.

[0037] Figure 2C Shown Figure 2B The integrated circuit device structure has Figure 2B A plan view 230 of a portion of the misaligned overlay that occurs from the third layer (L3) to the fourth layer (L4) 231. Figure 2A and Figure 2BFor the first three layers of the portion of the device structure shown in FIG, and following the same or similar design rules for a given IC device, a third CD measurement can be performed to determine whether the degree of misalignment remains within a predetermined tolerance for the third and fourth layers. For example, if the third misalignment 235 is found to be 4 μm from the center position of the fourth layer feature 233 in the +x direction and 4 μm from the center position in the +y direction, then for a total amount of the third misalignment 235 of approximately 5.7 μm, the overlay misalignment can still be considered to be within the predetermined tolerance.

[0038] However, from Figure 2A The first misalignment 207 of approximately 7.1 μm, the second misalignment 215 of approximately 4.2 μm, and the third misalignment 235 of approximately 5.7 μm are all considered cumulatively. Therefore, the total amount of misalignment from the first layer (L1) 201 to the fourth layer (L4) is 17.0 μm because each misalignment is in the same direction (e.g., equal amounts in the x-direction and the y-direction for layer-to-layer measurements). Therefore, in these examples where the misalignments are all in the same direction, the cumulative misalignments are directly additive. Therefore, the total overlay misalignment may not be within the predetermined tolerance level, and the IC device may be considered "bad" (NG), meaning that for a total overlay misalignment of 14.0 μm, the device failed to meet the predetermined tolerance level thresholds of less than or equal to x=10 μm and y=10 μm.

[0039] Therefore, at this point, the substrate on which the particular integrated circuit device is formed does not meet the predetermined tolerance level. For example, if one or more layer-to-layer tolerance values are not met, then an "offset coordinate value" may be sent to the lithography exposure tool (e.g., see below for reference). Figure 3 The stepper (described in more detail below) is used for future or subsequent substrate exposure and processing. In this example, if the misalignment is off by 4 μm in the +x direction and 4 μm in the +y direction, the offset coordinate value can be used to instruct the lithography exposure tool to expose a given feature by providing a coordinate offset of 4 μm in the -x direction and a coordinate offset of 4 μm in the -y direction.

[0040] Additionally, at least one of three steps can now be considered: (1) the entire substrate may be scrapped; (2) the last layer may be reworked after sending the offset coordinate values back to, for example, a lithography exposure tool that exposes features on the substrate; or (3) each of the dies that failed to pass the overlay misalignment tolerance value is marked. Then, after singulation, the affected die or dies marked as "bad" can be discarded. If the entire substrate is scrapped, the offset coordinates can be sent to a lithography stepper that exposes features on the substrate for subsequent substrate processing. In this way, for a given integrated circuit design, the desired offset can be saved in a memory location within the process recipe for all future substrates. Reference Figure 3 Describes an example of an offset memory location.

[0041] In various embodiments, an end user may be given the option to enable or disable layer-to-layer tolerance values for one or more layers relative to a first layer, or from one layer to a subsequent layer, with respect to tolerance values. For example, an end user may desire good overlay with the previous layer, and may tolerate total overlay drift relative to the first layer, as long as the total overlay drift is within a user-defined specification (e.g., a predetermined total overlay drift value). In other examples, an end user may desire to maintain good overlay relative to the first layer, and tolerate slightly more of a predefined value from one layer to a second layer. Each of these examples is contemplated by the disclosed subject matter. Additionally, "factor ratios" of additional compensation may be applied. For example, an end user may change or pre-select an additional compensation percentage if available to bring a given layer or layers back into tolerance. In this example, if the additional compensation value is 3 μm, where the factor ratio is set to 0.5, the final compensation value would be 3 μm (0.5) = 1.5 μm. These additional factors may also be incorporated into the signal sent, for example, at the "bad" (NG) operation 341, as described below with reference to Figure 3 described.

[0042] Now refer to Figure 2D , showing Figures 2A to 2C The integrated circuit device structure has Figure 2A The first layer (L1) 201 to Figure 2C A plan view 250 of a portion of the fourth layer (L4) 231 that appears gradually misaligned and overlaid.

[0043] Figure 3 An example of a method incorporated into manufacturing environment 300 to reduce or eliminate misaligned overlay according to various embodiments of the disclosed subject matter is shown. Figure 3 The system is shown as including a lithography module 310, a measurement analysis module 330, and a CD measurement module and input module 350. The CD measurement module and input module 350 is shown as including at least one measurement tool 351 (which can be an optical measurement tool, a laser-based measurement tool, an x-ray measurement tool, or any other type of measurement tool) and a user input overlay result module 353. In various embodiments, at least some of the lithography module 310, the measurement analysis module 330, and the CD measurement module and input module 350 can all communicate with each other via one or more networks, as described, for example, below with reference to Figure 5 described.

[0044] The lithography module 310 includes a substrate input database 311, a lithography exposure tool 313, and a substrate output database 315. The substrate input database 311 may include one or more memory devices (e.g., solid-state memory, a hard drive, random access memory (RAM), or any other type of volatile or non-volatile memory known in the art, such as described below with reference to Figure 5 ). The substrate input database 311 may be used to store patterns and various coordinates (e.g., x- and y-coordinates referenced to known locations) where exposure is to be performed or scanned on a substrate by the photolithography exposure tool 313. The substrate input database 311 may be used to store various coordinate locations on a substrate to drive the photolithography exposure tool 313. In addition, the substrate input database 311 may be used to store at least a portion of other process recipes for fabricating devices on the substrate.

[0045] As described above, the lithography exposure tool 313 may include various types of projection exposure systems, such as steppers and scanners. The substrate output database 315 may include one or more memory devices (e.g., solid-state memory, hard drive, random access memory (RAM), or any other type of volatile or non-volatile memory known in the art) that are the same or similar to the substrate input database 311. The substrate output database 315 may be used to store, for example, various coordinate offsets received from other components within the manufacturing environment 300, such as those received from the measurement analysis module 330 and the CD measurement module and input module 350. In various embodiments, the substrate input database 311 and the substrate output database 315 may be different parts of a common database.

[0046] The measurement analysis module 330 includes a first calculation module 333, a second calculation module 331, and a measurement overlay database 335. The measurement overlay database 335 receives measurement data and / or other input data from the CD measurement and input module 350.

[0047] The first computation module 333 receives raw overlay data from both the lithography exposure tool 313 and the second computation module 331. The first computation module 333 also supplies data to the second computation module 331. In an embodiment, the first computation module 333 receives the raw overlay data and, as needed, converts it into a form that can be read by other components within the manufacturing environment 300.

[0048] The second calculation module 331 calculates any offset that may be expected by the lithography exposure tool 313 and creates a correction file that can be stored, for example, in the substrate output database 315 or another memory / storage location. The lithography exposure tool 313 can later apply the stored correction if or when needed. In an embodiment, the second calculation module 331 can also calculate the cumulative or total overlay error, as described below with reference to Figure 4 If the value of the error exceeds a predefined threshold, the cumulative or total overlay error may be transmitted to a host computer (not shown). Thus, the first calculation module 333 and the second calculation module 331 calculate data and supply the data to the lithography exposure tool 313, as described below with reference to Figure 4 Describe in more detail.

[0049] The output 337 from the first computation module 333 is graphically illustrated to feed back a correction value to the first computation module 333 and / or the lithography exposure tool 313, for example, at a "pass" operation 339. Based on a determination that the value from the output 337 is outside a predetermined tolerance level threshold for overlay misalignment or an accumulated value of misalignment, a signal is sent to the second computation module 331 and / or the lithography exposure tool 313 at a "bad" (NG) operation 341. An operator (e.g., a process or line engineer) can then determine at that point whether to rework the substrate being manufactured or simply scrap the substrate.

[0050] Furthermore, after reading and understanding the disclosed subject matter, one of ordinary skill in the art will recognize that the first calculation module 333, the second calculation module 331, and the measurement overlay database 335 can include a single memory containing a database and one or more hardware-based processors to perform calculations. The calculations can include, for example, the determination of cumulative overlay error, the comparison of individual overlay errors to predetermined tolerance level thresholds for overlay misalignment, and possible corrections for the lithography exposure tool 313. Thus, the various components shown in the measurement analysis module 330 can be grouped together into a single component, or can include separate components.

[0051] As described above, the CD measurement module and input module 350 is shown to include at least one measurement tool 351 (which can be an optical measurement tool, a laser-based measurement tool, an x-ray measurement tool, or any other type of measurement tool) and a user input overlay results module 353. The measurement tool 351 can include one or more of various types of CD measurement tools known in the art, such as optical and mechanical profilometers, optical and electron microscopes, angle-resolved light scattering and scatterometry tools, or various other types of other manual inspection and automated inspection tools known in the art. CD measurements can be performed manually or automatically by the measurement tool 351. The user input overlay results module 353 provides input to the CD measurement and input module 350, where offline measurements can be input into the manufacturing environment 300 from another location or tool, for example, manually or automatically.

[0052] Figure 4 is an exemplary flow chart 400 of a method for aligning overlay features on an initial layer and subsequent layers formed on a substrate. Figure 3At operation 401, a first plurality of features are exposed on a first layer of a substrate. The features may include, for example, various types of through-substrate vias (TSVs, including through-silicon vias if the substrate is a silicon wafer), conductive contacts for RDLs, and other planned features. At operations 405 and 407, the x-coordinate offset and the y-coordinate offset are measured, respectively, for example, by measurement tool 351. If necessary, at operation 409, corrections for the x-coordinate offset and the y-coordinate offset are fed back (e.g., before etching the features) to the lithography module 310. In various embodiments, more specifically, the corrections are fed back to the lithography exposure tool 313.

[0053] If more than one layer has been exposed, then an accumulated overlay error, as defined herein, may be determined at operation 411. At operation 413, a determination is made as to whether additional layers are to be added to the substrate. If additional layers are to be added, then the method of exemplary flowchart 400 loops back to operation 403 at operation 415 to repeat at least a portion of the method again. For example, all of operations 405 through 411 may be performed again for at least one additional layer in the plurality of additional layers formed above the first layer. If no additional layers are to be added to the substrate, then a comparison of the total overlay error to a predefined threshold may be performed at operation 417.

[0054] The methods and techniques shown and described herein may be used as follows: Figure 5 The discussed machine 500 may be executed in part or in whole. Figure 5 An exemplary block diagram is shown of a machine 500 on which any one or more of the techniques discussed herein (e.g., methods, computations, etc.) may be performed. In various examples, machine 500 may operate as a standalone device or may be connected (e.g., networked) to other machines.

[0055] In a networked deployment, the machine 500 may operate in the capacity of a server or a client machine in server-client network environment. In one example, the machine 500 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 500 may be a personal computer (PC), a tablet, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a network router, a switch or bridge, or any other machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by the machine. While a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), or other computer cluster configurations.

[0056] Examples as described herein may include, or may be operated by, logic or multiple components or mechanisms. A circuit system is a collection of circuits implemented in a tangible entity including hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system may change over time and with potential hardware changes. A circuit system includes components that, when operated, can perform a specified operation individually or in combination. In one example, the hardware of the circuit system can be immutably designed to perform a specific operation (e.g., hardwired). In one example, the hardware comprising the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include computer-readable media that are physically modified (e.g., magnetically, electrically, such as by a change in physical state or a transformation of another physical property) to encode instructions for a specific operation. When the physical components are connected, the underlying electrical properties of the hardware components may, for example, change from insulating properties to conductive properties or vice versa. The instructions enable embedded hardware (e.g., execution units or loading mechanisms) to form members of the circuit system in hardware via variably connected components to perform portions of a specific operation when operated. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In one example, any physical component can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system or by a third circuit in the second circuit system at a different time.

[0057] Machine 500 (e.g., a computer system) may include a hardware-based processor 501 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), main memory 503, and static memory 505, some or all of which may communicate with each other via an interconnect 530 (e.g., a bus). Machine 500 may also include a display device 509, an input device 511 (e.g., an alphanumeric keyboard), and a user interface (UI) navigation device 513 (e.g., a mouse). In one example, display device 509, input device 511, and UI navigation device 513 may include at least a portion of a touch screen display. Machine 500 may additionally include a storage device 520 (e.g., a drive unit), a signal generating device 517 (e.g., a speaker), a network interface device 550, and one or more sensors 515 (such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors). The machine 500 may include an output controller 519, such as a serial controller or interface (e.g., a universal serial bus (USB)), a parallel controller or interface, or other wired or wireless (e.g., an infrared (IR) controller or interface, near field communication (NFC), etc.), which is coupled to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0058] The storage device 520 may include a machine-readable medium on which is stored one or more sets of data structures or instructions 524 (e.g., software or firmware) embodying or utilized by any one or more of the techniques or functionality described herein. The instructions 524 may also reside, completely or at least partially, within the main memory 503, within the static memory 505, within the mass storage device 507, or within the hardware-based processor 501 during execution by the machine 500. In an example, one or any combination of the hardware-based processor 501, the main memory 503, the static memory 505, or the storage device 520 may constitute a machine-readable medium.

[0059] Although a machine-readable medium is considered a single medium, the term “machine-readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store one or more instructions 524.

[0060] The term "machine-readable medium" may include any medium that can store, encode, or carry instructions for execution by the machine 500 and that causes the machine 500 to perform any one or more of the techniques of the present disclosure, or that can store, encode, or carry data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory and optical and magnetic media. Thus, a machine-readable medium is not a transient propagating signal. Specific examples of large-scale machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic or other phase-change or state-change memory circuits; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0061] The instructions 524 may also be sent or received over the communication network 521 using a transmission medium via the network interface device 550 using any of a variety of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include, among others, a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., a wireless network known as a cellular network). The Institute of Electrical and Electronics Engineers (IEEE) 802.22 family of standards, known as 26 family of standards), IEEE 802.25.4 family of standards, peer-to-peer (P2P) networks. In one example, network interface device 550 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to communications network 521. In one example, network interface device 550 may include multiple antennas for wireless communication using at least one of single-input, multiple-output (SIMO) technology, multiple-input, multiple-output (MIMO) technology, or multiple-input, single-output (MISO) technology. The term "transmission medium" should be understood to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 500, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0062] As used herein, the term "or" may be interpreted as inclusive or exclusive. Furthermore, upon reading and understanding the disclosure provided, one of ordinary skill in the art will appreciate other embodiments. Furthermore, one of ordinary skill in the art will readily appreciate that various combinations of the techniques and examples provided herein may all be applied in various combinations.

[0063] Throughout the specification, multiple instances can be implemented as parts, operations or structures described as single instances. Although each operation is shown and described as a separate operation, one or more of each operation can be performed simultaneously, and unless otherwise noted, these operations are not required to be performed in the order of illustration. The structure and function presented as a separate component in the example configuration can be implemented as a combined structure or parts. Similarly, the structure and function presented as a single component can be implemented as a separate component. These and other variations, modifications, additions and improvements all fall within the scope of the subject matter described herein.

[0064] Furthermore, although not explicitly shown, it will be understood by those skilled in the art that each of the various arrangements, amounts, and quantities of elements may vary (e.g., the number of layers to be added to the substrate, the number of features per layer measured for x- and y-coordinate positions, the number of comparisons to predefined thresholds, etc.). Furthermore, each of the examples shown and described herein represents only one possible configuration or method and should not be considered to limit the scope of the present disclosure.

[0065] Although various embodiments have been discussed individually, these individual embodiments are not intended to be considered independent techniques or designs. As indicated above, each of the various parts can be interrelated, and each can be used alone or in combination with other embodiments discussed herein. For example, although various embodiments of operations, systems, and processes have been described, these methods, operations, systems, and processes can be used alone or in various combinations.

[0066] Therefore, as will be apparent to those skilled in the art upon reading and understanding the disclosure provided herein, many modifications and variations may be made. Based on the foregoing description, in addition to those methods and apparatuses enumerated herein, functionally equivalent methods and apparatuses within the scope of the present disclosure will be apparent to those skilled in the art. Portions and features of some embodiments may be included in portions and features of other embodiments, or replace portions and features of other embodiments. Such modifications and variations are intended to fall within the scope of the appended claims. Therefore, the present disclosure is limited only by the terms of the appended claims and the full scope of equivalents to which these claims are entitled. It will also be understood that the terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting.

[0067] The Abstract is provided to allow the reader to quickly ascertain the essence of the present disclosure. It is submitted with the understanding that it will not be used to interpret or limit the claims. Furthermore, in the foregoing Detailed Description, it can be seen that various features may be grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be construed as limiting the claims. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

[0068] The description provided herein includes illustrative examples, devices and apparatus that embody various aspects of the subject matter described in this invention document. In this description, for the purpose of explanation, many specific details are set forth in order to provide an understanding of the various embodiments of the subject matter discussed. However, it will be apparent to one of ordinary skill in the art that the various embodiments of the disclosed subject matter can be practiced without these specific details. In addition, well-known structures, materials and techniques are not shown in detail to avoid obscuring the various exemplified embodiments. As used herein, the terms "about", "approximately" and "substantially" may refer to values within ±10% of a given value or range of values, for example.

[0069] The following numbered examples are specific embodiments of the disclosed subject matter.

[0070] Example 1: A method for correcting overlay error in a multi-layer process. In an embodiment, the method may include: exposing a first plurality of features on a first layer of a substrate, wherein the exposing is performed by a photolithography exposure tool. In an embodiment, for at least one additional layer of a plurality of additional layers formed above the first layer: measuring x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on a subsequent layer with reference to a common position of at least one feature in the first plurality of features and defined x-coordinates and y-coordinates of the first plurality of features on the substrate; and feeding back correction information for the x-coordinate offsets and the y-coordinate offsets of the subsequent plurality of features to the photolithography exposure tool before exposing additional subsequent layers.

[0071] Embodiment 2: The method of embodiment 1, wherein the first plurality of features and the subsequent plurality of features comprise conductive contacts of a redistribution layer (RDL).

[0072] Embodiment 3: The method of any preceding embodiment, wherein the first plurality of features and the subsequent plurality of features comprise a plurality of interconnected vias.

[0073] Embodiment 4: The method of any preceding embodiment, wherein the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features from the exposure positions of the plurality of features is performed automatically.

[0074] Embodiment 5: The method according to any of the preceding embodiments further comprises using user input to overlay results in addition to the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features.

[0075] Embodiment 6: The method according to any one of the preceding embodiments further includes calculating correction values for the x-coordinate offset and the y-coordinate offset based on shifting the x-coordinate offset and the y-coordinate offset of subsequent multiple features to the center position of the exposure position of the first multiple features.

[0076] Embodiment 7: The method according to any one of the preceding embodiments, further comprising comparing the total overlay error of a total of n layers with a predefined threshold of the n layers.

[0077] Embodiment 8: The method of embodiment 7 further comprising, based on determining that the total overlay error is greater than the predefined threshold, reworking one or more layers to provide a total overlay value less than or equal to the predefined threshold.

[0078] Embodiment 9: The method according to any one of the preceding embodiments further includes determining a cumulative overlay error after forming each layer on the substrate; and determining whether the cumulative overlay error is less than or equal to a predefined threshold determined for each layer.

[0079] Example 10. A system for correcting overlay errors in a multi-layer process. In various embodiments, the system may include a lithographic exposure tool for exposing a first plurality of features on a first layer of a substrate. In an embodiment, for at least one additional layer of a plurality of additional layers formed above the first layer: measuring x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on a subsequent layer using a metrology-based measurement tool with reference to a common position of at least one of the exposure positions of the first plurality of features and defined x-coordinates and y-coordinates of the first plurality of features on the substrate; and at least one computational module for feeding back corrections to the x-coordinate offsets and y-coordinate offsets of the subsequent plurality of features to the lithographic exposure tool before exposing additional subsequent layers.

[0080] Embodiment 11. The system of embodiment 10, wherein the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features from the exposure positions of the plurality of features is performed automatically.

[0081] Embodiment 12: The system of any one of Embodiments 10 or 11, further comprising using user input to overlay results in addition to the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features.

[0082] Embodiment 13. The system according to any one of the preceding embodiments 10 to 12 further includes calculating correction values for the x-coordinate offset and the y-coordinate offset based on shifting the x-coordinate offset and the y-coordinate offset of subsequent multiple features to the center position of the exposure position of the first multiple features.

[0083] Embodiment 14: The system according to any one of the preceding embodiments 10 to 13, further comprising comparing the total overlay error of a total of n layers with a predefined threshold value of the n layers.

[0084] Embodiment 15: The system of embodiment 14, further comprising, based on determining that the total overlay error is greater than the predefined threshold, reworking one or more layers to provide a total overlay value less than or equal to the predefined threshold.

[0085] Embodiment 16: The system according to any one of the preceding embodiments 10 to 15 further includes determining a cumulative overlay error after forming each layer on the substrate; and determining whether the cumulative overlay error is less than or equal to a predefined threshold determined for each layer.

[0086] Embodiment 17: The method or system according to any one of the preceding embodiments, wherein the embodiments are also applicable to substrate-to-substrate.

Claims

1. A method for correcting overlay errors in a multi-layer process, the method comprising: receiving a substrate having a first plurality of features in a first layer at a metrology tool; measuring x-coordinate offsets and y-coordinate offsets of the first plurality of features on the first layer; receiving the substrate having a subsequent plurality of features on a subsequent layer at a metrology tool; measuring x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on a subsequent layer with reference to the same location of at least one feature in the first plurality of features and the defined x- and y-coordinates of the at least one feature in the first plurality of features on the substrate; as well as Corrections for the x-coordinate offset and the y-coordinate offset for the subsequent plurality of features are fed back to a lithographic exposure tool prior to exposing additional subsequent layers. 2 . The method of claim 1 , wherein the first plurality of features and the subsequent plurality of features comprise conductive contacts of a redistribution layer (RDL). 3 . The method of claim 1 , wherein the first plurality of features and the subsequent plurality of features comprise a plurality of interconnected vias.

4. The method of claim 1 , wherein the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features from exposure positions of the plurality of features is performed automatically.

5. The method of claim 1, further comprising using user input to overlay results in addition to the measuring of the x-coordinate offset and the y-coordinate offset for at least a portion of the subsequent plurality of features.

6. The method of claim 1 , further comprising calculating values for corrections for the x-coordinate offset and the y-coordinate offset based on shifting the x-coordinate offset and the y-coordinate offset of a subsequent plurality of features to a center position of the exposure positions of the first plurality of features.

7. The method of claim 1, further comprising comparing a total overlay error of a total of n layers with a predefined threshold for the n layers.

8. The method according to claim 7, further comprising: Based on determining that the total overlay error is greater than the predefined threshold, one or more layers are reworked to provide a total overlay value that is less than or equal to the predefined threshold.

9. The method according to claim 1, further comprising: determining a cumulative overlay error after forming each layer on the substrate; as well as It is determined whether the accumulated overlay error is less than or equal to a predefined threshold determined for each layer.

10. A system for correcting overlay errors in a multi-layer process, the system comprising: A measurement tool, the measurement tool being configured to: receiving a substrate having a first plurality of features in a first layer; measuring x-coordinate offsets and y-coordinate offsets of the first plurality of features on the first layer; and sending correction information to a lithography exposure tool; wherein the metrology tool is for receiving the substrate having a subsequent plurality of features on a subsequent layer, and for measuring x-coordinate offsets and y-coordinate offsets of a subsequent plurality of features on a subsequent layer with reference to the same position of at least one feature in the first plurality of features and the defined x-coordinates and y-coordinates of the at least one feature in the first plurality of features on the substrate, and for sending correction information for the x-coordinate offsets and the y-coordinate offsets of the subsequent plurality of features back to the lithography exposure tool before exposing another subsequent layer.

11. The system of claim 10, wherein the measuring of the x-coordinate offset and the y-coordinate offset of at least a portion of the subsequent plurality of features from the exposure positions of the plurality of features is performed automatically.

12. The system of claim 10, further comprising overlaying results using user input in addition to the measurements of the x-coordinate offset and the y-coordinate offset for at least a portion of the subsequent plurality of features.

13. The system of claim 10, further comprising calculating values for corrections for the x-coordinate offset and the y-coordinate offset based on shifting the x-coordinate offset and the y-coordinate offset of a subsequent plurality of features to a center position of the exposure positions of the first plurality of features.

14. The system of claim 10, further comprising comparing a total overlay error of a total of n layers with a predefined threshold for the n layers.

15. The system of claim 14, further comprising: Based on determining that the total overlay error is greater than the predefined threshold, one or more layers are reworked to provide a total overlay value that is less than or equal to the predefined threshold.

16. The system of claim 10, further comprising: determining a cumulative overlay error after forming each layer on the substrate; as well as It is determined whether the accumulated overlay error is less than or equal to a predefined threshold determined for each layer.

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