Phased array antenna architecture

Abstract

A radio system architecture includes a receiver having a plurality of sub-arrays in a phased array configured to perform carrier aggregation (CA) and multiple input multiple output (MIMO) signal processing and provide independent beam management for a plurality of radio frequency (RF) signals received at each of the plurality of sub-arrays; and a data processor configured to receive the signal from the receiver and extract information about the wireless communication.

Description

Technical Field

[0001] The present disclosure relates generally to electronics, more particularly to wireless communication systems, and even more particularly to wireless communication devices with multiple-input and multiple-output (MIMO) and carrier aggregation (CA) capabilities. Background Art

[0002] Wireless communication devices and technologies are becoming increasingly common as communication systems operate at millimeter wave (mmW) and near-mmW frequencies. Some communication methods use a technique known as multiple-input, multiple-output (MIMO) and also use carrier aggregation (CA), where multiple signals on one or more frequencies are processed simultaneously.

[0003] 5G mmW communication systems typically use a time-domain duplex (TDD) communication method. For TDD systems, maintaining synchronization and preventing interference is crucial, which can be challenging when switching between transmit and receive modes. A guard period is used to isolate transmit and receive events, with a configurable total guard time expressed as an integer number of symbols.

[0004] Relative frame timing alignment is an important metric at the receiver in user equipment (UE). The Third Generation Partnership Project (3GPP) has defined the Maximum Receive Timing Difference (MRTD) as the maximum relative receive timing difference that the UE must be able to handle. MRTD includes the base station relative time alignment error (TAE) and the RF propagation delay difference (ΔTprop). In other words, MRTD = TAE + ΔTprop. For example, in a known 5G communication system that implements a single 5 GHz downlink channel bandwidth with common beam management (CMB) to enable carrier aggregation, the MRTD can be as tight as 0.26 usec. Due to the extreme wideband channel bandwidth, this arrangement introduces additional limitations and performance degradation. Summary of the Invention

[0005] Various implementations of systems, methods, and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, certain governing features are described herein.

[0006] Details of one or more specific implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions of the following figures may not be drawn to scale.

[0007] One aspect of the present disclosure provides a receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter wave (mmW) frequencies, the receiving system comprising: a phased array, the phased array having a plurality of groups, each group having a pair of sub-array structures, each sub-array structure having a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element having a low noise amplifier (LNA) and a phase shifter (PS), the plurality of groups comprising a first high-band (HB) group and a first low-band (LB) group. a downconverter circuit selectively connected to each subarray structure in a first high-band (HB) group and a first low-band (LB) group, each downconverter circuit having a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; and a combining circuit connected to each of the downconverter circuits selectively connected to the first high-band (HB) group and the first low-band (LB) group, the combining circuit being configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port.

[0008] Another aspect of the present disclosure provides a method for signal processing, the method comprising: receiving at least two radio frequency (RF) signals at a receiver; selectively phase shifting the at least two radio frequency (RF) signals; selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; simultaneously downconverting the at least two RF signals to an intermediate frequency (IF) signal; and connecting the at least two IF signals to at least one selected output port.

[0009] Another aspect of the present disclosure provides an apparatus comprising: means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; means for simultaneously downconverting the at least two RF signals to an intermediate frequency (IF) signal; and means for connecting the at least two IF signals to at least one selected output port.

[0010] Another aspect of the present disclosure provides a radio system architecture including: a receiver having a plurality of subarrays in a phased array, the plurality of subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing, and provide independent beam management for a plurality of radio frequency (RF) signals received at each of the plurality of subarrays; and a data processor configured to receive a signal from the receiver and extract information about wireless communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the drawings, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with alphabetic characters, such as "102a" or "102b," the alphabetic characters may distinguish between two similar parts or elements in the same figure. Alphabetic characters may be omitted from a reference numeral when it is intended that all parts having the same reference numeral in all figures be included.

[0012] Figure 1 is a diagram illustrating a wireless device communicating with a wireless communication system.

[0013] Figure 2A is a block diagram illustrating a wireless device in which example techniques of this disclosure may be implemented.

[0014] Figure 2B is a block diagram illustrating a wireless device in which example techniques of this disclosure may be implemented.

[0015] Figure 3 A schematic diagram showing the sub-array structure of a phased array.

[0016] Figure 4 shows a schematic diagram of a downconverter.

[0017] Figure 5 A schematic diagram of the signal combining circuit is shown.

[0018] Figure 6 A schematic diagram of an exemplary embodiment of a phased array is shown.

[0019] Figure 7 A schematic diagram of an exemplary embodiment of a phased array is shown.

[0020] Figure 8 A schematic diagram of an exemplary embodiment of a phased array is shown.

[0021] Figure 9 A schematic diagram of an exemplary embodiment of a phased array is shown.

[0022] Figure 10 A schematic diagram of an exemplary embodiment of a phased array is shown.

[0023] Figure 11 is a flow chart describing one example of the operation of a method for signal processing.

[0024] Figure 12 is a functional block diagram of a device for signal processing.

[0025] Figure 13 is a flow chart describing one example of the operation of a method for signal processing.

[0026] Figure 14 is a functional block diagram of a device for signal processing. DETAILED DESCRIPTION

[0027] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0028] A communication device may include a phased array antenna system and may include receive (Rx) MIMO capabilities. For example, a 5G New Radio (NR) communication device may support multiple transmitters, multiple receivers, and be capable of communicating on multiple communication bands. In some examples, a communication device may also include carrier aggregation (CA), allowing it to communicate on multiple communication bands simultaneously.

[0029] Figure 1 1 is a diagram showing a wireless device 110 communicating with a wireless communication system 120. The wireless communication system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G NR (New Radio) system, or some other wireless system. The CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown including two base stations 130 and 132 and one system controller 140. In general, a wireless communication system may include any number of base stations and any set of network entities.

[0030] Wireless device 110 may also be referred to as user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device 110 may be a cellular phone, a smartphone, a tablet device, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet computer, a cordless phone, a medical device, an automobile, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device 110 may communicate with wireless communication system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., broadcast station 134) and / or signals from satellites (e.g., satellites 150 in one or more global navigation satellite systems (GNSS)). Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0031] The wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some embodiments, carrier aggregation is used to transmit a single data stream across multiple carriers, as opposed to separate carriers for the respective data streams. The wireless device 110 is capable of operating in a variety of communication bands, including, for example, those used by LTE, WiFi, 5G, or other communication bands within a wide frequency range. The wireless device 110 is also capable of communicating directly with other wireless devices without communicating through a network.

[0032] Generally speaking, carrier aggregation (CA) can be categorized into two types: intra-band CA and inter-band CA. Intra-band CA refers to the operation of multiple carriers within the same frequency band, while inter-band CA refers to the operation of multiple carriers within different frequency bands.

[0033] Figure 2A is a block diagram illustrating a wireless device 200 in which exemplary techniques of the present disclosure may be implemented. The wireless device 200 may be, for example, Figure 1 An implementation of the wireless device 110 is illustrated.

[0034] Figure 2A An example of a transceiver 220 is shown with a transmitter 230 and a receiver 250. In general, the conditioning of the signals in the transmitter 230 and the receiver 250 may be performed by one or more stages of amplifiers, filters, upconverters, downconverters, etc. These circuit blocks are based on Figure 2A The configuration shown in is arranged differently. In addition, Figure 2A Other circuit blocks not shown in FIG may also be used to condition the signals in transmitter 230 and receiver 250, such as phase shifters as discussed further below. Figure 2A Any signal in , or any other diagram in the accompanying drawings, may be single-ended or differential. Figure 2A Some circuit blocks in the circuit can also be omitted.

[0035] exist Figure 2AIn the example shown, the wireless device 200 generally includes a transceiver 220 and a data processor 210. The data processor 210 may include a processor 296 operatively coupled to a memory 298. The memory 298 may be configured to store data and program code, generally indicated using reference numeral 299, and may generally include analog and / or digital processing components. The transceiver 220 includes a transmitter 230 and a receiver 250 that support bidirectional communication. In general, the wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of the transceiver 220 may be implemented on one or more analog integrated circuits (ICs), radio frequency integrated circuits (RFICs), mixed-signal ICs, and the like.

[0036] A transmitter or receiver can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multiple stages of frequency conversion between radio frequency (RF) and baseband, for example, in the case of a receiver, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 2A In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0037] In the transmit path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by data processor 210 into I and Q analog output signals (e.g., I and Q analog output signals) for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) to transceiver 220 in a digital form.

[0038] Within transmitter 230, lowpass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted image frequencies caused by the preceding digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from lowpass filters 232a and 232b, respectively, and provide I and Q baseband signals. Upconverter 240, including upconverting mixers 241a and 241b, upconverts the I and Q baseband signals using I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 290, and provides the upconverted signals. Filter 242 filters the upconverted signals to remove unwanted image frequencies caused by the frequency upconversion and noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to achieve the desired output power level and provide the transmit RF signal. The transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antenna 248, or alternatively, the transmit RF signal may be sent to a separate transmit antenna than the separate receive antenna. While the examples discussed herein utilize I and Q signals, those skilled in the art will appreciate that the components of the transceiver may be configured to utilize polar modulation.

[0039] In the receive path, antenna 248 receives the communication signal and provides a received RF signal, which is routed through a duplexer or switch 246 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate with specific RX and TX duplexer frequency separation, isolating the RX signal from the TX signal. Alternatively, there may be separate transmit and receive antennas, as mentioned above. In this case, RX and TX isolation can be achieved through limited coupling between the two antennas. In the case of separate RX and TX antennas, the RX antenna can be directly coupled to LNA 252. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Downconversion mixers 261a and 261b in downconverter 260 mix the output of filter 254 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from receive (RX) LO signal generator 280 to generate I and Q baseband signals. The I baseband signal and the Q baseband signal are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain I analog input signals and Q analog input signals, which are provided to the data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals into digital signals to be further processed by the data processor 210. In some embodiments, the ADCs 216a and 216b are included in the transceiver 220 and provide data to the data processor 210 in a digital form.

[0040] exist Figure 2A In the data processor 210, TX LO signal generator 290 generates I TX LO signal and Q TX LO signal for upconversion, while RX LO signal generator 280 generates I RX LO signal and Q RX LO signal for downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signal from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signal from LO signal generator 280.

[0041] In an exemplary embodiment, RX PLL 282, TX PLL 292, RX LO signal generator 280, and TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include a common or shared LO signal generator circuit to provide the TX LO signal and the RX LO signal. Alternatively, separate LO generator circuits may be used to generate the TX LO signal and the RX LO signal.

[0042] The wireless device 200 may support CA and may (i) receive multiple downlink signals transmitted by one or more cells at different frequencies on multiple downlink carriers and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers.

[0043] Figure 2A 2 functionally illustrates certain components of transceiver 220, and the illustrated configurations may or may not represent physical device configurations in certain implementations. For example, as described above, transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, and the like. In some embodiments, transceiver 220 is implemented on a substrate or board (such as a printed circuit board (PCB)) having various modules, chips, and / or components. For example, power amplifier 244, filter 242, and duplexer 246 may be implemented in separate modules or as discrete components, while the remaining components illustrated in transceiver 220 may be implemented in a single transceiver chip.

[0044] The power amplifier 244 may include one or more stages, including, for example, a driver stage, a power amplifier stage, or other components that may be configured to amplify communication signals at one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, the power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0045] In an exemplary embodiment in a superheterodyne architecture, filter 242, PA 244, LNA 252, and filter 254 may be implemented separately from other components in transmitter 230 and receiver 250 and may be implemented on a millimeter wave integrated circuit. Figure 2B An example superheterodyne architecture is illustrated in .

[0046] Figure 2B is a block diagram illustrating a wireless device in which example techniques of this disclosure may be implemented. Figure 2B Certain components of the wireless device 200a (eg, which may be indicated by the same reference numerals) may be similar to those of the wireless device 200a. Figure 2A The components of the wireless device 200 shown in FIG. 1 are configured as described above, and the description thereof will not be repeated. Figure 2B Description of the item with the same number in .

[0047] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture, in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and an intermediate frequency (IF). For example, upconverter 240 may be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include an upconverter mixer 276. Summing function 278 of upconverter 240 combines the I output and the Q output and provides the combined signal to mixer 276. The combined signal may be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and the TX RF LO signal from TX RF LO signal generator 277 and provide the upconverted RF signal to phase shift circuit 281. Although PLL 292 is in Figure 2B 277, but a respective PLL for each signal generator may be implemented.

[0048] In an exemplary embodiment, the components in phase shift circuit 281 may include one or more adjustable or variable phased array elements and may receive one or more control signals from data processor 210 via connection 294 and operate the adjustable or variable phased array elements based on the received control signals.

[0049] In an exemplary embodiment, phase shift circuit 281 includes phase shifters 283 and phased array elements 287. Although three phase shifters 283 and three phased array elements 287 are shown for ease of illustration, phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287.

[0050] Each phase shifter 283 can be configured to receive an RF transmit signal from the upconverter 275, change the phase by a certain amount, and provide the RF signal to a corresponding phased array element 287. Each phased array element 287 can include transmit and receive circuitry including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifter 283 can be incorporated into the corresponding phased array element 287.

[0051] The output of the phase shift circuit 281 is provided to the antenna array 248. In an exemplary embodiment, the antenna array 248 includes a number of antennas that generally corresponds to the number of phase shifters 283 and phased array elements 287, e.g., such that each antenna element is coupled to a respective phased array element 287. In an exemplary embodiment, the phase shift circuit 281 and the antenna array 248 may be referred to as a phased array.

[0052] In the receive direction, the output of the phase shift circuit 281 is provided to a downconverter 285. In an exemplary embodiment, the downconverter 285 may include a downconverting mixer 286. In an exemplary embodiment, the mixer 286 downconverts the received RF signal provided by the phase shift circuit 281 to an IF signal based on the RX RF LO signal provided by the RX RF LO signal generator 279. The I / Q generation function 291 of the downconverter 260 receives the IF signal from the mixer 286 and generates an I signal and a Q signal in the downconverter 260, which downconverts the IF signal to baseband as described above. Although the PLL 282 is in Figure 2B 279, but a respective PLL for each signal generator may be implemented.

[0053] In some embodiments, upconverter 275, downconverter 285, and phase shift circuit 281 are implemented on a common IC. In some embodiments, while summing function 278 and I / Q generation function 291 are implemented separately from mixers 276 and 286, such that mixers 276, 286, and phase shift circuit 281 are implemented on a common IC, summing function 278 and I / Q generation function 291 are not implemented on a common IC (e.g., summing function 278 and I / Q generation function 291 are implemented in another IC coupled to the IC with mixers 276, 286). In some embodiments, LO signal generators 277 and 279 are included in a common IC. In some embodiments where phase shift circuits 276, 286, 277, 278, 279, and / or 291 are implemented on a common IC, the common IC and antenna array 248 are included in a module that can be coupled to other components of transceiver 220 via a connector. In some embodiments, the phase shift circuit 281 (e.g., a chip on which the phase shift circuit 281 is implemented) is coupled to the antenna array 248 via interconnects, or both are mounted on the substrate. For example, the components of the antenna array 248 can be implemented on the substrate and coupled to the integrated circuit implementing the phase shift circuit 281 via a flexible printed circuit, or the integrated circuit can be mounted on the other side of the substrate.

[0054] In some embodiments, Figure 2A The illustrated architecture and Figure 2BThe illustrated architecture is implemented in the same device. For example, wireless device 110 or 200 may be configured to use Figure 2A The architecture illustrated in FIG communicates with signals having frequencies below about 7 GHz (eg, the FR1 band) and uses Figure 2B The architecture illustrated in FIG communicates with signals having frequencies above about 24 GHz. In devices implementing both architectures, Figure 2A and Figure 2B One or more components with the same number may be shared between the two architectures. For example, a signal that has been directly down-converted from RF to baseband and a signal that has been down-converted from RF to baseband by an IF stage may both be filtered by the same baseband filter 264. In other embodiments, a first version of the filter 264 is included in the implementation of the device. Figure 2A and a second version of the filter 264 is included in the implementation of the device Figure 2B section of the architecture.

[0055] Figure 3 A schematic diagram 300 is shown of a sub-array structure 310 of a phased array. The sub-array structure 310 may be located in a phased array circuit such as a phase shift circuit 281 ( Figure 2B ) is an example of a subarray structure among multiple subarray structures in a phased array. In one exemplary embodiment, there may be eight subarray structures in the phased array. Subarray structure 310 may include multiple phased array elements with transmit and / or receive capabilities. In one exemplary embodiment, an exemplary receive phased array element 315 may include receive circuitry including a low noise amplifier (LNA) 320 and a phase shifter 340. In one exemplary embodiment, subarray structure 310 may also include a multiplexer 330 connected to the output of each phase shifter 340. Each LNA 320 may be connected to port 317. In receive applications, port 317 may include one or more outputs of an antenna or antenna element. An exemplary antenna element 318 is shown for reference. Antenna element 318 may be one antenna element in a phased array of antenna elements. An antenna system in a phased array may have one or more antennas and one or more antenna elements, and may have one or more outputs. An example of an output from an antenna or antenna element 318 may be a vertically polarized (Vpol) output and a horizontally polarized (Hpol) output. In one exemplary embodiment, multiplexer 330 may be configured to provide signals from two of phase shifters 340 or all of phase shifters 340 at selected outputs to subsequent processing circuitry, such as, for example, frequency conversion circuitry (an example of which is shown in FIG. Figure 4), the frequency conversion circuitry may be configured to convert radio frequency (RF) signals to a lower frequency known as an intermediate frequency (IF); and / or circuitry for combining multiple signals output from multiplexer 330 (e.g., before being provided to the IF port). In other examples, signals received at multiplexer 330 are combined within multiplexer 330, and the combined signal is selectively provided to subsequent processing circuitry, such as frequency conversion circuitry. For example, the frequency conversion circuitry may be configured to convert a 24 GHz or 39 GHz signal at port 317 to a frequency of, for example, 10 GHz. Other frequencies are possible.

[0056] Figure 4 Schematic diagram 400 of a down converter 401 is shown. The down converter 401 may be Figure 2B 4 is an example of a downconverter 285, and in one exemplary embodiment, can be configured to downconvert a communication signal from an RF signal to an IF signal. In one exemplary embodiment, downconverter 401 can include one or more variable gain amplifiers (VGAs), with exemplary VGAs 402a and 402b shown as examples only. VGAs 402a and 402b can each be configured to amplify the RF signal. Downconverter 401 can also include a mixer 404, an IF VGA 406, and a filter 408. The outputs of VGAs 402a and 402b are coupled together and to the input of mixer 404. In one exemplary embodiment, mixer 404 can be a downconversion mixer configured to convert an RF signal to an IF signal. IF VGA 406 can be configured to further amplify the IF signal, and filter 408 can be configured to remove unwanted products from the IF signal amplified by IF VGA 406. In one exemplary embodiment, the RF VGAs 402a and 402b and the IF VGA 406 may be provided by the data processor 210 ( Figure 2B ) or a control signal from another controller. Although examples of down-conversion to IF and subsequent processing of the IF signal and examples of IF ports are described herein, it will be understood that the signal can be down-converted to baseband and the baseband signal can be subsequently processed; and the exemplary device may include a BB port, for example, in a direct conversion architecture, where the mixer 404 is configured to convert between RF and baseband.

[0057] Figure 5Schematic diagram 500 of a signal combining circuit 501 is shown. In one exemplary embodiment, combining circuit 501 may include one or more variable gain amplifiers (VGAs), with exemplary VGAs 502a and 502b shown for example only. The output of VGA 502b may be provided to attenuator 504. The output of VGA 502a and the output of attenuator 504 may be provided to matching network 506. Matching network 506 may include one or more of resistive, capacitive, and inductive elements configured to provide impedance matching. The output of matching network 506 may be provided to notch filter 508. The output of notch filter 508 may be provided to duplexer 510, which is configured to separate transmit and receive signals in time to facilitate, for example, time division duplex (TDD) communication.

[0058] Figure 6 A schematic diagram 600 of a phased array 602 is shown. In one exemplary embodiment, the phased array 602 includes eight (8) sub-array structures 310, referred to in this example as sub-array structures 310a, 310, 310c, 310d, 310e, 310f, 310g, and 310h. In one exemplary embodiment, the sub-array structures 310 may include an arrangement in which the sub-array structures 310c, 310d, 310g, and 310h on the right side of the figure are generally configured to process signals in a particular frequency band (such as a low frequency band), and the sub-array structures 310a, 310b, 310e, and 310f on the left side of the figure are generally configured to process signals in a particular frequency band (such as a high frequency band). As used herein, the terms "high" and "low" are relative. For example, the low frequency band signal may have a frequency of approximately 24 GHz, and the high frequency band signal may have a frequency of approximately 42 GHz. Other frequencies are possible, with the frequencies of 24 GHz and 42 GHz being used as examples only. Furthermore, the upper sub-array structures 310a, 310b, 310c, and 310d may be configured to process horizontally polarized (H pol) signals from respective antennas (e.g., from 16 respective antennas in the illustrated example), and the lower sub-array structures 310e, 310f, 310g, and 310h may be configured to process vertically polarized (V pol) signals from respective antennas (e.g., the same antennas to which the upper sub-array structures 310a, 310b, 310c, and 310d are coupled); however, this convention is one example of a variety of different possible configurations.

[0059] In one exemplary embodiment, subarray structures 310a and 310b associated with high-band H pol may include a high-band H pol quadrant 640, subarray structures 310c and 310d associated with low-band H pol may include a low-band H pol quadrant 650, subarray structures 310e and 310f associated with high-band V pol may include a high-band V pol quadrant 660, and subarray structures 310g and 310h associated with low-band V pol may include a low-band V pol quadrant 670. Each of quadrants 640, 650, 660, and 670 may be further divided into two sub-quadrants, each having a subarray structure 310.

[0060] Phased array 602 also includes a downconverter 401 associated with each subarray structure. Downconverters 401a and 401b may be associated with high-band H pol quadrant 640; downconverters 401c and 401d may be associated with low-band H pol quadrant 650; downconverters 401e and 401f may be associated with high-band V pol quadrant 660; and downconverters 401g and 401h may be associated with low-band V pol quadrant 670.

[0061] Synthesizer 612 may be configured to provide a local oscillator (LO) signal to down-converters 401a, 401b, 401e, and 401f, and synthesizer 614 may be configured to provide a local oscillator (LO) signal to down-converters 401c, 401d, 401g, and 401h. In an exemplary embodiment, synthesizer 612 may also be configured to provide a local oscillator (LO) signal to down-converters 401c, 401d, 401g, and 401h by selectively activating a switching circuit (not shown); and synthesizer 614 may also be configured to provide a local oscillator (LO) signal to down-converters 401a, 401b, 401e, and 401f by selectively activating a switching circuit (not shown).

[0062] In one exemplary embodiment, combinational circuit 501a may be associated with H pol quadrants 640 and 650, and combinational circuit 501b may be associated with V pol quadrants 660 and 670. Combinatorial circuit 501a may be connected to first IF port IF_1; and combinational circuit 501b may be connected to second IF port IF_2.

[0063] In an exemplary embodiment, one or more signals may be received by one or more antenna elements and downconverted from RF to IF and may be presented at a first IF port IF_1 and a second IF port IF_2. The signals at these ports may be transmitted via interconnects to a transceiver chip or other circuitry for further processing the one or more signals, such as an optional downconverter 260 (e.g., when using IF, as in this example, but downconverter 260 may be omitted in a direct conversion architecture) and amplifiers and / or filters 262, 264. After being processed by these components, data processor 210 may receive the signals and further process them to extract information about the wireless communication.

[0064] Figure 6 is described as having four quadrants. However, in other examples, there may not be four such quadrants. For example, in certain implementations where the antenna does not include both V pol and H pol, there may be fewer than four quadrants (e.g., only Figure 6 (top half of the image). Other configurations implementing fewer (or more) than four quadrants may be used. Furthermore, while the quadrants are illustrated as being distributed in the four corners of a rectangle, this representation is not limiting. The quadrants may be arranged on the chip in any number of ways. They may be arranged linearly, separated as shown, or overlapped. While some of the following descriptions refer to quadrants, a "grouping" of multiple (e.g., a pair) sub-array structures may also be used to describe the illustrated circuits, such as any of 640, 650, 660, and 670.

[0065] Figure 7 A schematic diagram 700 of an exemplary embodiment of a phased array 702 is shown. Figure 7 In FIG. 1 , a phased array 702 is capable of signal processing low-band multiple-input, multiple-output (LB MIMO) using independent beam management (IBM), and is capable of signal processing two LB signals using independent beam management (IBM) in a carrier aggregation (CA) system. An example of signal processing two LB signals using IBM in a CA system is illustrated, and components processing a first communication signal at a first frequency in this example are arbitrarily illustrated using bold dotted lines, and components processing a second communication signal at a second frequency in this example are arbitrarily illustrated using bold dashed lines. In one exemplary embodiment, a first RF communication signal at a first frequency (f1) is illustrated using arrow 703, and a second RF communication signal at a second frequency (f2) is illustrated using arrow 705. In one exemplary embodiment, the signals represented by arrows 703 and 705 in this example may be low-band signals of different frequencies.

[0066] In one exemplary embodiment, the phased array 702 can be configured such that a first RF communication signal 703 at a first frequency (f1) is received by some or all of the antenna ports on the subarray structure 310d and the subarray structure 310h; and a second RF communication signal 705 at a second frequency (f2) is received by some or all of the antenna ports on the subarray structure 310c and the subarray structure 310g. Figure 7 In the example shown in FIG, a first RF communication signal 703 at a first frequency (f1) is received by all of the antenna ports on sub-array structure 310d and sub-array structure 310h; and a second RF communication signal 705 at a second frequency (f2) is received by all of the antenna ports on sub-array structure 310c and sub-array structure 310g. However, by selectively enabling the LNA 320 and phase shifter 340 on any sub-array structure, the RF communication signal can be received by fewer than all of the antenna ports on any given sub-array structure. For example, the RF communication signal can be received by two of the four antenna ports on one or more of the sub-arrays. A first RF communication signal 703 at a first frequency (f1) from the H pol antenna port may be provided by a multiplexer in subarray structure 310d to and processed by downconverter 401d, and a first RF communication signal 703 at a first frequency (f1) from the V pol antenna port may be provided by a multiplexer in subarray structure 310h to and processed by downconverter 401h. For example, downconverters 401d and 401h may receive a local oscillator (LO) signal at a first frequency and may downconvert the first RF communication signal 703 at the first frequency (f1) to a first intermediate frequency (IF1) signal 713.

[0067] A second RF communication signal 705 at a second frequency (f2) from the H pol antenna port may be provided by a multiplexer in subarray structure 310c to and processed by downconverter 401c, and a second RF communication signal 705 at a second frequency (f2) from the V pol antenna port may be provided by a multiplexer in subarray structure 310g to and processed by downconverter 401g. For example, downconverters 401c and 401g may receive a local oscillator (LO) signal at a second frequency and may downconvert the second communication signal 705 at the second frequency (f2) to a second intermediate frequency (IF2) signal 715.

[0068] The output of the first communication signal 713 with the first intermediate frequency (IF1) of downconverter 401d may be provided to combining circuit 501a; and the output of the first communication signal 713 with the first intermediate frequency (IF1) of downconverter 401h may be provided to combining circuit 501b.

[0069] The output of downconverter 401c of second communication signal 715 with second intermediate frequency (IF2) may be provided to combining circuit 501a; and the output of downconverter 401g of second communication signal 715 with second intermediate frequency (IF2) may be provided to combining circuit 501b.

[0070] The output IF_1 of the combining circuit 501 a may have intermediate frequency (IF) signals 713 and 715 corresponding to the first communication signal 703 at the first frequency ( f1 ) and the second communication signal 705 at the second frequency ( f2 ), respectively.

[0071] The output IF_2 of the combining circuit 501 b may have intermediate frequency (IF) signals 713 and 715 corresponding to the first communication signal 703 at the first frequency ( f1 ) and the second communication signal 705 at the second frequency ( f2 ), respectively.

[0072] In an exemplary embodiment, the phase shifters in the sub-array structure 310d and the sub-array structure 310h can be configured to operate on the first RF communication signal 703 of the first frequency (f1) to produce a given beam angle at the output of the sub-array structure 310d and the output of the sub-array structure 310h; and the phase shifters in the sub-array structure 310c and the sub-array structure 310g can be configured to operate on the second RF communication signal 705 of the second frequency (f2) to produce a given beam angle at the output of the sub-array structure 310c and the output of the sub-array structure 310h. For example, to produce a given beam angle at the output of the sub-array structure 310d, the phase shifter 340 ( Figure 3 ) can be independently and individually controlled to produce a desired beam angle. For example, the phase shift applied by each of the phase shifters in a given subarray structure (in this example, 310d) can be controlled to apply the same or different phase shifts, thereby producing a desired beam angle for the signal at the output of the subarray structure. The phase shifters 340 in all subarray structures within the subarray structure can be similarly controlled to produce a given beam angle. In this manner, independent beam management (IBM) can be provided for a first RF communications signal 703 at a first frequency (f1) and a second RF communications signal 705 at a second frequency (f2). Furthermore, as described above, using fewer than all of the antenna ports in a subarray can facilitate IBM.

[0073] In this way, two different RF communication signals can be received separately and down-converted to IF to provide independent beam management (IBM) in a carrier aggregation (CA) system. In an exemplary embodiment, the phased array 702 allows independent beam management (IBM) and CA, and also allows the MRTD requirement to be relaxed to approximately 8µsec, rather than the strict 0.26µsec common beam management (CBM) MRTD requirement.

[0074] Figure 7 The example of FIG3 illustrates L+L IBM CA operation; however, the configuration of phased array 702 is also capable of processing signals in LB MIMO operation. For example, two instances of the same frequency signal can be received by subarray configuration 310c and subarray configuration 310d, respectively, and independently processed using different phase shift settings, thereby providing independent beam management. Similarly, instances of the same frequency signal can be received by subarray configuration 310g and subarray configuration 310h, respectively, and independently processed using different phase shift settings.

[0075] Figure 8 A schematic diagram 800 of an exemplary embodiment of a phased array 802 is shown. Figure 8 In FIG. 8 , phased array 802 is configured for mid / high-band multiple-input, multiple-output (M / HB MIMO) and is configured to process two mid / high-band (M / HB) signals using independent beam management (IBM). Components in this example that may process a first communication signal at a first frequency are arbitrarily illustrated using bold dotted lines, and components in this example that may process a second communication signal at a second frequency are arbitrarily illustrated using bold dashed lines. In one exemplary embodiment, phased array 802 will be described in the context of processing a single signal in MIMO operation. However, phased array 802 may also process signals having multiple frequencies. In one exemplary embodiment, a first RF communication signal at a first frequency (f1) is illustrated using arrow 803. In one exemplary embodiment, the signal represented by arrow 803 may be a high-band signal or a mid-band signal. The processing of signal 803 will be described in the following example.

[0076] In one exemplary embodiment, the phased array 802 may be configured such that a first RF communication signal 803 at a first frequency (f1) is received by the sub-array structure 310a and the sub-array structure 310e; and is also received by the sub-array structure 310b and the sub-array structure 310f. Figure 8 In the example shown in FIG, fewer than all of the LNAs and phase shifters are enabled in sub-array structures 310a, 310b, 310e, and 310f, with two exemplary LNAs and phase shifters shown as enabled. Fewer LNAs and phase shifters may be enabled in each sub-array structure 310.

[0077] A first RF communication signal 803 at a first frequency (f1) from the H pol antenna port may be provided by a multiplexer in the subarray structure 310a to downconverter 401a and processed by downconverter 401a and downconverter 401b; and a first RF communication signal 803 at a first frequency (f1) from the V pol antenna port may be provided by a multiplexer in the subarray structure 310e to downconverter 401e and processed by downconverter 401e and downconverter 401f. For example, downconverter 401a and downconverter 401e can receive a first local oscillator (LO) signal from synthesizer 612 at a first frequency and can convert a first RF communication signal 803 at a first frequency (f1) into a first intermediate frequency (IF1) signal 813; and downconverter 401b and downconverter 401f can receive a second local oscillator (LO) signal from synthesizer 614 at a second frequency (where the LO signal is shown in bold solid line) and can downconvert the first RF communication signal 803 at the first frequency (f1) into a second intermediate frequency (IF2) signal 817.

[0078] The output of the first communication signal 803 with the first intermediate frequency (IF1) 813 of the down converter 401a and the output of the first communication signal 803 with the second intermediate frequency (IF2) 817 of the down converter 401b can be provided to the combination circuit 501a; and the output of the first communication signal 803 with the first intermediate frequency (IF1) 813 of the down converter 401e and the output of the first communication signal 803 with the second intermediate frequency (IF2) 817 of the down converter 401f can be provided to the combination circuit 501b.

[0079] The output IF_1 of the combining circuit 501 a may have intermediate frequency (IF) signals 813 and 817 corresponding to the first RF communication signal 803 at the first frequency ( f1 ).

[0080] The output IF_2 of the combining circuit 501 b may have intermediate frequency (IF) signals 813 and 817 corresponding to the first RF communication signal 803 at the first frequency ( f1 ).

[0081] In one exemplary embodiment, the phase shifters in subarray structure 310a, subarray structure 310b, subarray structure 310e, and subarray structure 310f can be configured to operate on a first RF communication signal 803 at a first frequency (f1), thereby providing independent beam management (IBM) for instances of the first RF communication signal 803 at the first frequency (f1). Furthermore, as described above, enabling a subset of the LNAs and / or phase shifters in the subarrays can facilitate providing IBM.

[0082] In this manner, a single RF communication signal can be received separately in a MIMO architecture and down-converted into two or more separate IF signals to provide M / HB MIMO using independent beam management (IBM). In one exemplary embodiment, the phased array 802 allows for independent beam management (IBM) and also allows for the MRTD requirement to be relaxed to approximately 8µsec, rather than the stringent 0.26µsec common beam management (CBM) MRTD requirement.

[0083] Figure 9 A schematic diagram 900 of an exemplary embodiment of a phased array 902 is shown. Figure 9 In FIG. 1 , a phased array 902 is configured for mid-+high-band carrier aggregation (M+HB CA) and is configured to process two mid- / high-band (M / HB) signals using independent beam management (IBM). Components in this example that process a first RF communications signal at a first frequency are arbitrarily illustrated using bold dotted lines, and components in this example that process a second RF communications signal at a second frequency are arbitrarily illustrated using bold dashed lines. In one exemplary embodiment, the first RF communications signal at a first frequency (f1) is illustrated using arrow 903, and the second RF communications signal at a second frequency (f2) is illustrated using arrow 905. In one exemplary embodiment, the signals represented by arrows 903 and 905 in this example may be high-band or mid-band signals of different frequencies.

[0084] In an exemplary embodiment, the phased array 902 can be configured such that the first RF communication signal 903 at the first frequency (f1) is a high-band (HB) signal and is received by the sub-array structure 310a and the sub-array structure 310e; and the second RF communication signal 905 at the second frequency (f2) is a mid-band (MB) signal and is received by the sub-array structure 310b and the sub-array structure 310f. Figure 9 In the example shown in FIG, less than all of the LNAs and phase shifters are enabled in sub-array structures 310a, 310b, 310e, and 310f, with two exemplary LNAs and phase shifters shown as enabled. More or fewer LNAs and phase shifters may be enabled in each sub-array structure 310.

[0085] A first RF communication signal 903 at a first frequency (f1) from the H pol antenna port may be provided by a multiplexer in subarray structure 310a to downconverter 401a and processed by downconverter 401a, and a first RF communication signal 903 at a first frequency (f1) from the V pol antenna port may be provided by a multiplexer in subarray structure 310e to downconverter 401e and processed by downconverter 401e. For example, downconverters 401a and 401e may receive a local oscillator (LO) signal at a first frequency and may downconvert the first RF communication signal 903 at the first frequency (f1) to a first intermediate frequency (IF1) signal 913.

[0086] A second RF communication signal 905 at a second frequency (f2) from the H pol antenna port may be provided by a multiplexer in subarray structure 310b to and processed by downconverter 401b, and a second communication signal 905 at a second frequency (f2) from the V pol antenna port may be provided by a multiplexer in subarray structure 310f to and processed by downconverter 401f. For example, downconverters 401b and 401f may receive a local oscillator (LO) signal at a second frequency and may downconvert the second RF communication signal 905 at the second frequency (f2) to a second intermediate frequency (IF2) signal 915.

[0087] The output of downconverter 401a with the first communication signal 913 having the first intermediate frequency (IF1) may be provided to combining circuit 501a; and the output of downconverter 401e with the first communication signal 913 having the first intermediate frequency (IF1) may be provided to combining circuit 501b.

[0088] The output of downconverter 401b of second communication signal 915 with second intermediate frequency (IF2) may be provided to combining circuit 501a; and the output of downconverter 401f of second communication signal 915 with second intermediate frequency (IF2) may be provided to combining circuit 501b.

[0089] The output IF_1 of the combining circuit 501a may have intermediate frequency (IF) signals 913 and 915 corresponding to the first RF communication signal 903 at the first frequency (f1) and the second RF communication signal 905 at the second frequency (f2), respectively.

[0090] The output IF_2 of the combining circuit 501 b may have intermediate frequency (IF) signals 913 and 915 corresponding to the first RF communication signal 903 at the first frequency ( f1 ) and the second RF communication signal 905 at the second frequency ( f2 ), respectively.

[0091] In an exemplary embodiment, the phase shifters in the sub-array structure 310a and the sub-array structure 310e can be configured to operate on a first RF communication signal 903 at a first frequency (f1); and the phase shifters in the sub-array structure 310b and the sub-array structure 310f can be configured to operate on a second RF communication signal 905 at a second frequency (f2), thereby providing independent beam management (IBM) for the first RF communication signal 903 at the first frequency (f1) and the second RF communication signal 905 at the second frequency (f2).

[0092] In this manner, two distinct RF communication signals can be received separately and downconverted to an IF frequency to provide M+HB CA using independent beam management (IBM). Furthermore, as described above, enabling fewer than all of the LNAs and / or phase shifters in a subarray can help provide IBM. In one exemplary embodiment, phased array 902 enables independent beam management (IBM) and also allows for a relaxed MRTD requirement of approximately 8µsec, rather than the stringent 0.26µsec common beam management (CBM) MRTD requirement.

[0093] Figure 10 A schematic diagram 1000 of an exemplary embodiment of a phased array 1002 is shown. Figure 10 In FIG. 1 , a phased array 1002 is configured for low-plus-mid / high-band carrier aggregation (L+M / H CA) and is configured to simultaneously process low-band and mid / high-band (L / M / H) signals using independent beam management (IBM) and carrier aggregation (CA). Components in this example that process a first communication signal at a first frequency are arbitrarily illustrated using bold dotted lines, and components in this example that process a second communication signal at a second frequency are arbitrarily illustrated using bold dashed lines. In one exemplary embodiment, a first RF communication signal at a first frequency (f1) is illustrated using arrow 1003, and a second RF communication signal at a second frequency (f2) is illustrated using arrow 1005. In one exemplary embodiment, the signals represented by arrows 1003 and 1005 in this example may be low-band and mid / high-band signals of different frequencies.

[0094] In an exemplary embodiment, the phased array 1002 can be configured such that a first RF communication signal 1003 at a first frequency (f1) is a low-band (LB) signal and is received by the sub-array structure 310c, the sub-array structure 310d, the sub-array structure 310g, and the sub-array structure 310h; and a second RF communication signal 1005 at a second frequency (f2) is a mid / high-band (M / HB) signal and is received by the sub-array structure 310a, the sub-array structure 310b, the sub-array structure 310e, and the sub-array structure 310f. Figure 8In the example shown in FIG, less than all of the LNAs and phase shifters are enabled in sub-array structures 310a, 310b, 310c, 310d, 310e, 310f, 310g, and 310h, with two exemplary LNAs and phase shifters shown as enabled. More or fewer LNAs and phase shifters may be enabled in each sub-array structure 310.

[0095] A first RF communication signal 1003 at a first frequency (f1) from the H pol antenna port may be provided by multiplexers in subarray structures 310c and 310d to and processed by downconverter 401d, and a first RF communication signal 1003 at a first frequency (f1) from the V pol antenna port may be provided by multiplexers in subarray structures 310g and 310h to and processed by downconverter 401h. For example, downconverters 401d and 401h may receive a local oscillator (LO) signal at a first frequency and may downconvert the first RF communication signal 1003 at the first frequency (f1) to a first intermediate frequency (IF1) signal 1013.

[0096] A second RF communication signal 1005 at a second frequency (f2) from the H pol antenna port may be provided by multiplexers in subarray structures 310a and 310b to and processed by downconverter 401a, and a second RF communication signal 1005 at a second frequency (f2) from the V pol antenna port may be provided by multiplexers in subarray structures 310e and 310f to and processed by downconverter 401e. For example, downconverters 401a and 401e may receive a local oscillator (LO) signal at a second frequency and may downconvert the second RF communication signal 1005 at the second frequency (f2) to a second intermediate frequency (IF2) signal 1015.

[0097] The output of the first RF communication signal 1013 having the first intermediate frequency (IF1) of downconverter 401d may be provided to combining circuit 501a; and the output of the first communication signal 10013 having the first intermediate frequency (IF1) of downconverter 401h may be provided to combining circuit 501b.

[0098] The output of the second communication signal 1015 with the second intermediate frequency (IF2) of downconverter 401a may be provided to combining circuit 501a; and the output of the second communication signal 1015 with the second intermediate frequency (IF2) of downconverter 401e may be provided to combining circuit 501b.

[0099] The output IF_1 of the combining circuit 501a may have intermediate frequency (IF) signals 1013 and 1015 corresponding to the first RF communication signal 1003 at the first frequency (f1) and the second RF communication signal 1005 at the second frequency (f2), respectively.

[0100] The output IF_2 of the combining circuit 501 b may have intermediate frequency (IF) signals 1013 and 1015 corresponding to the first RF communication signal 1003 at the first frequency ( f1 ) and the second RF communication signal 1005 at the second frequency ( f2 ), respectively.

[0101] In an exemplary embodiment, the phase shifters in the subarray structure 310c, the subarray structure 310d, the subarray structure 310g, and the subarray structure 310h can be configured to operate on the first RF communication signal 1003 at the first frequency (f1); and the phase shifters in the subarray structure 310a, the subarray structure 310b, the subarray structure 310e, and the subarray structure 310f can be configured to operate on the second RF communication signal 1005 at the second frequency (f2), thereby providing independent beam management (IBM) for the first RF communication signal 1003 at the first frequency (f1) and the second RF communication signal 1005 at the second frequency (f2).

[0102] In this way, two different RF communication signals can be received separately and down-converted to IF to provide L+ / MH CA using independent beam management (IBM). In addition, as described above, enabling a subset of the LNAs and / or phase shifters in the sub-array can help provide IBM. In an exemplary embodiment, the phased array 1002 allows for independent beam management (IBM) and also allows the MRTD requirement to be relaxed to approximately 8µsec, rather than the stringent common beam management (CBM) MRTD requirement of 0.26µsec. Figures 7 to 10 In the embodiment of the present invention, the data processor 210 can be coupled to the IF port (eg, through other processing circuits) and configured to receive the processed signals (eg, CA, MIMO and / or IBM signals) and further process them to extract information about the wireless communications.

[0103] Figure 11 is a flow chart describing one example of the operation of a method 1100 for signal processing. The blocks in the method 1100 may or may not be performed in the order shown, and in some embodiments, may be performed at least partially in parallel.

[0104] In block 1102, a first radio frequency (RF) signal and a second RF signal are received at an RF receiver. For example, a first RF signal 703 at a first frequency may be received at the subarray structure 310d on the low-band H pol quadrant 650 and by the subarray structure 310h on the low-band V pol quadrant 670; and a second RF signal 705 at a second frequency may be received at the subarray structure 310c on the low-band H pol quadrant 650 and by the subarray structure 310g on the low-band V pol quadrant 670.

[0105] In block 1104, the first RF signal and the second RF signal are simultaneously down-converted to a first intermediate frequency (IF1) signal and a second IF2 signal. For example, down-converters 401d and 401h may down-convert first RF signal 703 to first IF signal 713; and down-converters 401c and 401g may down-convert second RF signal 705 to second IF signal 715.

[0106] In block 1106, the first IF signal and the second IF signal are provided on a single output port. For example, the first IF signal 713 and the second IF signal 715 may be provided simultaneously at the IF_1 port at the output of the combinational circuit 501a, and the first IF signal 713 and the second IF signal 715 may be provided simultaneously at the IF_2 port at the output of the combinational circuit 501b.

[0107] Figure 12 is a functional block diagram of an apparatus for signal processing. Apparatus 1200 includes a component 1202 for receiving a first radio frequency (RF) signal and a second RF signal. In certain embodiments, component 1202 for receiving a first radio frequency (RF) signal and a second RF signal may be configured to perform method 1100 ( Figure 11 ). In one exemplary embodiment, the means for receiving the first RF signal and the second RF signal 1202 may include a subarray structure 310d on the low-band H pol quadrant 650 and a subarray structure 310h on the low-band V pol quadrant 670 configured to receive the first RF signal 703; and a subarray structure 310c on the low-band H pol quadrant 650 and a subarray structure 310g on the low-band V pol quadrant 670 configured to receive the second RF signal 705.

[0108] The apparatus 1200 further includes a component 1204 for simultaneously down-converting the first RF signal and the second RF signal into a first intermediate frequency (IF1) signal and a second IF2 signal. In certain embodiments, the component 1204 for simultaneously down-converting the first RF signal and the second RF signal into a first intermediate frequency (IF1) signal and a second IF2 signal can be configured to perform the method 1100 ( Figure 11 ). In one exemplary embodiment, means 1204 for simultaneously down-converting the first RF signal and the second RF signal into a first intermediate frequency (IF1) signal and a second IF2 signal may include down-converter 401d and down-converter 401h configured to down-convert the first RF signal 703 into a first IF signal 713; and down-converter 401c and down-converter 401g configured to down-convert the second RF signal 705 into a second IF signal 715.

[0109] The apparatus 1200 further includes a component 1206 for providing the first IF signal and the second IF signal on a single output port. In some embodiments, the component 1206 for providing the first IF signal and the second IF signal on a single output port can be configured to perform the method 1100 ( Figure 11 ). In one exemplary embodiment, means 1206 for providing the first IF signal and the second IF signal on a single output port may include circuitry configured to simultaneously provide the first IF signal 713 and the second IF signal 715 at the IF_1 port at the output of the combining circuit 501 a; and circuitry configured to simultaneously provide the first IF signal 713 and the second IF signal 715 at the IF_2 port at the output of the combining circuit 501 b, such as the combining circuit 501.

[0110] Figure 13 is a flow chart describing one example of the operation of a method 1300 for signal processing. The blocks in the method 1300 may or may not be performed in the order shown, and in some embodiments, may be performed at least partially in parallel.

[0111] In block 1302, a first radio frequency (RF) signal is received at an RF receiver. For example, the first RF signal 803 may be received at the subarray structure 310a in the high-band H pol quadrant 640 and by the subarray structure 310e in the high-band V pol quadrant 660; and the first RF signal 803 may be received at the subarray structure 310b in the high-band H pol quadrant 640 and by the subarray structure 310f in the high-band V pol quadrant 660.

[0112] In block 1304, the first RF signal is simultaneously down-converted to a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal. For example, down-converters 401a and 401e may down-convert first RF signal 803 to first IF signal 813, and down-converters 401b and 401f may down-convert first RF signal 803 to second IF signal 817.

[0113] In block 1306, the first IF signal 813 and the second IF signal 817 are provided on the first output port and the second output port. For example, the first IF signal 813 and the second IF signal 817 may be provided simultaneously at the IF_1 port at the output of the combinational circuit 501a and the IF_2 port at the output of the combinational circuit 501b.

[0114] Figure 14 is a functional block diagram of an apparatus for signal processing. Apparatus 1400 includes means 1402 for receiving a first radio frequency (RF) signal at an RF receiver. In certain embodiments, means 1402 for receiving a first radio frequency (RF) signal at an RF receiver may be configured to perform method 1300 ( Figure 13 ). In one exemplary embodiment, the means 1402 for receiving a first radio frequency (RF) signal at an RF receiver may include a subarray structure 310a configured to receive the first RF signal 803 on the high-band H pol quadrant 640 and a subarray structure 310e configured to receive the first RF signal 803 on the high-band V pol quadrant 660; and a subarray structure 310b configured to receive the first RF signal 803 on the high-band H pol quadrant 640 and a subarray structure 310f configured to receive the first signal 803 on the high-band V pol quadrant 660.

[0115] The apparatus 1400 further includes a component 1404 for simultaneously down-converting the first RF signal into a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal. In some embodiments, the component 1404 for simultaneously down-converting the first RF signal into a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal can be configured to perform the method 1300 ( Figure 13). In an exemplary embodiment, means 1404 for simultaneously down-converting a first RF signal into a first intermediate frequency (IF1) signal and a second intermediate frequency (IF2) signal may include down-converter 401a and down-converter 401e configured to down-convert first RF signal 803 into a first IF signal 813; and down-converter 401b and down-converter 401f configured to down-convert first RF signal 803 into a second IF signal 817.

[0116] The apparatus 1400 further includes a component 1406 for providing a first IF1 signal and a second IF2 signal on a first output port and a second output port. In some embodiments, the component 1406 for providing a first IF1 signal and a second IF2 signal on a first output port and a second output port can be configured to perform the method 1300 ( Figure 13 ). In one exemplary embodiment, means 1406 for providing the first IF1 signal and the second IF2 signal on the first output port and the second output port may include circuitry configured to simultaneously provide the first IF1 signal 813 and the second IF2 signal 817 at the IF_1 port at the output of the combinatorial circuit 501a; and circuitry configured to simultaneously provide the first IF1 signal 813 and the second IF2 signal 817 at the IF_2 port at the output of the combinatorial circuit 501b, such as the combinatorial circuit 501.

[0117] Specific implementation examples are described in the following numbered clauses:

[0118] 1. A receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter wave (mmW) frequencies, the receiving system comprising: a phased array having a plurality of groups, each group having a pair of subarray structures, each subarray structure having a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element having a low noise amplifier (LNA) and a phase shifter (PS), the plurality of groups including a first high-band (HB) group and a first low-band (LB) group; and a downconverter circuit. , the downconverter circuit is selectively connected to each subarray structure in the first high-band (HB) group and the first low-band (LB) group, each downconverter circuit having a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; and a combining circuit is connected to each of the downconverter circuits selectively connected to the first high-band (HB) group and the first low-band (LB) group, the combining circuit being configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port.

[0119] 2. The system of clause 1, further comprising: a first (HB) synthesizer configured to generate a first local oscillator (LO) signal; and a second (LB) synthesizer configured to generate a second local oscillator (LO) signal, the first LO signal and the second LO signal being configured to be provided to any one of the downconverter circuits.

[0120] 3. A system according to any of clauses 1 or 2, wherein each sub-array structure is configured to provide independent beam management, the independent beam management comprising independent phase shifting between the sub-array structures.

[0121] 4. A system according to any of clauses 2 to 3, wherein the antenna elements comprise separate antenna arrays and are configured to implement independent beamforming (IBF) for inter-band carrier aggregation (CA) and 4x4 multiple-input multiple-output (MIMO) signal processing.

[0122] 5. The system according to any of clauses 2 to 4, wherein the receiving system is configured to receive at least two radio frequency signals having different frequencies at two or more sub-array structures.

[0123] 6. The system according to any of clauses 2 to 5, wherein the receiving system is configured to receive at least two radio frequency signals having the same frequency at two or more sub-array structures.

[0124] 7. A system according to clause 5, wherein the receiving system is configured to simultaneously down-convert the two RF signals of different frequencies into corresponding first and second IF signals, and provide the first and second IF signals on a single output port.

[0125] 8. The system of clause 6, wherein the receiving system is configured to simultaneously down-convert the two RF signals of the same RF into a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

[0126] 9. The system of any of clauses 2 to 8, wherein the plurality of groups comprises four quadrants and each antenna element has a horizontally polarized output and a vertically polarized output.

[0127] 10. The system according to any of clauses 2 to 9, wherein the IF port comprises at least a first output pin (IF_1), wherein a first intermediate frequency (IF) signal and a second IF signal are provided on the first output pin (IF_1).

[0128] 11. A method for signal processing, the method comprising: receiving at least two radio frequency (RF) signals at a receiver; selectively phase shifting the at least two radio frequency (RF) signals; selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; simultaneously downconverting the at least two RF signals to intermediate frequency (IF) signals; and connecting the at least two IF signals to at least one selected output port.

[0129] 12. The method of clause 11, wherein the at least two radio frequency signals have different frequencies and are received at different receiver subarray structures.

[0130] 13. The method of any of clauses 11 to 12, wherein the at least two radio frequency signals have the same frequency and are received at different receiver sub-array structures.

[0131] 14. The method of any one of clauses 11 to 13, further comprising: selectively routing the at least two IF signals from any one of a plurality of sub-array structures to any one of a first output port and a second output port.

[0132] 15. The method of any of clauses 11 to 14, further comprising selectively amplifying and phase shifting the at least two RF signals.

[0133] 16. An apparatus comprising: means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; means for simultaneously downconverting the at least two RF signals to an intermediate frequency (IF) signal; and means for connecting the at least two IF signals to at least one selected output port.

[0134] 17. The apparatus of clause 16, further comprising means for receiving the at least two radio frequency signals having different frequencies at different receiver sub-array structures.

[0135] 18. The apparatus of any of clauses 16 to 17, further comprising means for receiving the at least two radio frequency signals having the same frequency at different receiver sub-array configurations.

[0136] 19. The apparatus of any of clauses 16 to 18, further comprising means for selectively routing the at least two IF signals from any one of a plurality of sub-array structures to any one of a first output port and a second output port.

[0137] 20. The apparatus of any of clauses 16 to 19, further comprising means for selectively amplifying and phase shifting the at least two RF signals.

[0138] 21. A radio system architecture, the radio system architecture comprising: a receiver having a plurality of subarrays in a phased array, the plurality of subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and provide independent beam management for a plurality of radio frequency (RF) signals received at each of the plurality of subarrays; and a data processor configured to receive signals from the receiver and extract information about wireless communications.

[0139] 22. The radio system architecture of clause 21, wherein the phased array has 16 antenna elements.

[0140] 23. A radio system architecture according to any of clauses 21 to 22, wherein at least two radio frequency signals are received at two or more sub-arrays and have different frequencies.

[0141] 24. The radio system architecture of any of clauses 21 to 22, wherein at least two radio frequency signals are received at two or more sub-arrays and have the same frequency.

[0142] 25. A radio system architecture according to any of clauses 21 to 24, wherein the architecture is configured to simultaneously down-convert the two radio frequency signals of different frequencies into corresponding first and second intermediate frequency signals, and to provide the first and second intermediate frequency signals on a single output port.

[0143] 26. A radio system architecture according to any of clauses 21 to 24, wherein the architecture is configured to simultaneously down-convert the two radio frequency signals of the same radio frequency into a first intermediate frequency signal and a second intermediate frequency signal, and to provide the first intermediate frequency signal and the second intermediate frequency signal simultaneously on a single output port.

[0144] The circuit architecture described herein can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described herein can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistor (HBT), high electron mobility transistor (HEMT), silicon on insulator (SOI), etc.

[0145] The apparatus implementing the circuits described herein may be a standalone device or may be part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs that may include a memory IC for storing data and / or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a handset, or a mobile unit, (vii) and the like.

[0146] While selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A receiving system for performing carrier aggregation (CA) and multiple-input multiple-output (MIMO) operations at millimeter wave (mmW) frequencies, the receiving system comprising: A phased array, the phased array having a plurality of groups, each group having a pair of sub-array structures, each sub-array structure having a plurality of phased array elements and a multiplexer, each phased array element coupled to an antenna element, each phased array element having a low noise amplifier (LNA) and a phase shifter (PS), the plurality of groups including a first high-band (HB) group and a first low-band (LB) group; a downconverter circuit selectively connected to each subarray structure in the first high-band (HB) group and the first low-band (LB) group, each downconverter circuit having a radio frequency (RF) amplifier, a mixer, an intermediate frequency (IF) amplifier, and a filter; and a combining circuit connected to each of the downconverter circuits selectively connected to the first high-band (HB) group and the first low-band (LB) group, the combining circuit configured to provide a signal from each downconverter circuit to an intermediate frequency (IF) port.

2. The system according to claim 1, further comprising: a first (HB) synthesizer configured to generate a first local oscillator (LO) signal; and A second (LB) synthesizer is configured to generate a second local oscillator (LO) signal, the first LO signal and the second LO signal being configured to be provided to any one of the downconverter circuits.

3. The system of claim 1, wherein each sub-array structure is configured to provide independent beam management, the independent beam management comprising independent phase shifting between the sub-array structures.

4. The system of claim 1 , wherein the antenna elements comprise separate antenna arrays and are configured to implement independent beamforming (IBF) for inter-band carrier aggregation (CA) and 4x4 multiple-input multiple-output (MIMO) signal processing. 5 . The system according to claim 1 , wherein the receiving system is configured to receive at least two radio frequency signals having different frequencies at two or more sub-array structures. 6 . The system of claim 1 , wherein the receiving system is configured to receive at least two radio frequency signals having the same frequency at two or more sub-array structures.

7. The system according to claim 5, wherein the receiving system is configured to simultaneously down-convert the two RF signals of different frequencies into corresponding first and second IF signals, and provide the first and second IF signals on a single output port.

8. The system according to claim 6, wherein the receiving system is configured to simultaneously down-convert the two RF signals of the same RF into a first intermediate frequency signal and a second intermediate frequency signal, and simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

9. The system of claim 1, wherein the plurality of groups comprises four quadrants, and each antenna element has a horizontally polarized output and a vertically polarized output.

10. The system of claim 1, wherein the IF port comprises at least a first output pin (IF_1), wherein a first intermediate frequency (IF) signal and a second IF signal are provided on the first output pin (IF_1).

11. A method for signal processing, the method comprising: receiving at least two radio frequency (RF) signals at a receiver; selectively phase shifting the at least two radio frequency (RF) signals; selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; down-converting the at least two RF signals simultaneously to an intermediate frequency (IF) signal; as well as The at least two IF signals are connected to at least one selected output port.

12. The method of claim 11, wherein the at least two radio frequency signals have different frequencies and are received at different receiver subarray structures.

13. The method of claim 11, wherein the at least two radio frequency signals have the same frequency and are received at different receiver subarray structures.

14. The method according to claim 11, further comprising: The at least two IF signals are selectively routed from any one of the plurality of sub-array structures to any one of the first output port and the second output port.

15. The method of claim 11, further comprising selectively amplifying and phase shifting the at least two RF signals.

16. A device comprising: means for receiving at least two radio frequency (RF) signals at a receiver; means for selectively phase shifting the at least two radio frequency (RF) signals; means for selectively directing the at least two phase-shifted radio frequency (RF) signals to a selected downconverter circuit; means for simultaneously down-converting the at least two RF signals to an intermediate frequency (IF) signal; as well as Means for connecting the at least two IF signals to at least one selected output port.

17. The apparatus of claim 16, further comprising means for receiving the at least two radio frequency signals having different frequencies at different receiver sub-array structures.

18. The apparatus of claim 16, further comprising means for receiving the at least two radio frequency signals having the same frequency at different receiver subarray structures.

19. The apparatus of claim 16, further comprising means for selectively routing the at least two IF signals from any one of a plurality of sub-array structures to any one of a first output port and a second output port.

20. The apparatus of claim 16, further comprising means for selectively amplifying and phase shifting the at least two RF signals.

21. A radio system architecture, comprising: a receiver having a plurality of subarrays in a phased array, the plurality of subarrays configured to perform carrier aggregation (CA) and multiple-input multiple-output (MIMO) signal processing and to provide independent beam management for a plurality of radio frequency (RF) signals received at each of the plurality of subarrays; and A data processor is configured to receive the signal from the receiver and extract information regarding the wireless communication.

22. The radio system architecture of claim 21, wherein the phased array has 16 antenna elements.

23. The radio system architecture of claim 21, wherein at least two radio frequency signals are received at two or more sub-arrays and have different frequencies.

24. The radio system architecture of claim 21, wherein at least two radio frequency signals are received at two or more sub-arrays and have the same frequency.

25. The radio system architecture of claim 23, wherein the architecture is configured to simultaneously down-convert the two radio frequency signals of different frequencies into corresponding first and second intermediate frequency signals, and provide the first and second intermediate frequency signals on a single output port.

26. The radio system architecture of claim 24, wherein the architecture is configured to simultaneously down-convert the two RF signals of the same RF into a first intermediate frequency signal and a second intermediate frequency signal, and to simultaneously provide the first intermediate frequency signal and the second intermediate frequency signal on a single output port.

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