Parallel four-neighbor real-time multi-spot center detection method based on FPGA

Abstract

The present application relates to a kind of parallel four neighborhood real-time multi-spot center detection method based on FPGA, belong to optical measurement and laser radar technical field, solve the problem of high hardware resource occupation of existing FPGA multi-spot detection algorithm, calculation precision loss and insufficient real-time nature.Techinical scheme includes: through two-stage median filter, adaptive binarization and morphological processing module to complete image preprocessing;Label assignment, equivalence table merging and centroid calculation are realized using four neighborhood center detection module, and label analysis and coordinate accumulation are synchronously completed based on three-stage pipeline architecture.The present application realizes low resource occupation multi-spot sub-pixel level positioning by hardware-level parallel pipeline processing, improves detection real-time nature and environmental adaptability, and provides accurate and stable spot center detection scheme for high dynamic scene.

Description

Technical Field

[0001] This invention belongs to the field of optical measurement and lidar technology, and relates to a parallel four-neighborhood real-time multi-spot center detection method based on FPGA. Background Technology

[0002] Multi-spot center detection technology is a core technology in optical measurement, lidar, and defense science and technology fields. Its core objective is to quickly and accurately extract the sub-pixel-level center coordinates of multiple spots. In high-dynamic scenarios such as space laser communication and industrial precision inspection, the real-time positioning capability of the spot center directly affects the measurement accuracy and response speed of the system. Traditional methods mainly rely on general-purpose processing devices such as CPUs or ARM architectures to achieve spot detection through software algorithms. However, such methods have inherent drawbacks: general-purpose processors lack hardware-level parallel computing capabilities, resulting in large processing latency and high power consumption, making it difficult to meet the real-time processing requirements of high frame rates and high-resolution images.

[0003] In recent years, Field-Programmable Gate Arrays (FPGAs) have gradually become the preferred solution for real-time image processing due to their advantages in parallel computing and customizable hardware architecture. However, existing FPGA-based multi-spot detection algorithms still face significant challenges: First, connected component labeling algorithms require a large amount of storage resources to cache intermediate results, resulting in high hardware resource consumption. Second, existing methods suffer from computational accuracy loss during label merging and coordinate accumulation, affecting the sub-pixel accuracy of centroid localization. Third, the algorithm process relies on multiple full-image scans, making it difficult to achieve pipelined frame processing and data output, thus limiting the system's real-time performance.

[0004] Therefore, there is an urgent need for a multi-spot center detection method that can balance low resource consumption, high computational accuracy, and real-time performance, in order to resolve the contradiction between hardware resource efficiency, algorithm accuracy, and processing timeliness in existing FPGA implementation schemes. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a parallel four-neighborhood real-time multi-spot center detection method based on FPGA.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A parallel four-neighborhood real-time multi-spot center detection method based on FPGA includes two core functional modules: image preprocessing and connected component center detection module. The image preprocessing module includes a two-level median filtering submodule, an adaptive binarization submodule, and a morphological processing submodule.

[0008] Furthermore, the two-level median filtering submodule uses multiple synchronous FIFOs to buffer multiple rows of image data. The 3×3 median filtering template uses two synchronous FIFOs to buffer the first two rows of image data, and the 5×5 median filtering template uses four synchronous FIFOs to buffer the first four rows of data. These are combined with the current row of image data to form 3×3 and 5×5 image data matrices, respectively. The matrix window is slid to the right once every clock cycle, and the median of the matrix elements is used as the current pixel to achieve the median filtering function.

[0009] Furthermore, the adaptive binarization submodule uses the highest grayscale value of the previous frame as a reference, sets the threshold for binarization of the current frame to 1 / 2 or 1 / 4 of the reference value, outputs 0 for grayscale values ​​less than the threshold, and outputs 1 for grayscale values ​​greater than the threshold.

[0010] Furthermore, the morphological processing module uses one 3×3 erosion template and one 3×3 dilation template respectively. The dilation and erosion templates are implemented with the same code, and the functions of dilation and erosion can be achieved by setting different thresholds.

[0011] Furthermore, the four-neighbor center detection algorithm module includes the following steps:

[0012] Step 1: Input binarized image data;

[0013] Step 2: Filter target pixels and check their neighborhood labels;

[0014] Step 3: Assign new tags or merge equivalent tags;

[0015] Step 4: Accumulate the coordinates and pixel values ​​of the pixels corresponding to the labels;

[0016] Step 5: Determine if the current frame has been processed;

[0017] Step 6: Analyze the equivalence table and calculate the centroid.

[0018] Furthermore, in step 2, for each pixel in the input video data, it is determined whether its pixel value is greater than 0. If the pixel value is 0, it is considered to belong to the background and will not participate in subsequent calculations; if the pixel value is greater than 0, the process proceeds to the subsequent connected component labeling step.

[0019] Furthermore, step 3 uses a dual-port RAM to construct an equivalence table, using the RAM address as the node value and the value at the corresponding address as the label value. Then, the label values ​​of the current pixel and its four neighboring pixels (left, right, top, and top right) are assigned to the label1, label2, label3, label4, and label5 registers. Combinational logic is used to find the minimum non-zero value among these five labels. In the first clock cycle, sequential logic is used to assign the minimum label value to label1_r1 as the main label. In the second clock cycle, labels with a label value of 0 are marked separately to avoid invalid merging, and label_r1 is assigned to label_r2 as the main label. In the third clock cycle, the node of the label is pointed to the main label, completing the equivalence merging.

[0020] Furthermore, step 4 uses three dual-port RAMs to store the x-coordinate, y-coordinate, and accumulated pixel values ​​corresponding to different tag values. Since the RAM has a one-clock-cycle delay for reading data, it is impossible to read, modify, and write the value at the corresponding address in the RAM within one clock cycle. Therefore, two registers are defined to buffer the modified data after one and two clock cycles respectively, forming a two-stage pipeline structure to realize continuous read, modify, and write operations on the same address in the RAM.

[0021] Furthermore, step 6, parsing the equivalence table, involves traversing the equivalence table RAM by address to find labels with equivalence relationships and determining the center of the connected components under each equivalence label. The x-coordinate, y-coordinate, and pixel value of pixels with equivalence labels are stored in three distributed RAMs and accumulated. The spot centroid algorithm formula is then applied to each connected component.

[0022]

[0023] Where X and Y represent the center coordinates, N and M represent the range of values ​​for the x and y coordinates of the current connected component, respectively, x and y represent the coordinate values ​​of the current pixel, and I(x,y) represents the gray value of the current pixel coordinates. In the binarized image, I(x,y) = 1, so this term can be ignored.

[0024] A detection system for implementing the method includes:

[0025] The image acquisition module is configured to receive 8-bit grayscale image signals and output them through a parallel data bus.

[0026] The preprocessing module includes a cascaded 5×5 median filter unit, a 3×3 median filter unit, an adaptive binarization unit, and a morphological processing unit, wherein:

[0027] The 5×5 median filtering unit buffers the first four rows of image data using four synchronous FIFOs.

[0028] The 3×3 median filtering unit buffers the first two rows of image data using two synchronous FIFOs.

[0029] The morphological processing unit uses a 3×3 sliding window and is configured to perform dilation or erosion operations.

[0030] The real-time processing module receives the binary image signal output by the preprocessing module, including:

[0031] The four-neighbor label analysis unit is configured to assign labels to target pixels and merge equivalence relations.

[0032] The centroid calculation unit is configured to parse label data and calculate the coordinates of the light spot center.

[0033] The output interface module outputs centroid coordinate data via the AXI-Stream protocol;

[0034] The system employs a global synchronous clock and an asynchronous reset signal, and the modules are connected via a pipelined architecture, satisfying the following:

[0035] The row buffer delay between the image acquisition module and the preprocessing module is 2 clock cycles.

[0036] The label assignment and equivalence table merging operations of the real-time processing module take 3 clock cycles.

[0037] The centroid coordinate output delay does not exceed one frame period.

[0038] The beneficial effects of this invention are as follows:

[0039] (1) The four-neighbor connected domain labeling algorithm combined with the two-stage pipeline accumulation mechanism is adopted. Tag merging and coordinate calculation are realized through on-chip storage, which greatly reduces external storage dependence and reduces hardware resource consumption, enabling the system to run efficiently on a low-cost FPGA platform.

[0040] (2) Based on pixel-level pipeline processing and intra-frame parallel computing, the seamless connection between spot detection and centroid output is realized. After the transmission of a frame image, the center positioning of all connected domains can be completed without secondary scanning, meeting the microsecond-level real-time response requirements in high dynamic scenes.

[0041] (3) By using two-level median filtering and adaptive binarization to denoise, the influence of environmental interference on the light spot contour is suppressed; at the same time, the dynamic merging strategy of equivalence table combined with the sub-pixel centroid algorithm ensures the accurate extraction of connected domain edges and the sub-pixel positioning of center coordinates.

[0042] (4) The morphological processing module can flexibly configure erosion and expansion parameters to adapt to spot morphology correction under different noise environments; the adaptive threshold mechanism dynamically adjusts the segmentation threshold according to the grayscale features of the previous frame to improve the detection stability under complex lighting conditions.

[0043] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0044] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0045] Figure 1 This is a system architecture diagram of a parallel four-neighborhood real-time multi-spot center detection method based on FPGA;

[0046] Figure 2 This is a module connection diagram for a parallel four-neighborhood real-time multi-spot center detection method based on FPGA.

[0047] Figure 3 Generate a schematic diagram for a pixel matrix sliding window based on FPGA;

[0048] Figure 4 The flowchart shows the parallel four-neighbor center detection algorithm based on FPGA.

[0049] Figure 5 The schematic diagram of the operation principle of constructing the equivalence table RAM for the FPGA-based parallel four-neighbor center detection algorithm;

[0050] Figure 6 This diagram illustrates the read, modify, and write operations of the pixel coordinate accumulation RAM in an FPGA-based parallel four-neighbor center detection algorithm.

[0051] Figure 7 A comparison of simulation results between MATLAB and VIVADO connected component center detection algorithms;

[0052] Figure 8 This is a timing diagram of key signals inside the FPGA-based parallel four-neighbor center detection algorithm module. Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0054] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0055] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0056] This invention proposes a parallel four-neighborhood real-time multi-spot center detection method based on FPGA. Compared with traditional hardware connected domain multi-spot algorithms, it reduces hardware resource consumption and improves algorithm computational accuracy and real-time performance. Therefore, this invention is of great significance in scenarios with stringent requirements for real-time performance, hardware resources, and computational accuracy.

[0057] like Figure 1 As shown, a parallel four-neighborhood real-time multi-spot center detection method based on FPGA includes: a two-level median filtering submodule, an adaptive binarization submodule, a morphological processing submodule, and a parallel four-neighborhood centering algorithm module.

[0058] Each module according to Figure 2The modules are connected in a manner that reuses clock and reset interfaces. An 8-bit grayscale video signal is used as input and connected to a 5×5 median filter module. The output of the 5×5 median filter is then connected to the input of a 3×3 median filter module for noise reduction. The output of the 3×3 median filter module is connected to the input of an adaptive binarization module for binarization. The output of the adaptive binarization module is connected to a pre-set threshold and the input of a morphological processing module for morphological processing. Finally, the output of the morphological processing module is connected to the input of a four-neighborhood centering algorithm module for multi-spot center detection.

[0059] Furthermore, both the median filtering module and the dilation / erosion module construct a critical sliding window, the construction process of which is as follows: Figure 3 As shown, FIFO-2 and FIFO-1 form a chain-like buffer structure. The data read in the current row is first buffered in FIFO-2. After reading a row of data, when reading the next row of data, the data is written to FIFO-2 and read from FIFO-2 and written to FIFO-1. When the third row of data is read, FIFO-2 and FIFO-1 have buffered the image data of the previous row and the row before that, respectively. At the same time, the data is read from FIFO-2 and FIFO-1, and together with the data of the current row, a 3×3 sliding pixel window is formed. By calculating the median of the pixel values ​​in the window, the median value is used as the current pixel value to achieve the median filtering function.

[0060] Repeat the above operation. After obtaining a 3×3 sliding pixel window, accumulate all pixels in the window and compare it with a pre-set threshold. If the accumulated pixel value in the window is greater than the threshold, set the current pixel value to 1; if it is less than the threshold, set the current pixel value to 0. This achieves the functions of dilation and erosion.

[0061] Furthermore, after completing two stages of median filtering, binarization, and morphological processing, the resulting binarized spot image is used as input to execute a parallel four-neighbor center detection algorithm. The algorithm flow is as follows: Figure 4 As shown, it includes the following steps:

[0062] Step 1: Input binarized image data;

[0063] Step 2: Filter target pixels and check their neighborhood labels;

[0064] Step 3: Assign new tags or merge equivalent tags;

[0065] Step 4: Accumulate the coordinates and pixel values ​​of the pixels corresponding to the labels;

[0066] Step 5: Determine if the current frame has been processed;

[0067] Step 6: Analyze the equivalence table and calculate the centroid.

[0068] Furthermore, the workflow of step 3 is as follows: Figure 5 As shown, during the pixel labeling process, pixels with a value of 1 are treated as target pixels, while pixels with a value of 0 are not processed. To label a target pixel, a register-type variable `label_cnt` is first declared. `label_cnt` records the current label value starting from 1. Upon encountering a target pixel, it checks if there are any already labeled pixels to the left, upper left, upper right, and right of the target pixel. If so, the pixel with the smallest label value among these four neighbors is selected as the label for the current target pixel. If there are no already labeled pixels around the target pixel, the value of `label_cnt` is used as the label value for that target pixel, and `label_cnt + 1` is assigned to `label_cnt`.

[0069] While performing the tagging operation, it is necessary to merge the tags. An equivalence table RAM is constructed using a dual-port RAM. The address of this RAM is used as the root tag, and the value of the RAM is used as the tag equivalent to the corresponding address. The pixel tag value of pixel coordinate (2,2) is 1, and the pixel tag value of the left neighbor of this pixel is 2. Therefore, the value corresponding to address 2 of the equivalence table RAM is assigned as 1, indicating that the pixels corresponding to tag value 1 and tag value 2 are in the same connected component.

[0070] Furthermore, step 4 involves constructing three dual-port RAMs to accumulate the x-coordinate, y-coordinate, and pixel values ​​of pixels with the same label, such as... Figure 6 As shown, a pixel value accumulation RAM is constructed. When the video signal is transmitted to the pixel coordinate (4, 3), there are already 7 pixels with a label value of 1 in front of this pixel. Therefore, the value of address 1 of the pixel value accumulation RAM is 7. The value 7 at this address is read in the first clock cycle, and the value is incremented by 1 in the second clock cycle to replace the value at address 1 of the pixel value accumulation RAM. Similarly, X-axis coordinate accumulation RAM and Y-axis coordinate accumulation RAM can be constructed to store the horizontal and vertical coordinate accumulation values ​​of pixels with the same label value.

[0071] Furthermore, in step 6, after the transmission of one frame of image is completed, the equivalence table RAM in step 3 is traversed by address. During the traversal, if the address and value of the equivalence table RAM are different, the value of the equivalence table RAM is used as the main label, and the address of the equivalence table RAM is used as the sub-label. The main label and sub-label are used as the addresses of the pixel, horizontal, and vertical coordinate accumulation value RAM in step 4. The value at the address corresponding to the main label is read as the main value, and the value at the address corresponding to the sub-label is read as the sub-value. The sub-values ​​are accumulated to the main value and written back to the address corresponding to the main label. Then, the value at the address corresponding to the sub-label is set to zero. The above operation is repeated to finally obtain the pixel, horizontal, and vertical coordinate accumulation value RAM after label equivalence merging. The addresses corresponding to non-zero values ​​in these RAMs represent connected component labels. If the address and value of the equivalence table RAM are the same, no operation is performed.

[0072] Finally, by substituting the accumulated pixel, horizontal, and vertical coordinates at different addresses in RAM into the centroid algorithm described above, the center coordinates of different connected domains can be obtained.

[0073] Furthermore, the parallel four-neighbor center detection algorithm was simulated using VIVADO. Sixteen consecutive 64×64 binary images were input, each containing two connected components. The coordinates of the centers of these two connected components were calculated and recorded. The same 16 images were then processed using the MATLAB (R2022b) system function [L,n]=bwlabel(BW,conn). The parameters of the bwlabel function are shown in Table 1. The coordinates of the centers of the two connected components were calculated again, and these coordinates were used as a reference value. The difference between this difference and the coordinates obtained from the VIVADO simulation was taken, and the absolute value was calculated as follows: Figure 7 As shown in the comparison results, the absolute errors of the four center coordinates obtained by the FPGA parallel four-neighbor center detection algorithm and the four center coordinates obtained by the MATLAB function are all between 0 and 0.02 pixels. Therefore, the parallel four-neighbor center detection algorithm can meet the requirements of high-precision calculation.

[0074] Table 1

[0075] L Tag matrix n Number of connected objects BW Binary image conn Pixel connectivity (default 8-connectivity)

[0076] Furthermore, a time delay analysis was performed on the parallel four-neighbor center detection algorithm. During the simulation, key signals within the parallel four-neighbor center detection algorithm module, such as... Figure 8As shown in the figure, the signals are explained in Table 2. Theoretically, the next frame of data can be received after the global RAM initialization signal is pulled low. Therefore, we can use the time from when the input frame synchronization signal is pulled low to when the global RAM initialization signal is pulled low to represent the algorithm's running time. If the system uses a 50MHz clock, i.e., a clock period of 20ns, the number of clock cycles from when the input frame synchronization signal is pulled low to when the global RAM initialization signal is pulled low is approximately 544. Therefore, the algorithm's running time is 544 × 20 = 10880ns. This time is only related to the FPGA system clock and the internal RAM depth, and is independent of the frame rate and resolution of the input video, which can meet the real-time processing requirements of high frame rate and high resolution images.

[0077] Table 2

[0078] clk clock signal pre_img_vsync Input frame synchronization signal post_img_vsync Output frame synchronization signal find_ET Find the equivalence table signal find_ET_cnt[7:0] Lookup Equivalence Table Counter output_flag Output signal of center coordinates of connected domain output_flag_cnt[4:0] Connected domain center coordinate output counter init_RAM Global RAM initialization signal init_RAM_cnt[7:0] Global RAM initialization counter

[0079] Furthermore, the functional modules involved in this invention are placed and routed in VIVADO. The FPGA selected is the xc7z020clg400-2 chip, which is a mid-to-low-end SOC+FPGA heterogeneous chip from Xilinx. The hardware resource usage after placement and routing is checked, as shown in Table 3. The utilization rate of key resources is mostly below 10%. Therefore, this algorithm can be implemented using a lower-end FPGA, effectively reducing device costs.

[0080] Table 3

[0081] LUT 6486 53200 12.19 LUTRAM 1020 17400 5.86 FF 1997 106400 1.88 BRAM 4 140 2.88 BUFG 1 32 3.13

[0082] In summary, this invention implements a parallel four-neighbor center detection algorithm using FPGA, which has the advantages of low processing latency, low resource consumption, and accurate results.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A parallel four-neighborhood real-time multi-spot center detection method based on FPGA, characterized in that: Includes the following steps: The input image is noise-removed by a two-stage median filtering submodule, where the first stage uses a 5×5 filtering template and the second stage uses a 3×3 filtering template. The filtered image is converted into a binary image through an adaptive binarization submodule, which employs a dynamic threshold generation mechanism. Edge optimization processing of binary images is performed using a morphological processing submodule; Multi-spot center detection is performed using a four-neighborhood center detection algorithm module, which includes: Filter target pixels and check their neighboring label status. Assign new labels or merge equivalent labels based on the status of neighboring labels. The pixel coordinates corresponding to the labels are accumulated and stored using a two-stage pipeline architecture. After image frame processing is completed, the equivalence relation is parsed and the centroid coordinates of the spot are calculated. The two-stage median filtering submodule uses a first-in-first-out (FIFO) memory to construct a sliding window, wherein: The 5×5 filter template uses four synchronous FIFOs to buffer the first four rows of data. The 3×3 filter template uses two synchronous FIFOs to buffer the first two rows of data. Each clock cycle, the sliding window shifts one position to the right to calculate the median; The threshold generation method of the adaptive binarization submodule is as follows: in, Indicates the first k Frame threshold, α The scaling factor for the interval (0,1) is... Indicates the first k -1 frame's highest grayscale value When the pixel value is greater than Output 1 if the condition is met, otherwise output 0. The two-stage pipeline architecture includes: Three independent dual-port RAMs store the accumulated values ​​of the horizontal and vertical coordinates, and the pixel count, respectively. Configure two registers to build a read-modify-write pipeline. Each clock cycle completes the address read → value update → write-back operation; The formula for calculating the centroid coordinates is: in For the first connected component i The coordinates of a pixel. N The total number of pixels in the connected components. The calculation begins within one clock cycle after the image frame processing is completed.

2. The FPGA-based parallel four-neighborhood real-time multi-spot center detection method according to claim 1, characterized in that: The morphological processing submodule adopts a configurable template structure, which is implemented by setting different operation thresholds: Dilation is performed when the cumulative pixel value within the template exceeds the first threshold. Erosion operation is performed when the cumulative pixel value within the template is less than the second threshold. The template structure uses a 3×3 neighborhood window.

3. The FPGA-based parallel four-neighborhood real-time multi-spot center detection method according to claim 1, characterized in that: The equivalent label merging method of the four-neighbor center detection algorithm module includes: Construct the storage equivalence relation of dual-port random access memory (RAM). Compare the current pixel with its left, right, top, and top-right neighbor labels. The master label is determined and the equivalence table is updated using a three-level pipeline structure. The third-level pipeline points the equivalent tag node to the main tag.

4. The FPGA-based parallel four-neighborhood real-time multi-spot center detection method according to claim 1, characterized in that: The method, when implemented on an FPGA, includes: At a clock frequency of 50MHz, The processing delay per frame is t = (544±10) clock cycles, Hardware resource utilization is less than 15%. Among them, the LUT resource utilization rate is ≤12.2%, and the BRAM resource utilization rate is ≤2.9%.

5. A detection system for implementing the method of any one of claims 1 to 4, characterized in that: include: The image acquisition module is configured to receive 8-bit grayscale image signals and output them through a parallel data bus. The preprocessing module includes a cascaded 5×5 median filter unit, a 3×3 median filter unit, an adaptive binarization unit, and a morphological processing unit, wherein: The 5×5 median filtering unit buffers the first four rows of image data using four synchronous FIFOs. The 3×3 median filtering unit buffers the first two rows of image data using two synchronous FIFOs. The morphological processing unit uses a 3×3 sliding window and is configured to perform dilation or erosion operations. The real-time processing module receives the binary image signal output by the preprocessing module, including: The four-neighbor label analysis unit is configured to assign labels to target pixels and merge equivalence relations. The centroid calculation unit is configured to parse label data and calculate the coordinates of the light spot center. The output interface module outputs centroid coordinate data via the AXI-Stream protocol; The system employs a global synchronous clock and an asynchronous reset signal, and the modules are connected via a pipelined architecture, satisfying the following: The row buffer delay between the image acquisition module and the preprocessing module is 2 clock cycles. The label assignment and equivalence table merging operations of the real-time processing module take 3 clock cycles. The centroid coordinate output delay does not exceed one frame period.

Images