Lossy compression in memory

Abstract

The invention relates to lossy compression in memory. In some embodiments, a controller may receive a command from a host device to write data to a memory location. The controller may compress the data using a lossy compression operation to obtain compressed data. The controller may cause the compressed data to be written to the memory location.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 551,778, filed on February 9, 2024, and entitled “LOSSY COMPRESSION IN MEMORY.” The disclosure of the prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to memory devices, memory device operations, and lossy compression in, for example, memory. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. Memory devices include memory cells. A memory cell is an electronic circuit that can be programmed into one of two or more data states. For example, a memory cell can be programmed into a data state representing a single binary value, typically represented by a binary "1" or a binary "0." As another example, a memory cell can be programmed into a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a group of memory cells. To access the stored information, the electronic device can read or sense the stored state from the group of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for extended periods of time even in the absence of an external power source. Volatile memory (e.g., DRAM) may lose stored data over time unless the volatile memory is refreshed by power. In some examples, a memory device may be associated with Compute Express Link (CXL). For example, the memory device may be a CXL-compatible memory device and / or may include a CXL interface. Summary of the Invention

[0006] In one aspect, the present disclosure provides a memory system comprising: one or more memory components configurable as one or more logical memory devices, wherein the one or more logical memory devices are to be configured to enable lossy compression or disable lossy compression; and a controller configured to: receive a command from a host device to write data to a memory location; in response to the memory location corresponding to a logical memory device of the one or more logical memory devices that is configured to enable lossy compression, compress the data to obtain compressed data; and cause the compressed data to be written to the memory location.

[0007] In another aspect, the present disclosure provides a system comprising: one or more host devices; and a memory pool comprising: a non-compressed memory system; and a compressed memory system comprising: one or more memory components configurable as one or more logical memory devices, wherein the one or more logical memory devices are configured to enable lossy compression or disable lossy compression; and a controller configured to: receive a command from the host device to write data to a memory location; in response to the memory location corresponding to a logical memory device in the one or more logical memory devices that is configured to enable lossy compression, compress the data using a lossy compression operation to obtain compressed data; and write the compressed data to the memory location.

[0008] In another aspect, the present disclosure provides a method comprising: receiving, by a controller of a memory system, a command from a host device to write data to a memory location; compressing, by the controller, the data using a lossy compression operation to obtain compressed data; and causing, by the controller, the compressed data to be written to the memory location. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system capable of lossy compression in memory.

[0010] Figure 2 is a diagram illustrating an example system capable of lossy compression in memory.

[0011] Figure 3 is a diagram illustrating an example CXL structural configuration capable of lossy compression in memory.

[0012] Figures 4A to 4C is a diagram of an example of lossy compression in memory.

[0013] Figure 5 is a diagram of an instance of a controller.

[0014] Figure 6 is a diagram of an example system with memory pooling.

[0015] Figure 7 is a flow diagram of an example method associated with in-memory lossy compression. DETAILED DESCRIPTION

[0016] Emerging computing applications (such as artificial intelligence, cloud computing, or virtual reality) may involve the use of very large data sets. Efficient processing of large data sets requires large amounts of memory (e.g., random access memory (RAM)). In some cases, virtual memory, which uses storage devices (e.g., disk storage devices) to provide a virtual address space that can exceed the capacity of main memory, is a technique for accommodating large data sets. However, virtual memory may be associated with reduced system performance. In addition, expanding the system's main memory may be cost-prohibitive.

[0017] Compression enables data size reduction, thereby increasing memory capacity, reducing energy costs, and reducing bandwidth consumption. For example, compression can alleviate memory bandwidth pressure by reducing the amount of data transferred between main memory and the processor. Typically, main memory compression is performed at the system level (e.g., by the host system). Furthermore, main memory compression typically employs lossless compression methods, which are not associated with high compression ratios.

[0018] Some embodiments described herein utilize memory disaggregation to enable data compression to be performed by the memory system (e.g., CXL memory modules) rather than performing compression at the host processor. This enables a relatively small amount of memory to provide increased memory capacity. In some embodiments, the compression performed by the memory system may be lossy compression (e.g., used in approximate computing), which can be utilized with a broad class of applications that tolerate approximations. For example, the memory system may include a lossy compression and decompression engine. "Lossy compression" refers to a data compression technique that reduces the data size of content by selectively and permanently discarding portions of the content's original data.

[0019] At the system level, one or more memory systems equipped with lossy compression may be part of a memory pool (e.g., along with one or more memory systems not equipped with lossy compression). In some embodiments, a host system may mark pages allocated to an application as approximable or non-approximable based on the application's configuration indicating whether a particular data region is approximable. The "approximable" information may be sufficiently represented or approximated with an acceptable degree of accuracy so that less important details can be removed to achieve compression. Memory systems equipped with lossy compression may be used to compress and store approximable pages, thereby efficiently utilizing the resources of the memory pool. In this way, large amounts of data may be managed in memory without using storage devices (e.g., disk storage devices), thereby improving system performance. In addition, the high compression ratios associated with lossy compression enable increased memory capacity in a relatively small amount of memory. Therefore, due to the flexibility of the disaggregated system, these high-capacity memory resources may be used in racks or structures and may be used to meet the needs of applications that tolerate approximation.

[0020] Figure 1 1 is a diagram illustrating an example system 100 capable of lossy compression in memory. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 through 120-N (where N ≥ 1). The memory devices may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via respective memory interfaces 145, shown as memory interfaces 145-1 through 145-N (where N ≥ 1).

[0021] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or airplane), and / or an Internet of Things (IoT) device. Host system 105 can include host processor 150. Host processor 150 can include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 can include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or another type of processing component.

[0022] The memory system 110 may be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 may be a hard disk drive, a solid-state drive (SSD), a flash memory system (e.g., a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (e.g., a secure digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), and / or a RAM device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0023] The memory system controller 115 can be any device configured to control the operation of the memory system 110 and / or the operation of the memory devices 120. For example, the memory system controller 115 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the memory system controller 115 can communicate with the host system 105 and can instruct one or more memory devices 120 regarding memory operations to be performed by those memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 can provide instructions to the local controllers 125 regarding memory operations to be performed by the local controllers 125 in conjunction with the corresponding memory devices 120.

[0024] The memory device 120 may include a local controller 125 and one or more memory arrays 130. In some implementations, the memory device 120 includes a single memory array 130. In some implementations, each memory device 120 of the memory system 110 may be implemented in a separate semiconductor package or on a separate die that includes a respective local controller 125 and a respective memory array 130 for that memory device 120. The memory system 110 may include multiple memory devices 120.

[0025] The local controller 125 can be any device configured to control the memory operations of the memory device 120 in which it is included (e.g., and not control the memory operations of other memory devices 120). For example, the local controller 125 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the local controller 125 can communicate with the memory system controller 115 and can control operations performed on the memory array 130 coupled to the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 can be an SSD controller, and the local controller 125 can be a NAND controller.

[0026] The memory array 130 may include an array of memory cells configured to store data. For example, the memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some implementations, the memory system 110 may include one or more volatile memory arrays 135. The volatile memory array 135 may include an SRAM array and / or a DRAM array, among other examples. The one or more volatile memory arrays 135 may be included in the memory system controller 115, in one or more memory devices 120, and / or in both the memory system controller 115 and the one or more memory devices 120. In some implementations, the memory system 110 may include both non-volatile memory capable of maintaining stored data after the memory system 110 is powered off, and volatile memory (e.g., the volatile memory array 135) that requires power to maintain stored data and loses stored data after the memory system 110 is powered off. For example, the volatile memory array 135 may cache data read from or to be written to the non-volatile memory and / or may cache instructions to be executed by the controller of the memory system 110 .

[0027] The host interface 140 enables communication between the host system 105 (e.g., the host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 may include, for example, a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, an NVMe interface, a USB interface, a universal flash storage (UFS) interface, an eMMC interface, a double data rate (DDR) interface, and / or a DIMM interface.

[0028] In some examples, memory device 120 may be a Compute Express Link (CXL)-compatible memory device 120. For example, memory device 120 may include a PCIe / CXL interface (e.g., host interface 140 may be associated with a PCIe / CXL interface). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry-standard open interface for high-speed communication. CXL technology is built on the PCIe infrastructure, leveraging the PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols, and coherent interfaces.

[0029] The memory interface 145 enables communication between the memory system 110 and the memory device 120. The memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0030] Although the example memory system 110 described above includes a memory system controller 115, in some embodiments, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in the host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, "controller" may refer to the memory system controller 115, the local controller 125, or an external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of operations may be performed by the memory system controller 115, and a second subset of operations may be performed by the local controller 125. Furthermore, depending on the context, the term "memory device" may refer to either the memory system 110 or the memory device 120.

[0031] A controller (e.g., memory system controller 115, local controller 125, or external controller) can control operations performed on a memory (e.g., memory array 130), for example, by executing one or more instructions. For example, memory system 110 and / or memory device 120 can store one or more instructions as firmware in memory, and the controller can execute those one or more instructions. Additionally or alternatively, the controller can receive one or more instructions from host system 105 and / or from memory system controller 115 and can execute those one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by the controller. The controller can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller causes the controller, memory system 110, and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, a controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands."

[0032] For example, a controller (e.g., memory system controller 115, local controller 125, or external controller) can transmit signals to and / or receive signals from a memory (e.g., one or more memory arrays 130) based on one or more instructions, such as to transfer data to (e.g., write or program) all or a portion of a memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory), transfer data from (e.g., read), erase, and / or refresh all or a portion of the memory. Additionally or alternatively, the controller can be configured to control access to the memory and / or provide a translation layer between the host system 105 and the memory (e.g., for mapping logical addresses to physical addresses of the memory array 130). In some embodiments, the controller can translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0033] Figure 1 The number and arrangement of components shown are provided as examples. Figure 1 There may be additional components, fewer components, different components, or components arranged differently than those shown. Figure 1 Two or more components shown may be implemented in a single component, or Figure 1A single component shown may be implemented as multiple distributed components. Additionally or alternatively, Figure 1 The illustrated set of components (e.g., one or more components) may execute the functions described as being Figure 1 One or more actions performed by another set of components are shown.

[0034] Figure 2 is a diagram illustrating an example system 200 capable of lossy compression in memory. System 200 may include one or more devices, apparatuses, and / or components for performing the operations described herein. In some embodiments, system 200 is a CXL system. For example, system 200 may be configured to utilize memory pooling with multiple logical devices.

[0035] As shown, system 200 may include multiple host devices 205 and multiple memory devices 210. Host devices 205 may include a CPU. In some implementations, each host device 205 corresponds to host system 105 and / or host processor 150. Memory devices 210 may include CXL devices (e.g., CXL-compatible devices). In some implementations, memory devices 210 may include Type 3 CXL devices. For example, memory devices 210 may include memory modules and / or memory expansion devices (e.g., volatile memory devices). As an example, memory devices 210 may include a memory controller (e.g., a CXL ASIC controller) and one or more memory components (e.g., memory packages) coupled to the memory controller. In some implementations, each memory device 210 may correspond to memory system 110 or memory device 120.

[0036] Host device 205 and memory device 210 may be communicatively coupled via a switch 215 (e.g., one or more switches 215). In some implementations, switch 215 is a CXL switch. Switch 215 may include a hardware bridge, such as a PCIe bridge. In some implementations, system 200 (e.g., host device 205, memory device 210, and / or switch 215) may be configured in a fabric. For example, system 200 (e.g., host device 205, memory device 210, and / or switch 215) may be configured in a CXL fabric.

[0037] System 200 may include a manager component 220. Manager component 220 may be a device or implemented in a device. For example, manager component 220 is shown as a component of switch 215, but in some examples may reside external to switch 215. Manager component 220 may be configured to manage the fabric of system 200 (e.g., manager component 220 may be a fabric manager). Manager component 220 may be implemented in hardware and / or software.

[0038] The memory devices 210 may form a memory pool for the host device 205. In some embodiments, the memory (e.g., memory components) of the memory device 210 may be mapped to one or more (e.g., multiple) logical memory devices 225. At the system level, a logical memory device 225 may correspond to a memory address range. The logical memory devices 225 of the memory device 210 may be available to one or more of the host devices 205. For example, all logical memory devices 225 of a single memory device 210 may be available to a particular host device 205, or a subset of the logical memory devices 225 of a single memory device 210 may be available to a particular host device 205. In some embodiments, the logical memory devices 225 available to a particular host device 205 may be distributed across multiple memory devices 210.

[0039] Figure 2 The number and arrangement of components shown are provided as examples. Figure 2 There may be additional components, fewer components, different components, or components arranged differently than those shown. Figure 2 Two or more components shown may be implemented in a single component, or Figure 2 A single component shown may be implemented as multiple distributed components. Additionally or alternatively, Figure 2 The illustrated set of components (e.g., one or more components) may execute the functions described as being Figure 2 One or more actions performed by another set of components are shown.

[0040] Figure 3 is a diagram illustrating an example CXL fabric configuration 300 capable of lossy compression in memory. As shown, multiple devices 305 (e.g., CXL-compatible devices) may be interconnected via a CXL fabric 310. Multiple devices 305 may include one or more host devices (e.g., host device 205), one or more Type 1 CXL devices (e.g., specialized accelerators such as network interface controllers), one or more Type 2 CXL devices (e.g., general-purpose accelerators such as GPUs, ASICs, or FPGAs), and / or one or more Type 3 CXL devices (e.g., global fabric attached memory (GFAM) devices, such as memory device 210). CXL fabric 310 may be configured to interconnect devices 305 to enable communication (e.g., peer-to-peer communication) between devices 305. The CXL fabric may be implemented in hardware and / or software. As further shown, CXL fabric configuration 300 may include a manager component 315, similar to manager component 220 described herein.

[0041] In some embodiments, Figures 1 to 3One or more systems, devices, apparatuses, components and / or controllers may be configured to receive a command from a host device to write data to a memory location; in response to the memory location corresponding to a logical memory device configured to enable lossy compression, compress the data to obtain compressed data; and cause the compressed data to be written to the memory location.

[0042] In some embodiments, Figures 1 to 3 One or more systems, devices, apparatuses, components and / or controllers may be configured to receive a command from a host device to write data to a memory location; in response to the memory location corresponding to a logical memory device configured to enable lossy compression, compress the data using a lossy compression operation to obtain compressed data; and write the compressed data to the memory location.

[0043] In some embodiments, Figures 1 to 3 One or more systems, devices, apparatuses, components and / or controllers may be configured to receive a command from a host device to write data to a memory location; compress the data using a lossy compression operation to obtain compressed data; and cause the compressed data to be written to the memory location.

[0044] Figure 3 The number and arrangement of components shown are provided as examples. Figure 3 There may be additional components, fewer components, different components, or components arranged differently than those shown. Figure 3 Two or more components shown may be implemented in a single component, or Figure 3 A single component shown may be implemented as multiple distributed components. Additionally or alternatively, Figure 3 The illustrated set of components (e.g., one or more components) may execute the functions described as being Figure 3 One or more actions performed by another set of components are shown.

[0045] Figures 4A to 4C 4 is a diagram of an example of lossy compression in memory. As shown, example 400 includes a host device 405 and a memory system 410. Host device 405 may correspond to host system 105, host processor 150, host device 205, and / or device 305. Memory system 410 may correspond to memory system 110, memory device 120, memory device 210, and / or device 305. For example, host device 405 and memory system 410 may be in system 200 and / or in a CXL configuration 300.

[0046] In some implementations, memory system 410 is a Type 3CXL device. For example, memory system 410 may include memory modules and / or memory expansion devices. As shown, memory system 410 includes a controller 412 and one or more memory components 414 (e.g., memory packages). Controller 412 may include an ASIC, FGPA, or the like. In some implementations, controller 412 may include a lossy compression / decompression engine 416. Lossy compression / decompression engine 416 enables memory system 410 to compress data using lossy compression operations. Lossy compression / decompression engine 416 may be implemented in hardware and / or software.

[0047] As shown, the memory system 410 may have a logical representation 418. In the logical representation 418 of the memory system 410, the memory component 414 may be configured as a plurality of logical memory devices 420, as described herein. In some implementations, one or more of the logical memory devices 420 may be configured to enable lossy compression (e.g., logical memory devices 420-2 and 420-3 in example 400). In addition, one or more of the logical memory devices 420 may be configured to disable lossy compression (e.g., logical memory devices 420-1, 420-4, and 420-n in example 400). In other words, the memory system 410 is configurable such that lossy compression (e.g., lossy compression / decompression engine 416) may be selectively enabled or disabled in each logical memory device 420 (e.g., enabled or disabled on a per-logical memory device basis). In some implementations, the memory component 414 may be configured as a single logical memory device 420 that is configured to enable or disable lossy compression. In some implementations, the logical memory device 420 is selectively configurable to enable or disable lossy compression upon initialization (eg, booting) of the memory system 410 .

[0048] As further shown, the logical representation 418 may include one or more logical ports 422 (also referred to as "CXL ports" or "heads") configured to handle requests to the logical memory device 420. For example, the logical memory device 420 may be mapped to one or more logical ports 422. In some implementations, the logical representation 418 may include multiple logical ports 422.

[0049] Host device 405 may implement one or more applications (e.g., artificial intelligence applications, graphics applications, or the like). Certain data areas of an application may be configured (e.g., annotated) as approximable (e.g., by the application's programmer using specialized system calls). For example, in a graphics application, data related to the background of an image may be configured as approximable. In some embodiments, the approximable data may be configured (e.g., by the application's programmer) with one or more error thresholds. For example, a first threshold may limit the allowable error introduced by a single compression event, and a second threshold may limit the total accumulated error over the entire lifetime of the application.

[0050] Host device 405 may allocate one or more pages for an application executing on host device 405. If the allocated page will contain application data that is configured to be approximable, host device 405 may mark the page as approximable. For example, host device 405 may mark the page as approximable or non-approximable. As an example, each entry for a page in a page table and / or a translation lookaside buffer (TLB) may include an approximability indication (e.g., an additional bit) indicating whether the page is approximable.

[0051] If the data to be written to the memory is associated with a flag indicating that the data is approximable (e.g., in a page table and / or TLB), the host device 405 may map the data to a memory location (e.g., a memory address) associated with a logical memory device 420 configured to enable lossy compression. For example, the host device 405 may store information indicating one or more address ranges associated with a logical memory device 420 configured to enable lossy compression and / or one or more address ranges associated with a logical memory device 420 configured to disable lossy compression (or not capable of lossy compression). In this manner, one or more logical memory devices 420 configured to enable lossy compression can be used to store approximable pages.

[0052] like Figure 4A , and shown by reference numeral 450, the host device 405 can transmit a command to write data to a memory location, and the controller 412 can receive the command. The controller 412 can recognize that the memory location corresponds to a logical memory device 420 configured to enable lossy compression (e.g., logical memory device 420-2 or 420-3), indicating that the data will be compressed before being written.

[0053] As shown by reference numeral 455, in response to the memory location corresponding to the logical memory device 420 configured to enable lossy compression, the controller 412 can use a lossy compression operation to compress the data to obtain compressed data. For example, the controller 412 can be configured to use the lossy compression / decompression engine 416 to compress the data. The lossy compression operation can reduce the size of the data. The lossy compression operation can use a lossy compression model or algorithm. For example, the lossy compression operation can use a fast, error-bounded lossy high-performance computing (HPC) data compression, such as a squeeze (SZ) algorithm, an SZx algorithm, or another algorithm.

[0054] As shown by reference numeral 460, the controller 412 may cause compressed data to be written to a memory location (e.g., the controller 412 may write compressed data to a memory location). For example, the controller 412 may cause compressed data to be written to one or more memory components 414 that are mapped to the logical memory device 420. Writing compressed data to memory instead of the original uncompressed data may increase the virtual memory capacity of the memory system 410.

[0055] In some embodiments, before writing the compressed data to the memory location, the controller 412 may determine an error value for the compressed data. To determine the error value, the controller 412 may decompress the compressed data (e.g., using the lossy compression / decompression engine 416) to obtain decompressed data and compare the decompressed data with the original data. For example, the error value may be based on the difference between the decompressed data and the original data. Thus, the controller 412 may cause the compressed data to be written to the memory location in response to the error value meeting a threshold (e.g., the error value does not exceed the threshold). Otherwise, if the error value does not meet the threshold (e.g., the error value exceeds the threshold), the controller 412 may discard the compressed data and may cause the original uncompressed data to be written to the memory location (e.g., skipping compression of the data).

[0056] In some implementations, if the relative error of each individual value of the block (e.g., calculated as described above) does not exceed a first percentage threshold, the controller 412 may cause the compressed data to be written to the memory location. Additionally or alternatively, if the average relative error across all values of the block does not exceed a second percentage threshold, the controller 412 may cause the compressed data to be written to the memory location.

[0057] In some embodiments, the controller 412 can determine the updated virtual memory capacity of the logical memory device 420 resulting from writing the compressed data to the memory location. For example, compressing the data can result in an increased virtual memory capacity. The controller 412 can output an indication of the updated virtual memory capacity to the host device 405. In some embodiments, the memory system 410 can utilize the CXL dynamic capacity feature to manage capacity changes due to compression.

[0058] like Figure 4B , and shown by reference numeral 465, the host device 405 may transmit an additional command to read from a memory location, and the controller 412 may receive the command. The controller 412 may recognize that the memory location corresponds to a logical memory device 420 configured to enable lossy compression (e.g., logical memory device 420-2 or 420-3), indicating that the data being read is to be decompressed.

[0059] As shown by reference numeral 470, in response to the memory location corresponding to the logical memory device 420 configured to enable lossy compression, the controller 412 can read the compressed data from the memory location and decompress the compressed data using a decompression operation to obtain decompressed data. For example, the controller 412 can be configured to decompress the data using the lossy compression / decompression engine 416. The decompression operation can be related to the lossy compression operation (e.g., the decompression operation can provide decompression of data compressed by the lossy compression operation). As shown by reference numeral 475, the memory system 410 (e.g., the controller 412) can then output the decompressed data to the host device 405.

[0060] like Figure 4C As shown in FIG4 and shown by reference numeral 480, the host device 405 may transmit an additional command to write additional data to the additional memory location, and the controller 412 may receive the command. The controller 412 may recognize that the additional memory location corresponds to a different logical memory device 420 configured to disable lossy compression (e.g., logical memory device 420-1, 420-4, or 420-n), indicating that the additional data is to be written uncompressed. Therefore, as shown by reference numeral 485, in response to the memory location corresponding to a different logical memory device 420 configured to disable lossy compression, the controller 412 may cause the additional data to be written to the additional memory location without using lossy compression (e.g., the controller 412 may write the additional data to the additional memory location without lossy compression). For example, the controller 412 may cause the additional data to be written to one or more memory components 414 mapped to the different logical memory device 420 without lossy compression.

[0061] As indicated above, FIG4 is provided as an example. Other examples may differ from what is described with respect to FIG4.

[0062] Figure 5 is a diagram of an example of a controller 412. As shown, a PCIe / CXL interconnect 502 (e.g., based on a PCIe physical link layer and the CXL protocol) can be connected to a CXL physical layer (PHY) component 504 of the controller 412. The controller 412 can include a CXL control component 506, a lossy compression / decompression engine 416, a channel interleaver component 508 (e.g., configured to remap addresses to physical memory addresses), one or more error manager components 510, one or more DDR control components 512, and / or one or more DDR PHY components 514. The DDR PHY component 514 can be configured to drive a memory bus interface via one or more DDR interconnects 516. The controller 412 may also include one or more peripheral devices, such as an inter-integrated circuit (I2C) and / or improved inter-integrated circuit (I3C) component 518, a joint test action group (JTAG) component 520, a quad serial peripheral interface (QSPI) component 522 and / or a CPU 524 (e.g., for peripheral computing operations, such as security operations), among other examples.

[0063] As instructed above, Figure 5 Provided as an example. Other examples may vary from the Figure 5 The content described.

[0064] Figure 6 6 is a diagram of an example system 600 with memory pooling. System 600 is illustrated as a rack system, but other configurations of system 600 may be employed. As shown, system 600 may include one or more compute servers 605 (e.g., each corresponding to a host device 405 or collectively corresponding to a host device 405), a memory pool 610, and a switch 615 (e.g., a top-of-rack (TOR) switch that may correspond to switch 215).

[0065] Memory pool 610 may include multiple memory systems 620. Memory system 620 may be a Type 3CXL device. For example, memory system 620 may include memory modules and / or memory expansion devices. Memory system 620 may include one or more non-compressed memory systems 620a and / or one or more compressed memory systems 620b. Non-compressed memory system 620a may lack the ability to perform lossy compression. For example, non-compressed memory system 620a may lack a lossy compression / decompression engine, as described herein. Compressed memory system 620b may have the ability to perform lossy compression. For example, compressed memory system 620b may correspond to memory system 410. As an example, compressed memory system 620b may be represented as multiple logical memory devices, and lossy compression may be enabled or disabled on a per-logical memory device basis, as described herein.

[0066] As instructed above, Figure 6 Provided as an example. Other examples may vary from the Figure 6 The content described.

[0067] Figure 7 700 is a flow chart of an example method 700 associated with lossy compression in memory. In some implementations, a controller (e.g., controller 412) may execute or be configured to execute method 700. In some implementations, another device or group of devices (e.g., memory system 410) independent of or including the controller may execute or be configured to execute method 700. Additionally or alternatively, one or more components of the controller (e.g., lossy compression / decompression engine 416) may execute or be configured to execute method 700. Thus, means for executing method 700 may include the controller and / or one or more components of the controller. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the controller, cause the controller to execute method 700.

[0068] like Figure 7 As shown in FIG, method 700 may include receiving a command from a host device to write data to a memory location (block 710). Figure 7 As further shown in FIG. 7 , method 700 may include compressing the data using a lossy compression operation to obtain compressed data (block 720). Figure 7 As further shown in FIG. 7 , method 700 may include causing the compressed data to be written to a memory location (block 730 ).

[0069] Method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0070] In a first aspect, a memory system includes one or more memory components configured as one or more logical memory devices.

[0071] In a second aspect, alone or in combination with the first aspect, in response to the memory location corresponding to a logical memory device of the one or more logical memory devices configured to enable lossy compression, the data is compressed.

[0072] In a third aspect, alone or in combination with one or more of the first and second aspects, method 700 includes receiving an additional command to write additional data to an additional memory location, and in response to the additional memory location corresponding to an additional logical memory device of the one or more logical memory devices that is configured to disable lossy compression, causing the additional data to be written to the additional memory location without using a lossy compression operation.

[0073] In a fourth aspect, alone or in combination with one or more of the first through third aspects, the one or more logical memory devices include a plurality of logical memory devices mapped to a plurality of logical ports.

[0074] In a fifth aspect, alone or in combination with one or more of the first to fourth aspects, method 700 includes receiving an additional command to read from a memory location, decompressing compressed data using a decompression operation to obtain decompressed data, and outputting the decompressed data.

[0075] although Figure 7 Example blocks of method 700 are shown, but in some embodiments, Figure 7 Method 700 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than those depicted in the preceding text. Additionally or alternatively, two or more blocks of method 700 may be performed in parallel. Method 700 is an example of a method that may be performed by one or more devices described herein. These one or more devices may perform or be configured to perform one or more other methods based on the operations described herein.

[0076] In some implementations, a memory system includes one or more memory components configurable as one or more logical memory devices, wherein the one or more logical memory devices are to be configured to enable lossy compression or disable lossy compression; and a controller configured to: receive a command from a host device to write data to a memory location; in response to a memory location corresponding to a logical memory device of the one or more logical memory devices that is configured to enable lossy compression, compress the data to obtain compressed data; and cause the compressed data to be written to the memory location.

[0077] In some embodiments, a system includes one or more host devices; and a memory pool including: a non-compressed memory system; and a compressed memory system including: one or more memory components configurable as one or more logical memory devices, wherein the one or more logical memory devices are configured to enable lossy compression or disable lossy compression; and a controller configured to: receive a command from the host device to write data to a memory location; in response to a memory location corresponding to a logical memory device of the one or more logical memory devices configured to enable lossy compression, compress the data using a lossy compression operation to obtain compressed data, the compressed data being configured to enable lossy compression; and write the compressed data to the memory location.

[0078] In some implementations, a method includes: receiving, by a controller of a memory system and from a host device, a command to write data to a memory location; compressing, by the controller, the data using a lossy compression operation to obtain compressed data; and causing, by the controller, the compressed data to be written to the memory location.

[0079] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0080] As used herein, "satisfies a threshold" may refer to a value being greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like, depending on the context.

[0081] Even if a particular combination of features is described in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner not specifically described in the claims and / or disclosed in the specification. For example, the present disclosure includes each dependent claim in the claim set and each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, a phrase referring to "at least one" in a list of items refers to any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination with multiples of the same element (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other arrangement of a, b, and c).

[0082] When a "component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (either within a single claim or across multiple claims) as performing or being configured to perform multiple operations, this language is intended to broadly cover a variety of architectures and environments. For example, unless expressly stated otherwise (e.g., through use of "a first component" and "a second component" or other language that distinguishes components in the claims), this language is intended to encompass a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform operations. For example, when a claim has the form "one or more components configured to: perform X; perform Y; and perform Z," the claim should be interpreted to mean "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z."

[0083] Unless explicitly described, any element, behavior or instruction used herein should not be interpreted as critical or necessary. Moreover, as used herein, the article "a / an" is intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more items cited in conjunction with the article "the" and can be used interchangeably with "the one or more". If it is desired to use only one item, then the phrase "only one", "single" or similar language is used. In addition, as used herein, the term "has / have / having" or the like is intended to be an open term that does not limit the element it modifies (for example, an element "having" A may also have B). In addition, the phrase "based on" is intended to mean "at least partially based on", unless otherwise explicitly stated. As used herein, the term "multiple" can be replaced with "multiple", and vice versa. Furthermore, as used herein, the term "or" is intended to be inclusive when used in a series and is used interchangeably with "and / or" unless expressly stated otherwise (e.g., if used in combination with "either" or "only one of...").

Claims

1. A memory system comprising: One or more memory components, which may be configured as one or more logical memory devices, wherein the one or more logical memory devices are to be configured to enable lossy compression or disable lossy compression; and A controller configured to: receiving a command from a host device to write data to a memory location; in response to the memory location corresponding to a logical memory device of the one or more logical memory devices configured to enable lossy compression, compressing the data to obtain compressed data; and The compressed data is caused to be written to the memory location.

2. The memory system of claim 1, wherein the controller is configured to compress the data using a lossy compression operation using a lossy compression and decompression engine of the controller.

3. The memory system of claim 1 , wherein the controller is further configured to: receiving additional commands to write additional data to additional memory locations; and In response to the additional memory location corresponding to an additional logical memory device of the one or more logical memory devices that is configured to disable lossy compression, the additional data is caused to be written to the additional memory location without using the lossy compression operation.

4. The memory system of claim 1 , wherein the controller is further configured to: receiving an additional command to read from the memory location; decompressing the compressed data using a decompression operation to obtain decompressed data; and The decompressed data is output.

5. The memory system of claim 1 , wherein the controller is further configured to: determining an updated virtual memory capacity of the one or more logical memory devices resulting from writing the compressed data to the memory location; and An indication of the updated virtual memory capacity is output. The memory system of claim 1 , wherein the data is associated with a flag indicating that the data is approximable.

7. The memory system of claim 1, wherein the one or more memory components comprise volatile memory.

8. A system comprising: one or more host devices; and A storage pool comprising: Uncompressed memory systems; and A compressed memory system comprising: One or more memory components, which may be configured as one or more logical memory devices, wherein the one or more logical memory devices are to be configured to enable lossy compression or disable lossy compression; and A controller configured to: receiving a command from a host device to write data to a memory location; In response to the memory location corresponding to a logical memory device of the one or more logical memory devices that is configured to enable lossy compression, compressing the data using a lossy compression operation to obtain compressed data; and The compressed data is written to the memory location.

9. The system of claim 8, wherein the one or more logical memory devices comprises a plurality of logical memory devices.

10. The system of claim 8, wherein the controller is further configured to: receiving additional commands to write additional data to additional memory locations; and In response to the additional memory location corresponding to an additional logical memory device of the one or more logical memory devices that is configured to disable lossy compression, the additional data is caused to be written to the additional memory location without using the lossy compression operation.

11. The system of claim 8, wherein the controller is further configured to: receiving an additional command to read from the memory location; decompressing the compressed data using a decompression operation to obtain decompressed data; and The decompressed data is output.

12. The system of claim 8, wherein the controller is further configured to: determining an error value for the compressed data, Wherein the controller is configured to cause the compressed data to be written to the memory location in response to the error value satisfying a threshold.

13. The system of claim 12, wherein to determine the error value, the controller is configured to: decompressing the compressed data to obtain decompressed data; and comparing the decompressed data with the data, Wherein the error value is based on a difference between the decompressed data and the data.

14. The system of claim 8, wherein the compressed memory system is a Type 3 Compute Express Link (CXL) device.

15. A method comprising: receiving, by a controller of the memory system from a host device, a command to write data to a memory location; compressing, by the controller, the data using a lossy compression operation to obtain compressed data; and The compressed data is caused, by the controller, to be written to the memory location.

16. The method of claim 15, wherein the memory system comprises one or more memory components configured as one or more logical memory devices.

17. The method of claim 16, wherein in response to the memory location corresponding to a logical memory device of the one or more logical memory devices that is configured to enable lossy compression, the data is compressed.

18. The method of claim 16, further comprising: receiving an additional command to write additional data to an additional memory location; and In response to the additional memory location corresponding to an additional logical memory device of the one or more logical memory devices that is configured to disable lossy compression, the additional data is caused to be written to the additional memory location without using the lossy compression operation.

19. The method of claim 16, wherein the one or more logical memory devices comprise a plurality of logical memory devices mapped to a plurality of logical ports.

20. The method of claim 15, further comprising: receiving an additional command to read from the memory location; decompressing the compressed data using a decompression operation to obtain decompressed data; and The decompressed data is output.

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