Implementation method of rt-thread priority scheduling based on RISC-V instruction set

Abstract

The present invention discloses a method for implementing RT-thread priority scheduling based on the RISC-V instruction set, belonging to the field of data processing technology. The method comprises: representing 256 priorities using a two-layer priority bitmap; executing a function X in the first layer to search for the first bit a that is 1 in the 32-bit priority bitmap from low to high; searching for a corresponding group in the second layer based on a, and then executing a function Y on this group to search for the first bit b that is 1 in the 8-bit priority bitmap from low to high; using 8*a+b as the highest priority sequence number among the 256 priorities, obtaining a linked list of ready thread control block pointers with a priority of 8*a+b, extracting the first thread control block pointer in the linked list of thread control block pointers; and switching the thread corresponding to the highest priority to the processor to complete the thread switching. The method for implementing RT-thread priority scheduling based on the RISC-V instruction set solves the problems of large space usage, branch instructions, and low memory read efficiency of current operating system RT-threads.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to an RT-thread priority scheduling implementation method based on the RISC-V instruction set. Background Art

[0002] The main function of the operating system kernel is to manage and schedule threads. During this process, threads are switched. This step is implemented by the RTOS kernel programming. The thread switching of the domestic operating system RT-thread switches the highest priority thread to the processor. RT-thread supports 256 thread priorities. The current RT-thread thread switching steps are as follows:

[0003] In the current rt-thread, the implementation of function Z uses an array of 256 elements as a lookup table. Each element occupies one byte. The 8-bit subscript of each element is used as the key, and the 8-bit content of each element is used as the value. The value is the sequence number of the first 1 bit in the 8-bit binary number corresponding to the key from the low bit to the high bit. The lookup table array for:

[0004] 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0005] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0006] 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0007] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0008] 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0009] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0010] 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0011] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0012] 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0013] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0014] 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0015] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0016] 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0017] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0018] 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0,

[0019] 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0

[0020] The logical flow of function Z is:

[0021]

[0022] This code uses a table lookup to obtain the sequence number of the first 1-bit in a binary number, from low to high. This method divides the 32-bit number into four 8-bit bits, with each 8-bit being used as an array subscript to read the corresponding element. The array element value represents the sequence number of the first 1-bit bit from bit 0 to bit 7 in a single 8-bit byte (calculated and stored in the array in advance). Adding 1, 9, 17, and 25, the bit sequence numbers corresponding to bits 0 to 7, 8 to 15, 16 to 23, and 24 to 31 respectively correspond to the bit sequence numbers of the bytes in the four cases (because 0 indicates no ready thread, this bit sequence number starts at 1 and is subtracted by 1 when used outside the Z function).

[0023] The assembly language code obtained after cross-compiling the RISC-V open source chip is:

[0024]

[0025] The 33 assembly language lines in this code correspond to 33 machine instructions, but in the worst case, when the branch is "if (value&0xff0000)," a maximum of 33-21+6=18 instructions will be executed. Here's the calculation process: In the array read phase, there are 21 instructions for the four branches; in the worst case, all four branches must be judged, resulting in 33-21=12 instructions for branch judgment; only one branch's array read instruction is actually executed at a time, and the maximum number of instructions selected in the last two array reads is 6. Figure 1 The test results of the function Z are shown. The data ranges from a maximum of 36 to a minimum of 7 clock cycles, with a real-time jitter of 29 clock cycles. Real-time performance only concerns the worst case, so the maximum clock cycle value of 36 is taken here.

[0026] This code has the following three defects that need to be improved:

[0027] 1. Space occupation: The array occupies 256 bytes of memory space, which is a huge waste of space when the embedded chip is very small.

[0028] 2. Branch instructions: There are four branch instructions after the code is assembled. When branch prediction fails, real-time jitter will occur, destroying real-time performance.

[0029] 3. Memory Reading: After code assembly, there are four memory read instructions. Memory read and write times far exceed those of general register reads, potentially tens, hundreds, or even thousands of times longer. This low memory read efficiency significantly reduces real-time performance. Summary of the Invention

[0030] In order to overcome the defects of the prior art, the present invention provides an rt-thread priority scheduling implementation method based on the RISC-V instruction set to solve the above problems.

[0031] The technical solution adopted by the present invention to solve the technical problem is: a method for implementing rt-thread priority scheduling based on the RISC-V instruction set, comprising the following steps:

[0032] S1: 256 priorities are represented by a two-layer priority bitmap;

[0033] The first-layer priority bitmap has 32 bits, and bit a is used to identify the priority of the first-layer priority bitmap;

[0034] The second-level priority bitmap has 256 bits, with 8 bits as a group, for a total of 32 groups. The group number corresponds to bit a in the first-level priority bitmap, and the bit sequence number bit b within the group is used to identify the priority within the group;

[0035] In the 8 bits of group a, if only one bit is 1, bit a of the first-level priority bitmap is 1; if all bits are 0, bit a of the first-level priority bitmap is 0;

[0036] S2: Set function X and function Y; for the first layer, execute function X and search the 32-bit priority bitmap for the first bit a that is 1 in the direction from low to high.

[0037] Use a to find the corresponding group in the second layer, and then execute function Y on the group to find the first bit b that is 1 in the 8-bit priority bitmap of the group from the lowest to the highest bit.

[0038] S3: Take 8*a+b as the highest priority number among the 256 priorities, obtain a list of ready thread control block pointers with a priority of 8*a+b, and take out the first thread control block pointer in the list;

[0039] S4: The thread pointed to by the retrieved thread control block pointer is used as the thread corresponding to the highest priority; and thread switching is completed by switching the thread corresponding to the highest priority to the processor.

[0040] Optionally, in step S2, the function X includes:

[0041] Performing a two's complement operation on the 32-bit priority bitmap, performing an AND operation on the result of the two's complement operation and the original 32-bit priority bitmap to obtain a first operation unsigned integer, and subtracting 1 from the first operation unsigned integer to obtain a first preprocessing unsigned integer;

[0042] Shift the first pre-processed unsigned integer right by 11 bits and then perform AND operation with 16 to obtain the value ;

[0043] Right shift the first preprocessed unsigned integer The result of the AND operation with 8 after shifting right by 4 bits is the same as the value Perform an OR operation to obtain a value ;

[0044] Right shift the first preprocessed unsigned integer The result of the AND operation with 4 after shifting the bit right by 1 bit is the same as the value Perform an OR operation to obtain a value ;

[0045] Right shift the first preprocessed unsigned integer The result of the AND operation with 2 is the same as the value Perform an OR operation to obtain a value ;

[0046] Right shift the first preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ; ;

[0047] Let bit a be the first bit that is 1 in the 32-bit priority bitmap in the low-to-high direction.

[0048] It is worth noting that the first pre-processed unsigned integer is shifted right by 11 bits and then ANDed with 16 to obtain the value The steps include:

[0049] Shift the first pre-processed unsigned integer right by 15 bits to shift the 15th bit of the first pre-processed unsigned integer right to bit 0, then shift it left by 4 bits, and at the same time shift 0x8000 right by 11 bits to get 0x10; perform AND operation on the result of shifting the first pre-processed unsigned integer right by 15 bits and then left by 4 bits and 0x10 to get the value .

[0050] Specifically, in step S2, the function Y includes:

[0051] Performing a complement operation on the 8-bit priority bitmap, performing an AND operation on the result of the complement operation and the original 8-bit priority bitmap to obtain a second operation unsigned integer, and subtracting 1 from the second operation unsigned integer to obtain a second preprocessed unsigned integer;

[0052] Shift the second pre-processed unsigned integer right by 1 bit and perform AND operation with 4 to obtain the value ;

[0053] Right shift the second preprocessed unsigned integer The result of the AND operation after the bit and 2 is the same as the value Perform an OR operation to obtain a value ;

[0054] Right shift the second preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ; .

[0055] It is worth noting that the second pre-processed unsigned integer is shifted right by 1 bit and then ANDed with 4 to obtain the value The steps include:

[0056] Shift the second pre-processed unsigned integer right by 3 bits to shift the result of the AND operation from the 3rd bit to the 0th bit, then shift it left by 2 bits, and then perform the AND operation with the binary 100 to obtain the value .

[0057] The beneficial effects of the present invention are as follows: in the RISC-V instruction set-based rt-thread priority scheduling implementation method, the resulting RISC-V assembly language code has the following advantages: 1. Except for single complement and minus 1, all operations are logical operations such as AND or OR and shift operations; compared to mathematical operations such as addition, subtraction, multiplication, and division, the use of digital circuit-level logical operations and shift operations can greatly reduce computational overhead, improve operational efficiency, and enhance real-time performance; all MCUs support logical and shift operations, which enhances compatibility with various MCUs compared to some MCUs that do not have hardware multiplication or dividers. 2. There is no table lookup operation, which saves memory space occupied by the lookup table, and logical operations and shift operations are used instead of table lookups. 3. There are no branch instructions, which will not generate real-time jitter and will not damage real-time performance. 4. Since there is no lookup table, there is no memory read operation during table lookup, which can improve efficiency and enhance real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 Take a screenshot of the running test of function Z in the existing rt-thread;

[0059] Figure 2 This is a flowchart of a method for implementing rt-thread priority scheduling based on the RISC-V instruction set in one embodiment of the present invention;

[0060] Figure 3 This is a screenshot of the running test of function X in one embodiment of the present invention;

[0061] Figure 4 Screenshot of the existing code running test to find the first 1 bit in the priority bitmap from low to high using a lookup table array. DETAILED DESCRIPTION

[0062] The following is a further description of specific embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is intended to facilitate understanding of the present invention and does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0063] like Figure 1-4As shown, a method for implementing rt-thread priority scheduling based on the RISC-V instruction set includes the following steps:

[0064] The 256 priorities are represented by a two-layer priority bitmap. The first layer has a 32-bit priority bitmap. Bit a (a ranges from 0 to 31) is used to identify the priority of the first layer priority bitmap. However, bit a of this layer is only used for the 32 priorities in the first layer priority bitmap.

[0065] The second-level priority bitmap has 256 bits, with 8 bits as a group, for a total of 32 groups. The group number corresponds to the range of a, and the bit number within the group is bit b (the range of b is 0 to 7);

[0066] In the 8 bits of group a, if there is only one 1, the first layer bit a is 1, if all are 0, the first layer bit a is 0;

[0067] The specific usage of the function Z currently set by rt-thread includes:

[0068] By executing the function Z on the first layer, the first bit a that is 1 in the direction from low to high is found from the 32-bit priority bitmap; through a, the corresponding group is found on the second layer, and then the function Z is executed on the group to find the first bit b that is 1 in the direction from low to high from the 8-bit priority bitmap of the group; finally, by taking 8*a+b as the highest priority number among the 256 priorities, the ready thread control block pointer linked list with a priority of 8*a+b is obtained, and the first thread control block pointer in the thread control block pointer linked list is taken out. Among the 256 priorities, the ready thread control block pointer linked lists corresponding to priorities 0 to 255, the 256 ready thread control block pointer linked lists constitute an array of 256 elements; if the value of a certain priority is 0, it means that there is no ready thread control block pointer in the ready thread control block pointer linked list of that priority; if the value of a certain priority is 1, it means that there is at least one ready thread in the ready thread control block pointer linked list of that priority; the ready thread control block pointer linked list is composed of one or more ready thread control block pointers of corresponding priorities, and each thread control block pointer points to a ready thread.

[0069] This solution uses functions X and Y instead of function Z, thereby improving efficiency:

[0070] Execute the function X for the first layer and find the first bit a that is 1 in the 32-bit priority bitmap from the low bit to the high bit.

[0071] Find the corresponding group in the second layer through a, and then execute the function Y for the group to find the first bit b that is 1 in the direction from low to high in the 8-bit priority bitmap of the group;

[0072] Finally, by calculating 8*a+b, we can get the highest priority number among the 256 priorities, use the number to get the corresponding thread control block pointer list, and take out the first thread control block pointer in the thread control block pointer list;

[0073] The thread pointed to by the pointer of the retrieved thread control block is used as the thread corresponding to the highest priority; and the thread switching is completed by switching to the processor according to the thread corresponding to the highest priority.

[0074] In this solution, the function X:

[0075] Performing a two's complement operation on the 32-bit priority bitmap, performing an AND operation on the result of the two's complement operation and the original 32-bit priority bitmap to obtain a first operation unsigned integer, subtracting 1 from the first operation unsigned integer to obtain a first preprocessed unsigned integer; in this embodiment, the two's complement operation is to negate the value and then add 1;

[0076] Shift the first pre-processed unsigned integer right by 11 bits and then perform AND operation with 16 to obtain the value ;

[0077] Right shift the first preprocessed unsigned integer The result of the AND operation with 8 after shifting right by 4 bits is the same as the value Perform an OR operation to obtain a value ;

[0078] Right shift the first preprocessed unsigned integer The result of the AND operation with 4 after shifting the bit right by 1 bit is the same as the value Perform an OR operation to obtain a value ;

[0079] Right shift the first preprocessed unsigned integer The result of the AND operation with 2 is the same as the value Perform an OR operation to obtain a value ;

[0080] Right shift the first preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ;

[0081] ;

[0082] Let bit a be the first bit that is 1 in the 32-bit priority bitmap in the low-to-high direction.

[0083] The assembly language code corresponding to function X is:

[0084]

[0085] like Figure 3 As shown in the figure, after cross-compiling the RISC-V open-source chip, assembly language code is generated. The 19 assembly language lines in this code correspond to 19 machine instructions, which are executed in 22 clock cycles. There is no real-time jitter, and the worst-case scenario is 22 clock cycles, demonstrating strong real-time performance.

[0086] For example, the code for finding the first 1 bit in the priority bitmap from low to high by multiplication using a lookup table array is as follows:

[0087]

[0088] The above C language code is assembled into RISC_V instructions as follows:

[0089]

[0090] There are 11 machine instructions in total, and the test screenshots are as follows: Figure 4 As shown, 15 clock cycles. Due to the presence of a lookup table array, memory access instructions are required to access the memory lookup table. When the memory where the constant array data is located has a slow read speed, or when there is a cache but a miss, execution efficiency drops sharply. Due to the presence of multiplication instructions, if the chip does not have an integrated hardware multiplier, multiple instruction loops must be executed to replace the multiplication operation, and performance will also drop sharply. The replacement instructions are as follows:

[0091]

[0092] It can be seen that the real-time performance of the above algorithm is greatly limited by hardware differences.

[0093] By comparing with the above example and function Z, the assembly language code corresponding to function X implements the following features:

[0094] 1. Except for one's complement and minus 1, all other operations are logical operations such as AND or OR and shift operations.

[0095] Compared with mathematical operations such as addition, subtraction, multiplication and division, using logical operations and shift operations at the digital circuit level can greatly reduce computational overhead, improve operational efficiency and enhance real-time performance.

[0096] All MCUs support logical and shift operations, which enhances compatibility with various MCUs compared to some MCUs that do not have hardware multiplication or division.

[0097] 2. There is no table lookup operation, which saves the memory space occupied by the lookup table, and uses logical operations and shift operations instead of table lookup.

[0098] 3. Branch instructions: Without branch instructions, there will be no real-time jitter and no destruction of real-time performance.

[0099] 4. Since there is no lookup table, there is no memory read operation when looking up the table, which can improve efficiency and enhance real-time performance.

[0100] Figure 3 Relative to Figure 1 , there is only one clock cycle number 22. Without branch statements, the dazzling probability distribution of quantum states quickly collapses into a macroscopic constant. The worst-case clock cycle number is only Figure 1 As shown, 61.1% of the 36 clock cycles are optimized to nearly half of the RT-thread. This not only saves space but is also faster and quantitatively accurate, making it ideal for real-time deterministic timing requirements.

[0101] The number of 1s in the first preprocessed unsigned integer is the first bit number whose value is 1 in the direction from bit 0 to bit 31, so the operation of finding the first bit number whose value is 1 in the direction from bit 0 to bit 31 is converted into counting the number of 1s in the first preprocessed unsigned integer.

[0102] The first pre-processed unsigned integer is shifted right by 11 bits and then ANDed with 16 to obtain the value. This step shows the following evolution process:

[0103] According to the characteristics of the first preprocessed unsigned integer, the first bit with a value of 1, all bits in the direction of bit 0 have a value of 1, and the first bit with a value of 1 and all bits in the direction of bit 31 have a value of 0, the code is:

[0104]

[0105] First, perform an AND operation on the unsigned integer and 0x8000 (bit 15 is 1), and then right shift 15 bits. There are two possible results:

[0106] The result is 1, indicating that bits 0 to 15 are all 1, that is, the lower 16 bits are all 1. Shift the result left by 4 bits, that is, multiply by 16. 1 times 16 equals 16, indicating that there are 16 1s in bits 0 to 15. 16 is the known number of 1s and is stored in A5. The number of 1s in bits 16 to 31 is unknown and will be determined by subsequent operations.

[0107] The result is 0, indicating that bits 16 to 31 are all 0, that is, the upper 16 bits are all 0. Shift the result left by 4 bits, that is, multiply by 16. 0 multiplied by 16 is 0, indicating that there are a total of 0 1s from bits 16 to 31. 0 is stored in A5 as the known number of 1s. The number of 1s from bits 0 to 15 is unknown and needs to be determined by subsequent operations.

[0108] In this process, when encountering a shift in the opposite direction, the shift subtraction can be combined into one, that is, the first right shift of 15 bits and then the left shift of 4 bits can be combined into a right shift of 11 bits to reduce one instruction;

[0109] When the RISC-V instruction set architecture has more than 11 bits of immediate value, the following code will be added as the first immediate value 0x8000 load instruction:

[0110]

[0111] In this embodiment, the above calculation process is adjusted as follows: the first pre-processed unsigned integer is not first ANDed with 0x8000. The first pre-processed unsigned integer is first shifted right by 15 bits and then left by 4 bits (after being combined into one instruction, it is right-shifted by 11 bits). At the same time, the immediate number 0x8000 is also synchronously shifted right by 15 bits and then left by 4 bits (after being combined into one instruction, it is right-shifted by 11 bits). The immediate number 0x8000 is shifted right by 11 bits (corresponding to being right-shifted by 15 bits and then left by 4 bits) to become 0x10 (i.e., 16). The two numbers are then ANDed, and the AND operation is adjusted to the end. On the basis of ensuring the correctness of the calculation result, the immediate number 0x8000 with a valid bit exceeding 11 bits can be shifted right so that the valid bit of the immediate number of the instruction does not exceed 11 bits, thereby eliminating the need for an immediate number loading instruction. Finally, three instructions are optimized, leaving only two instructions for right shifting and ANDing in the following code:

[0112]

[0113] The above calculation takes 32-bit word length as an example. Since the instruction length of RISC-V will not exceed 32 bits, the above techniques have performance advantages in RISC-V processors with word length not exceeding 2 to the power of 11 (2048).

[0114] In this solution, the function Y:

[0115] Performing a complement operation on the 8-bit priority bitmap, performing an AND operation on the result of the complement operation and the original 8-bit priority bitmap to obtain a second operation unsigned integer, and subtracting 1 from the second operation unsigned integer to obtain a second preprocessed unsigned integer;

[0116] Shift the second pre-processed unsigned integer right by 1 bit and perform AND operation with 4 to obtain the value ;

[0117] Right shift the second preprocessed unsigned integer The result of the AND operation with 2 is the same as the value Perform an OR operation to obtain a value ;

[0118] Right shift the second preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ;

[0119] ;

[0120] Let bit b be the first bit that is 1 in the 8-bit priority bitmap in the low-to-high direction.

[0121] Assume that the 8-bit priority bitmap value is 01011000, 01011000 is complemented by 10101000, 10101000 is ANDed with itself 01011000 to get 00001000, and finally 1 is subtracted to get 00000111; (1) 00000111 is shifted right by 1 bit to get 0000011, and ANDed with 4 (binary 100) to get 0, so is 0; (2) 00000111 is shifted right After that, due to is 0, so the result is also 00000111, and 2 (binary 10) is binary 10, and then After OR operation, =10 in binary; (3) 00000111 is shifted right bit, due to is 2 (10 in binary), so the result is 000001, which is the same as After OR operation, It is 11 in binary, which is 3 in decimal, so b=3, which corresponds to the first 1 bit in the direction from low to high in 01011000.

[0122] The assembly language code corresponding to function Y is:

[0123]

[0124] The number of 1s in the second preprocessed unsigned integer is the first bit number whose value is 1 in the direction from bit 0 to bit 7, so the operation of finding the first bit number whose value is 1 in the direction from bit 0 to bit 7 is converted into counting the number of 1s in the second preprocessed unsigned integer.

[0125] The second pre-processed unsigned integer is shifted right by 1 bit and then ANDed with 4 to obtain the value. This step shows the following evolution process:

[0126] According to the characteristics of the second preprocessing unsigned integer number, the first bit with a value of 1, all bits in the direction of bit 0 have a value of 1, and the first bit with a value of 1 and all bits in the direction of bit 7 have a value of 0, the code is:

[0127]

[0128] The second preprocessing operation is to AND the unsigned integer with 8 (binary 1000, bit 3 is 1) and then right shift 3 bits. There are two possible results:

[0129] The result is 1, indicating that bits 0 through 3 are all 1, meaning the lowest four bits are all 1. Shift the result left by 2, multiplying by 4. 1 times 4 equals 4, meaning there are four 1s in bits 0 through 3. 4 is the known number of 1s and is stored in B3. The number of 1s in bits 4 through 7 is unknown and will be determined by subsequent operations.

[0130] The result is 0, indicating that bits 4 to 7 are all 0, that is, the upper 4 bits are all 0. Shift the result left by 2 bits, that is, multiply by 4. 0 multiplied by 4 is 0, indicating that there are a total of 0 1s from bits 4 to 7. 0 is stored in B3 as the known number of 1s, while the number of 1s from bits 0 to 3 is unknown and needs to be determined by subsequent operations.

[0131] During this process, when encountering a shift in the opposite direction, the displacement can be combined into one by subtracting it, that is, combining the right shift of 3 bits and the left shift of 2 bits into the right shift of 1 bit to reduce one instruction.

[0132] Adjust the above calculation process as follows: The second pre-processed unsigned integer is not ANDed with 0x8. Instead, it is first shifted right by 3 bits and then left by 2 bits (combined into one instruction, it is a 1-bit right shift). Simultaneously, the immediate binary value 1000 (i.e., 8) is also synchronously shifted right by 3 bits and then left by 2 bits (combined into one instruction, it is a 1-bit right shift). The immediate binary value 1000 (i.e., 8) is shifted right by 1 bit (corresponding to a 3-bit right shift followed by a 2-bit left shift) to become the binary value 100 (i.e., 4). The two numbers are then ANDed together, moving the AND operation to the end. The only two instructions left are the right shift and the AND operation, as shown in the following code:

[0133]

[0134] Function Y, after cross-compiling on the RISC-V open-source chip, generates the assembly language code corresponding to the aforementioned function Y. This code contains 11 assembly language instructions corresponding to 11 machine instructions, which is 8 fewer instructions than function X and offers better real-time performance.

[0135] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It is apparent to those skilled in the art that various changes, modifications, substitutions, and variations to these embodiments may be made without departing from the principles and spirit of the present invention, and these changes and modifications still fall within the scope of protection of the present invention.

Claims

1. A method for implementing rt-thread priority scheduling based on the RISC-V instruction set, characterized in that: The following steps are involved: S1: 256 priorities are represented by a two-layer priority bitmap; The first-layer priority bitmap has 32 bits, and bit a is used to identify the priority of the first-layer priority bitmap; The second-level priority bitmap has 256 bits, with 8 bits as a group, for a total of 32 groups. The group number corresponds to bit a in the first-level priority bitmap, and the bit sequence number bit b within the group is used to identify the priority within the group; In the 8 bits of group a, if only one bit is 1, bit a of the first-level priority bitmap is 1; if all bits are 0, bit a of the first-level priority bitmap is 0; S2: Set function X and function Y; for the first layer, execute function X and search the 32-bit priority bitmap for the first bit a that is 1 in the direction from low to high. Use a to find the corresponding group in the second layer, and then execute function Y on the group to find the first bit b that is 1 in the 8-bit priority bitmap of the group from the lowest to the highest bit. S3: Take 8*a+b as the highest priority number among the 256 priorities, obtain a list of ready thread control block pointers with a priority of 8*a+b, and take out the first thread control block pointer in the list; S4: The thread pointed to by the retrieved thread control block pointer is used as the thread corresponding to the highest priority; Thread switching is completed by switching the thread corresponding to the highest priority to the processor.

2. The RISC-V instruction set-based rt-thread priority scheduling implementation method according to claim 1, wherein: In step S2, the function X includes: Performing a two's complement operation on the 32-bit priority bitmap, performing an AND operation on the result of the two's complement operation and the original 32-bit priority bitmap to obtain a first operation unsigned integer, and subtracting 1 from the first operation unsigned integer to obtain a first preprocessing unsigned integer; Shift the first pre-processed unsigned integer right by 11 bits and then perform AND operation with 16 to obtain the value ; Right shift the first preprocessed unsigned integer The result of the AND operation with 8 after shifting right by 4 bits is the same as the value Perform an OR operation to obtain a value ; Right shift the first preprocessed unsigned integer The result of the AND operation with 4 after shifting the bit right by 1 bit is the same as the value Perform an OR operation to obtain a value ; Right shift the first preprocessed unsigned integer The result of the AND operation with 2 is the same as the value Perform an OR operation to obtain a value ; Right shift the first preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ; ; Let bit a be the first bit that is 1 in the 32-bit priority bitmap in the low-to-high direction.

3. The rt-thread priority scheduling implementation method based on the RISC-V instruction set according to claim 2 is characterized in that: Shift the first pre-processed unsigned integer right by 11 bits and then perform AND operation with 16 to obtain the value The steps include: Shift the first pre-processed unsigned integer right by 15 bits to shift the 15th bit of the first pre-processed unsigned integer right to bit 0, then shift it left by 4 bits, and at the same time shift 0x8000 right by 11 bits to get 0x10; perform AND operation on the result of shifting the first pre-processed unsigned integer right by 15 bits and then left by 4 bits and 0x10 to get the value .

4. The rt-thread priority scheduling implementation method based on the RISC-V instruction set according to claim 1, characterized in that In step S2, the function Y includes: Performing a two's complement operation on the 8-bit priority bitmap, performing an AND operation on the result of the two's complement operation and the original 8-bit priority bitmap to obtain a second operation unsigned integer, and subtracting 1 from the second operation unsigned integer to obtain a second preprocessed unsigned integer; Shift the second pre-processed unsigned integer right by 1 bit and perform AND operation with 4 to obtain the value ; Right shift the second preprocessed unsigned integer The result of the AND operation with 2 is the same as the value Perform an OR operation to obtain a value ; Right shift the second preprocessed unsigned integer The result after the digit is the same as the value Perform an OR operation to obtain a value ; ; Let bit b be the first bit that is 1 in the 8-bit priority bitmap in the low-to-high direction.

5. The rt-thread priority scheduling implementation method based on the RISC-V instruction set according to claim 4 is characterized in that, Shift the second pre-processed unsigned integer right by 1 bit and perform AND operation with 4 to obtain the value The steps include: Shift the second pre-processed unsigned integer right by 3 bits to shift the result of the AND operation from the 3rd bit to the 0th bit, then shift it left by 2 bits, and then perform the AND operation with the binary 100 to obtain the value .

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