Generating three-dimensional (3D) model using one or more neural networks

Abstract

Generating a three-dimensional (3D) model using one or more neural networks is disclosed. Devices, systems, and techniques for performing one or more tasks using one or more neural networks. In at least one embodiment, the one or more neural networks use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints.

Description

Technical Field

[0001] At least one embodiment involves a processing resource using one or more neural networks to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of the object obtained by two or more cameras placed at different angles. Background Art

[0002] Generating three-dimensional (3D) models using neural networks can sometimes lead to inaccuracies because the training data (e.g., images) used to train the neural network lacks information due to occlusions, restricted angles, corrupted data, and so on. For example, the information in the training data may be limited to only the front view of the object in the image used to train the neural network. Therefore, improvements can be made to better train neural networks to generate 3D models. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A system for training one or more neural networks to generate one or more three-dimensional (3D) models using one or more text descriptions is shown in accordance with at least one embodiment;

[0004] Figure 2 shows an image collage of one or more objects from two or more viewpoints in accordance with at least one embodiment;

[0005] Figure 3 A system for achieving 3D asset optimization according to at least one embodiment is shown;

[0006] Figure 4 is a flow chart illustrating 2D model fine-tuning according to at least one embodiment;

[0007] Figure 5 is a flow chart illustrating 3D asset optimization according to at least one embodiment;

[0008] Figure 6 An example of a processor according to at least one embodiment is shown;

[0009] Figure 7 is a block diagram illustrating a driver and / or runtime including one or more libraries to provide one or more APIs according to at least one embodiment;

[0010] Figure 8A illustrates logic according to at least one embodiment;

[0011] Figure 8B illustrates logic according to at least one embodiment;

[0012] Figure 9illustrates the training and deployment of a neural network according to at least one embodiment;

[0013] Figure 10 An example data center system is shown in accordance with at least one embodiment;

[0014] Figure 11A An example of an autonomous vehicle according to at least one embodiment is shown;

[0015] Figure 11B According to at least one embodiment, Figure 11A Examples of camera positions and fields of view for autonomous vehicles;

[0016] Figure 11C According to at least one embodiment Figure 11A A block diagram of an example system architecture for an autonomous vehicle;

[0017] Figure 11D is a diagram illustrating a method for one or more cloud-based servers and Figure 11A A diagram of a system for communicating between autonomous vehicles;

[0018] Figure 12 is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 14 A computer system according to at least one embodiment is shown;

[0021] Figure 15 A computer system according to at least one embodiment is shown;

[0022] Figure 16A A computer system according to at least one embodiment is shown;

[0023] Figure 16B A computer system according to at least one embodiment is shown;

[0024] Figure 16C A computer system according to at least one embodiment is shown;

[0025] Figure 16D A computer system according to at least one embodiment is shown;

[0026] Figure 16E and Figure 16F illustrates a shared programming model according to at least one embodiment;

[0027] Figure 17An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0028] 18A to 18B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figures 19A to 19B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0030] Figure 20 A computer system according to at least one embodiment is shown;

[0031] Figure 21A A parallel processor according to at least one embodiment is shown;

[0032] Figure 21B shows a partition unit according to at least one embodiment;

[0033] Figure 21C illustrates a processing cluster according to at least one embodiment;

[0034] Figure 21D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0035] Figure 22 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0036] Figure 23 A graphics processor according to at least one embodiment is shown;

[0037] Figure 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0038] Figure 25 A deep learning application processor according to at least one embodiment is shown;

[0039] Figure 26 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0040] Figure 27 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0041] Figure 28 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0042] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0043] Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0044] Figure 31 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0045] FIG. 32A to FIG. 32B Thread execution logic is shown that includes an array of processing elements of a graphics processor core, in accordance with at least one embodiment.

[0046] Figure 33 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0047] Figure 34 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0048] Figure 35 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0049] Figure 36 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0050] Figure 37 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0051] Figure 38 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0052] Figure 39 includes an example illustration of a high-level computational pipeline for processing imaging data according to at least one embodiment;

[0053] Figure 40A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0054] Figure 40B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0055] Figure 41A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment; and

[0056] Figure 41B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model, according to at least one embodiment.

[0057] Figure 42 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0058] In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to train one or more neural networks using software to generate a three-dimensional (3D) model from an input text description, wherein the one or more neural networks are trained using multiple viewpoints of an object. In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to train one or more neural networks using software to generate a three-dimensional (3D) model from an input image. In at least one embodiment, the one or more neural networks generate the 3D model using multiple images from different viewpoints, and during training, a loss is calculated based on whether the 3D model matches the multiple images simultaneously.

[0059] In at least one embodiment, one or more neural networks generate one or more 3D models from text that have no biased shape and appearance. In at least one embodiment, the one or more 3D models are generated by debiasing a text-to-image diffusion model. In at least one embodiment, a dataset of image-text pairs is created, where the images are rendered from a corpus of 3D computer-aided design (CAD) models. In at least one embodiment, the diffusion model is fine-tuned to simultaneously generate N viewpoints of the same object, where the N viewpoints are spaced at a certain angle from each other and organized as a tiled image. In at least one embodiment, when the fine-tuned diffusion model is used as a critic for text-to-3D generation, the critic ensures that the rendered image from any set of similar and relatively spaced N viewpoints should fall within the joint distribution of images at these viewpoints. In at least one embodiment, this ensures that the shape and appearance of the viewpoints are always jointly rendered and modeled, thereby achieving viewpoint-debiased text-to-3D generation.

[0060] In at least one embodiment, a text-to-3D generator generates one or more 3D representations based on a text description of an object using one or more images of the object obtained by two or more cameras positioned at different angles. In at least one embodiment, the text description is a prompt of input text (e.g., a text string, a word, the result of a speech-to-text generator, an image, etc.) from a user. In at least one embodiment, the text-to-3D generator is an image-to-3D generator and generates one or more 3D representations based on the image input by the user. In at least one embodiment, the text-to-3D generator includes one or more neural networks that train a text-to-image diffusion model on a dataset comprising a dataset of image-text pairs. In at least one embodiment, biases in the text-to-image diffusion model (e.g., relative to one or more specific viewpoints, such as a frontal view primarily depicting a face) are eliminated by retraining the dataset, wherein the dataset includes one or more images of one or more objects obtained by two or more cameras positioned at different angles.

[0061] In at least one embodiment, the debiased dataset used for retraining comprises one or more digitally rotatable 3D CAD representations of two or more images of one or more objects. In at least one embodiment, another image-text pair dataset is created, wherein the images are rendered from a 3D CAD model corpus. In at least one embodiment, the two or more images comprise digitally rotatable 3D N-viewpoint CAD representations, where N is 2 or greater. In at least one embodiment, the N-viewpoint CAD representations are captured by cameras that are substantially located within a plane and surround one or more objects designated as targets. In at least one embodiment, the cameras are equidistantly spaced and completely occupy the plane. In at least one embodiment, the two or more images are associated together as a (debiased) collage. In at least one embodiment, the collage is associated with descriptive text as an image-text pair. In at least one embodiment, the image-text pair is converted into a digitally rotatable 3D CAD representation of the target.

[0062] In at least one embodiment, the diffusion model serves as a critic for training images to train the text-to-3D generator. In at least one embodiment, the 2D diffusion model only requires relative angular offsets, which are known during the tile assembly process. In at least one embodiment, the 2D diffusion model provides guidance from multiple viewpoints simultaneously during 3D asset optimization. In at least one embodiment, the 2D diffusion model interprets these views as being from the same underlying object.

[0063] In at least one embodiment, the text-to-3D generator generates a 3D model from an unbiased collage. In at least one embodiment, the diffusion model evaluates the 3D model. In at least one embodiment, the diffusion model is fine-tuned to simultaneously generate N viewpoints of the target object. In at least one embodiment, the diffusion model indicates which versions of the generated model have high confidence. In at least one embodiment, the diffusion model is trained to select only 3D models that are free of artifacts, thereby reducing artifacts when the text-to-3D generator attempts to generate a 3D model from a set of images captured at random times and / or random vantage points.

[0064] In at least one embodiment, a 3D object representation generated by the text-to-3D generator is compared to a ground truth representation using a loss function. In at least one embodiment, weights of the text-to-3D generator are adjusted based on the output of the loss function. In at least one embodiment, loss functions include mean squared error, regression, classification, autoencoder, and diffusion model losses, among others.

[0065] In at least one embodiment, one or more neural networks are trained to generate a model (e.g., predict or infer information) from input data, including but not limited to image data. In at least one embodiment, the one or more neural networks generate a 3D model using multiple images captured using a photo library or randomly captured by a camera from different vantage points and / or at different times (e.g., a model constructed using view-dependent cues). In this manner, a 3D model can be constructed compared to using separate networks to construct different models. In at least one embodiment, the model is constructed using training data specifically designed for 3D modeling, with minimal bias towards any particular viewpoint. In at least one embodiment, the model is further constructed using training data captured simultaneously from specific random vantage points. In at least one embodiment, to improve the ability of the neural network to generate a 3D model, the techniques described herein enable a processor having one or more circuits to generate information about the one or more objects while training the neural network.

[0066] A neural network that generates a 3D model of an object from text generates a 3D model with parts of the object that shouldn't be there (such as a nose on one side of a face). This is because the neural network is trained by generating a 3D model, using the 3D model to generate 2D images of the object from viewpoints where there is a true 2D image from the same viewpoint, and adjusting weights based on a loss measure of how well the 2D images match. However, the true 2D images are biased towards the same viewpoint (meaning the neural network learns parts of the object from those viewpoints) and are not trained with information indicating how different viewpoints should appear relative to each other (e.g., if one viewpoint has a nose, then another viewpoint shouldn't have an extra nose). In at least one embodiment, the techniques described herein train a neural network to generate a 3D model from text, where the neural network is trained using multiple viewpoints of an object.

[0067] In the preceding and following descriptions, various techniques are described. For ease of explanation, specific configurations and details are set forth to provide a thorough understanding of possible ways to implement the techniques. However, it will be apparent that the techniques described below can be practiced in different configurations without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0068] Figure 1 An example / system 100 is shown for training 102 a neural network 108 to generate 110 one or more three-dimensional (3D) models of an object 112 from text 112 in accordance with at least one embodiment. In at least one embodiment, training data 104 is used as input by a training framework 106 to train 102 one or more untrained neural networks 108 using a generative adversarial network (GAN) that includes a bidirectional encoder representation from a transformer (BERT) discriminator, as described below in conjunction with Figure 2 and Figure 3 In at least one embodiment, training data 104 is a set of images or image data and optional labels or classifications to provide a set of examples on which one or more untrained neural networks 108 learn to perform a function, such as converting one type of image 112 to another type of image 116.

[0069] In at least one embodiment, training data 104 is a set of data, such as image data, on which one or more untrained neural networks 108 are trained to operate. In at least one embodiment, training data 104 includes a set of images. In at least one embodiment, training data 104 includes a set of images with labels or classifications. In at least one embodiment, training data 104 includes image data. In at least one embodiment, training data 104 includes images from CAD. In at least one embodiment, training data 104 includes medical images. In at least one embodiment, training data 104 is one or more other types of data that training framework 106 utilizes to train 102 one or more untrained neural networks 108 to perform operations such as image generation, as described below in conjunction with Figures 2 to 7 As stated.

[0070] In at least one embodiment, the training framework 106 is a set of software instructions that, when executed on one or more computing devices, manages the training 102 of one or more untrained neural networks 108 using training data 104 (such as the image training data 104 described above). In at least one embodiment, the one or more untrained neural networks 108 are trained by the training framework 106, which facilitates the one or more untrained neural networks 108 to learn based on the training data 104. In at least one embodiment, the training framework 106 trains the one or more untrained neural networks using a GAN, as described below in conjunction with Figure 2 and Figure 3 Further description.

[0071] In at least one embodiment, training framework 106 trains one or more untrained neural networks 108 without supervision. In at least one embodiment, training framework 106 trains one or more untrained neural networks 108 without supervision and using only training data 104. In at least one embodiment, training framework 106 uses any available supervision in conjunction with training data 104 to train one or more untrained neural networks 108.

[0072] In at least one embodiment, the training framework 106 uses the training data 104 with supervision in the form of classifications, labels, bounding boxes, pixel-level annotations, image-level annotations, points containing locations corresponding to objects, or lines containing locations corresponding to objects. In at least one embodiment, the training framework 106 uses the training data 104 to train one or more untrained neural networks 108 using any other form of supervision to facilitate the training 102 of the one or more untrained neural networks 108. In at least one embodiment, the training framework 106 does not use supervision on some or all of the training data 104.

[0073] In at least one embodiment, one or more untrained neural networks 108 are trained by training framework 106 using supervision. In at least one embodiment, supervision includes various types of assistance, as described above, used to facilitate the training 102 of one or more untrained neural networks 108 by training framework 106. In at least one embodiment, supervision includes input information describing one or more aspects of training data 104, such as objects or styles, or classifications of the training data 104, to assist training framework 106 in training one or more untrained neural networks 108. In at least one embodiment, supervision is strong, where the input information provides direct identification of objects, styles, or other aspects of items (such as images) in training data 104. In at least one embodiment, supervision is weak, where the input information provides partial identification of objects, styles, or other aspects of the input training data 104 items. In at least one embodiment, strong supervision is input information such as bounding boxes, where one or more objects are outlined in the input training data 104 items. In at least one embodiment, weak supervision includes input information such as points, where individual locations in the input training data 104 items are identified as being within one or more objects. In at least one embodiment, weak supervision includes input information such as a line, wherein each point in the line within an item of input training data 104 is identified by the weak supervision as being within one or more objects. In at least one embodiment, weak supervision includes input information such as a label or tag, wherein the label or tag identifies that an item of input training data 104 contains one or more specific objects or has a specific classification.

[0074] In at least one embodiment, one or more untrained neural networks 108 are trained by training framework 106 to perform operations such as translating a collage of CAD images 112 into 3D model 116. In at least one embodiment, one or more neural networks 108 and one or more neural networks 114 are individually any type of neural network described further herein. In at least one embodiment, each of one or more neural networks 108 and one or more neural networks 114 includes a set of nodes, where each node calculates a value based on one or more inputs using an activation function. In at least one embodiment, one or more neural networks 108 and one or more neural networks 116 are implemented in software having instructions that perform operations when executed and memory that stores calculation results based on input data items. In at least one embodiment, each of one or more neural networks 108 and one or more neural networks 114 is any type of neural network described further herein.

[0075] In at least one embodiment, one or more trained neural networks 114 perform inference 110 using text description 112. In at least one embodiment, one or more trained neural networks 114 convert collage image 112 into 3D model 116. In at least one embodiment, one or more trained neural networks 114 perform inference 110 whereby one medical image (such as collage image 112) is converted into another image (such as 3D model 116) by the one or more trained neural networks 114. In at least one embodiment, input data 112 includes any type of data that one or more trained neural networks 114 are trained 102 to operate via training framework 106.

[0076] In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 106 that are trained 102 by training framework 106 to perform operations based on training data 104. In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 108 that are trained 102 by training framework 106 without supervision based on training data 104. In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 108 that are trained 102 by training framework 106 with supervision based on training data 104.

[0077] In at least one embodiment, one or more trained neural networks 114 generate output data 116 based on input data 112. In at least one embodiment, one or more trained neural networks 114 perform the operations for which they have been trained 102 by training framework 106 on input data 112 to generate output data 116. In at least one embodiment, output data 116 includes a generated set of images, such as 3D model 116.

[0078] In at least one embodiment, system 100 generates high-resolution 3D content from input text prompt 112 in a coarse-to-fine manner at inference 114, as follows Figures 2 to 5 . In at least one embodiment, in a first stage, a low-resolution diffusion prior is used to optimize the neural field representations (color, density, and normal fields) to obtain the coarse model. In at least one embodiment, a textured 3D mesh is differentiably extracted from the density field and color field of the coarse model. In at least one embodiment, a high-resolution latent diffusion model is used to fine-tune the textured 3D mesh. In at least one embodiment, after optimization, the model generates a high-quality 3D mesh with detailed textures at inference 114.

[0079] Figure 2 A quadrant image collage dataset is shown for training a 2D model to fine-tune one or more neural networks and as combined Figure 4 The process 400 is further described to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of the object obtained by two or more cameras placed at different angles. In at least one embodiment, the diffusion model is fine-tuned with a new dataset. In at least one embodiment, the new dataset can access multiple viewpoints 202, viewpoint 204, viewpoint 206, viewpoint 208 simultaneously. In at least one embodiment, the new dataset including viewpoint 202, viewpoint 204, viewpoint 206, viewpoint 208 is a dataset of 3D object renderings and these 3D automatic renderings are pre-created or pre-generated for fine-tuning the diffusion model. In at least one embodiment, the fine-tuned 2D diffusion model is able to simulate what an object will look like from multiple viewpoints simultaneously. In at least one embodiment, the fine-tuned diffusion model provides consistent 2D guidance that can be used with Figures 3 to 6 The system and / or flow chart described in the embodiment of the present invention can be used in combination with the system and / or flow chart described in the embodiment of the present invention.

[0080] Figure 3A system 300 is shown for training one or more neural networks to generate one or more 3D models of one or more first objects based at least in part on four images of a second object from four viewpoints, according to at least one embodiment. In at least one embodiment, the system 300 includes four cameras 310A-310D having fixed relative poses for training one or more neural networks for 3D asset optimization, such as in conjunction with Figure 5 The process 500 is further described to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of the object obtained by four cameras placed at different angles. In at least one embodiment, the cameras 310A-310D are randomly sampled in one iteration. In at least one embodiment, the 3D object is projected onto these cameras 310A-310D, resulting in four images that are combined together to form a quadrant image collage. In at least one embodiment, the collage falls into the quadrant image collage described above in conjunction with Figure 2 In at least one embodiment, as described above, Figure 2 The process 200 described may be used to fine-tune the diffusion model in process 300 to update what the projections of the multiple viewpoints should be, and will inform and update the desired generated 3D model.

[0081] Figure 4 An example flow chart of a process 400 for generating a 3D model from a 2D image collage, including 2D model fine-tuning, in at least one embodiment is shown. In at least one embodiment, some or all of process 400 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems, such as those shown in FIG. 8 through FIG. Figure 42 The computer systems described in the foregoing are configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more application programs) that is executed together on one or more processors through hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes multiple computer-readable instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium.

[0082] In at least one embodiment, process 400 may implement the following algorithm:

[0083] Dataset creation

[0084] Given: 3D asset {A1...A m}(3D CAD model)

[0085] For each asset A1

[0086] 1. → Randomly sample N camera viewpoints with fixed relative angle offsets (default N = 4)

[0087] 2. → Render image {I i1 ...I iN} and assembled into collage c i

[0088] 3. → (Optional) Repeat to generate multiple tiles

[0089] 4.→ Output: Image collage dataset {c1...c k}

[0090] In at least one embodiment, the 2D model fine-tuning process 412 may randomly initialize the creation of the collage image dataset at step 402. In at least one embodiment, the process may be initialized in other ways, such as by being set to all zeros.

[0091] In at least one embodiment, at step 404, a dataset of 3D assets {A1 ... A N In at least one embodiment, the 3D asset dataset comprises a CAD model. The noise value t is set to a maximum noise value T.

[0092] In at least one embodiment, the NN camera viewpoints are randomly sampled with fixed relative angular offsets. At step 406, the value s is calculated. g In at least one embodiment, NN=4, as shown above. In at least one embodiment, s g can be calculated as the input reference image x ref The mean squared error of a single 2D image (e.g., such as input image 202) and the gradient of a rendering of a current 3D model from a first camera pose, where R represents the rendering function.

[0093] In at least one embodiment, as shown in rows 1-4 of the dataset creation above, and / or as described below with reference to Figure 5 In step 408, the rendered image {I1...I N}.

[0094] In at least one embodiment, process 400 optionally repeats, looping back to step 408 to generate multiple tiles. In at least one embodiment, these images are generated by a neural network, such as neural network 108 and / or neural network 114, as described above and discussed in more detail below.

[0095] In at least one embodiment, at step 410, a pre-trained diffusion model D0 is input, and at step 412, as shown, the collage dataset {c1...c N Fine-tune the 2D diffusion model.

[0096] In at least one embodiment, at step 414 , the fine-tuned diffusion model D is output.

[0097] Figure 5 Shown includes generating consistent multi-view Figure 2 An example flow chart of a process 500 for generating a 3D model from a single 2D image. Figure 5 The following algorithm can be implemented.

[0098] In at least one embodiment, at step 502 , a text prompt is input for generating a 3D model of a first object.

[0099] In at least one embodiment, the input includes a learnable 3D model ΘΘ comprising a hash dictionary and at least one neural network and a fine-tuned diffusion model D.

[0100] In at least one embodiment, at step 506 , embeddings of input text prompts from a text-to-image diffusion model are pre-extracted.

[0101] In at least one embodiment, at step 508 , the 3D asset is randomly initialized, for example, by setting the index i to 1 (although the count for i can start at any value).

[0102] In at least one embodiment, at step 510, N camera viewpoints are randomly sampled as {v i1 …v iN}, where the viewpoint has the same angular offset as during 2D model fine-tuning.

[0103] In at least one embodiment, at step 512, N selected viewpoints are rendered to obtain an image {x i1 ...x iN}f(θ;).

[0104] In at least one embodiment, at step 514, the images {x i1 ...x iN}Combined into collage x i .

[0105] In at least one embodiment, at step 516, the SDS guidance loss is calculated using a 2D diffusion model, including the following four sub-steps:

[0106] a) At 516A, a random time step t of the diffusion model is sampled

[0107] b) At 516B, Gaussian noise is added to the rendered image in

[0108] c) At 516C, a diffusion model is used to predict the added noise

[0109] d) At 516D, calculate the noise difference

[0110] In at least one embodiment, at step 518, as shown in line 5 above, gradient descent is evaluated to optimize the 3D model In at least one embodiment, at step 520, i is incremented, and at step 522, it is determined whether i has reached its maximum value T. In at least one embodiment, if i has reached T, process 500 returns to s upon termination. g (e.g., for step 412); otherwise, process 500 loops back to step 504. In at least one embodiment, at step 524, process 500 terminates. In at least one embodiment, step 408 and / or the above combined Figure 4 Lines 1-4 of the discussion can be written as Figure 5 Implementation shown.

[0111] Figure 6 An example of a processor 600 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 602 performs one or more processes such as described herein to cause one or more neural networks to use one or more text descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints. In at least one embodiment, the processor 602 performs the process described in conjunction with Figure 1 In at least one embodiment, the processor 602 performs one or more processes, such as in conjunction with Figures 1 to 5 Describe the process.

[0112] In at least one embodiment, processor 602 is or otherwise includes one or more processors, such as a processor in conjunction with Figures 7 to 42In at least one embodiment, the processor 602 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, DPUs, and / or variants thereof. In at least one embodiment, the processor 602 includes all or any subset of the following models: a neural network training module 604 and a 3D model generation module 606. In at least one embodiment, the neural network training module 604 and the 3D model generation module 606 are part of the processor 602 and / or one or more other processors. In at least one embodiment, the neural network training module 604 and the 3D model generation module 606 are part of the processor 602 and / or one or more other processors distributed among multiple processors that communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication process (as described herein).

[0113] In at least one embodiment, as used in any implementation described herein, unless the context clearly indicates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry, alone or in any combination. In at least one embodiment, modules may be embodied collectively or individually as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, a module performs one or more processes in association with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof.

[0114] In at least one embodiment, the neural network training module 604 is a module that trains one or more neural networks. In at least one embodiment, the neural network training module 604 performs one or more processes, such as one or more processes described herein, by at least including or otherwise encoding instructions that cause the execution of the one or more processes or are otherwise operable to perform the one or more processes described (e.g., by the processor 602). In at least one embodiment, the neural network training module 604 obtains or otherwise provides one or more neural networks (e.g., through one or more systems, such as in conjunction with Figure 1 In at least one embodiment, the neural network training module 604 uses the training data set through one or more processes (such as combining Figures 1 to 5In at least one embodiment, the neural network training module 604 trains the one or more neural networks using any suitable training process, such as the process described herein.

[0115] In at least one embodiment, the 3D model generation module 606 is a module that generates a 3D model of a first object based on an image that is trained at least in part based on images of one or more second objects from two or more viewpoints. For example, the 3D model generation module uses one or more neural networks to use one or more text descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints. In at least one embodiment, the text description includes text input by a user describing the object. In at least one embodiment, the 3D model generation module 606 performs one or more processes (such as those described herein) by at least including or otherwise encoding instructions that result in the execution of the one or more processes or are otherwise usable to perform the one or more processes (e.g., executed by the processor 602). In at least one embodiment, the 3D model generation module 606 includes a network trained in conjunction with the neural network training module 604. In at least one embodiment, the 3D model generation module 606 generates one or more three-dimensional (3D) models of one or more first objects using one or more text description ... Figures 1 to 5 The process described in the preceding paragraph) performs data processing.

[0116] Figure 7 7 is a block diagram 700 illustrating one or more library drivers and / or runtimes for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, the software program 702 is a software module. In at least one embodiment, the software program 702 includes one or more software modules. In at least one embodiment, Figure 5 In at least one embodiment, one or more APIs 710 are software instruction sets that, if executed, cause one or more processors (e.g., Figure 5In at least one embodiment, the one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, runtimes 704, drivers 704, and / or any other grouping of software and / or executable code described further herein. In at least one embodiment, the one or more APIs 710 perform one or more computing operations in response to a call by a software program 702. In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets (such as APIs 710 or API functions 712) to be executed. In at least one embodiment, the functionality provided by the one or more APIs 710 includes software functions 712, such as software functions 712 that can be used to accelerate one or more parts of a software program 702 using one or more parallel processing units (PPUs), such as a graphics processing unit (GPU).

[0117] In at least one embodiment, the API 710 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 710 described herein are implemented to perform the following operations in conjunction with Figures 1 to 5 In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the following operations in conjunction with Figures 1 to 6 One or more techniques further described.

[0118] In at least one embodiment, a software program 702, such as a user-implemented software program, utilizes one or more application programming interfaces (APIs) 710 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, the one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and / or functions, that each perform one or more computational operations, such as computational operations associated with parallel computing. For example, in one embodiment, the one or more APIs 710 provide functions 712 to cause a neural network to denoise one or more audio signals based at least in part on two or more differently sized segments of the one or more audio signals and / or otherwise perform the operations described herein.

[0119] In at least one embodiment, one or more software programs 702 interact or otherwise communicate with one or more APIs 710 to perform one or more computing operations using one or more PPUs (such as GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more computing operations that are accelerated by being performed at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to perform audio-to-text processing.

[0120] In at least one embodiment, the interface is software instructions that, when executed, provide access to one or more functions 712 provided by the one or more APIs 710. In at least one embodiment, the software programs 702 use native interfaces when a software developer compiles the one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that includes instructions to implement the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are dynamically compiled and the one or more software programs are linked to the one or more precompiled libraries 706 that include the one or more APIs 710 using a linker.

[0121] In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that utilizes or otherwise communicates with a library 706 including one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 706 including the one or more APIs 710 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, the one or more libraries 706 including the one or more APIs 710 are executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702.

[0122] In at least one embodiment, a processor (e.g., processor 502) executing or using one or more software programs 702 calls, uses, executes, or otherwise implements one or more APIs 710 to allocate or otherwise manage memory 714 to be used by the software programs 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory 714 to be used by one or more portions of the software programs 702 for acceleration using one or more PPUs (such as GPUs or any other accelerators or processors described further herein). These software programs 702 can request that a neural network perform signal processing using functions 712 provided by one or more APIs 710, in one embodiment.

[0123] In at least one embodiment, API 710 is an API that facilitates parallel computing. In at least one embodiment, API 710 is any other API described further herein. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, a driver (e.g., driver and / or runtime 704) is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 712 of API 710 during the loading and execution of one or more portions of software program 702. In at least one embodiment, runtime 704 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 712 of API 710 during the execution of software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform combined arithmetic operations by the one or more software programs 702 during execution by one or more PPUs, such as a GPU.

[0124] In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to perform combined arithmetic operations for one or more PPUs, such as GPUs. In at least one embodiment, the one or more APIs 710 provide combined arithmetic operations through the driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve one or more memory blocks 714 of memory 814 of one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve memory blocks 714. In at least one embodiment, the one or more APIs 710 call a neural network to cause 716 the neural network to generate one or more 3D models using one or more text descriptions, such as in conjunction with any Figures 1 to 5 Describe the neural network.

[0125] To improve the usability of the software program 702 and / or to enable one or more parts of the software program 702 to be accelerated by one or more PPUs (such as GPUs), in one embodiment, the one or more APIs 710 provide one or more API functions 712 to enable 716 a neural network to generate one or more 3D models using one or more text descriptions, as described above, and in conjunction with the following. Figures 1 to 5 Further Description: In at least one embodiment, exemplary block diagram 700 depicts a processor (eg, processor 1102) that includes one or more circuits to enable execution of one or more neural networks (eg, CNNs).

[0126] logic

[0127] Figure 8A Logic 815 is shown, as described elsewhere herein, which may be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is reasoning and / or training logic. Figure 8A and / or Figure 8BDetailed information is provided regarding logic 815. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, where the logic may collectively or individually be embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU).

[0128] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0129] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 801 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 801 is internal or external to a processor, e.g., or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0130] In at least one embodiment, logic 815 may include, but is not limited to, code and / or data storage 805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 805 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software to control the timing and / or sequence in which weight and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0131] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 805 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 805 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 805 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 805 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0132] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be the same storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0133] In at least one embodiment, logic 815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 810 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from a layer or neuron within a neural network) stored in activation storage 820, which are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, the activations stored in activation storage 820 are generated based on linear algebra and / or matrix-based math performed by ALU 810 in response to executing instructions or other code, with weight values stored in code and / or data storage 805 and / or code and / or data storage 801 used as operands, as well as other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or other on-chip or off-chip storage.

[0134] In at least one embodiment, one or more ALUs 810 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 810 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 810 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0135] In at least one embodiment, activation storage 820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 820 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0136] In at least one embodiment, Figure 8A The logic 815 shown in FIG may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8A The illustrated logic 815 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0137] Figure 8B Logic 815 is shown in accordance with at least one embodiment. In at least one embodiment, logic 815 is inference and / or training logic. In at least one embodiment, logic 815 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 8B The logic 815 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 8BThe logic 815 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the logic 815 includes, but is not limited to, code and / or data storage 801 and code and / or data storage 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 8B In at least one embodiment shown in FIG, code and / or data storage 801 and code and / or data storage 805 are each associated with dedicated computing resources, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, computing hardware 802 and computing hardware 806 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 801 and code and / or data storage 805, respectively, with the results being stored in activation storage 820.

[0138] In at least one embodiment, each of the code and / or data stores 801 and 805 and the corresponding computing hardware 802 and 806 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 801 / 802 of the code and / or data store 801 and computing hardware 802 are provided as inputs to the next storage / computation pair 805 / 806 of the code and / or data store 805 and computing hardware 806, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 801 / 802 and 805 / 806 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 815 after or in parallel with the storage / computation pairs 801 / 802 and 805 / 806.

[0139] Neural network training and deployment

[0140] Figure 9The training and deployment of a deep neural network according to at least one embodiment is illustrated. In at least one embodiment, an untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is the PyTorch framework, while in other embodiments, the training framework 904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 904 trains the untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, weights may be selected randomly or through pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner. In at least one embodiment, weights may be selected randomly or through pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0141] In at least one embodiment, untrained neural network 906 is trained using supervised learning, where training dataset 902 includes inputs paired with expected outputs for the inputs, or where training dataset 902 includes inputs with known outputs and the outputs of neural network 906 are manually graded. In at least one embodiment, untrained neural network 906 is trained in a supervised manner, processing inputs from training dataset 902 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 906. In at least one embodiment, training framework 904 adjusts the weights that control untrained neural network 906. In at least one embodiment, training framework 904 includes tools for monitoring the degree to which untrained neural network 906 converges toward a model (such as trained neural network 908) suitable for generating correct answers (such as results 914) based on input data (such as new dataset 912). In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine the output of the untrained neural network 906 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 reaches a desired accuracy. In at least one embodiment, the trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0142] In at least one embodiment, unsupervised learning is used to train the untrained neural network 906, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn the groupings within the training dataset 902 and can determine how the individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 908, which can perform operations useful for reducing the dimensionality of the new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 912 that deviate from the normal pattern of the new dataset 912.

[0143] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 902. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to new datasets 912 without forgetting the knowledge that was infused into the trained neural network 908 during initial training.

[0144] In at least one embodiment, the training framework 904 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0145] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0146] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or variations thereof.

[0147] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variations thereof.

[0148] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0149] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0150] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0151] Data Center

[0152] Figure 10 An example data center 1000 is shown in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0153] In at least one embodiment, Figure 10As shown, the data center infrastructure layer 1010 may include a resource coordinator 1012, grouped computing resources 1014, and node computing resources ("node CRs") 1016(1)-1016(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1016(1)-1016(N) may be a server having one or more of the above-mentioned computing resources.

[0154] In at least one embodiment, the grouped computing resources 1014 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in a number of racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1014 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0155] In at least one embodiment, resource coordinator 1012 may configure or otherwise control one or more nodes CR 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource coordinator 1012 may comprise a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource coordinator 1012 may comprise hardware, software, or some combination thereof.

[0156] In at least one embodiment, Figure 10As shown, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework that supports software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application 1042 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be, but is not limited to, a type of free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1028 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1022 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as the software layer 1030 and the framework layer 1020 including Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, the resource manager 1026 may be capable of managing the mapping or allocation of clustered or grouped computing resources to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 1014 at the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

[0157] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least portions of the nodes CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0158] In at least one embodiment, the one or more applications 1042 included in the application layer 1040 may include one or more types of applications used by at least portions of the nodes CRs 1016(1)-1016(N), the grouped computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0159] In at least one embodiment, any of the configuration manager 1024, resource manager 1026, and resource coordinator 1012 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve the data center operator of the data center 1000 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0160] In at least one embodiment, data center 1000 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1000. In at least one embodiment, the resources described above with respect to data center 1000 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks using weight parameters computed using one or more training techniques described herein.

[0161] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0162] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in data center 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0163] In at least one embodiment, data center 1000 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 10 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 10 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0164] autonomous vehicles

[0165] Figure 11A An example of an autonomous vehicle 1100 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1100 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1100 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0166] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of such standards). In at least one embodiment, the vehicle 1100 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0167] In at least one embodiment, the vehicle 1100 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1100 may include, but is not limited to, a propulsion system 1150, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1150 may be connected to a drive train of the vehicle 1100, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1100. In at least one embodiment, the propulsion system 1150 may be controlled in response to receiving a signal from a throttle / accelerator 1152.

[0168] In at least one embodiment, when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion), a steering system 1154 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1100 (e.g., along a desired path or route). In at least one embodiment, steering system 1154 may receive signals from steering actuator 1156. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1146 may be used to operate vehicle brakes in response to signals received from brake actuator 1148 and / or brake sensors.

[0169] In at least one embodiment, one or more controllers 1136, which may include, but are not limited to, one or more system-on-chips ("SoCs") ( Figure 11A) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1100. For example, in at least one embodiment, one or more controllers 1136 can send signals to operate vehicle brakes via brake actuator 1148, operate steering system 1154 via one or more steering actuators 1156, and operate propulsion system 1150 via one or more throttle / accelerator 1152. In at least one embodiment, one or more controllers 1136 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1100. In at least one embodiment, one or more controllers 1136 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0170] In at least one embodiment, the one or more controllers 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1158 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (IMU) sensors 1166 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1196, one or more stereo cameras 1168, one or more wide-angle cameras 1170 (e.g., fisheye cameras), one or more infrared cameras 1172, one or more surround cameras 1174 (e.g., 360-degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 11A Not shown), mid-range camera ( Figure 11A), one or more speed sensors 1144 (e.g., for measuring the speed of the vehicle 1100), one or more vibration sensors 1142, one or more steering sensors 1140, one or more brake sensors (e.g., as part of a brake sensor system 1146), and / or other sensor types.

[0171] In at least one embodiment, one or more controllers 1136 may receive input (e.g., represented by input data) from a dashboard 1132 of the vehicle 1100 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface (“HMI”) display 1134, an audible annunciator, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 11A ), location data (e.g., the location of the vehicle 1100, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1136, etc. For example, in at least one embodiment, the HMI display 1134 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0172] In at least one embodiment, the vehicle 1100 further includes a network interface 1124 that can communicate over one or more networks using one or more wireless antennas 1126 and / or one or more modems. For example, in at least one embodiment, the network interface 1124 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1126 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as protocols such as LoRaWAN, SigFox, and the like).

[0173] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 can be used in vehicle 1000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0174] In at least one embodiment, vehicle 1100 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, at least a portion of the system shown in FIG. 11 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 11 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0175] Figure 11B According to at least one embodiment, Figure 11A 1100. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 1100.

[0176] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1100. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0177] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0178] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to remove stray light and reflected light from within the vehicle 1100 (e.g., reflected light from the dashboard reflecting in the windshield mirror), which may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0179] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1100 can be used for surround vision to help identify the path ahead and obstacles, as well as assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1136 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0180] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1170 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 11B Only one wide-angle camera 1170 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1100. In at least one embodiment, any number of remote cameras 1198 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1198 can also be used for object detection and classification and basic object tracking.

[0181] In at least one embodiment, any number of stereo cameras 1168 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1168 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1100's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1168 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1100 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or in place of those described herein.

[0182] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1100 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1174 (e.g., Figure 11B The four surround cameras shown) can be positioned on the vehicle 1100. In at least one embodiment, the one or more surround cameras 1174 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 can use three surround cameras 1174 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0183] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1100 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1198 and / or one or more mid-range cameras 1176, one or more stereo cameras 1168, one or more infrared cameras 1172, etc.), as described herein.

[0184] In at least one embodiment, vehicle 1100 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 10 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 11B At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0185] Figure 11C is a diagram illustrating a method according to at least one embodiment Figure 11AA block diagram of an example system architecture for an autonomous vehicle 1100 is provided. In at least one embodiment, Figure 11C Each of the components, features, and systems of vehicle 1100 is shown as being connected via bus 1102. In at least one embodiment, bus 1102 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1100 that assists in controlling various features and functions of vehicle 1100, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1102 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1102 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1102 can be an ASIL B compliant CAN bus.

[0186] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1102, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1102 may communicate with any component of vehicle 1100, and two or more buses in bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1104 (e.g., SoC 1104(A) and SoC 1104(B)), each of one or more controllers 1136, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1100) and can be connected to a common bus, such as a CAN bus.

[0187] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Figure 11AIn at least one embodiment, the controller 1136 can be used for a variety of functions. In at least one embodiment, the controller 1136 can be coupled to any of the various other components and systems of the vehicle 1100 and can be used to control the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment and / or other functions of the vehicle 1100.

[0188] In at least one embodiment, the vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, but is not limited to, a central processing unit ("CPU(s)") 1106, a graphics processing unit ("GPU(s")) 1108, one or more processors 1110, one or more caches 1112, one or more accelerators 1114, one or more data stores 1116, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1104 may be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1104 may be combined in a system (e.g., a system of the vehicle 1100) along with a high-definition ("HD") map 1122 that may be downloaded from one or more servers (e.g., a system of the vehicle 1100) via a network interface 1124. Figure 11C ) to obtain map refreshes and / or updates.

[0189] In at least one embodiment, one or more CPUs 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1106 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1106 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1106 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1106 may be active at any given time.

[0190] In at least one embodiment, one or more CPUs 1106 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1106 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0191] In at least one embodiment, one or more GPUs 1108 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1108 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1108 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1108 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1108 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0192] In at least one embodiment, one or more GPUs 1108 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1108 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0193] In at least one embodiment, one or more GPUs 1108 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0194] In at least one embodiment, one or more GPUs 1108 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1108 to directly access the page tables of one or more CPUs 1106. In at least one embodiment, when the memory management unit ("MMU") of a GPU in one or more GPUs 1108 experiences a miss, an address translation request may be sent to the one or more CPUs 1106. In response, in at least one embodiment, two of the one or more CPUs 1106 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1108. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1106 and the one or more GPUs 1108, thereby simplifying programming the one or more GPUs 1108 and porting applications to the one or more GPUs 1108.

[0195] In at least one embodiment, one or more GPUs 1108 may include any number of access counters that can track the frequency with which one or more GPUs 1108 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0196] In at least one embodiment, one or more SoCs 1104 may include any number of caches 1112, including those described herein. For example, in at least one embodiment, one or more caches 1112 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1106 and one or more GPUs 1108. In at least one embodiment, one or more caches 1112 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0197] In at least one embodiment, one or more SoCs 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1104 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1108 and offload some tasks of one or more GPUs 1108 (e.g., to free up more cycles of one or more GPUs 1108 to perform other tasks). In at least one embodiment, one or more accelerators 1114 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network (“RCNN”) and a fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0198] In at least one embodiment, one or more accelerators 1114 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0199] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1108, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1108. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1108 and / or one or more accelerators 1114.

[0200] In at least one embodiment, one or more accelerators 1114 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0201] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0202] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of one or more CPUs 1106. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0203] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0204] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0205] In at least one embodiment, one or more accelerators 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1114. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0206] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may conform to the International Organization for Standardization ("ISO") 26262 or the International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0207] In at least one embodiment, one or more SoCs 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0208] In at least one embodiment, one or more accelerators 1114 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithmic domain that requires predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1100, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0209] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0210] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0211] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1166 associated with vehicle 1100 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1164 or one or more RADAR sensors 1160).

[0212] In at least one embodiment, one or more SoCs 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, one or more data stores 1116 may be on-chip memory of one or more SoCs 1104 that may store neural networks to be executed on one or more GPUs 1108 and / or DLAs. In at least one embodiment, one or more data stores 1116 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1116 may include one or more L2 or L3 caches.

[0213] In at least one embodiment, one or more SoCs 1104 may include any number of processors 1110 (e.g., embedded processors). In at least one embodiment, one or more processors 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1104 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1104 thermal and temperature sensors, and / or manage one or more SoCs 1104 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1104 may use the ring oscillator to detect the temperature of one or more CPUs 1106, one or more GPUs 1108, and / or one or more accelerators 1114. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1104 into a lower power state and / or place the vehicle 1100 into a driver's safe parking mode (e.g., bringing the vehicle 1100 to a safe stop).

[0214] In at least one embodiment, one or more processors 1110 may further include a set of embedded processors that can serve as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0215] In at least one embodiment, one or more processors 1110 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0216] In at least one embodiment, one or more processors 1110 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1110 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1110 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0217] In at least one embodiment, one or more processors 1110 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1170, one or more surround cameras 1174, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1104, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0218] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, in the presence of motion in the image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0219] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1108 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1108 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1108 to improve performance and responsiveness.

[0220] In at least one embodiment, one or more of the SoCs 1104 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1104 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0221] In at least one embodiment, one or more of the SoCs 1104 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1104 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1164, one or more RADAR sensors 1160, etc., which may be connected via an Ethernet channel), data from the bus 1102 (e.g., vehicle 1100 speed, steering wheel position, etc.), data from one or more GNSS sensors 1158 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1104 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1106 from routine data management tasks.

[0222] In at least one embodiment, one or more SoCs 1104 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1104 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1114, when combined with one or more CPUs 1106, one or more GPUs 1108, and one or more data stores 1116, can provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0223] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0224] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1120) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0225] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1108.

[0226] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1104 provide protection against theft and / or carjacking.

[0227] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1104 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1158. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1162 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0228] In at least one embodiment, the vehicle 1100 may include one or more CPUs 1118 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1118 may include, for example, an X86 processor. The one or more CPUs 1118 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1104, and / or monitoring the status and health of one or more controllers 1136 and / or an infotainment system on a chip ("infotainment SoC") 1130. In at least one embodiment, the one or more SoCs 1104 include one or more interconnects, and the interconnects may include a Peripheral Component Interconnect Express (PCIe).

[0229] In at least one embodiment, the vehicle 1100 may include one or more GPUs 1120 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 1100 (e.g., sensor data).

[0230] In at least one embodiment, vehicle 1100 may further include a network interface 1124, which may include, but is not limited to, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1100 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1100 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1100). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1100.

[0231] In at least one embodiment, the network interface 1124 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1136 to communicate over a wireless network. In at least one embodiment, the network interface 1124 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0232] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1104) storage. In at least one embodiment, the one or more data stores 1128 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0233] In at least one embodiment, the vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0234] In at least one embodiment, the vehicle 1100 may further include one or more RADAR sensors 1160. In at least one embodiment, the one or more RADAR sensors 1160 may be used by the vehicle 1100 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting data generated by the one or more RADAR sensors 1160) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1160 are pulse Doppler RADAR sensors.

[0235] In at least one embodiment, one or more RADAR sensors 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1160 can help distinguish between static objects and moving objects and can be used by the ADAS system 1138 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1160 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1100 at a higher speed with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1100 .

[0236] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1160 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1138 for blind spot detection and / or lane change assistance.

[0237] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, one or more ultrasonic sensors 1162, which may be positioned at the front, rear, and / or side of the vehicle 1100, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1162 may operate at an ASIL B functional safety level.

[0238] In at least one embodiment, the vehicle 1100 can include one or more LIDAR sensors 1164. In at least one embodiment, the one or more LIDAR sensors 1164 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1164 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1100 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1164 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0239] In at least one embodiment, one or more LIDAR sensors 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1164 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 1100. In at least one embodiment, one or more LIDAR sensors 1164 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1164 may be configured for a horizontal field of view between 45 and 135 degrees.

[0240] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1100. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1100 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1100. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0241] In at least one embodiment, the vehicle 1100 may also include one or more IMU sensors 1166. In at least one embodiment, the one or more IMU sensors 1166 may be located at the center of the rear axle of the vehicle 1100. In at least one embodiment, the one or more IMU sensors 1166 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1166 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0242] In at least one embodiment, the one or more IMU sensors 1166 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1166 can enable the vehicle 1100 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1166, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1166 and the one or more GNSS sensors 1158 can be combined in a single integrated unit.

[0243] In at least one embodiment, the vehicle 1100 can include one or more microphones 1196 positioned within and / or around the vehicle 1100. In at least one embodiment, the one or more microphones 1196 can be used for emergency vehicle detection and identification.

[0244] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including one or more stereo cameras 1168, one or more wide angle cameras 1170, one or more infrared cameras 1172, one or more surround cameras 1174, one or more long range cameras 1198, one or more mid range cameras 1176, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1100. In at least one embodiment, the type of camera used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the camera types and the camera types used. Figure 11A and Figure 11B Each camera is described in more detail.

[0245] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the one or more vibration sensors 1142 may measure vibrations of a component (e.g., an axle) of the vehicle 1100. For example, in at least one embodiment, changes in vibration may indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0246] In at least one embodiment, the vehicle 1100 may include an ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1138 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0247] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and suggests that the vehicle 1100 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0248] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1124 and / or one or more wireless antennas 1126. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1100 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1100, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0249] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0250] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0251] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1100 crosses a lane marking. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1100 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1100.

[0252] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0253] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1100 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0254] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1100 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1138 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0255] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0256] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1104.

[0257] In at least one embodiment, the ADAS system 1138 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially with respect to failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and non-identical software code running on the auxiliary computer provides consistent overall results, the supervisory MCU may have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0258] In at least one embodiment, the output of the ADAS system 1138 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0259] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1100. For example, the infotainment SoC 1130 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 may be further configured to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1100, such as information from the ADAS system 1138, autonomous driving information (e.g., planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0260] In at least one embodiment, the infotainment SoC 1130 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 can communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1136 (e.g., the vehicle's 1100 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1130 can place the vehicle 1100 in a driver-to-safety parking mode, as described herein.

[0261] In at least one embodiment, the vehicle 1100 may further include an instrument panel 1132 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1132 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the instrument panel 1132. In at least one embodiment, the instrument panel 1132 may be included as part of the infotainment SoC 1130, or vice versa.

[0262] In at least one embodiment, vehicle 1100 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 10 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 11C At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0263] Figure 11D In accordance with at least one embodiment, one or more cloud-based servers and Figure 11AFIG1 is a diagram of a system for communicating between autonomous vehicles 1100. In at least one embodiment, the system may include, but is not limited to, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, one or more servers 1178 may include, but is not limited to, multiple GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected using a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1188 and / or PCIe connection 1186 developed by NVIDIA. In at least one embodiment, the GPUs 1184 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1178 may include, but is not limited to, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, one or more servers 1178 may each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0264] In at least one embodiment, one or more servers 1178 may receive image data representing an image from a vehicle via one or more networks 1190 that depicts an unexpected or altered road condition, such as a recently begun roadwork. In at least one embodiment, one or more servers 1178 may transmit an updated neural network 1192 and / or map information 1194 to the vehicle via one or more networks 1190, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1194 may include, but not limited to, updates to the HD map 1122, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1192 and / or map information 1194 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1178 and / or other servers).

[0265] In at least one embodiment, one or more servers 1178 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1190, and / or the machine learning model can be used by one or more servers 1178 to remotely monitor the vehicle.

[0266] In at least one embodiment, one or more servers 1178 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1178 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1178 can include the deep learning infrastructure of a data center using CPU power.

[0267] In at least one embodiment, the deep learning infrastructure of one or more servers 1178 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1100, such as an image sequence and / or objects that the vehicle 1100 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI in the vehicle 1100 is malfunctioning, the one or more servers 1178 may send a signal to the vehicle 1100 instructing the vehicle's 1100 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0268] In at least one embodiment, one or more servers 1178 may include one or more GPUs 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 815 are used to execute one or more embodiments. Figure 8A and / or Figure 8B Provides details about the hardware structure 815.

[0269] Computer system

[0270] Figure 12 1 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1200 may include, but is not limited to, components such as processor 1202 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1200 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1200 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0271] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0272] In at least one embodiment, the computer system 1200 may include, but is not limited to, a processor 1202, which may include, but is not limited to, one or more execution units 1208 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1200 is a single-processor desktop or server system, but in another embodiment, the computer system 1200 may be a multi-processor system. In at least one embodiment, the processor 1202 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210, which may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0273] In at least one embodiment, processor 1202 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1206 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0274] In at least one embodiment, an execution unit 1208, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1202. In at least one embodiment, the processor 1202 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1208 may include logic for processing a packed instruction set 1209. In at least one embodiment, by including the packed instruction set 1209 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0275] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, but is not limited to, memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1220 may store one or more instructions 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0276] In at least one embodiment, the system logic chip can be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to the memory 1220 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1216 can direct data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, the memory 1220, and the system I / O interface 1222. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via a high-bandwidth memory path 1218 , and the graphics / video card 1212 may be coupled to the MCH 1216 via an accelerated graphics port (“AGP”) interconnect 1214 .

[0277] In at least one embodiment, the computer system 1200 can use the system I / O interface 1222 as a proprietary hub interface bus to couple the MCH 1216 to the I / O controller hub ("ICH") 1230. In at least one embodiment, the ICH 1230 can provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 1220, the chipset, and the processor 1202. Examples can include, but are not limited to, an audio controller 1229, a firmware hub ("flash BIOS") 1228, a wireless transceiver 1226, a data store 1224, a traditional I / O controller 1223 including a user input and keyboard interface 1225, a serial expansion port 1227 (such as a universal serial bus ("USB") port), and a network controller 1234. In at least one embodiment, the data store 1224 can include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0278] In at least one embodiment, Figure 12 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 12 An exemplary SoC may be shown. In at least one embodiment, Figure 12The devices shown in FIG1200 may be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using a Compute Express Link (CXL) interconnect.

[0279] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computer system 1200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0280] In at least one embodiment, computer system 1200 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 12 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 12 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0281] Figure 13 1 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0282] In at least one embodiment, the electronic device 1300 may include, but is not limited to, a processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled using a bus or interface, such as an I 2C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, Universal Serial Bus ("USB") (Revision 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 13 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 13 An exemplary SoC may be shown. In at least one embodiment, Figure 13 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 13 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0283] In at least one embodiment, Figure 13 It may include a display 1324, a touch screen 1325, a touchpad 1330, a near field communication unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, an express chipset (“EC”) 1335, a trusted platform module (“TPM”) 1338, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0284] In at least one embodiment, other components may be communicatively coupled to processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, a speaker 1363, an earpiece 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352 and the WWAN unit 1356 may be implemented as a next generation form factor ("NGFF").

[0285] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in electronic device 1300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0286] In at least one embodiment, electronic device 1300 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 13 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 13 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0287] Figure 14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement the various processes and methods described throughout this disclosure.

[0288] In at least one embodiment, computer system 1400 includes, but is not limited to, at least one central processing unit ("CPU") 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1400 includes, but is not limited to, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1404, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1400.

[0289] In at least one embodiment, computer system 1400 includes, but is not limited to, input device 1408, parallel processing system 1412, and display device 1406, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1408 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0290] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding inference and / or training logic 815. In at least one embodiment, logic 815 can be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0291] In at least one embodiment, computer system 1400 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 14 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 14 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0292] Figure 15 A computer system 1500 is shown according to at least one embodiment. In at least one embodiment, computer system 1500 includes, but is not limited to, a computer 1510 and a USB drive 1520. In at least one embodiment, computer 1510 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1510 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0293] In at least one embodiment, the USB disk 1520 includes, but is not limited to, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1530 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1530 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0294] In at least one embodiment, USB interface 1540 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 can include any number and type of logic that enables processing unit 1530 to interface with a device (e.g., computer 1510) via USB connector 1540.

[0295] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0296] In at least one embodiment, computer system 1500 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 15 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 15 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0297] Figure 16AAn exemplary architecture is shown in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed links 1640(1)-1640(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1640(1)-1640(N) support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values of which may vary from figure to figure. In at least one embodiment, as Figure 19A and Figure 19B As disclosed, one or more of the plurality of GPUs 1610(1)-1610(N) include one or more graphics cores (also referred to simply as "cores") 1900. In at least one embodiment, the one or more graphics cores 1900 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0298] Furthermore, in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed links 1629(1)-1629(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be connected via high-speed link 1628, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 16A All communications between the various system components shown in . In at least one embodiment, one or more of the plurality of GPUs 1610(1)-1610(N) include Figure 19A and 19BDisclosed are one or more graphics cores (which may also be referred to simply as "cores") 1900. In at least one embodiment, one or more graphics cores 1900 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., a 16-core, a ray tracing unit, a thread director, or a scheduler).

[0299] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1601(1)-1601(M) and GPU memory 1620 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1601 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0300] As described herein, although each multi-core processor 1605 and GPU 1610 can be physically coupled to a specific memory 1601, 1620, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1601(1)-1601(M) can each include 64GB of system memory address space, and GPU memories 1620(1)-1620(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values of N and M are possible.

[0301] Figure 16BAdditional details are shown for the interconnection between multi-core processor 1607 and graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, graphics acceleration module 1646 may include one or more GPU chips integrated on a line card that is coupled to processor 1607 via a high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1646 may alternatively be integrated on a package or chip with processor 1607.

[0302] In at least one embodiment, processor 1607 includes multiple cores 1660A-1660D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by groups of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which may include Figure 16A Processor memory 1601(1)-1601(M) in.

[0303] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1662A-1662D, 1656 and system memory 1614 via inter-core communication over a coherency bus 1664. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate over the coherency bus 1664 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1664 to snoop cache accesses.

[0304] In at least one embodiment, proxy circuitry 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, thereby allowing graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, interface 1635 provides connectivity to proxy circuitry 1625 via high-speed link 1640, and interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0305] In at least one embodiment, the accelerator integrated circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 comprise a combination of Figure 19A and Figure 19B The one or more graphics cores 1900 discussed. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1646 may be a GPU having multiple graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0306] In at least one embodiment, the accelerator integrated circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1614. In at least one embodiment, the MMU 1639 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1638 may store commands and data for efficient access by the graphics processing engines 1631(1)-1631(N). In at least one embodiment, a fetch unit 1644 may be used to keep data stored in the cache 1638 and graphics memory 1633(1)-1633(M) consistent with the core caches 1662A-1662D, 1656, and system memory 1614. As previously described, this can be implemented on behalf of cache 1638 and memory 1633(1)-1633(M) via proxy circuit 1625 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 to cache 1638 and receiving updates from cache 1638).

[0307] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages thread contexts. For example, context management circuitry 1648 can perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1648 can store current register values to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1647 receives and processes interrupts received from system devices.

[0308] In at least one embodiment, the MMU 1639 converts virtual / effective addresses from the graphics processing engine 1631 into real / physical addresses in the system memory 1614. In at least one embodiment, the accelerator integrated circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 can be dedicated to a single application executing on the processor 1607, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1631 (1)-1631 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0309] In at least one embodiment, the accelerator integrated circuit 1636 acts as a bridge to the system for the graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1636 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1631(1)-1631(N).

[0310] In at least one embodiment, because the hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped into the real address space seen by host processor 1607, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1636 is the physical separation of graphics processing engines 1631(1)-1631(N) so that they appear to the system as independent units.

[0311] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each graphics processing engine 1631(1)-1631(N), respectively, with N=M. In at least one embodiment, graphics memories 1633(1)-1633(M) store instructions and data being processed by each graphics processing engine 1631(1)-1631(N). In at least one embodiment, graphics memories 1633(1)-1633(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0312] In at least one embodiment, to reduce data traffic on high-speed link 1640, a biasing technique may be used to ensure that the data stored in graphics memory 1633(1)-1633(M) is the data most frequently used by graphics processing engines 1631(1)-1631(N), and preferably is not used (at least not frequently) by cores 1660A-1660D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1631(1)-1631(N)) in caches 1662A-1662D, 1656, and system memory 1614.

[0313] Figure 16C Another exemplary embodiment is shown in which an accelerator integrated circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integrated circuit 1636 via interface 1637 and interface 1635 (again, which can be any form of bus or interface protocol) over a high-speed link 1640. In at least one embodiment, the accelerator integrated circuit 1636 can perform operations related to Figure 16B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1664 and caches 1662A-1662D, 1656. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1636 and a programming model controlled by the graphics acceleration module 1646.

[0314] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0315] In at least one embodiment, graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1631(1)-1631(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1631(1)-1631(N) to provide access to each process or application.

[0316] In at least one embodiment, the graphics acceleration module 1646 or individual graphics processing engines 1631(1)-1631(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1614 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1631(1)-1631(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0317] Figure 16D An exemplary accelerator integrated slice 1690 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1636. In at least one embodiment, the application is an effective address space 1682 in system memory 1614, which stores a process element 1683. In at least one embodiment, the process element 1683 is stored in response to a GPU call 1681 from the application 1680 executing on the processor 1607. In at least one embodiment, the process element 1683 contains the process state of the corresponding application 1680. In at least one embodiment, the work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of the application.

[0318] In at least one embodiment, the graphics acceleration module 1646 and / or the individual graphics processing engines 1631(1)-1631(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1684 to the graphics acceleration module 1646 to start a job in a virtualized environment.

[0319] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when a graphics acceleration module 1646 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1646 is assigned, the operating system initializes the accelerator integrated circuit 1636 for the owned process.

[0320] In operation, in at least one embodiment, a WD fetch unit 1691 in the accelerator integrated slice 1690 fetches a next WD 1684, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in registers 1645 and used by the MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of the MMU 1639 includes segment / page walk circuitry for accessing segment / page tables 1686 within the OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process interrupt events 1692 received from the graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, effective addresses 1693 generated by the graphics processing engines 1631(1)-1631(N) are converted to real addresses by the MMU 1639.

[0321] In at least one embodiment, registers 1645 are replicated for each graphics processing engine 1631(1)-1631(N) and / or graphics acceleration module 1646, and these registers 1645 can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1690. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0322] Table 1 – Registers initialized by the hypervisor

[0323]

[0324]

[0325] Example registers that may be initialized by the operating system are shown in Table 2.

[0326] Table 2 – Registers initialized by the operating system

[0327]

[0328] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information needed by the graphics processing engine 1631(1)-1631(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0329] Figure 16E 16. Additional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 is accessible via a hypervisor 1696 that virtualizes a graphics acceleration module engine for an operating system 1695.

[0330] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1646. In at least one embodiment, there are two programming models where the graphics acceleration module 1646 is shared by multiple processes and partitions, namely, time-sliced sharing and graphics-directed sharing.

[0331] In at least one embodiment, in this model, the hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for the graphics acceleration module 1646 to support virtualization through the hypervisor 1696, the graphics acceleration module 1646 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) the graphics acceleration module 1646 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1646 provides the ability to preempt job processing, and (3) the graphics acceleration module 1646 must ensure fairness between processes when operating in a directed shared programming model.

[0332] In at least one embodiment, the application 1680 is required to make an operating system 1695 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1646 and can take the form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1646.

[0333] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1636 (not shown) and the graphics acceleration module 1646 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1696 may selectively apply the current AMR value before placing the AMR into the process element 1683. In at least one embodiment, the CSRP is one of the registers 1645 that contains the effective address of an area in the application's effective address space 1682 for the graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0334] Upon receiving the system call, the operating system 1695 can verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. Then, in at least one embodiment, the operating system 1695 calls the hypervisor 1696 using the information shown in Table 3.

[0335] Table 3 – OS to Hypervisor call parameters

[0336]

[0337] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been granted permission to use graphics acceleration module 1646. Then, in at least one embodiment, hypervisor 1696 places process element 1683 into a linked list of process elements of the corresponding type of graphics acceleration module 1646. In at least one embodiment, the process element may include the information shown in Table 4.

[0338] Table 4 – Process element information

[0339]

[0340] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1690 registers 1645 .

[0341] like Figure 16F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1601(1)-1601(N) and GPU memory 1620(1)-1620(N). In this implementation, operations executed on GPUs 1610(1)-1610(N) utilize the same virtual / effective memory address space to access processor memory 1601(1)-1601(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1601(1), a second portion is allocated to second processor memory 1601(N), a third portion is allocated to GPU memory 1620(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1601 and GPU memory 1620, thereby allowing any processor or GPU to access any physical memory using a virtual address mapped to that memory.

[0342] In at least one embodiment, bias / coherency management circuitry 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherency between the caches of one or more host processors (e.g., 1605) and GPU 1610 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 16F Multiple instances of bias / coherence management circuits 1694A- 1694E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1605 and / or within an accelerator integrated circuit 1636 .

[0343] One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1605 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1610. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0344] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1620, with or without a bias cache in GPU 1610 (e.g., for caching frequently / recently used entries in the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0345] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1620 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1610 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1620. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1605 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1605 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1610. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0346] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1605 bias to GPU bias, but not for the reverse migration.

[0347] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1605, and vice versa.

[0348] One or more hardware structures 815 are used to execute one or more embodiments. Figure 8A and / or Figure 8B Details regarding one or more hardware structures 815 are provided.

[0349] Figure 17An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0350] Figure 17 1700 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I / O controller. 2 S / I 2 IC controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industry Processor Interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1770.

[0351] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in integrated circuit 1700 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0352] In at least one embodiment, system-on-chip integrated circuit 1700 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5). In at least one embodiment, Figure 17 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 17 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0353] Figures 18A-18B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0354] Figures 18A-18B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 18A An exemplary graphics processor 1810 of a system-on-chip integrated circuit is shown, which may be fabricated using one or more IP cores, in accordance with at least one embodiment. Figure 18B An additional exemplary graphics processor 1840 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 18A The graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 can be Figure 17 A variation of the graphics processor 1710 .

[0355] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1815A-1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0356] In at least one embodiment, the graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, one or more caches 1825A-1825B, and one or more circuit interconnects 1830A-1830B. In at least one embodiment, the one or more MMUs 1820A-1820B provide virtual to physical address mapping for the graphics processor 1810 (including for the vertex processor 1805 and / or the fragment processors 1815A-1815N), which can reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1825A-1825B. In at least one embodiment, the one or more MMUs 1820A-1820B can synchronize with other MMUs within the system, including with Figure 17 One or more MMUs associated with one or more application processors 1705, graphics processor 1715, and / or video processor 1720 enable each processor 1705-1720 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0357] In at least one embodiment, graphics processor 1840 includes: Figure 18B One or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F through 1855N-1 and 1855N) are shown, which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within the scene or to optimize the use of internal caches.

[0358] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processors 1810 and / or 1840 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0359] In at least one embodiment, graphics processor 1810 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, at least a portion of the system shown in FIG. 18 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 18 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0360] Figures 19A-19B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figures 19A-19B Shown in and about Figures 19A-19B The components described are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other type of processor. In at least one embodiment, Figure 19A Shows that can be included in Figure 17 Graphics core 1900 within graphics processor 1710 of FIG. 17 and, in at least one embodiment, may be such as Figure 18B Unified shader cores 1855A-1855N are shown. Figure 19B A highly parallel general-purpose graphics processing unit ("GPGPU," which may be referred to as a "graphics processing unit") 1930 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1700 includes graphics core 1900, e.g., to form an integrated circuit and / or to form a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0361] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920 (e.g., including L1, L2, L3, last level cache, or other caches), which are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to graphics core 1900. In at least one embodiment, slices 1901A-1901N have sub-slices, which are portions of slices 1901A-1901N. In at least one embodiment, slices 1901A-1901N may be independent of other slices or dependent on other slices. In at least one embodiment, the slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N may include a set of additional function units (AFUs 1912A-1912N), floating point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address calculation units (ACUs 1913A-1913N), double precision floating point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, the MPUs 1917A-1917N are referred to as a matrix engine.

[0362] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in artificial intelligence, machine learning, or large data set workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also known as "FP16"), 32-bit floating point (also known as "FP32"), or 64-bit floating point (also known as "FP64"). In at least one embodiment, one or more slices 1901A-1901N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix extensions. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, graphics core 1900 includes one or more matrix engines for computing matrix operations, such as when computing tensor operations.

[0363] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, the ray tracing units compute ray traversals, triangle intersections, bounding box intersections, or other ray tracing operations.

[0364] In at least one embodiment, one or more slices 1901A-1901N comprise a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video quality operations on video data.

[0365] In at least one embodiment, one or more slices 1901A-1901N are linked to an L2 cache and memory structure, a link connector, a high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data (e.g., data corresponding to instructions); one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more layered depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 1901A-1901N include memory structures, such as an L2 cache.

[0366] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1917A-1917N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1912A-1912N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0367] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics core 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0368] In at least one embodiment, graphics core 1900 includes an interconnect and link fabric sublayer attached to a switch and GPU-GPU bridge that enables interconnection of multiple graphics processors 1900 (e.g., eight) with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900 without requiring glue to each other. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0369] In at least one embodiment, graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where the individual dies can be connected using an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1900 includes compute tiles, memory tiles (e.g., where memory tiles can be exclusively accessed by different tiles or different chipsets (such as Rambo tiles)), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, where all tiles are packaged together in graphics core 1900 as part of a GPU. In at least one embodiment, graphics core 1900 can include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile can have 8 graphics cores 1900, an L1 cache; and a base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected via fine-pitch 36 micron microbumps (e.g., copper pillars) in a face-to-face (F2F) on-chip bonding manner. In at least one embodiment, graphics core 1900 includes a memory structure (which includes memory) and is accessible to multiple tiles. In at least one embodiment, graphics core 1900 stores, accesses, or loads its own hardware context in memory, where the hardware context is a set of data loaded from registers before the process resumes, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0370] In at least one embodiment, graphics core 1900 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or converts a parallel data stream into a serial data stream.

[0371] In at least one embodiment, graphics core 1900 includes a high-speed coherent unified fabric (GPU to GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0372] In at least one embodiment, graphics core 1900 executes an API that abstracts the hardware of graphics core 1900 and accesses libraries with instructions to perform mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0373] In at least one embodiment, graphics core 1900 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, at least a portion of the system shown in FIG. 19 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 19 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0374] Figure 19BA GPGPU 1930 is shown in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 for connecting to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 (which can be referred to as a thread sequencer and / or asynchronous compute engine) to assign execution threads associated with those commands to a set of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 may be used as a higher level cache for cache memory within compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H include slices or also referred to as "slices." In at least one embodiment, GPGPU 1930 is part of a SoC, such as part of integrated circuit 1700 ( Figure 17 ).

[0375] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0376] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Figure 19AThe graphics core 1900 may include multiple types of integer and floating-point logic units that can perform computational operations across a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0377] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1936A-1936H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU link 1940, which enables direct connections to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible via host interface 1932. In at least one embodiment, GPU link 1940 may be configured to enable connection to a host processor in addition to or in lieu of host interface 1932 .

[0378] In at least one embodiment, GPGPU 1930 can be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inference platform. In at least one embodiment, when using GPGPU 1930 for inference, GPGPU 1930 can include fewer compute clusters 1936A-1936H than when using GPGPU 1930 for training a neural network. In at least one embodiment, the memory technology associated with memories 1944A-1944B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1930 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0379] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in GPGPU 1930 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0380] In at least one embodiment, GPGPU 1930 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 In at least one embodiment, at least a portion of the system shown in FIG. 19 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 19 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0381] Figure 20 2 is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, computing system 2000 includes a processing subsystem 2001 having one or more processors 2002 and system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset assembly or may be integrated within one or more processors 2002. In at least one embodiment, memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O hub 2007, which enables computing system 2000 to receive input from one or more input devices 2008. In at least one embodiment, I / O hub 2007 may enable a display controller, which may be included in one or more processors 2002, to provide output to one or more display devices 2010A. In at least one embodiment, the one or more display devices 2010A coupled to the I / O hub 2007 may include local, internal, or embedded display devices.

[0382] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 coupled to a memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use one of any number of standard based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2012 form a parallel or vector processing system in a computational cluster, which can include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 2012 form a graphics processing subsystem that can output pixels to one of one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the one or more parallel processors 2012 can also include a display controller and display interface (not shown) for enabling direct connection to one or more display devices 2010B. In at least one embodiment, one or more parallel processors 2012 include one or more cores, such as graphics core 1900 discussed herein.

[0383] In at least one embodiment, a system storage unit 2014 can be connected to the I / O hub 2007 to provide a storage mechanism for the computing system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism for enabling connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that can be integrated into the platform, as well as various other devices that can be added via one or more additional devices 2020. In at least one embodiment, the network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2019 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0384] In at least one embodiment, the computing system 2000 may include other components not explicitly shown that may also be connected to the I / O hub 2007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as the NV-Link high-speed interconnect or interconnect protocol). Figure 20The communication paths between the various components in the system.

[0385] In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU), e.g., one or more parallel processors 2012 include graphics core 1900. In at least one embodiment, one or more parallel processors 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, memory hub 2005, one or more processors 2002, and I / O hub 2007 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 2000 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0386] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in computing system 2000 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0387] In at least one embodiment, computing system 2000 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 20 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 20 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0388] processor

[0389] Figure 21A 2100 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2100 is shown as a processor according to an exemplary embodiment. Figure 20 Variations of one or more parallel processors 2012 are shown. In at least one embodiment, parallel processor 2100 includes one or more graphics cores 1900.

[0390] In at least one embodiment, parallel processor 2100 includes parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects to other devices using a hub or switch interface (e.g., memory hub 2105). In at least one embodiment, the connection between memory hub 2105 and I / O unit 2104 forms a communication link 2113. In at least one embodiment, I / O unit 2104 is connected to a host interface 2106 and a memory crossbar switch 2116, where host interface 2106 receives commands for performing processing operations and memory crossbar switch 2116 receives commands for performing memory operations.

[0391] In at least one embodiment, when host interface 2106 receives command buffers via I / O unit 2104, host interface 2106 can direct work operations for executing those commands to front end 2108. In at least one embodiment, front end 2108 is coupled with scheduler 2110 (which can be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before assigning tasks to clusters within processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing cluster array 2112. In at least one embodiment, host software can identify workloads for scheduling on processing cluster array 2112 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically distributed across the processing cluster array 2112 by scheduler 2110 logic within a microcontroller that includes scheduler 2110 .

[0392] In at least one embodiment, the processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, each cluster 2114A-2114N in the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may use various scheduling and / or work distribution algorithms to distribute work to the clusters 2114A-2114N in the processing cluster array 2112, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2110 or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N in the processing cluster array 2112 may be assigned to process different types of programs or to perform different types of computations.

[0393] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2112 can include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0394] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2102 may transfer data from system memory via the I / O units 2104 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to the system memory.

[0395] In at least one embodiment, when parallel processing units 2102 are used to perform graphics processing, scheduler 2110 can be configured to divide the processing workload into tasks of approximately equal size to better facilitate the distribution of graphics processing operations to multiple clusters 2114A-2114N in processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2114A-2114N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2114A-2114N for further processing.

[0396] In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be executed via the scheduler 2110, which receives commands defining the processing tasks from the front end 2108. In at least one embodiment, the processing tasks can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2110 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2108. In at least one embodiment, the front end 2108 can be configured to ensure that the processing cluster array 2112 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0397] In at least one embodiment, each of the one or more instances of parallel processing unit 2102 can be coupled to parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing cluster array 2112 and I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which can be coupled to a portion of parallel processor memory 2122 (e.g., a memory unit). In at least one embodiment, the number of partition units 2120A-2120N is configured to be equal to the number of memory cells, such that the first partition unit 2120A has a corresponding first memory cell 2124A, the second partition unit 2120B has a corresponding second memory cell 2124B, and the Nth partition unit 2120N has a corresponding Nth memory cell 2124N. In at least one embodiment, the number of partition units 2120A-2120N may not be equal to the number of memory cells.

[0398] In at least one embodiment, memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write to portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2122. In at least one embodiment, local instances of parallel processor memory 2122 may be eliminated in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0399] In at least one embodiment, any of the clusters 2114A-2114N in the processing cluster array 2112 can process data to be written to any memory unit 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transmit the output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2114A-2114N can communicate with a memory interface 2118 via the memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar switch 2116 has connections to memory interface 2118 for communicating with I / O unit 2104, and connections to local instances of parallel processor memory 2122, which enables processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar switch 2116 can use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0400] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include a higher precision floating point unit than other instances. In at least one embodiment, a system including one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0401] Figure 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is Figure 21A 2120N。In at least one embodiment, the partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and an ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 2116 and the ROP 2126. In at least one embodiment, the L2 cache 2121 outputs read misses and urgent write-back requests to the frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 2125 for processing. In at least one embodiment, the frame buffer interface 2125 communicates with memory units in the parallel processor memory (such as Figure 21A One of the memory units 2124A-2124N (e.g., within parallel processor memory 2122)) is coupled.

[0402] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2126 then outputs the processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data on a per-tile basis.

[0403] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., Figure 21A In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are routed through memory crossbar 2116. In at least one embodiment, the processed graphics data may be displayed on a display device such as a Figure 20 2010), routed by processor 2002 for further processing, or by Figure 21A One of the processing entities within parallel processor 2100 is routed for further processing.

[0404] Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 21A In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0405] In at least one embodiment, the operation of the processing cluster 2114 can be controlled via a pipeline manager 2132 that allocates processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 Figure 21AThe scheduler 2110 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2134 and / or the texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and the data crossbar 2140 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2140.

[0406] In at least one embodiment, each graphics multiprocessor 2134 within a processing cluster 2114 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0407] In at least one embodiment, instructions transmitted to the processing cluster 2114 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2134. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines can be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2134, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 2134.

[0408] In at least one embodiment, the graphics multiprocessor 2134 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 can abandon the internal cache and use cache memory within the processing cluster 2114 (e.g., L1 cache 2148). In at least one embodiment, each graphics multiprocessor 2134 can also access a partition unit (e.g., Figure 21A L2 cache within partition units 2120A-2120N) of the graphics multiprocessor 2134 is shared across all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134, which can share common instructions and data, which can be stored in L1 cache 2148.

[0409] In at least one embodiment, each processing cluster 2114 may include a memory management unit ("MMU") 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside in Figure 21A 2148 . In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2145 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0410] In at least one embodiment, the processing clusters 2114 can be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to a data crossbar 2140 to provide the processed tasks to another processing cluster 2114 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or in system memory via the memory crossbar 2116. In at least one embodiment, a preROP 2142 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2134 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 21A In at least one embodiment, the PreROP 2142 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0411] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 can be used in graphics processing cluster 2114 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0412] In at least one embodiment, parallel processor 2100 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, at least a portion of the system shown in FIG. 21 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 21 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0413] Figure 21D A graphics multiprocessor 2134 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to a pipeline manager 2132 of a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 has an execution pipeline that includes, but is not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166, wherein the one or more load / store units 2166 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU core 2162 and the load / store unit 2166 are coupled to a cache memory 2172 and a shared memory 2170 via a memory and cache interconnect 2168. In at least one embodiment, the GPGPU core 2162 is part of a SoC (such as a processor). Figure 17 a portion of the integrated circuit 1700 in FIG.

[0414] In at least one embodiment, the instruction cache 2152 receives a stream of instructions to be executed from the pipeline manager 2132. In at least one embodiment, the instructions are cached in the instruction cache 2152 and dispatched for execution by the instruction unit 2154. In at least one embodiment, the instruction unit 2154 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2162. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2156 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2166.

[0415] In at least one embodiment, register file 2158 provides a set of registers for the functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands for data paths connected to the functional units of graphics multiprocessor 2134 (e.g., GPGPU core 2162, load / store unit 2166). In at least one embodiment, register file 2158 is divided between each functional unit such that a dedicated portion of register file 2158 is allocated to each functional unit. In at least one embodiment, register file 2158 is divided between different warps (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2134.

[0416] In at least one embodiment, the GPGPU cores 2162 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2134. In at least one embodiment, the architectures of the various GPGPU cores 2162 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 2162 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed-function or special-function logic.

[0417] In at least one embodiment, the GPGPU core 2162 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that implement the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0418] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that allows the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 can operate at the same frequency as the GPGPU core 2162, resulting in very low latency for data transfers between the GPGPU core 2162 and the register file 2158. In at least one embodiment, the shared memory 2170 can be used to facilitate communication between threads executing on the functional units within the graphics multiprocessor 2134. In at least one embodiment, the cache memory 2172 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2136. In at least one embodiment, the shared memory 2170 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2172, threads executing on GPGPU core 2162 may programmatically store data in shared memory.

[0419] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a SoC includes a parallel processor or GPGPU as described herein, wherein the parallel processor or GPGPU executes on the SoC. In at least one embodiment, the GPU can be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0420] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8BDetails are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics multiprocessor 2134 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0421] In at least one embodiment, graphics multiprocessor 2134 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, at least a portion of the system shown in FIG. 21 is used to implement a combination of Figures 1 to 7 For example, in at least one embodiment, at least one component shown or described in connection with FIG. 21 may be used to cause one or more neural networks to use one or more textual descriptions to generate a response based on the response. Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0422] Figure 22A multi-GPU computing system 2200 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 2200 may include a processor 2202 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that couples the processor 2202 to a PCI Express bus, over which the processor 2202 can communicate with the GPGPUs 2206A-D. In at least one embodiment, the GPGPUs 2206A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2216. In at least one embodiment, the GPU-to-GPU links 2216 connect to each of the GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU links 2216 enable direct communication between each of the GPGPUs 2206A-D without requiring communication through the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2216, host interface bus 2204 remains available for system memory access or communication with other instances of multi-GPU computing system 2200, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2206A-D are connected to processor 2202 via host interface switch 2204, in at least one embodiment, processor 2202 includes direct support for P2P GPU link 2216 and can connect directly to GPGPUs 2206A-D. In at least one embodiment, GPGPUs 2206A-D are part of a SoC (such as a Figure 17 ), wherein the GPGPUs 2206A-D perform the operations described herein.

[0423] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in multi-GPU computing system 2200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0424] In at least one embodiment, multi-GPU computing system 2200 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5 ). In at least one embodiment, Figure 22 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 22 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0425] In at least one embodiment, the multi-GPU computing system 2200 can be used to utilize parallel denoising Figures 1 to 7 Diffusion model of dynamic time-varying error threshold in.

[0426] Figure 23 2 is a block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 2300 includes graphics core 1900.

[0427] In at least one embodiment, the graphics processor 2300 receives batches of commands via a ring interconnect 2302. In at least one embodiment, the incoming commands are interpreted by a command streamer 2303 in a pipeline front end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2303 provides the commands to a geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to a video front end 2334, which is coupled to a media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380 .

[0428] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources featuring graphics cores 2380A-2380N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 may have any number of graphics cores 2380A. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each of which includes a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each of the sub-cores 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include shared cache memory and pixel manipulation logic. In at least one embodiment, the graphics processor 2300 includes a load / store unit in the pipeline front end 2304.

[0429] Logic 815 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 8A and / or Figure 8B Details are provided regarding logic 815. In at least one embodiment, logic 815 may be used in graphics processor 2300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0430] In at least one embodiment, graphics processor 2300 may be used to implement system 100 (see Figure 1 ), collage 200 (see Figure 2 ), system 300 (see Figure 3 ), process 400 (see Figure 4 ) and / or process 500 (see Figure 5). In at least one embodiment, Figure 23 At least a portion of the system shown in Figures 1 to 7 For example, in at least one embodiment, in combination with one or more systems, techniques, functions and / or processes described herein, Figure 23 At least one component shown or described can be used to cause one or more neural networks to use one or more text descriptions to generate a response based on a combination of Figures 1 to 7 One or more techniques, functions, and / or processes described in any one of the preceding claims generate one or more 3D models of one or more first objects.

[0431] Figure 24 is a block diagram illustrating a microarchitecture for a processor 2400 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as 64-bit wide MMX registers in microprocessors implemented with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in both integer and floating point formats can operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2400 can execute instructions that accelerate machine learning or deep learning algorithms, training, or reasoning.

[0432] In at least one embodiment, the processor 2400 includes an in-order front end ("front end") 2401 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2401 may include several units. In at least one embodiment, an instruction prefetcher 2426 fetches instructions from memory and feeds the instructions to an instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2428 decodes the received instructions into one or more operations called "micro-operations" or "microinstructions" (also known as "micro ops" or "uops" or "μ-ops") that the machine can execute. In at least one embodiment, the instruction decoder 2428 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2430 can assemble the decoded micro-ops into a program-ordered sequence or trace in the micro-op queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, microcode ROM 2432 provides the micro-ops needed to complete the operation.

[0433] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 2432 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 completes serializing the micro-ops for the instruction, the front end 2401 of the machine may resume fetching micro-ops from the trace cache 2430.

[0434] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2403 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as the instruction flow moves down the pipeline and is scheduled for execution...

Claims

1. A processor, comprising: One or more circuits for causing one or more neural networks to use the one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints.

2. The processor of claim 1 , wherein the one or more neural networks are configured to generate the one or more 3D models based at least in part on the two or more images as a result of being trained based at least in part on the two or more images of the one or more second objects from the two or more viewpoints.

3. The processor of claim 1 , wherein the one or more neural networks are trained based at least in part on one or more loss measures corresponding to a comparison of the 3D models of the one or more second objects from the two or more viewpoints and the two or more images of the one or more second objects.

4. The processor of claim 1 , wherein the two or more images of the one or more second objects from the two or more viewpoints are combined into an image collage for training the one or more neural networks.

5. The processor of claim 1 , wherein the one or more neural networks comprise one or more diffusion models. 6 . The processor of claim 1 , wherein the two or more images of the one or more second objects from the two or more viewpoints are in an image tile used to fine-tune a two-dimensional (2D) diffusion model.

7. The processor of claim 1, wherein the one or more circuits are further configured to refine the one or more 3D models based at least in part on the one or more textual descriptions and the two or more images of the one or more second objects.

8. A system comprising: One or more processors for causing one or more neural networks to use the one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints.

9. The system of claim 8 , wherein the one or more neural networks are configured to generate the one or more 3D models based at least in part on the two or more images as a result of training based at least in part on one or more loss measurements identified by comparing the two or more images of the one or more second objects from the two or more viewpoints and the one or more 3D models generated.

10. The system of claim 8, wherein the one or more neural networks are trained based at least in part on a loss that measures how well the 3D models of the one or more second objects from the two or more viewpoints match the two or more images of the one or more second objects.

11. The system of claim 8, wherein the two or more images of the two or more second objects from the two or more viewpoints are in an image tile used to train the one or more neural networks.

12. The system of claim 8, wherein the one or more neural networks comprise one or more diffusion models.

13. The system of claim 8, wherein the one or more processors randomly samples one or more camera viewpoints with fixed relative angular offsets to generate image collages based on three-dimensional (3D) computer-aided design (CAD) model rendered images for training the one or more neural networks.

14. The system of claim 8, wherein the two or more viewpoints are captured by one or more cameras located at evenly spaced locations.

15. A method comprising: One or more neural networks are used to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints using the one or more textual descriptions.

16. The method of claim 15, further comprising: As a result of training based at least in part on the two or more images of the one or more second objects from the two or more viewpoints, the one or more 3D models are generated based at least in part on the two or more images.

17. The method of claim 15, wherein the one or more neural networks are trained based at least in part on a loss that measures how well the 3D models of the one or more second objects match the two or more images of the one or more second objects from the two or more viewpoints.

18. The method of claim 15, wherein the two or more images of the two or more second objects from the two or more viewpoints are in an image tile used to train the one or more neural networks.

19. The method of claim 15, wherein the one or more neural networks comprises a text-to-image diffusion model.

20. The method of claim 15, wherein the two or more viewpoints are captured by four or more cameras that are evenly spaced apart.

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