Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving circuit and pixels arranged in an array. The driving circuit comprises m shift register units, and the xth shift register unit is electrically connected with at least part of pixels in the xth row; each shift register unit is used for outputting a gate driving signal according to the first type of clock signal, the second type of clock signal and an input signal; the shift register units form n shift register unit groups; the shift register units in the same shift register unit group are cascaded with each other; in the same shift register unit group, the first-stage shift register unit receives a starting signal, and the starting signals received by the shift register unit groups are different; the driving period of the display panel comprises n touch stages, and the yth touch stage is located after the grid driving signal output effective level of the last-stage shift register unit in the yth shift register unit group and before the starting signal output effective level received by the (y + 1) th shift register unit group.

Description

Technical Field

[0001] The present invention relates to the field of display, and in particular to a display panel and a display device. Background Art

[0002] Current display panels typically randomly insert touch phases into the display phase of each display frame to ensure timely response to touch operations. During the touch phase, the shift register in the driver circuit that should currently be outputting scan signals pauses, causing all shift register units to pause. After the touch phase completes, the current shift register resumes outputting scan signals, allowing subsequent shift registers in the cascade to sequentially output scan signals.

[0003] However, since the shift register that pauses outputting the scanning signal during the touch phase is interrupted, the components therein will experience severe characteristic drift, causing the output scanning signal to be inaccurate and deformed, resulting in visible light / dark horizontal stripes on the display screen. Summary of the Invention

[0004] The present invention provides a display panel and a display device to solve the problem of visible bright / dark horizontal stripes on a display screen due to an inserted touch stage, thereby improving the display effect.

[0005] The present invention provides a display panel, comprising: a driving circuit and pixels arranged in an array;

[0006] The driving circuit includes m shift register units, wherein the xth shift register unit is electrically connected to at least part of the pixels in the xth row;

[0007] The shift register unit includes a signal input terminal, a first clock terminal, a second clock terminal and a signal output terminal; the first clock terminal is used to receive a first type of clock signal, and the second clock terminal is used to receive a second type of clock signal; each shift register unit is used to output a gate drive signal according to the first type of clock signal, the second type of clock signal and the input signal of the signal input terminal;

[0008] m shift register units constitute n shift register unit groups; the shift register units in the same shift register unit group are cascaded; in the same shift register unit group, the first-stage shift register unit receives a start signal, and the start signals received by each shift register unit group are different;

[0009] The driving cycle of the display panel includes n touch control phases, wherein the yth touch control phase is located after the gate driving signal of the last shift register unit in the yth shift register unit group outputs a valid level and before the start signal received by the y+1th shift register unit group outputs a valid level;

[0010] Among them, m, n, x, and y are all positive integers, x≤m, n≤m, y≤n.

[0011] Based on the same inventive concept, the present invention further provides a display device including the display panel of the present invention.

[0012] The display panel provided by the present invention includes: a driving circuit and pixels arranged in an array; the driving circuit includes m shift register units, and in each shift register unit, the xth shift register unit is electrically connected to at least part of the pixels in the xth row; the shift register unit includes a signal input terminal, a first clock terminal, a second clock terminal and a signal output terminal; the first clock terminal is used to receive a first type of clock signal, and the second clock terminal is used to receive a second type of clock signal; each shift register unit is used to output a gate drive signal based on the first type of clock signal, the second type of clock signal and the input signal of the signal input terminal; the m shift register units constitute n shift registers Register unit group; the shift register units located in the same shift register unit group are cascaded with each other; in the same shift register unit group, the first-stage shift register unit receives a start signal, and the start signals received by each shift register unit group are different; the driving cycle of the display panel includes n touch phases, the yth touch phase is located after the gate drive signal of the last-stage shift register unit in the yth shift register unit group outputs a valid level, and before the start signal received by the y+1th shift register unit group outputs a valid level; wherein m, n, x, and y are all positive integers, x≤m, n≤m, and y≤n. The present invention configures n shift register groups by arranging m shift register units in a shift register circuit, so that the shift register units in the same shift register group are cascaded with each other, so that the shift register units in the same shift register group can sequentially output the effective level of the gate drive signal. By setting different start signals received by different shift register groups, the effective levels of the start signals received by different shift register groups can have a controllable time interval. By setting a drive cycle of the display panel to include n touch stages, the yth touch stage is located between the gate drive signal output effective level of the last shift register unit in the yth shift register group. After the touch stage, and before the start signal received by the y+1th shift register unit group outputs the valid level, the shift register unit group receives the valid level of the input signal after the touch stage is completed, so that the valid level of the input signal will not be stored for a long time in the first-stage shift register unit of the shift register unit group, so that the characteristics of the devices therein will not be shifted due to long-term bias, which can improve the accuracy and stability of the gate drive signal output after the touch stage. When the shift register units of each level are cascaded in sequence, the accuracy of the gate drive signal output by the shift register units of each level after the touch stage can also be improved, thereby effectively improving the display effect of the display panel.

[0013] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a schematic structural diagram of a display panel in the prior art;

[0016] Figure 2 This is a driving timing diagram of a driving circuit in the prior art;

[0017] Figure 3 This is a schematic structural diagram of a display panel provided by the present invention;

[0018] Figure 4 is a structural schematic diagram of another display panel provided by the present invention;

[0019] Figure 5 This is a driving timing diagram of a driving circuit provided by the present invention.

[0020] Figure 6 This is a driving timing diagram of another driving circuit provided by the present invention;

[0021] Figure 7 This is a structural diagram of another display panel provided by the present invention;

[0022] Figure 8 This is a driving timing diagram of another driving circuit provided by the present invention;

[0023] Figure 9 This is a schematic structural diagram of another display panel provided by the present invention;

[0024] Figure 10 This is a driving timing diagram of another driving circuit provided by the present invention;

[0025] Figure 11 and Figure 12 This is a driving timing diagram of another driving circuit provided by the present invention;

[0026] Figure 13 and Figure 14 This is a driving timing diagram of another driving circuit provided by the present invention;

[0027] Figure 15 and Figure 16 This is a schematic structural diagram of another display panel provided by the present invention;

[0028] Figure 17 and Figure 18 This is a driving timing diagram of another driving circuit provided by the present invention;

[0029] Figure 19 It is a structural schematic diagram of a display device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] As described in the background technology, Figure 1 This is a schematic diagram of the structure of a display panel in the prior art. Figure 2 This is a driving timing diagram of a driving circuit in the prior art. Figure 1 and Figure 2The display panel 100′ includes a driving circuit 10′ and pixels 20′. The driving circuit 10′ includes n stages of cascaded shift register units G′ (G(1)′, G(2)′, …, G(m-1)′, G(m)′, …, G(m+1)′, G(n)′). The input end of the first stage shift register unit G(1)′ is electrically connected to the start signal end STV′ to receive the start signal stv′. In the other stages of the shift register units G′, the gate drive signal of the previous stage shift register unit G′ is the input signal of the next stage shift register unit G′. The output end of each stage shift register unit G′ is electrically connected to the scan signal line SCAN′ in a one-to-one correspondence. By outputting the enable level of the gate drive signal to each scan signal line SCAN′ in turn, the row-by-row scanning function of each pixel 20′ in the display panel is realized, so that the display panel 100′ presents a corresponding display screen. After the gate drive signals Gout(1)′, Gout(2)′, ..., Gout(m-1)′ of the first-stage shift register unit G1′ to the m-1-stage shift register unit G(m-1)′ sequentially output valid levels, the touch stage TP′ is inserted. At this time, the m-stage shift register unit G(m)′ stops outputting the valid level of the gate drive signal Gout(m)′ until the touch stage TP′ is completed. The m-stage shift register unit G(m)′ continues to output the valid level of the gate drive signal Gout(m)′, so that the gate drive signals Gout(m+1)′, ..., Gout(n)′ of each subsequent stage shift register unit G(m+1)′, ..., G(n)′ all output valid levels in sequence.

[0033] However, the gate drive signal Gout(m-1)′ of the m-1th shift register unit G(m-1)′, as the input signal of the m-th shift register unit G(m)′, has been input into the m-th shift register unit G(m)′ for storage in the ta′ stage, so that the device in the m-th shift register unit G(m)′ is in a biased state for a long time in the touch stage TP′ and a characteristic offset occurs. As a result, when the m-th shift register unit G(m)′ resumes the working state and outputs the effective level of the gate drive signal Gout(m)′, the output gate drive signal Gout(m)′ is inaccurate. When the gate drive signal Gout(m)′ is output to the pixel 20′, at least part of the pixels 20′ in the row cannot be displayed normally, thereby causing the display screen to produce dark horizontal lines visible to the human eye, affecting the display effect of the display panel.

[0034] In order to solve the above technical problems, an embodiment of the present invention provides a display panel, comprising: a driving circuit and pixels arranged in an array; the driving circuit comprises m shift register units, and in each shift register unit, the xth shift register unit is electrically connected to at least part of the pixels in the xth row; the shift register unit comprises a signal input terminal, a first clock terminal, a second clock terminal and a signal output terminal; the first clock terminal is used to receive a first type of clock signal, and the second clock terminal is used to receive a second type of clock signal; each shift register unit is used to output a gate drive signal according to the first clock signal, the second clock signal and the input signal of the signal input terminal; the m shift register units The touch display panel is characterized in that the touch display panel comprises n shift register unit groups, wherein the first-stage shift register unit in the same shift register unit group receives a start signal, and the start signals received by the first-stage shift register unit in the same shift register unit group are different. The touch display panel comprises n touch phases, and the yth touch phase is located after the gate drive signal of the last-stage shift register unit in the yth shift register unit group outputs a valid level and before the start signal received by the y+1th shift register unit group outputs a valid level. wherein m, n, x, and y are all positive integers, and x≤m, n≤m, and y≤n.

[0035] By adopting the above technical solution, by setting the xth shift register unit among the m shift register units to be electrically connected to at least part of the pixels in the xth row, each shift register unit can be connected to the pixels in each row in sequence. By setting the shift register unit to receive the first type of clock signal and the second type of clock signal, the shift register unit can output a gate drive signal according to the first type of clock signal, the second type of clock signal and the input signal of the signal input terminal. By setting the m shift register units in the shift register circuit to form n shift register unit groups, the shift register units located in the same shift register unit group can be cascaded with each other, so that the shift register units located in the same shift register unit group can output the effective level of the gate drive signal in sequence. By setting different shift register unit groups to receive different start signals, the effective levels of the start signals received by different shift register unit groups can be controllable. By setting the driving cycle of the display panel to include n touch stages, the yth touch stage is located after the gate drive signal of the last shift register unit in the yth shift register unit group outputs a valid level and before the start signal received by the y+1th shift register unit group outputs a valid level, so that the shift register unit group receives the valid level of the input signal after the touch stage is completed, so that the valid level of the input signal is not stored for a long time in the first shift register unit of the shift register unit group, so that the characteristics of the devices therein are not shifted due to long-term bias, and the accuracy and stability of the gate drive signal output after the touch stage can be improved. When the shift register units of each stage are cascaded in sequence, the accuracy of the gate drive signal output by the shift register units of each stage after the touch stage can also be improved, thereby effectively improving the display effect of the display panel.

[0036] The above is the core concept of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without inventive work are within the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings.

[0037] Optional, Figure 3 is a structural schematic diagram of a display panel provided by the present invention, Figure 4 is a schematic structural diagram of another display panel provided by the present invention, Figure 5 This is a driving timing diagram of a driving circuit provided by the present invention. Figure 6 This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figures 3 to 6The display panel 100 includes: a driving circuit 10 and pixels 20 arranged in an array, in each shift register unit G, the xth shift register unit G(x) is electrically connected to at least part of the pixels 20 in the xth row; the driving circuit 10 includes m stages of shift register units G; the shift register unit G includes a signal input terminal IN, a first clock terminal CK1, a second clock terminal CK2 and a signal output terminal GOUT; the first clock terminal CK1 is used to receive a first type of clock signal cka, and the second clock terminal CK2 is used to receive a second type of clock signal ckb; each shift register unit G is used to output a gate drive signal Gout according to the first type of clock signal cka, the second type of clock signal ckb and the input signal of the signal input terminal IN; m shift registers The memory units G constitute n shift register unit groups B; the shift register units G in the same shift register unit group B are cascaded with each other; in the same shift register unit group 11, the first-stage shift register unit G receives the start signal Stv, and the start signal stv received by each shift register unit group B is different; the driving cycle T0 of the display panel 100 includes n touch phases TP, the yth touch phase TP is located after the gate drive signal Gout of the last stage shift register unit G in the yth shift register unit group B outputs a valid level, and before the start signal Stv received by the y+1th shift register unit group G outputs a valid level; wherein m, n, x, and y are all positive integers, x≤m, n≤m, and y≤n.

[0038] Specifically, among the pixels 20 arranged in the array, at least some of the pixels 20 in the same row can be configured to receive the same gate drive signal Gout, so that each shift register unit G can drive the pixels 20 in the same row. Figure 3 and Figure 4 The example in FIG. 1 shows a case where all pixels 20 in the same row receive the same gate drive signal Gout. In other feasible embodiments of the present invention, it is also possible to configure a portion of the pixels 20 in the same row to receive the same gate drive signal Gout, and this embodiment of the present invention is not specifically limited to this. In each shift register unit G, the x-th shift register unit G(x) is electrically connected to at least a portion of the pixels 20 in the x-th row, so that each shift register unit G is sequentially connected to the pixels 20 in each row.

[0039] Exemplary, reference Figure 3 or Figure 4The display panel 100 includes a display area A1 and a non-display area A2 surrounding the display area A1; the driving circuit 10 is located in the non-display area A2; in the display area A1, the display panel 100 further includes a plurality of scanning signal lines LG extending along a first direction X and arranged along a second direction Y, and at least part of the pixels 20 in the same row share one scanning signal line LG; the scanning signal line LG is used to transmit a gate driving signal Gout; among the m shift register units G, the x-th shift register unit G(x) is electrically connected to the x-th scanning signal line LG along the second direction Y.

[0040] Specifically, the driving circuit 10 can be disposed in the non-display area A2 without occupying space in the display area A1, thereby facilitating ensuring the pixel density of the display area A1 and improving the display effect of the display panel 100. At least some of the pixels 20 in the same row are electrically connected to the same scan signal line LG, so that each shift register unit G can drive the pixels 20 in the same row. Figure 3 and Figure 4 The example in the figure shows that all pixels 20 in the same row are electrically connected to the same scan signal line LG. In other feasible embodiments of the present invention, it is also possible to set that some pixels 20 in the same row are electrically connected to the same scan signal line LG. The embodiment of the present invention is not specifically limited to this. Among the m shift register units G, the x-th shift register unit G(x) is electrically connected to the x-th scan signal line LG along the second direction Y. Then, the x-th shift register unit G(x) can drive the pixels 20 in the x-th row, so that each shift register unit G is corresponding to each row of pixels 20.

[0041] The driving circuit 10 can include a total of m levels of shift register units G. Assume that the m levels of shift register units G are, in sequence, the first shift register unit G(1), the second shift register unit G(2), ..., the i-th shift register unit G(i), the i+1-th shift register unit G(i+1), the i+2-th shift register unit G(i+2), ..., the m-1-th shift register unit G(m-1) and the m-th shift register unit G(m). The shift register units G at each level can be electrically connected to each row of pixels 20 in sequence through the scanning signal line LG to provide a gate driving signal Gout to each row of pixels 20 respectively.

[0042] The display panel 100 may further include multiple clock signal lines to provide a first-type clock signal cka and a second-type clock signal ckb to each shift register unit, respectively. The first-type clock signal cka is the clock signal received by the first clock terminal CK1 of each shift register unit G, and the second-type clock signal ckb is the clock signal received by the second clock terminal CK2 of each shift register unit G. The first-type clock signal cka and the second-type clock signal ckb may have different transition states, i.e., when the first-type clock signal cka is high, the second-type clock signal ckb is low, and vice versa. Each shift register unit G may output a corresponding gate drive signal Gout under the control of the first-type clock signal cka, the second-type clock signal ckb, and the input signal.

[0043] Illustratively, in the same shift register unit group B, the first clock signal terminal CK1 of each shift register unit G receives the same first-type clock signal cka, and the second clock signal terminal CK2 of each shift register unit receives the same second-type clock signal ckb.

[0044] Specifically, the first clock end CK1 of each shift register unit G located in the same shift register unit group B is electrically connected to the same clock signal line for transmitting the first type of clock signal cka to receive the same first type of clock signal cka, and the second clock end CK2 of each shift register unit G located in the same shift register unit group B is electrically connected to the same clock signal line for transmitting the second type of clock signal ckb to receive the same second type of clock signal ckb, so that each shift register unit G can output the gate drive signal Gout under the drive of the first type of clock signal cka, the second type of clock signal ckb and the input signal.

[0045] For example, reference Figure 3 or Figure 4Corresponding to the two groups of shift register unit groups B, the display panel 100 may include two clock signal lines (a first clock signal line Ck1 and a third clock signal line Ck3) for transmitting the first type of clock signal cka, and two clock signal lines (a second clock signal line Ck2 and a fourth clock signal line Ck4) for transmitting the second type of clock signal ck2. The first clock signal line Ck1 is electrically connected to the first clock end CK1 of each shift register unit G in the first shift register unit group B1 to provide the first clock signal ck1 to each shift register unit G, so that the first clock signal ck1 is the first type of clock signal cka of each shift register unit G in the first shift register unit group B1; the second clock signal line Ck2 is electrically connected to the second clock end CK2 of each shift register unit G in the first shift register unit group B1 to provide the second clock signal ck2 to each shift register unit G, so that the second clock signal ck2 is the second type of clock signal ckb of each shift register unit G in the first shift register unit group B1; then, each shift register unit G in the first shift register unit group B1 can output the gate drive signal Gout under the drive of the first clock signal ck1, the second clock signal ck2 and the input signal. The third clock signal line Ck3 is electrically connected to the first clock terminal CK1 of each shift register unit G in the second shift register unit group B2 to provide a third clock signal ck3 to each shift register unit G, such that the third clock signal ck3 serves as the first-type clock signal cka for each shift register unit G in the second shift register unit group B2. The fourth clock signal line Ck4 is electrically connected to the second clock terminal CK2 of each shift register unit G in the second shift register unit group B2 to provide a fourth clock signal ck4 to each shift register unit G, such that the fourth clock signal ck4 serves as the second-type clock signal ckb for each shift register unit G in the second shift register unit group B2. This enables each shift register unit G in the second shift register unit group B2 to output a gate drive signal Gout driven by the first clock signal ck1, the second clock signal ck2, and the input signal. Consequently, each shift register unit G in the second shift register unit group B2 can output a gate drive signal Gout driven by the third clock signal ck3, the fourth clock signal ck4, and the input signal.

[0046] The m shift register units G can be divided into n shift register unit groups B, such that the shift register units G in the same shift register unit group B are cascaded, while the shift register units G in different shift register unit groups B do not affect each other. In the same shift register unit group B, the signal input terminal IN of the first-stage shift register unit G is electrically connected to the start signal terminal STV to receive the start signal stv provided by the start signal terminal STV. In each subsequent-stage shift register unit G, the signal input terminal IN of the subsequent-stage shift register unit G is electrically connected to the signal output terminal GOUT of the previous-stage shift register unit G, such that the gate drive signal Gout of the previous-stage shift register unit G serves as the input signal of the subsequent-stage shift register unit G. When the gate drive signal Gout of the previous-stage shift register unit G includes a valid level, the subsequent-stage shift register unit G can be driven, so that the gate drive signal Gout output by the subsequent-stage shift register unit G includes a valid level.

[0047] Different shift register unit groups B receive different start signals stv, and the time for each start signal stv to output a valid level can be set according to the time length of the touch stage TP, so that each shift register unit G in different shift register unit groups B can output the valid level of the gate drive signal Gout in a time-sharing manner. When realizing a global scan of each row of pixels 20, the effective levels of the gate drive signal Gout output by different shift register unit groups B can have a controllable time interval.

[0048] Exemplary, with reference to Figure 3 and Figure 5 , the effective level of the gate driving signal Gout of the m-stage shift register unit G is shifted in sequence; the adjacent k-stage shift register units G constitute a shift register unit group B; k is a positive integer and 1<k<m.

[0049] Specifically, the first shift register unit G(1) to the kth shift register unit G(k) may be configured to form a shift register unit group B (i.e., a first shift register unit group B1), and the k+1th shift register unit G(k+1) to the mth shift register unit G(m) may be configured to form a shift register unit group B (i.e., a second shift register unit group B2). The number of shift register units G in different shift register unit groups B may be the same or different. For ease of description, the embodiment of the present invention takes the case where the number of shift register units G in different shift register unit groups B is the same as an example to exemplify the technical solution of the present invention, where m=2*k. In the first shift register unit group B1, the signal input terminal IN of the first shift register unit group G(1) is electrically connected to the first start signal terminal STV1 to receive the first start signal stv1, and, in the second shift register unit G(2) to the i-th shift register unit G(i), the signal input terminal IN of the subsequent shift register unit G is electrically connected to the signal output terminal GOUT of the previous shift register unit G, so that the first shift register unit group G(1) to the i-th shift register unit G(i) are cascaded in sequence. In the second shift register unit group B2, the signal input terminal IN of the k+1th shift register unit G(k+1) is electrically connected to the second start signal terminal STV2 to receive the second start signal stv2, and, in the k+2th shift register unit G(k+2) to the mth shift register unit G(m), the signal input terminal IN of the next-stage shift register unit G is electrically connected to the signal output terminal GOUT of the previous-stage shift register unit G, so that the k+1th shift register unit G(k+1) to the mth shift register unit G(m) are cascaded in sequence. Partition scanning of the display area A1 can be achieved, and by setting the time when the second start signal stv2 outputs the effective level, the time when the k+1th shift register unit G(k+1) outputs the effective level of the gate drive signal Gout(k+1) and the time when the kth shift register unit G(k) outputs the effective level of the gate drive signal Gout(k) have a certain time interval. At the same time, the input signal received by the k+1th shift register unit G(k+1), that is, the second start signal stv2, will not be stored for a long time, which can avoid the long-term bias of the devices therein, thereby improving the accuracy of the gate drive signal Gout(k+1) output by the k+1th shift register unit G(k+1). When the k+1th shift register unit G(k+1) is cascaded with the subsequent shift register units G in sequence, the accuracy of the gate drive signal Gout output by each shift register unit G in the second shift register unit group B2 can be improved, thereby improving the display effect of the display panel 100.

[0050] Or, as Figure 4As shown, among the m shift register units, the signal input terminals IN of the first n shift register units G receive the start signal stv, and the start signals stv received by the first n shift register units G are different; and, among the m shift register units G, the output terminal of the i-th shift register unit G is electrically connected to the signal input terminal IN of the i+n-th shift register unit G(i+n).

[0051] Specifically, the signal input terminals IN of the first n shift register units G are set to receive different start signals stv, and the first n shift register units G can be respectively the first-stage shift register units G of the n shift register unit groups B, and can provide input signals to the subsequent-stage shift register units G cascaded therewith while outputting the gate drive signal Gout to the corresponding pixel 20, so that the shift register units G at each stage in the same shift register unit group B output the effective level of the gate drive signal Gout in sequence.

[0052] For example, n can be set to an even number, so that the odd-numbered shift register units G connected to the pixels 20 in each odd row constitute at least one shift register unit group B, and the even-numbered shift register units G connected to the pixels 20 in each even row constitute at least one shift register unit group B.

[0053] refer to Figure 4When n=2, the first shift register unit G(1) is electrically connected to the first start signal terminal STV1 to receive the first start signal stv1, the signal input terminal IN of the third shift register unit G(3) is electrically connected to the signal output terminal GOUT of the first shift register unit G(1), and so on, until the signal input terminal IN of the m-1th shift register unit G(m-1) is electrically connected to the signal output terminal GOUT of the m-3th shift register unit G(m-3), so that each odd-numbered shift register unit G constitutes a shift register unit group B, that is, the first shift register unit G(1), the third shift register unit G(3), the fifth shift register unit G(3), ..., the m-1th shift register unit G(m-1) constitute the first shift register unit group B1. Furthermore, the second shift register unit G(2) is electrically connected to the second start signal terminal STV2 to receive the second start signal stv2, the signal input terminal IN of the fourth shift register unit G(4) is electrically connected to the signal output terminal GOUT of the second shift register unit G(2), and so on, until the signal input terminal IN of the m-th shift register unit G(m) is electrically connected to the signal output terminal GOUT of the m-th shift register unit G(m-2), so that each even-numbered shift register unit G constitutes a shift register unit group B, that is, the second shift register unit G(2), the fourth shift register unit G(4), the sixth shift register unit G(6), ..., the m-th shift register unit G(m) constitute a second shift register unit group B2. In this way, a shift register unit group B can be used to perform interlaced global scanning of the pixels 20 in the display area A1. When the scanning drive of the two shift register unit groups B is set to have a time interval, that is, after the m-1th shift register unit G(m-1) in the first shift register unit group B outputs the gate drive signal Gout(m-1) at an effective level, the second start signal stv2 is output at an effective level after a period of time. In this case, the display panel will not have obvious partitioned display phenomenon, which can further improve the display effect of the display panel. In this embodiment, it is preferred that the number of shift register units G in different shift register unit groups B is the same, that is, m can be set to an even number.

[0054] Combined with reference Figure 3 and Figure 5 , or combined with reference Figure 4 or Figure 6, corresponding to the number n of shift register unit groups B, a driving cycle T0 of the display panel 100 can be set to include n touch phases. The driving cycle T0 can be understood as the time taken for all shift register units G to output the effective level of the gate driving signal Gout and complete the drive refresh of all rows of pixels 20. Among them, the y-th touch phase TP is set to be located after the gate driving signal Gout of the last shift register unit G in the y-th shift register unit group B outputs the effective level, and before the start signal Stv received by the y+1-th shift register unit G group outputs the effective level. This can make the touch phase TP located between the time intervals between the outputs of the gate driving signal Gout by two adjacent shift register unit groups B, and after the completion of the current touch phase TP, the start signal stv received by each shift register unit G of the next shift register unit group B is made to output the effective level, thereby avoiding the first shift register unit in the shift register unit group B that works after the touch phase TP. The input signal received by the unit G is stored for a long time, which can prevent the devices therein from being in a biased state for a long time during the touch phase TP due to the early writing of the input signal. After the touch phase TP is completed, a stable and accurate gate drive signal Gout can be output, thereby realizing the drive control of the connected pixels 20, so that the row of pixels 20 can be displayed normally without the phenomenon of dark lines and horizontal stripes, thereby effectively improving the display effect. In addition, when the first-stage shift register unit G and the subsequent shift register units G are cascaded in sequence, the accuracy of the gate drive signal Gout output by the subsequent shift register units G can be improved, thereby further improving the display effect of the display panel 100.

[0055] For example, combined with reference Figure 3 and Figure 5, after the last - stage shift register cell G in the first shift - register cell group B1, that is, the i - th shift register cell G(i) outputs the effective level of the gate driving signal Gout in the t01 stage, insert the first touch stage TP1. After the first touch stage TP1 is completed, the second start signal stv2 received by the first - stage shift register cell G (i.e., the (i + 1)-th shift register cell G(i + 1)) in the second shift - register cell group B2 outputs the effective level in the t02 stage, making the first touch stage TP1 located between the t01 stage and the t02 stage, and making the second start signal stv2 output the effective level after the first touch stage TP1 is completed. Thus, the effective level of the input signal of the (i + 1)-th shift register cell G(i + 1) will not be stored for a long time, so that the situation where the device characteristics shift due to long - term biasing will not occur, which can improve the accuracy and stability of the gate driving signal Gout output by the (i + 1)-th shift register cell G(i + 1). When the (i + 1)-th shift register cell G(i + 1) is cascaded with the subsequent shift register cells G in sequence, it can also improve the accuracy of the gate driving signal Gout output by each stage of the shift register cells G in the second shift - register cell group B2, thereby effectively improving the display effect of the display panel 100. Similarly, the second touch stage TP2 is located after the last - stage shift register cell G (i.e., the eighth shift register cell G(8)) outputs the effective level of the gate driving signal Gout(8) in the t03 stage. After the current touch stage TP2 is completed, a driving cycle T0 of the driving circuit is completed. And, it can be determined that the last - stage shift register cell G of the second shift - register cell group B2 is the eighth shift register cell G(8) by m - n + j = 8 - 2+2 = 8.

[0056] Similarly, referring to Figure 4 and Figure 6 , the j - th touch stage TP is located after the gate driving signal Gout of the (m - n + j)-th shift register cell G outputs the effective level and before the start signal stv received by the (j + 1)-th shift register cell G outputs the effective level; where i and j are both positive integers, i ≤ m, and j < n. Then the (m - n + j)-th shift register cell G is the last - stage shift register cell G in a shift - register cell group B, in order to Figure 4For example, assuming m=8 and n=2, the first two shift register units G receive the start signal stv, that is, the first shift register unit G(1) receives the first start signal stv1, and the second shift register unit G(2) receives the second start signal stv2. The first touch phase TP1 (i.e., j=1) is located after the seventh shift register unit G(7) outputs the valid level of the gate drive signal Gout at the t11 stage, and after the first touch phase TP1 is completed, the first stage shift register unit G in the second shift register unit group B2 receives the second start signal stv2 which outputs the valid level at the t12 stage. Among them, the last stage shift register unit G of the first shift register unit group B1 can be determined to be the seventh shift register unit G(7) by m-n+j=8-2+1=7, and the first stage shift register unit G in the second shift register unit group B2 can be determined to be the second shift register unit G(2) by j+1=1+1=2. In this way, the first touch phase TP1 is located between the phases t11 and t12, and the second start signal stv2 outputs a valid level after the first touch phase TP1 is completed, so that the valid level of the input signal received by the second shift register unit G(2) will not be stored in the second shift register unit G(2) for a long time, so that the device therein will not have a characteristic shift due to long-term bias, which can improve the accuracy and stability of the gate drive signal Gout output by the second-stage shift register unit G(2). When the second shift register unit G(2) is cascaded with the even-numbered shift register units G of the subsequent stage, the accuracy of the gate drive signal Gout output by each stage of the shift register unit G in the second shift register unit group B2 can also be improved, thereby effectively improving the display effect of the display panel 100. Similarly, the second touch phase TP2 occurs after the last shift register unit G (i.e., the eighth shift register unit G(8)) outputs the gate drive signal Gout(8) at the valid level at phase t13. After the current touch phase TP2 is completed, one drive cycle T0 of the drive circuit is completed. Furthermore, m-n+j=8-2+2=8 can be used to determine that the last shift register unit G of the second shift register group B2 is the eighth shift register unit G(8).

[0057] Understandably, Figure 3 and Figure 4 The example shown in the figure is n=2, that is, each shift register unit G is divided into two groups. In other feasible embodiments of the present invention, n≥2 can be set to facilitate inserting more touch phases TP. The embodiment of the present invention does not make any specific limitation on this.

[0058] It can also be understood that the embodiment of the present invention is illustratively described by taking the effective level of the gate drive signal Gout as a high level and the invalid level as a low level as an example. In other feasible embodiments of the present invention, the effective level of the gate drive signal Gout can also be set to a low level and the invalid level to a high level. The embodiment of the present invention does not specifically limit this.

[0059] In addition, in the display area A1, the display panel 100 may further include a plurality of data signal lines LD. At least some of the pixels 20 in the same column are electrically connected to the same data signal line LD, so that one data signal line LD can provide a data signal to the pixels 20 in the same column. In one embodiment, when the gate drive signal Gout provided to the pixel 20 is at an active level, the data signal can be written to the pixel 20, causing the pixel to display according to the data signal.

[0060] In a display panel provided by an embodiment of the present invention, by arranging that the xth shift register unit among m shift register units is electrically connected to at least part of the pixels in the xth row, each shift register unit can be sequentially connected to the pixels in each row, and by arranging that the shift register unit receives a first type of clock signal and a second type of clock signal, the shift register unit can output a gate drive signal according to the first type of clock signal, the second type of clock signal, and the input signal of the signal input terminal. By arranging that the m shift register units in the shift register circuit constitute n shift register unit groups, each shift register unit in the same shift register unit group can be cascaded with each other, and each shift register unit in the same shift register unit group can sequentially output the effective level of the gate drive signal. By setting different shift register unit groups to receive different start signals, the effective levels of the start signals received by different shift register unit groups can be made to have different values. A controllable time interval is provided. By setting a drive cycle of the display panel to include n touch phases, the yth touch phase is located after the gate drive signal of the last shift register unit in the yth shift register unit group outputs a valid level and before the start signal received by the y+1th shift register unit group outputs a valid level. This allows the shift register unit group to receive the valid level of the input signal after the touch phase is completed, so that the valid level of the input signal will not be stored for a long time in the first shift register unit of the shift register unit group, thereby preventing the characteristics of the devices therein from shifting due to long-term bias. This can improve the accuracy and stability of the gate drive signal output after the touch phase. When the shift register units of each level are cascaded in sequence, the accuracy of the gate drive signal output by the shift register units of each level after the touch phase can also be improved, thereby effectively improving the display effect of the display panel.

[0061] Optional, Figure 7 is a structural diagram of another display panel provided by an embodiment of the present invention. Figure 8is a driving timing diagram of another driving circuit provided by an embodiment of the present invention. Figure 9 is a structural diagram of another display panel provided by an embodiment of the present invention. Figure 10 This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figure 7 and Figure 8 , or combined with reference Figure 9 and Figure 10 , along the first direction X, the non-display area A2 includes a first non-display sub-area A21 and a second non-display sub-area A22 located on opposite sides of the display area A1; the effective levels of the start signal stv received by the two adjacent shift register unit groups B along the second direction Y are shifted in sequence, and, the two adjacent shift register unit groups B along the second direction Y are respectively located in the first non-display sub-area A21 and the second non-display sub-area A22.

[0062] Specifically, by configuring the non-display area A2 to include a first non-display sub-area A21 and a second non-display sub-area A22 located on opposite sides of the display area A1 along the first direction X, the shift register units m can be dispersed in the first non-display sub-area A21 and the second non-display sub-area A22, facilitating a symmetrical design of the display panel 100. The effective levels of the start signal stv received by two adjacent shift register unit groups B along the second direction Y are sequentially shifted. That is, the two adjacent shift register unit groups B along the second direction Y are shift register unit groups B operating before and after the same touch phase TP, respectively. By configuring the two adjacent shift register unit groups B along the second direction Y to be located in the first non-display sub-area A21 and the second non-display sub-area A22, respectively, the shift register units G can be distributed as evenly as possible in the non-display area A2, facilitating an aesthetically pleasing design of the display panel 100.

[0063] For ease of understanding, Figure 7 and Figure 8By way of example, m=12, n=4 is shown, that is, the driving circuit 10 includes 12 shift register units G, and the 12 shift register units G are divided into 4 shift register unit groups B, but the present invention is not limited thereto. Among them, corresponding to the third shift register unit group B3, the non-display area A2 of the display panel 100 also includes a fifth clock signal line Ck5 for transmitting a fifth clock signal ck5, and a sixth clock signal line Ck6 for transmitting a sixth clock signal ck6, the first clock terminal CK1 of each shift register unit G in the third shift register unit group B3 is electrically connected to the fifth clock signal line Ck5, and the second clock terminal CK2 of each shift register unit G in the third shift register unit group B3 is electrically connected to the sixth clock signal line Ck6; corresponding to the fourth shift register unit group B4, the non-display area A2 of the display panel 100 also includes a seventh clock signal line Ck7 for transmitting a seventh clock signal ck7, and an eighth clock signal line Ck8 for transmitting an eighth clock signal ck8, the first clock terminal CK1 of each shift register unit G in the fourth shift register unit group B4 is electrically connected to the seventh clock signal line Ck7, and the second clock terminal CK2 of each shift register unit G in the fourth shift register unit group B4 is electrically connected to the eighth clock signal line Ck8.

[0064] refer to Figure 7 Each shift register unit group B includes three shift register units G, wherein the first shift register unit G(1) is electrically connected to the first start signal terminal STV1 to receive the first start signal stv1, and the first shift register unit G(1), the second shift register unit G(2) and the third shift register unit G(3) are sequentially cascaded to form the first shift register unit group B1. The fourth shift register unit G(4) is electrically connected to the second start signal terminal STV2 to receive the second start signal stv2, and the fourth shift register unit G(4), the fifth shift register unit G(5) and the sixth shift register unit G(6) are sequentially cascaded to form the second shift register unit group B2. The signal input terminal IN of the seventh shift register unit G(7) is electrically connected to the third start signal terminal STV3 to receive the third start signal stv3, and the seventh shift register unit G(7), the eighth shift register unit G(8) and the ninth shift register unit G(9) are sequentially cascaded to form a third shift register unit group B3. The signal input terminal IN of the tenth shift register unit G(10) is electrically connected to the fourth start signal terminal STV4 to receive the fourth start signal stv4, and the tenth shift register unit G(10), the eleventh shift register unit G(11) and the twelfth shift register unit G(12) are sequentially cascaded to form a fourth shift register unit group B4. Figure 7 and Figure 8The effective levels of the first start signal stv1, the second start signal stv2, the third start signal stv3, and the fourth start signal stv4 are shifted in sequence, so that each shift register unit G can scan the pixels 20 row by row. By arranging the first shift register unit group B1 and the third shift register unit group B3 in the same non-display sub-area (for example, the first non-display sub-area A21), and arranging the second shift register unit group B2 and the fourth shift register unit group B4 in another non-display sub-area (for example, the second non-display sub-area A22), the shift register unit groups B can be alternately arranged on opposite sides of the display area A1, so that the shift register units G can be distributed as evenly as possible in the non-display area A2, which is conducive to the aesthetic design of the display panel 100. In addition, after the third shift register unit G(3) in the first shift register unit group B1 outputs the valid level of the gate driving signal Gout(3) at the stage t31, the first touch phase TP1 is inserted, and at the stage t32 after the first touch phase TP1, the second start signal stv2 received by the fourth shift register unit G(4) in the second shift register unit group B2 outputs the valid level; after the sixth shift register unit G(6) in the second shift register unit group B2 outputs the valid level of the gate driving signal Gout(6) at the stage t33, the second touch phase TP2 is inserted, and at the stage t34 after the second touch phase TP2, the seventh shift register unit G( 7) receives the third start signal stv3 and outputs a valid level; after the ninth shift register unit G(9) in the third shift register unit group B3 outputs the valid level of the gate drive signal Gout(5) at the t35 stage, the third touch control stage TP3 is inserted, and after the third touch control stage TP3 at the t36 stage, the fourth start signal stv4 received by the tenth shift register unit G(10) in the fourth shift register unit group B4 outputs the valid level; after the twelfth shift register unit G(12) in the fourth shift register unit group B4 outputs the valid level of the gate drive signal Gout(6) at the t37 stage, the fourth touch control stage TP4 is inserted, thereby completing one driving cycle T0 of the display panel 100.

[0065] refer to Figure 8, n=4, that is, the first four shift register units G receive different start signals stv, then each shift register unit G is divided into four shift register unit groups B, and each shift register unit group B includes three shift register units G. Among them, the signal input terminal IN of the first shift register unit G(1) is electrically connected to the first start signal terminal STV1 to receive the first start signal stv1, and based on the way that the output terminal of the i-th shift register unit G is electrically connected to the signal input terminal IN of the i+n-th shift register unit G(i+n), the first shift register unit G(1), the fifth shift register unit G(5) and the ninth shift register unit G(9) are sequentially cascaded to form the first shift register unit group B1. The second shift register unit G(2) is electrically connected to the second start signal terminal STV2 to receive the second start signal stv2, and based on the way that the output terminal of the i-th shift register unit G is electrically connected to the signal input terminal IN of the i+n-th shift register unit G(i+n), the second shift register unit G(2), the sixth shift register unit G(6) and the tenth shift register unit G(10) are sequentially cascaded to form a second shift register unit group B2. The signal input terminal IN of the third shift register unit G(3) is electrically connected to the third start signal terminal STV3 to receive the third start signal stv3, and based on the way that the output terminal of the i-th shift register unit G is electrically connected to the signal input terminal IN of the i+n-th shift register unit G(i+n), the third shift register unit G(3), the seventh shift register unit G(7) and the eleventh shift register unit G(11) are sequentially cascaded to form a third shift register unit group B3. The signal input terminal IN of the fourth shift register unit G(4) is electrically connected to the fourth start signal terminal STV4 to receive the fourth start signal stv4, and based on the way that the output terminal of the i-th shift register unit G is electrically connected to the signal input terminal IN of the i+n-th shift register unit G(i+n), the eighth shift register unit G(8) and the twelfth shift register unit G(12) are sequentially cascaded to form a fourth shift register unit group B4. Figure 7 and Figure 8The effective levels of the first start signal stv1, the second start signal stv2, the third start signal stv3, and the fourth start signal stv4 are sequentially shifted, allowing each shift register group B to perform global interlaced scanning on the pixels 20. This prevents the display screen from experiencing a partitioned visual effect due to the time interval caused by the touch phase TP after the touch phase TP is inserted, further improving the display quality of the display panel 100. By arranging the first shift register group B1 and the third shift register group B3 in the same non-display sub-area (e.g., the first non-display sub-area A21), and arranging the second shift register group B2 and the fourth shift register group B4 in another non-display sub-area (e.g., the second non-display sub-area A22), the shift register groups B can be alternately arranged on opposite sides of the display area A1, thereby ensuring that the shift register units G are distributed as evenly as possible in the non-display area A2, which is beneficial to the aesthetic design of the display panel 100. In addition, after the ninth shift register unit G(9) in the first shift register unit group B1 outputs the valid level of the gate driving signal Gout(9) at the stage t41, the first touch phase TP1 is inserted, and at the stage t42 after the first touch phase TP1, the second start signal stv2 received by the second shift register unit G(2) in the second shift register unit group B2 outputs the valid level; after the sixth shift register unit G(10) in the second shift register unit group B2 outputs the valid level of the gate driving signal Gout(10) at the stage t43, the second touch phase TP2 is inserted, and at the stage t44 after the second touch phase TP2, the third shift register unit G( 3) the received third start signal stv3 outputs a valid level; after the eleventh shift register unit G(11) in the third shift register unit group B3 outputs a valid level of the gate drive signal Gout(11) at stage t45, the third touch phase TP3 is inserted, and after the third touch phase TP3 at stage t46, the fourth start signal stv4 received by the fourth shift register unit G(4) in the fourth shift register unit group B4 outputs a valid level; after the twelfth shift register unit G(12) in the fourth shift register unit group B4 outputs a valid level of the gate drive signal Gout(12) at stage t47, the fourth touch phase TP4 is inserted, thereby completing one driving cycle T0 of the display panel 100.

[0066] Wherein, based on the first touch stage TP1, i.e., when j=1, the last-stage shift register unit G of the first shift register unit group B1 can be determined as the ninth shift register unit G(9) by m-n+j=12-4+1=9, and the first-stage shift register unit G in the second shift register unit group B2 can be determined as the second shift register unit G(2) by j+1=1+1=2; based on the second touch stage TP2, i.e., when j=2, the last-stage shift register unit G of the second shift register unit group B2 can be determined as the tenth shift register unit G(10) by m-n+j=12-4+2=10, and the third shift register unit group B can be determined as j+1=2+1=3. 3 is the third shift register unit G(3); based on the third touch stage TP3, that is, when j=3, the last shift register unit G of the third shift register unit group B3 can be determined as the tenth shift register unit G(10) by m-n+j=12-4+3=11, and the first shift register unit G in the fourth shift register unit group B4 can be determined as the fourth shift register unit G(4) by j+1=3+1=4; based on the fourth touch stage TP4, that is, when j=4, the last shift register unit G of the fourth shift register unit group B4 can be determined as the twelfth shift register unit G(12) by m-n+j=12-4+4=12.

[0067] Optional, reference Figure 7 or Figure 9 The number of shift register unit groups B in the first non-display sub-area A21 is equal to the number of shift register unit groups B in the second non-display sub-area A22. In this way, the shift register unit groups B can be distributed as evenly as possible on opposite sides of the display area A1, which is beneficial to the aesthetic design of the display panel 100.

[0068] Optional, reference Figure 5 、 Figure 6 、 Figure 8 and Figure 10 In any of the figures, different shift register unit groups B receive different transition times of the first type clock signal cka, and different shift register unit groups B receive different transition times of the second type clock signal ckb.

[0069] Specifically, the transition moment can be one of the moments when the high level transitions to the low level or the moments when the low level transitions to the high level. For example, the transition moment is the moment when the high level transitions to the low level. Figure 5 and Figure 6The first clock signal cka and the second clock signal ckb received by each shift register unit G in the first shift register unit group B1 are the first clock signal ck1 and the second clock signal ck2, respectively. The first clock signal cka and the second clock signal ckb received by each shift register unit G in the second shift register unit group B2 are the third clock signal ck3 and the fourth clock signal ck4, respectively. The transition moment ta1 of the first clock signal ck1 is different from the transition moment ta2 of the third clock signal ck3, with a certain delay. The transition moment tb1 of the second clock signal ck2 is different from the transition moment tb2 of the fourth clock signal ck4, with a certain delay. The interval between the transition moments ta1 and ta2, as well as the interval between the transition moments tb1 and tb2, can be set according to the resolution of the display panel 100 to meet the design requirements of the resolution of the display panel 100.

[0070] Optional, Figure 11 and Figure 12 This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figure 7 and Figure 11 , or combined with reference Figure 9 and Figure 12 , after the start signal stv received by the yth shift register unit group B outputs a valid level, and before the yth touch phase TP, the first type clock signal cka and the second type clock signal ckb received by the yth shift register unit group B include alternating high levels and low levels; before the start signal stv received by the yth shift register unit group B is a valid level, and after the yth touch phase TP, the first type clock signal cka and the second type clock signal ckb received by the yth shift register unit group B both remain at a low level.

[0071] Specifically, after the start signal stv received by the yth shift register unit group B outputs a valid level, and before the yth touch stage TP, the gate drive signal Gout of each shift register unit G in the yth shift register unit group B outputs a valid level in sequence. At this time, the first type of clock signal cka and the second type of clock signal ckb received by the shift register unit group B are set to maintain normal transition conditions, that is, the first type of clock signal cka and the second type of clock signal ckb received by the shift register unit group B include alternating high levels and low levels, so that each level of shift register unit G can output the valid level of the gate drive signal Gout in sequence under the drive of the first type of clock signal cka, the second type of clock signal ckb and the input signal. Before the start signal stv received by the yth shift register unit group B is at a valid level, and after the yth touch stage TP, the gate drive signal Gout output by each shift register unit G in the yth shift register unit group B is maintained at an invalid level. At this time, the first type of clock signal cka and the second type of clock signal ckb received by the shift register unit group B can be controlled to maintain a low level and no longer jump, that is, only the first type of clock signal cka and the second type of clock signal ckb received by the shift register unit G that outputs the valid level of the gate drive signal Gout jump normally, and the first type of clock signal cka and the second type of clock signal ckb received by the shift register unit G that outputs the invalid level of the gate drive signal Gout remain at a low level and do not jump. Figure 11 and Figure 12In the embodiment, from the moment when the first start signal stv1 received by the first shift register unit group B1 is at the valid level until the stage before the first touch phase TP1, that is, stage t51, the first clock signal ck1 and the second clock signal ck2 perform normal transitions between high and low levels, so that the gate drive signals Gout of the shift register units G at all levels in the first shift register unit group B1 sequentially output valid levels, while the other clock signals (that is, the third clock signal ck3 to the eighth clock signal ck8) remain at low levels and do not transition; based on the same principle, in stage t52, the third clock signal ck3 and the fourth clock signal ck4 perform normal transitions between high and low levels, so that the gate drive signals Gout of the shift register units G at all levels in the second shift register unit group B2 sequentially output valid levels, while the other clock signals (that is, the first clock signal ck1, the second clock signal ck2, the fifth clock signal ck8) remain at low levels and do not transition. The first clock signal ck1 to the fourth clock signal ck4, and the seventh clock signal ck7 and the eighth clock signal ck8) remain at a low level and do not transition; in the t53 stage, the fifth clock signal ck5 and the sixth clock signal ck6 perform normal transitions between high and low levels, so that the gate drive signals Gout of the shift register units G at all levels in the third shift register unit group B3 output valid levels in sequence, while the other clock signals (i.e., the first clock signal ck1 to the fourth clock signal ck4, and the seventh clock signal ck7 and the eighth clock signal ck8) remain at a low level and do not transition; in the t54 stage, the seventh clock signal ck7 and the eighth clock signal ck8 perform normal transitions between high and low levels, so that the gate drive signals Gout of the shift register units G at all levels in the third shift register unit group B3 output valid levels in sequence, while the other clock signals (i.e., the first clock signal ck1 to the sixth clock signal ck6) remain at a low level and do not transition. In this way, the power consumption caused by the continuous jump of the first clock signal cka and the second clock signal ckb can be effectively reduced based on the effective level of the normal output gate driving signal Gout output by each shift register unit G and the touch phase TP.

[0072] Optional, Figure 13 and Figure 14 This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figure 7 and Figure 13 , or combined with reference Figure 9 and Figure 14 , the first type clock signal cka received by each shift register unit G outputs a valid level and an invalid level at the same time, and the second type clock signal ckb received by each shift register unit G outputs a valid level and an invalid level at the same time.

[0073] Specifically, it is also possible to set the first type clock signal cka received by each shift register unit G to have the same transition condition, and set the second type clock signal ckb received by each shift register unit G to have the same transition condition, such as Figure 13 and Figure 14 The first clock signal ck1, the third clock signal ck3, the fifth clock signal ck5 and the seventh clock signal ck7 used as the first type of clock signal cka have the same transition conditions, and the second clock signal ck2, the fourth clock signal ck4, the sixth clock signal ck6 and the eighth clock signal ck8 used as the second type of clock signal ckb have the same transition conditions.

[0074] by Figure 13 and Figure 14 For example, refer to the embodiment shown in Figure 13After the first start signal stv1 received by the first shift register unit G(1) outputs an effective level, the first shift register unit G(1), the second shift register unit G(2) and the third shift register unit G(3) can output gate drive signals Gout(1), Gout(2) and Gout(3) whose effective levels are shifted in sequence under the control of the first clock signal ck1 and the second clock signal ck2; after the third shift register unit G(3) outputs the effective level of the gate drive signal Gout(3), the first touch phase TP1 is inserted. After the completion of the segment TP1, the second start signal stv2 outputs a valid level, so that the fourth shift register unit G(4), the fifth shift register unit G(5) and the sixth shift register unit G(6) can output the gate drive signals Gout(4), Gout(5) and Gout(6) of which the valid levels are shifted in sequence under the control of the third clock signal ck3 and the fourth clock signal ck4; after the sixth shift register unit G(6) outputs the valid level of the gate drive signal Gout(6), the second touch stage TP2 is inserted. After the completion of the second touch stage TP2, the fourth shift register unit G(4), the fifth shift register unit G(5) and the sixth shift register unit G(6) can output the gate drive signals Gout(4), Gout(5) and Gout(6) of which the valid levels are shifted in sequence; after the sixth shift register unit G(6) outputs the valid level of the gate drive signal Gout(6), the second touch stage TP2 is inserted. The third start signal stv3 outputs a valid level, so that the seventh shift register unit G(7), the eighth shift register unit G(8) and the ninth shift register unit G(9) can output the gate drive signals Gout(7), Gout(8) and Gout(9) whose valid levels are sequentially shifted under the control of the fifth clock signal ck5 and the sixth clock signal ck6; after the ninth shift register unit G(9) outputs the valid level of the gate drive signal Gout(9), the third touch stage TP3 is inserted, and after the third touch stage TP3 is completed, the fourth start signal stv4 is output. Outputting effective levels enables the tenth shift register unit G (10), the eleventh shift register unit G (11) and the twelfth shift register unit G (12) to output gate drive signals Gout (10), Gout (11) and Gout (12) whose effective levels are sequentially shifted under the control of the seventh clock signal ck7, the eighth clock signal ck8 and the received input signal, and then inserting the fourth touch phase TP4 after the twelfth shift register unit G (12) outputs the effective level of the gate drive signal Gout (12) to complete the current driving cycle T0. In this way, the accuracy of the gate drive signal output by each shift register unit G can be maintained without affecting the accuracy of the gate drive signal output by each shift register unit G, and on the basis of each shift register unit G outputting the effective level of the normal output gate drive signal Gout, the control process of each first-class clock signal cka and the second-class clock signal ck2 can be simplified.

[0075] Alternatively, refer to Figure 14After the first start signal stv1 received by the first shift register unit G(1) outputs an effective level, the first shift register unit G(1), the fifth shift register unit G(5) and the ninth shift register unit G(9) can output gate drive signals Gout(1), Gout(5) and Gout(9) whose effective levels are sequentially shifted under the control of the first clock signal ck1 and the second clock signal ck2; after the ninth shift register unit G(9) outputs an effective level of the gate drive signal Gout(9), the first touch phase TP1 is inserted. In the first touch phase T After P1 is completed, the second start signal stv2 outputs a valid level, so that the second shift register unit G(2), the sixth shift register unit G(6) and the tenth shift register unit G(10) can output the gate drive signals Gout(2), Gout(6) and Gout(10) whose valid levels are shifted in sequence under the control of the third clock signal ck3 and the fourth clock signal ck4; after the tenth shift register unit G(10) outputs the valid level of the gate drive signal Gout(10), the second touch phase TP2 is inserted. After the second touch phase TP2 is completed, the first shift register unit G(2), the sixth shift register unit G(6) and the tenth shift register unit G(10) can output the gate drive signals Gout(2), Gout(6) and Gout(10) whose valid levels are shifted in sequence; after the tenth shift register unit G(10) outputs the valid level of the gate drive signal Gout(10), the second touch phase TP2 is inserted. The third start signal stv3 outputs a valid level, so that the third shift register unit G(3), the seventh shift register unit G(7) and the eleventh shift register unit G(11) can output the gate drive signals Gout(3), Gout(7) and Gout(11) whose valid levels are shifted in sequence under the control of the fifth clock signal ck5 and the sixth clock signal ck6; after the eleventh shift register unit G(11) outputs the valid level of the gate drive signal Gout(11), the third touch phase TP3 is inserted, and after the third touch phase TP3 is completed, the fourth start signal stv4 outputs a valid level, so that the fourth shift register unit G(4), the eighth shift register unit G(8) and the twelfth shift register unit G(12) can output gate drive signals Gout(10), Gout(11) and Gout(12) with valid levels shifted in sequence under the control of the seventh clock signal ck7, the eighth clock signal ck8 and the received input signal, and then the fourth touch phase TP4 is inserted after the twelfth shift register unit G(12) outputs the valid level of the gate drive signal Gout(12), completing the current driving cycle T0. In this way, the accuracy of the gate drive signal output by the shift register unit G is not affected when the touch phase TP is inserted, and on the basis of each shift register unit G outputting the valid level of the normal output gate drive signal Gout, the control process of each first-class clock signal cka and second-class clock signal ck2 is simplified.

[0076] Optional, Figure 15 and Figure 16 is a structural diagram of another display panel provided by an embodiment of the present invention. Figure 17 and Figure 18This is another driving timing diagram of a driving circuit provided by an embodiment of the present invention, combined with reference to Figure 15 and Figure 17 , or combined with reference Figure 16 and Figure 18 , each shift register unit G receives the same first-type clock signal cka, and each shift register unit G receives the same second-type clock signal ckb.

[0077] Specifically, since the first-type clock signal cka received by each shift register unit G can have the same transition condition, and the second-type clock signal ckb received by each level of shift register unit G can have the same transition condition, each shift register unit G can be set to receive the same first-type clock signal cka, and each shift register unit G can receive the same second-type clock signal ckb. In this way, the number of signals provided by the driving chip can be reduced, and the number of signal lines in the display panel can be reduced, which is beneficial to the miniaturized design of the display panel 100.

[0078] It should be noted that Figure 15 and Figure 16 The example shows the case where the first clock signal line Ck1 and the second clock signal line Ck2 are set in the first non-display sub-area A21 and the second non-display sub-area A22. In this case, the display panel 100 can be designed symmetrically, which is beneficial to the aesthetics of the display panel 100. It can be understood that in other feasible embodiments of the present invention, the first clock signal line Ck1 and the second clock signal line Ck2 can be set only in one of the first non-display sub-area A21 and the second non-display sub-area A22. In this way, the number of signal lines in the display panel 100 can be further reduced, thereby further simplifying the circuit structure in the display panel 100. At this time, in the non-display sub-area where the first clock signal line Ck1 and the second clock signal line Ck2 are not set, each shift register unit G can be electrically connected to the first clock signal line Ck1 and the second clock signal line Ck2 through an auxiliary line, so as to receive the first clock signal ck1 as the first type of clock signal cka, and receive the second clock signal ck2 as the second type of clock signal ck2.

[0079] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device provided by an embodiment of the present invention includes the technical features of the display panel provided by any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided by any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided by the embodiment of the present invention, and will not be repeated here.

[0080] For example, Figure 19 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 19 As shown, the display device 200 includes the display panel 100 provided in an embodiment of the present invention. The display device 200 provided in an embodiment of the present invention can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present invention does not specifically limit this.

[0081] It can be seen from the above embodiments that the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0082] The display panel provided by the present invention includes: a driving circuit and pixels arranged in an array; the driving circuit includes m shift register units, and in each shift register unit, the xth shift register unit is electrically connected to at least part of the pixels in the xth row; the shift register unit includes a signal input terminal, a first clock terminal, a second clock terminal and a signal output terminal; the first clock terminal is used to receive a first type of clock signal, and the second clock terminal is used to receive a second type of clock signal; each shift register unit is used to output a gate drive signal based on the first type of clock signal, the second type of clock signal and the input signal of the signal input terminal; the m shift register units constitute n shift registers Register unit group; the shift register units located in the same shift register unit group are cascaded with each other; in the same shift register unit group, the first-stage shift register unit receives a start signal, and the start signals received by each shift register unit group are different; the driving cycle of the display panel includes n touch phases, the yth touch phase is located after the gate drive signal of the last-stage shift register unit in the yth shift register unit group outputs a valid level, and before the start signal received by the y+1th shift register unit group outputs a valid level; wherein m, n, x, and y are all positive integers, x≤m, n≤m, and y≤n. The present invention configures n shift register groups by arranging m shift register units in a shift register circuit, so that the shift register units in the same shift register group are cascaded with each other, so that the shift register units in the same shift register group can sequentially output the effective level of the gate drive signal. By setting different start signals received by different shift register groups, the effective levels of the start signals received by different shift register groups can have a controllable time interval. By setting a drive cycle of the display panel to include n touch stages, the yth touch stage is located between the gate drive signal output effective level of the last shift register unit in the yth shift register group. After the touch stage, and before the start signal received by the y+1th shift register unit group outputs the valid level, the shift register unit group receives the valid level of the input signal after the touch stage is completed, so that the valid level of the input signal will not be stored for a long time in the first-stage shift register unit of the shift register unit group, so that the characteristics of the devices therein will not be shifted due to long-term bias, which can improve the accuracy and stability of the gate drive signal output after the touch stage. When the shift register units of each level are cascaded in sequence, the accuracy of the gate drive signal output by the shift register units of each level after the touch stage can also be improved, thereby effectively improving the display effect of the display panel.

[0083] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0084] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: Driving circuit and array-arranged pixels; The driving circuit includes m shift register units, and among the shift register units, the xth shift register unit is electrically connected to at least part of the pixels in the xth row; The shift register unit includes a signal input terminal, a first clock terminal, a second clock terminal and a signal output terminal; the first clock terminal is used to receive a first type of clock signal, and the second clock terminal is used to receive a second type of clock signal; each of the shift register units is used to output a gate drive signal according to the first type of clock signal, the second type of clock signal and the input signal of the signal input terminal; m shift register units constitute n shift register unit groups; the shift register units in the same shift register unit group are cascaded; in the same shift register unit group, the first-stage shift register units receive a start signal, and the start signals received by each shift register unit group are different; The driving cycle of the display panel includes n touch control phases, the yth touch control phase is located after the gate driving signal of the last shift register unit in the yth shift register unit group outputs a valid level, and before the start signal received by the y+1th shift register unit group outputs a valid level; Among them, m, n, x, and y are all positive integers, x≤m, n≤m, y≤n.

2. The display panel according to claim 1, wherein: Among the m shift register units, signal input terminals of the first n shift register units receive a start signal, and the start signals received by the first n shift register units are different; and, among the m shift register units, an output terminal of the i-th shift register unit is electrically connected to a signal input terminal of the i+n-th shift register unit; The jth touch control phase is located after the gate driving signal of the (m-n+j)th shift register unit outputs a valid level, and before the start signal received by the (j+1)th shift register unit outputs a valid level; Where i and j are both positive integers, i≤m, and j <n。 3. The display panel according to claim 1, wherein: The effective levels of the gate driving signals of the m shift register units are shifted in sequence; The adjacent k-stage shift register units constitute a shift register unit group; k is a positive integer and 1<k<m.

4. The display panel according to claim 1, wherein: n is an even number.

5. The display panel according to claim 1, wherein: In the same shift register unit group, the first clock signal terminal of each shift register unit receives the same first-type clock signal, and the second clock signal terminal of each shift register unit receives the same second-type clock signal.

6. The display panel according to claim 5, wherein: Different shift register unit groups receive different transition moments of the first type of clock signal, and different shift register unit groups receive different transition moments of the second type of clock signal.

7. The display panel according to claim 5, wherein: After the start signal received by the yth shift register unit group outputs a valid level and before the yth touch control phase, the first type of clock signal and the second type of clock signal received by the yth shift register unit group include alternating high levels and low levels; Before the start signal received by the yth shift register unit group is at a valid level and after the yth touch control phase, the first type clock signal and the second type clock signal received by the yth shift register unit group are both kept at a low level.

8. The display panel according to claim 1, wherein: The first type clock signal received by each of the shift register units outputs a valid level and an invalid level simultaneously, and the second type clock signal received by each of the shift register units outputs a valid level and an invalid level simultaneously. 9 . The display panel according to claim 1 , wherein each of the shift register units receives a same first-type clock signal, and each of the shift register units receives a same second-type clock signal.

10. The display panel according to claim 1, wherein Also includes: a display area and a non-display area surrounding the display area; The driving circuit is located in the non-display area; In the display area, the display panel further includes a plurality of scanning signal lines extending along the first direction and arranged along the second direction; at least some of the pixels in the same row share one scanning signal line; the scanning signal line is used to transmit the gate drive signal; Among the m shift register units, the xth shift register unit is electrically connected to the xth scanning signal line along the second direction.

11. The display panel according to claim 10, wherein: Along the first direction, the non-display area includes a first non-display sub-area and a second non-display sub-area located on opposite sides of the display area; The effective levels of the start signals received by two shift register unit groups adjacent along the second direction are shifted in sequence, and the two shift register unit groups adjacent along the second direction are respectively located in the first non-display sub-area and the second non-display sub-area.

12. The display panel according to claim 11, wherein: The number of the shift register unit groups in the first non-display sub-area is equal to the number of the bit register unit groups in the second non-display sub-area.

13. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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