Gate drive circuit, display panel and display device

Abstract

The invention provides a gate drive circuit, a display panel and a display device, and relates to the technical field of display. The output end of a first input unit in the shift register is electrically connected with a first node, the control end of the first input unit receives a clock signal, the control end of a first output unit is electrically connected with a second node, and the output end of a second input unit and the control end of the second output unit are electrically connected with a third node. The output end of the first output unit and the output end of the second output unit are electrically connected with an output signal end, and the output signal end outputs scanning signals. The first end of the isolation unit is electrically connected with the first node, the second end of the isolation unit is electrically connected with the second node, the control end of the isolation unit receives a control signal, and the time period where the invalid level of the control signal is located is overlapped with the time period where the valid level of the scanning signal is located. According to the embodiment of the invention, the electric leakage of the shift register is reduced, and the electric leakage of the gate drive circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit, a display panel and a display device. Background Art

[0002] A display panel generally includes a display area and a non-display area. The display area is provided with a plurality of pixel driving circuits and light-emitting elements. The pixel driving circuit is used to drive the light-emitting elements to emit light to display images. The non-display area is provided with a gate driving circuit for providing a scanning control signal to the pixel driving circuit so that the light-emitting elements are lit up row by row under the drive of the pixel driving circuit.

[0003] In the related art, the gate driving circuit has a leakage problem. Summary of the Invention

[0004] The present invention provides a gate drive circuit, a display panel and a display device, so as to reduce the leakage of a shift register and reduce the leakage of a gate drive circuit.

[0005] In a first aspect, the present invention provides a gate drive circuit, the gate drive circuit comprising:

[0006] A plurality of cascaded shift registers, characterized in that the shift register comprises a first input unit, a first output unit, a second input unit, a second output unit and an isolation unit;

[0007] The output end of the first input unit is electrically connected to the first node, the control end of the first input unit receives a clock signal, the control end of the first output unit is electrically connected to the second node, the output end of the second input unit and the control end of the second output unit are electrically connected to the third node, the output end of the first output unit and the output end of the second output unit are electrically connected to the output signal end, and the output signal end outputs a scan signal;

[0008] A first end of the isolation unit is electrically connected to the first node, a second end of the isolation unit is electrically connected to the second node, and a control end of the isolation unit receives a control signal;

[0009] A period in which the control signal is at an inactive level overlaps a period in which the scan signal is at an active level.

[0010] In a second aspect, an embodiment of the present invention provides a display panel, comprising the gate driving circuit described in the first aspect.

[0011] In a third aspect, an embodiment of the present invention provides a display device comprising the display panel described in the second aspect.

[0012] In the gate drive circuit provided by an embodiment of the present invention, the second node is electrically connected to the control end of the first output unit. When the potential information of the second node includes a valid level, the first output unit is turned on so that the output signal end outputs the valid level of the scan signal. The first end of the isolation unit is electrically connected to the first node, and the second end of the isolation unit is electrically connected to the second node. The control end of the isolation unit receives a control signal. When the potential information of the control signal includes an invalid level, the isolation unit is turned off, that is, the first node and the second node are disconnected. Then, by setting the invalid period of the control signal to overlap with the valid level period of the scan signal, when the potential information of the second node includes a valid level, the isolation unit is in the off state, thereby reducing leakage in the circuit branch where the first node and the second node are located. Wherein, leakage refers to leakage current in the off state, or voltage change caused by leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 1 is a circuit diagram of a gate drive circuit provided by an embodiment of the present invention;

[0014] Figure 2 1 is a circuit diagram of a shift register provided by an embodiment of the present invention;

[0015] Figure 3 This is a driving timing diagram of a shift register provided by an embodiment of the present invention;

[0016] Figure 4 A driving timing diagram of another shift register provided by an embodiment of the present invention;

[0017] Figure 5 A circuit diagram of another gate drive circuit provided by an embodiment of the present invention;

[0018] Figure 6 A driving timing diagram of another shift register provided by an embodiment of the present invention;

[0019] Figure 7 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0020] Figure 8 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0021] Figure 9 1 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0022] Figure 10 1 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0023] Figure 11This is another driving timing diagram of a shift register provided by an embodiment of the present invention;

[0024] Figure 12 1 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0025] Figure 13 1 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0026] Figure 14 1 is a circuit diagram of another shift register provided by an embodiment of the present invention;

[0027] Figure 15 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0028] Figure 16 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be fully described below in conjunction with the drawings in the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention, which is obvious to those skilled in the art. Therefore, the present invention is intended to cover modifications and changes of the present invention that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents.

[0030] Furthermore, the terms "first," "second," and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a," "an," or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprising" mean that the element or object preceding the term includes the elements or objects listed after the term, and their equivalents, without excluding other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. Furthermore, terms such as "same" or "equal" used in the embodiments of the present disclosure do not mean that two objects are exactly the same size or shape. Approximately the same or approximately equal within a certain error range is permitted. It should be noted that the embodiments provided in the embodiments of the present disclosure can be combined with each other if there is no contradiction.

[0031] Figure 1 is a circuit diagram of a gate drive circuit provided by an embodiment of the present invention, Figure 2 1 is a circuit diagram of a shift register provided by an embodiment of the present invention. Figure 3 This is a driving timing diagram of a shift register provided by an embodiment of the present invention. Figure 1-Figure 3 The gate driving circuit includes a plurality of cascaded shift registers 100, each of which includes a first input unit 110, a first output unit 120, a second input unit 130, a second output unit 140, and an isolation unit 150. An output terminal of the first input unit 110 is electrically connected to a first node Q1, a control terminal of the first input unit 110 receives a clock signal, a control terminal of the first output unit 120 is electrically connected to a second node Q2, an output terminal of the second input unit 130 and a control terminal of the second output unit 140 are electrically connected to a third node QB1, an output terminal of the first output unit 120 and an output terminal of the second output unit 140 are electrically connected to an output signal terminal OUT, which outputs a scan signal, a first terminal of the isolation unit 150 is electrically connected to the first node Q1, a second terminal of the isolation unit 150 is electrically connected to the second node Q2, a control terminal of the isolation unit receives a control signal, and a period in which the control signal is at an inactive level overlaps a period in which the scan signal is at an active level.

[0032] Specifically, such as Figure 2As shown, the input terminal of the first input unit 110 is electrically connected to the cascade output signal terminal STV, the output terminal of the first input unit 110 is electrically connected to the first node Q1, and the control terminal of the first input unit 110 is electrically connected to the first clock signal terminal CK1 or the second clock signal terminal CK2, which provides a clock signal to the control terminal of the first input unit 110. The following embodiment uses the example of the first clock signal terminal CK1 providing a clock signal to the control terminal of the first input unit 110. When the clock signal provided by the first clock signal terminal CK1 is at an active level, the first input unit 110 is turned on, and the cascade signal provided by the cascade output signal terminal STV can be transmitted to the first node Q1. The control terminal of the first output unit 120 is electrically connected to the second node Q2, the input terminal of the first output unit 120 is electrically connected to the first voltage terminal VGH, and the output terminal of the first output unit 120 is electrically connected to the output signal terminal OUT. When the potential information of the second node Q2 includes a valid level, the first output unit 120 is turned on, and the first voltage terminal VGH provides a first voltage to the output signal terminal OUT, so that the scan signal output by the output signal terminal OUT includes a valid level. When the potential information of the second node Q2 includes an invalid level, the first output unit 120 is turned off. The output terminal of the second input unit 130 and the control terminal of the second output unit 140 are connected to the third node QB1, the input terminal of the second output unit 140 is electrically connected to the second voltage terminal VGL, and the output terminal of the second output unit 140 is electrically connected to the output signal terminal OUT. When the potential information of the third node QB1 includes a valid level, the second output unit 140 is turned on, and the second voltage terminal VGL outputs a second voltage to the output signal terminal OUT, so that the scan signal output by the output signal terminal OUT includes an invalid level.

[0033] In addition, a first end of the isolation unit 150 is electrically connected to the first node Q1, a second end of the isolation unit 150 is electrically connected to the second node Q2, and a control end of the isolation unit 150 is electrically connected to the control signal end Ctr. The control signal end Ctr outputs a control signal to the control end of the isolation unit 150. When the control signal includes a valid level, the isolation unit 150 is turned on to connect the first node Q1 and the second node Q2. When the control signal includes an invalid level, the isolation unit 150 is turned off to disconnect the first node Q1 and the second node Q2.

[0034] For example, Figure 3In the illustrated embodiment, the example in which the effective level of the control signal and the effective level of the scan signal are both high, and the ineffective level of the control signal and the ineffective level of the scan signal are both low is used for illustration. In the embodiment of the present invention, the period during which the control signal is ineffective overlaps with the period during which the scan signal is effective. Specifically, the output signal terminal OUT outputs the scan signal. Since the control terminal of the first output unit 120 is electrically connected to the second node Q2, the input terminal of the first output unit 120 is electrically connected to the first voltage terminal VGH, and the output terminal of the first output unit 120 is electrically connected to the output signal terminal OUT, the period during which the effective level of the scan signal is the period during which the potential information of the second node Q2 is at an effective level. When the potential information of the second node Q2 is at an effective level (high level), a leakage path is formed from the second node Q2 to the first node Q1 to the first input unit 110 to the cascade output signal terminal STV, resulting in leakage in the gate drive circuit. Therefore, by setting the time period of the invalid level of the control signal to overlap with the time period of the valid level of the scanning signal, when the potential information of the second node Q2 includes the valid level (high level), the isolation unit 150 is in the off state to disconnect the leakage path of the second node Q2-the first node Q1-the first input unit 110-the cascade output signal terminal STV, thereby reducing the leakage of the gate drive circuit.

[0035] Optionally, based on the above embodiment, Figure 4 This is another driving timing diagram of a shift register provided by an embodiment of the present invention. Figure 4 , the clock signal includes multiple clock pulses, and the effective level period of the control signal overlaps with the multiple clock pulses. Specifically, Figure 4 As shown, the clock signal provided by the first clock signal terminal CK1 includes multiple clock pulses with the same period, each of which includes a rising edge and a falling edge. The effective level of the control signal provided by the control signal terminal Ctr overlaps with the multiple clock pulses during the period, that is, the control signal provided by the control signal terminal Ctr is different from the clock signal provided by the first clock signal terminal CK1.

[0036] Optionally, based on the above embodiment, continue to refer to Figure 4 The clock signal includes multiple clock pulses, the clock pulses include a setting pulse t1, the starting time of the setting pulse t1 is aligned with the starting time of the effective level of the scanning signal, and the starting time of the invalid level of the control signal is after the end time of the setting pulse t1.

[0037] For details, see Figure 3 and Figure 4, the driving timing of the shift register includes a T1 time period. At the beginning of the T1 time period, the potential information of the clock signal provided by the first clock signal terminal CK1 is switched from an invalid level to a valid level, and the potential information of the control signal provided by the control signal terminal Ctr is a valid level. Then, at the beginning of the T1 time period, the clock signal of the valid level controls the first input unit 110 to be turned on, and the control signal terminal Ctr controls the isolation unit 150 to be turned on. Since the cascade signal output by the cascade output signal terminal STV is a valid level at this time, the cascade signal of the valid level is transmitted to the second node Q2 through the first node Q1 to change the potential information of the second node Q2 from an invalid level to a valid level. The effective level is pulled up to the effective level, the first output unit 120 is turned on, and the output signal terminal OUT starts to output the scanning signal of the effective level, that is, the clock pulse of the clock signal in the T1 time period is the setting pulse t1, and the starting time of the setting pulse t1 is aligned with the starting time of the effective level of the scanning signal, that is, the starting time of the setting pulse t1 is aligned with the starting time of the effective level of the second node Q2, so that at the starting time of the T1 time period, the potential information of the second node Q2 is switched from the invalid level to the effective level, ensuring that in the T1 time period, the first output unit 120 can normally output the first voltage, that is, the output signal terminal OUT can normally output the effective level of the scanning signal.

[0038] From the above, it can be seen that in the T1 period, the effective level of the setting pulse t1 is used to pull the potential information of the second node Q2 from the invalid level to the effective level. If the starting time of the invalid level of the control signal is before the ending time of the setting pulse t1, that is, the starting time of the invalid level of the control signal overlaps with the effective level of the setting pulse t1, since the invalid level of the control signal is used to turn off the isolation unit 150 to disconnect the first node Q1 and the second node Q2, therefore, in the T1 period, the effective level of the cascade signal cannot be transmitted from the first node Q1 to the second node Q2, that is, the second node cannot be disconnected. The invalid level of Q2 is pulled up to the valid level, so that the scanning signal output by the output signal terminal OUT is abnormal. Then, by setting the starting time of the invalid level of the control signal to be after the end time of the setting pulse t1, at the time when the valid level of the setting pulse t1 is located, the control signal terminal Ctr controls the isolation unit 150 to remain turned on, so as to ensure that the potential information of the second node Q2 can be switched from the invalid level to the valid level in the T1 time period, and to ensure that in the T1 time period, the first output unit 120 can normally output the first voltage, that is, the output signal terminal OUT can normally output the valid level of the scanning signal.

[0039] Optionally, based on the above embodiment, continue to refer to Figure 4 , the end time of the invalid level of the control signal is after the end time of the valid level of the scanning signal.

[0040] Specifically, such as Figure 4 As shown, the driving timing of the shift register includes a T3 period. At the end of the T3 period, the potential information of the second node Q2 begins to switch from an active level to an inactive level, the first output unit 120 is turned off, and the first voltage provided by the first voltage terminal VGH cannot be transmitted to the output signal terminal OUT. At the same time, the potential information of the third node QB1 begins to switch from an inactive level to an active level, the second output unit 140 is turned on, and the second voltage provided by the second voltage terminal VGL is transmitted to the output signal terminal OUT, so that the scan signal output by the output signal terminal OUT switches to an inactive level. Based on the above, the potential information of the second node Q2 is maintained at an active level during the period between the end of the setting pulse t1 and the end of the T3 period. The active level of the second node Q2 is the active level of the scan signal. Therefore, by setting the end time of the inactive level of the control signal after the end time of the active level of the scan signal, the overlap time of the inactive level of the control signal and the active level of the second node Q2 can be increased, thereby minimizing the leakage of the second node Q2 as much as possible during the period when the potential information of the second node Q2 is at an active level.

[0041] Optionally, based on the above embodiment, Figure 5 A circuit diagram of another gate drive circuit provided by an embodiment of the present invention, Figure 6 A driving timing diagram of another shift register provided by an embodiment of the present invention. Figure 5 The shift register includes an i-th shift register VSR(i) and a j-th shift register VSR(j), where i and j are positive integers and i is less than j. The control terminal of the isolation unit 150 in the i-th shift register is electrically connected to the third node QB1 of the j-th shift register.

[0042] For example, Figure 5 and Figure 6 In the embodiment shown, i and j are adjacent positive integers, and the description is made as an example, that is, the j-th stage shift register VSR(j) is the next stage of the i-th stage shift register VSR(i). Figure 6In the driving timing of the i-th stage shift register VSR(i), the clock signal provided by the first clock signal terminal CK1 includes a setting pulse t1, and the starting time of the setting pulse t1 is aligned with the starting time of the effective level of the scanning signal output by the output signal terminal OUT(i) in the i-th stage shift register VSR(i). Since the start time of the invalid level of the third node QB1(j) of the j-th stage shift register VSR(j) is after the end time of the setting pulse t1 in the i-th stage shift register VSR(i), the potential signal of the third node QB1 of the j-th stage shift register VSR(j) can be multiplexed as the control signal of the isolation unit 150 in the i-th stage shift register VSR(i), that is, the third node QB1 of the j-th stage shift register VSR(j) is multiplexed as the control signal terminal Ctr of the i-th stage shift register VSR(i). Through the third node QB1 of the j-th stage shift register VSR(j), when the potential information of the second node Q2 in the i-th stage shift register VSR(i) includes a valid level, the leakage path of the second node Q2 in the i-th stage shift register VSR(i) - the first node Q1 - the first input unit 110 - the cascade output signal terminal STV is disconnected, thereby reducing the leakage of the i-th stage shift register VSR(i).

[0043] It should be noted that the above embodiment is only illustratively described by taking i and j as adjacent positive integers, but is not limited thereto. In other embodiments, the difference between i and j may also be 2 or 3. It is understandable that when the difference between i and j is 2 or 3, the start time of the invalid level of the third node QB1(j) of the j-th stage shift register VSR(j) is located after the end time of the setting pulse t1 in the i-th stage shift register VSR(i), and the end time of the invalid level of the third node QB1(j) of the j-th stage shift register VSR(j) is located after the end time of the valid level of the output signal terminal OUT(i) in the i-th stage shift register VSR(i).

[0044] Optionally, based on the above embodiment, continue to refer to Figure 5 and Figure 6, the input end of the first input unit 110 in the j-th shift register VSR(j) is electrically connected to the i-th shift register VSR(i). That is, the j-th shift register VSR(j) is the next stage of the i-th shift register VSR(i). At this time, the start time of the inactive level of the third node QB1(j) in the j-th shift register VSR(j) is closest to the end time of the setting pulse t1 in the i-th shift register VSR(i). This increases the overlap time between the period in which the third node QB1(j) in the j-th shift register VSR(j) is inactive and the period in which the output signal terminal OUT(i) in the i-th shift register VSR(i) is active. This reduces the leakage of the second node Q2 in the i-th shift register VSR(i) as much as possible during the period in which the second node Q2 in the i-th shift register VSR(i) is active.

[0045] Optionally, based on the above embodiment, continue to refer to Figure 5 The plurality of shift registers include at least one dummy register VSR(n) and a plurality of scanning shift registers. The first-stage shift register VSR(1) to the M-stage shift register VSR(M) are scanning shift registers, where M is greater than or equal to j and less than n. The control terminal of the isolation unit 150 in the M-stage shift register VSR(M) is electrically connected to the third node QB1(n) of the dummy register VSR(n). Specifically, the dummy register VSR(n) is the last stage of the plurality of shift registers, and the dummy register VSR(n) is not used to output a scanning signal, but rather provides a control signal to the control terminal of the isolation unit 150 in the M-stage shift register VSR(M) of the last scanning shift register, so as to reduce leakage current of the M-stage shift register VSR(M) of the last scanning shift register, thereby reducing leakage current of the entire gate drive circuit.

[0046] Optionally, based on the above embodiment, Figure 7 is a circuit diagram of another shift register provided by an embodiment of the present invention, see Figure 7 The isolation unit 150 includes an isolation transistor M1 , a first electrode of the isolation transistor M1 is electrically connected to the first node Q1 , a second electrode of the isolation transistor M1 is electrically connected to the second node Q2 , and a gate of the isolation transistor M1 receives a control signal.

[0047] Exemplarily, the gate drive circuit includes a plurality of thin film transistors, at least one of which is an oxide transistor. The semiconductor layer of the oxide transistor includes a metal oxide, wherein the metal oxide may include, for example, indium gallium zinc oxide (IGZO).

[0048] Exemplarily, the thin film transistor includes an N-type transistor. The gate of the N-type transistor is turned on under the control of a positive level (including a high level), and the gate of the N-type transistor is turned off under the control of a negative level. For the N-type transistor, the invalid level is a negative level (including a low level), and the effective voltage is a positive level. In other embodiments, the thin film transistor includes a P-type transistor. The gate of the P-type transistor is turned off under the control of a positive level, and the gate of the P-type transistor is turned on under the control of a negative level. For the P-type transistor, the invalid level is a positive level, and the effective level is a negative level. Among them, the positive level is greater than the negative level. For simplicity, in various embodiments of the present invention, the thin film transistor includes an N-type transistor as an example for explanation, but is not limited to this.

[0049] like Figure 3 and Figure 7 In the illustrated embodiment, the isolation transistor M1 is an N-type transistor with an active level of high and an inactive level of low. A first electrode of the isolation transistor M1 is electrically connected to the first node Q1, a second electrode of the isolation transistor M1 is electrically connected to the second node Q2, and a gate of the isolation transistor M1 is electrically connected to the control signal terminal Ctr. The control signal terminal Ctr outputs a control signal to the gate of the isolation transistor M1. When the control signal includes an active level, the isolation transistor M1 is turned on, thereby connecting the first node Q1 to the second node Q2. When the control signal includes an inactive level, the isolation transistor M1 is turned off, thereby disconnecting the first node Q1 from the second node Q2. Furthermore, by setting the period of the inactive level of the control signal to overlap with the period of the active level of the scan signal, the isolation transistor M1 is turned off when the potential information of the second node Q2 includes a high level, thereby disconnecting the leakage path from the second node Q2 to the first node Q1, the first input unit 110, and the cascade output signal terminal STV, thereby reducing leakage in the gate drive circuit.

[0050] Optionally, based on the above embodiment, Figure 8 Schematic diagram of another shift register circuit provided by an embodiment of the present invention. Figure 8 The shift register 100 further includes a first switching transistor M2 and a first shutoff unit 160. A first electrode of the first switching transistor M2 is electrically connected to the second node Q2. A control terminal of the first shutoff unit 160 is electrically connected to the second node Q2, a first terminal of the first shutoff unit 160 is electrically connected to the second electrode of the first switching transistor M2, and a second terminal of the first shutoff unit 160 is electrically connected to the first voltage terminal VGH.

[0051] Specifically, such as Figure 8In the illustrated embodiment, the gate of the first switching transistor M2 is electrically connected to the third node QB1, the first electrode of the first switching transistor M2 is electrically connected to the second node Q2, and the second electrode of the first switching transistor M2 is electrically connected to the first terminal of the first shut-off unit 160. The first switching transistor M2 is turned on or off under the control of the potential information of the third node Q3. The control terminal of the first shut-off unit 160 is connected to the second node Q2, the first terminal of the first shut-off unit 160 is electrically connected to the second electrode of the first switching transistor M2, and the second terminal of the first shut-off unit 160 is electrically connected to the first voltage terminal VGH. When the potential information of the second node Q2 is at a valid level, the first shut-off unit 160 is turned on, and the first voltage provided by the first voltage terminal VGH is written into the second electrode of the first switch transistor M2. Wherein, when the first voltage is at a valid level, the first electrode of the first switch transistor M2 and the second electrode of the first switch transistor M2 are both at a valid level. When the gate of the first switch transistor M2 is at an invalid level, the valid level applied to the second electrode of the first switch transistor M2 turns off the first switch transistor M2 more completely, thereby reducing leakage through the first switch transistor M2 and reducing leakage in the circuit branch where the second node Q2 and the first switch transistor M2 are located.

[0052] Optionally, based on the above embodiment, Figure 9 1 is a circuit diagram of another shift register provided by an embodiment of the present invention. Figure 9 The shift register further includes a second switching transistor M3, the gates of the first switching transistor M2 and the second switching transistor M3 are electrically connected to the third node QB1, the first electrode of the second switching transistor M3 is electrically connected to the second electrode of the first switching transistor M2, the second electrode of the second switching transistor M3 is electrically connected to the second voltage terminal VGL, and the second voltage terminal VGL and the first voltage terminal VGH provide different fixed voltages.

[0053] Specifically, such as Figure 9As shown, the gates of the first switch transistor M2 and the second switch transistor M3 are both electrically connected to the third node QB1. The first switch transistor M2 and the second switch transistor M3 are turned on or off according to the potential signal provided by the third node QB1. The first electrode of the second switch transistor M3 is electrically connected to the second electrode of the first switch transistor M2. On the one hand, when the gate of the first switch transistor M2 is at an inactive level, the active level applied to the second electrode of the first switch transistor M2 turns off the first switch transistor M2 more completely, reducing leakage through the first switch transistor M2 and reducing leakage in the circuit branch where the second node Q2, the first switch transistor M2, and the second switch transistor M3 are located. On the other hand, the first shutdown unit 160 forms a node interlock with the first switch transistor M2 and the second switch transistor M3. For example, when the third node QB1 is at an inactive level, the first switch transistor M2 and the second switch transistor M3 are both turned off. The second voltage provided by the second voltage terminal VGL cannot be transmitted to the second node Q2 through the second switch transistor M3. The second voltage is at an inactive level. At this time, the second node Q2 maintains an active level. When the third node QB1 is at a valid level, the first switching transistor M2 and the second switching transistor M3 are both turned on, and the second voltage provided by the second voltage terminal VGL is transmitted to the second node Q2 through the second switching transistor M3 and the first switching transistor M2 to reset the potential information of the second node Q2 to an invalid level, thereby ensuring the normal output timing of the shift register.

[0054] Optionally, based on the above embodiment, continue to refer to Figure 9 The first shut-off unit 160 includes a first shut-off transistor M4, a gate of which is electrically connected to the second node Q2, a first electrode of which is electrically connected to the second electrode of the first switch transistor M2, and a second electrode of which is electrically connected to the first voltage terminal VGH. Specifically, when the potential information of the second node Q2 includes an active level, the first shut-off transistor M4 is turned on. The active level applied by the first voltage terminal VGH to the second electrode of the first switch transistor M2 more completely turns off the first switch transistor M2, thereby reducing leakage through the first switch transistor M2 and reducing leakage in the circuit branch where the second node Q2, the first switch transistor M2, and the second switch transistor M3 are located.

[0055] Optionally, based on the above embodiment, Figure 10 1 is a circuit diagram of another shift register provided by an embodiment of the present invention. Figure 10 The input end of the second input unit 130 receives the clock signal. The shift register further includes a third switching transistor M5. The gate of the third switching transistor M5 is electrically connected to the input end of the first input unit 110. The first electrode of the third switching transistor M5 is electrically connected to the control end of the second input unit 130.

[0056] For example, Figure 10 In the illustrated embodiment, the shift register further includes a third switching transistor M5, the first input unit 110 further includes a first transistor M6, and the second input unit 130 further includes a second transistor M7 and a first capacitor C1. A first electrode of the first transistor M6 and a gate of the third switching transistor M5 are both connected to the cascade output signal terminal STV, a gate of the first transistor M6 is electrically connected to the first clock signal terminal CK1, and a second electrode of the first transistor M6 is electrically connected to the first node Q1. A first electrode of the third switching transistor M5 and a gate of the second transistor M7 are connected to a fourth node QB2, and a second terminal of the third switching transistor M5 is electrically connected to the second voltage terminal VGL. A first electrode of the second transistor M7 is electrically connected to the first clock signal terminal CK1, and a second electrode of the second transistor M7 is electrically connected to the third node QB1. A first plate of the first capacitor C1 is electrically connected to the fourth node QB2, and a second plate of the first capacitor C1 is electrically connected to the first electrode of the second transistor M7. The first output unit 120 includes a third transistor M8 and a second capacitor C2. The gate of the third transistor M8 is electrically connected to the second node Q2. The first electrode of the third transistor M8 is electrically connected to the first voltage terminal VGH. The second electrode of the third transistor M8 is electrically connected to the output signal terminal OUT. The first plate of the second capacitor C2 is electrically connected to the second node Q2. The second plate of the second capacitor C2 is electrically connected to the output signal terminal OUT. The second output unit 140 includes a fourth transistor M9 and a third capacitor C3. The first electrode of the fourth transistor M9 is electrically connected to the second voltage terminal VGL. The second electrode of the fourth transistor M9 is electrically connected to the output signal terminal OUT. The gate of the fourth transistor M9 is electrically connected to the third node QB1. The first plate of the third capacitor C3 is electrically connected to the second voltage terminal VGL. The second plate of the third capacitor C3 is electrically connected to the third node QB1. In addition, the shift register further includes a reset transistor M10. The first electrode of the reset transistor M10 is electrically connected to the second voltage terminal VGL. The second electrode of the reset transistor M10 is electrically connected to the third node QB1. The gate of the reset transistor M10 is electrically connected to the first node Q1.

[0057] Based on the above circuit structure, Figure 11 This is another driving timing diagram of a shift register provided by an embodiment of the present invention, see Figure 11, the driving timing of the shift register includes a T0 time period, a T1 time period, a T2 time period, a T3 time period, a T4 time period, and a T5 time period. Among them, the effective level is a high level, and the ineffective level is a low level. In the T0 time period, the first clock signal terminal CKL1 provides a low level, the first transistor M6 is turned off, and the first node Q1 is a low level. The control signal provided by the control signal terminal Ctr is a high level, the isolation transistor M1 is turned on, the second node Q2 is a low level, and the third transistor M8 is turned off. The cascade signal provided by the cascade output signal terminal STV is a high level, the third switching transistor M5 is turned on, the second voltage VGL transmits a low level to the fourth node QB2, and the second transistor M7 is turned off. The first node Q1 is a low level, the reset transistor M10 is turned off, the third node QB1 is a high level, the fourth transistor M9 is turned on, and the output signal terminal OUT outputs a low-level scan signal. In addition, the second node Q2 is a low level and the third transistor M8 is turned off. The third node QB1 is at a high level, the first switch transistor M2 and the second switch transistor M3 are turned on, and the low level provided by the second voltage terminal VGL is transmitted to the second node Q2, keeping the second node Q2 at a low level.

[0058] During time period T1, the cascade signal provided by the cascade output signal terminal STV is at a high level, the third switching transistor M5 is turned on, the second voltage terminal VGL transmits a low level to the fourth node QB2, and the second transistor M7 is turned off. The clock signal provided by the first clock signal terminal CK1 becomes high, the first transistor M6 is turned on, and the high level of the cascade signal is transmitted to the first node Q1, causing the first node Q1 to become high. The control signal provided by the control signal terminal Ctr is high, the isolation transistor M1 is turned on, and the second node Q2 becomes high. When the first node Q1 is high, the reset transistor M10 is turned on, the second voltage terminal VGL provides a low level to the third node QB1, causing the third node QB1 to become low, and the fourth transistor M9 is turned off. Since the second node Q2 is high, the third transistor M8 is turned on, and the first voltage terminal VGH provides a high level to the output signal terminal OUT, causing the output signal terminal OUT to output a high level. During this process, the output signal terminal OUT jumps from a low level to a high level, and through the bootstrap effect of the second capacitor C2, the high level of the second node Q2 is pulled high, so that the second node Q2 is coupled to a higher potential, the third transistor M8 is turned on more thoroughly, and the output signal terminal OUT can fully output a high level.

[0059] During time period T2, the clock signal provided by the first clock signal terminal CK1 goes low, turning off the first transistor M6. The first node Q1 remains high, and the third node QB1 remains low. The control signal output by the control signal terminal Ctr goes low, turning off the isolation transistor M1, maintaining a high node Q2, turning on the third transistor M8, and outputting a high node OUT. The third node QB1 goes low, turning off the first and second switching transistors M2 and M3. The second node Q2 remains high, and the first turn-off transistor M4 turns on. The first voltage terminal VGH transmits a high voltage to the second electrode of the first switching transistor M2. When both the first and second electrodes of the first switching transistor M2 are high and the gate is low, the gate-source voltage of the first switching transistor M2 is very negative. The gate-source voltage minus the threshold voltage is a very negative value, and the first switching transistor M2 is completely turned off. Subsequently, the clock signal provided by the first clock signal terminal CK1 goes high, turning on the first transistor M6. The high voltage level of the cascade signal is transmitted to the first node Q1, which remains high. The control signal provided by the control signal terminal Ctr is at a low level, the isolation transistor M1 is turned off, the second node Q2 maintains a high level, the third node QB1 maintains a low level, and the output signal terminal OUT outputs a high level.

[0060] During time period T3, the cascade signal provided by the cascade output signal terminal STV is at a low level, the third switching transistor M5 is turned off, and the fourth node QB2 remains at a low level. The clock signal provided by the first clock signal terminal CK1 becomes low, the first transistor M6 is turned off, and the first node Q1 remains at a high level. The control signal provided by the control signal terminal Ctr is at a low level, the isolation transistor M1 is turned off, and the second node Q2 remains at a high level. Because the first node Q1 remains at a high level, the reset transistor M10 is turned on, the second power supply terminal VGL transmits a low level to the third node QB1, and the third node QB1 remains at a low level, and the output signal terminal outputs a high level.

[0061] During time period T4, the cascade signal provided by the cascade output signal terminal STV remains low, the third switching transistor M5 is turned off, and the fourth node QB2 remains low. The clock signal provided by the first clock signal terminal CK1 becomes high, turning on the first transistor M6. The low level of the cascade signal is transmitted to the first node Q1, causing the first node Q1 to become low. The control signal provided by the control signal terminal Ctr becomes low, turning off the isolation transistor M1. Since the first node Q1 is low, the reset transistor M10 is turned off. The clock signal provided by the first clock signal terminal CK1 becomes high. Through the bootstrap effect of the first capacitor C1, the fourth node QB2 becomes high. The second transistor M7 turns on, and the high level provided by the first clock signal terminal CK1 is transmitted to the third node QB1. The fourth transistor M9 turns on, and the second voltage terminal VGL provides a low level to the output signal terminal OUT, which then outputs a low level. The third node QB1 becomes high, turning on the first and second switching transistors M2 and M3. The second voltage terminal VGL provides a low level to the second node Q2, resetting the second node Q2 to a low level.

[0062] During time period T5, the clock signal provided by the first clock signal terminal CK1 goes low, the first transistor M6 turns off, the first node Q1 remains low, the control signal provided by the control signal terminal Ctr goes high, the isolation transistor M1 turns on, the second node Q2 remains low, and the first node Q1 remains low. Through the bootstrap effect of the first capacitor C1, the fourth node QB2 goes low, the second transistor M7 turns off, the third node QB1 remains high, the fourth transistor M9 turns on, and the output signal terminal OUT outputs a low level. Because the third node QB1 is high, the first switching transistor M2 and the second switching transistor M3 turn on, and the low level provided by the second voltage terminal VGL is transmitted to the second node Q2, causing the second node Q2 to go low. The third transistor M8 and the first shut-off transistor M4 turn off.

[0063] Optionally, based on the above embodiment, Figure 12 1 is a circuit diagram of another shift register provided by an embodiment of the present invention. Figure 12 The shift register further includes a second shutoff unit 170. A control end of the second shutoff unit 170 is electrically connected to the control end of the second input unit 130, a first end of the second shutoff unit 170 is electrically connected to the second electrode of the third switch transistor M5, and a second end of the second shutoff unit 170 is electrically connected to the first voltage terminal VGH.

[0064] Specifically, such as Figure 12In the illustrated embodiment, the gate of the third switch transistor M5 is electrically connected to the cascade output signal terminal STV, the second electrode of the third switch transistor M5 is electrically connected to the first terminal of the second shutdown unit 170, and the first electrode of the third switch transistor M5 and the control terminal of the second shutdown unit 170 are both electrically connected to the fourth node QB2. Therefore, when the potential information of the fourth node QB2 is at a valid level, the second shutdown unit 170 is turned on, the first voltage terminal VGH provides a valid level to the second electrode of the third switch transistor M5, and the first electrode of the third switch transistor M5 is at a valid level. Thus, when the cascade signal is at an inactive level, the valid level applied to the second electrode of the third switch transistor M5 more completely turns off the third switch transistor M5, reducing leakage through the third switch transistor M5 and reducing leakage at the fourth node QB2 and the circuit branch in which the third switch transistor M5 is located.

[0065] Optionally, based on the above embodiment, continue to refer to Figure 12 The shift register further includes a fourth switch transistor M11. A gate of the fourth switch transistor M11 is electrically connected to the input terminal of the first input unit 110, a first electrode of the fourth switch transistor M11 is electrically connected to the second electrode of the third switch transistor M5, and a second electrode of the fourth switch transistor M11 is electrically connected to the second voltage terminal VGL. The second voltage terminal VGL and the first voltage terminal VGH provide different fixed voltages.

[0066] Specifically, the gates of the third switch transistor M5 and the fourth switch transistor M11 are both electrically connected to the cascade output signal terminal STV. The third switch transistor M5 and the fourth switch transistor M11 are turned on or off according to the cascade signal of the cascade output signal terminal STV. The first electrode of the fourth switch transistor M11 is electrically connected to the second electrode of the third switch transistor M5, and the first end of the second shutdown unit 170 is electrically connected to the second electrode of the third switch transistor M5. In this way, when the gate of the third switch transistor M5 is at an inactive level, the active level applied to the second electrode of the third switch transistor M5 turns off the third switch transistor M5 more completely, reducing leakage through the third switch transistor M5, and reducing leakage in the circuit branch where the fourth node QB2, the third switch transistor M5, and the fourth switch transistor M11 are located.

[0067] Optional, see Figure 12The second shut-off unit 170 includes a second shut-off transistor M12. The gate of the second shut-off transistor M12 is electrically connected to the control terminal of the second input unit 130. The first electrode of the second shut-off transistor M12 is electrically connected to the second electrode of the third switch transistor M5. The second electrode of the second shut-off transistor M12 is electrically connected to the first voltage terminal VGH. When the potential information of the fourth node QB2 includes an active level, the second shut-off transistor M12 is turned on. The active level applied by the first voltage terminal VGH to the second electrode of the third switch transistor M5 more completely turns off the third switch transistor M5, reducing leakage through the third switch transistor M5 and reducing leakage in the circuit branch where the fourth node QB2, the third switch transistor M5, and the fourth switch transistor M11 are located.

[0068] Optionally, based on the above embodiment, Figure 13 This is a circuit diagram of another shift register provided by an embodiment of the present invention, see Figure 13 The shift register further includes a fifth switching transistor M13 and a third shut-off unit 180. A gate of the fifth switching transistor M13 is electrically connected to the control terminal of the second input unit 130, a first electrode of the fifth switching transistor M13 is electrically connected to the third node QB1, and a second electrode of the fifth switching transistor M13 is electrically connected to the output terminal of the second input unit 130. A control terminal of the third shut-off unit 180 is electrically connected to the third node QB1, a first terminal of the third shut-off unit 180 is electrically connected to the second electrode of the fifth switching transistor M13, and a second terminal of the third shut-off unit 180 is electrically connected to the first voltage terminal VGH.

[0069] Specifically, such as Figure 13 In the illustrated embodiment, the second input unit 130 includes a second transistor M7, and the second electrode of the fifth switch transistor M13 is electrically connected to the first electrode of the second transistor M7. The first terminal of the third shutdown unit 180 is electrically connected to the second terminal of the fifth switch transistor M13, and the first electrode of the fifth switch transistor M13 and the control terminal of the third shutdown unit 180 are both electrically connected to the third node QB1. The second terminal of the third shutdown unit 180 is electrically connected to the first voltage terminal VGH. When the potential information of the third node QB1 is at an inactive level, the third shutdown unit 180 is turned on, and the first voltage terminal VGH transmits an active level to the second electrode of the fifth switch transistor M13. That is, when the gate of the fifth switch transistor M13 is at an inactive level, the first and second electrodes of the fifth switch transistor M13 are both at active levels. In this way, the active level applied to the second electrode of the fifth switch transistor M13 by the third shutdown unit 180 more completely turns off the fifth switch transistor M13, reducing leakage through the fifth switch transistor M13 and reducing leakage in the fourth node QB2 and the circuit branch where the fifth switch transistor M13 is located.

[0070] Optionally, based on the above embodiment, continue to refer to Figure 13 The third turn-off unit 180 includes a third turn-off transistor M14, a gate of the third turn-off transistor M14 is electrically connected to the third node QB1, a first electrode of the third turn-off transistor M14 is electrically connected to the second electrode of the fifth switch transistor M13, and a second electrode of the third turn-off transistor M14 is electrically connected to the first voltage terminal VGH.

[0071] Specifically, when the potential information of the third node QB1 includes a valid level, the third turn-off transistor M14 is turned on, the first voltage terminal VGH outputs a first voltage of a valid level to the second electrode of the fifth switch transistor M13, and the first electrode of the fifth switch transistor M13 is electrically connected to the third node QB1. That is, when the second electrode of the fifth switch transistor M13 is at a valid level, the first electrode of the fifth switch transistor M13 is also at a valid level. Then, when the fifth switch transistor M13 is turned off, the effective level applied by the third turn-off transistor M14 to the second electrode of the fifth switch transistor M13 turns off the fifth switch transistor M13 more completely, thereby reducing leakage through the fifth switch transistor M13, and reducing leakage of the fourth node QB2 and the circuit branch where the fifth switch transistor M13 is located.

[0072] Optionally, based on the above embodiment, Figure 14 1 is a circuit diagram of another shift register provided by an embodiment of the present invention. Figure 14 The shift register includes a second voltage terminal VGL, which includes a first sub-voltage terminal VGL1 and a second sub-voltage terminal VGL2. The voltage of the first sub-voltage terminal VGL1 is less than or equal to the voltage of the second sub-voltage terminal VGL2. The second output unit 140 includes an output transistor M16, wherein the gate of the output transistor M16 is electrically connected to the third node QB1, the first electrode of the output transistor M16 is electrically connected to the second sub-voltage terminal VGL2, and the second electrode of the output transistor M16 is electrically connected to the output signal terminal OUT. The shift register also includes a reset transistor M10, wherein the gate of the reset transistor M10 is electrically connected to the first node Q1, the first electrode of the reset transistor M10 is electrically connected to the third node QB1, and the second electrode of the reset transistor M10 is electrically connected to the first sub-voltage terminal VGL1.

[0073] Specifically, such as Figure 14In the illustrated embodiment, the output signal terminal OUT includes a first output signal terminal OUT1 and a second output signal terminal OUT2. The first output unit 120 includes a third transistor M8 and a sixth transistor M15. The first voltage terminal VGH includes a third sub-voltage terminal VGH1 and a fourth sub-voltage terminal VGH2, where the voltage of the third sub-voltage terminal VGH1 is greater than or equal to the voltage of the fourth sub-voltage terminal VGH2. The gates of the third transistor M8 and the sixth transistor M15 are both electrically connected to the second node Q2. The first electrode of the third transistor M8 is electrically connected to the third sub-voltage terminal VGH1, and the second electrode of the third transistor M8 is electrically connected to the first output signal terminal OUT1. The first electrode of the sixth transistor M15 is electrically connected to the fourth sub-voltage terminal VGH2, and the second electrode of the sixth transistor M15 is electrically connected to the second output signal terminal OUT2. The second output unit 140 includes a fourth transistor M9 and an output transistor M16, the gates of the fourth transistor M9 and the output transistor M16 are both electrically connected to the third node QB1, the first electrode of the fourth transistor M9 is electrically connected to the first sub-voltage terminal VGL1, the second electrode of the fourth transistor M9 is electrically connected to the first output signal terminal OUT1, the first electrode of the output transistor M16 is electrically connected to the second sub-voltage terminal VGL2, and the second electrode of the output transistor M16 is electrically connected to the second output signal terminal OUT2.

[0074] Based on the above circuit, when the first node Q1 is at a high level, the reset transistor M10 is turned on. The voltage provided by the first sub-voltage terminal VGL1 is transmitted to the third node QB1 through the reset transistor M10. When the voltage of the second output signal terminal OUT2 is at a high level, the gate-source voltage difference of the output transistor M16 is negative. Even if the threshold voltage of the output transistor M16 drifts negatively, the output transistor M16 can be turned off, thereby improving the operating stability of the shift register. As an example, the voltage provided by the first sub-voltage terminal VGL1 is -10V, and the voltage provided by the second sub-voltage terminal VGL2 is -8V.

[0075] Figure 15 A schematic diagram of a display panel provided by an embodiment of the present invention, referring to Figure 15 The display panel includes the gate driving circuit 200 in the above embodiment. Since the display panel provided by the embodiment of the present invention includes the gate driving circuit 200 in the above embodiment, the shift register 100 in the gate driving circuit 200 can have a smaller leakage.

[0076] For example, refer to Figure 15The display panel includes a display area AA and a non-display area NAA. The gate drive circuit 200 is located in the non-display area NAA, and the pixel drive circuit 330 is located in the display area AA. The plurality of pixel drive circuits 330 are arranged in an array along a first direction X and a second direction Y. The display panel also includes a plurality of scan lines 121, which extend along the first direction X and are arranged along the second direction Y. The output signal terminal OUT of the shift register 100 is electrically connected to a scan line 121. The pixel drive circuit 330 can, for example, adopt a pixel drive circuit known in the art such as 2T1C or 7T1C, and will not be described in detail here.

[0077] Figure 16 A schematic diagram of a display device provided by an embodiment of the present invention. Figure 16 The display device includes any one of the display panels provided in the embodiments of the present invention. The display device can specifically be a mobile phone, a tablet computer, a vehicle-mounted display device, a smart wearable device, and the like.

[0078] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate drive circuit comprising a plurality of cascaded shift registers, characterized in that: The shift register includes a first input unit, a first output unit, a second input unit, a second output unit and an isolation unit; The output end of the first input unit is electrically connected to the first node, the control end of the first input unit receives a clock signal, the control end of the first output unit is electrically connected to the second node, the output end of the second input unit and the control end of the second output unit are electrically connected to the third node, the output end of the first output unit and the output end of the second output unit are electrically connected to the output signal end, and the output signal end outputs a scan signal; A first end of the isolation unit is electrically connected to the first node, a second end of the isolation unit is electrically connected to the second node, and a control end of the isolation unit receives a control signal; A period in which the control signal is at an inactive level overlaps a period in which the scan signal is at an active level.

2. The gate drive circuit according to claim 1, wherein: The clock signal includes a plurality of clock pulses, and a period in which the effective level of the control signal is present overlaps with the plurality of clock pulses.

3. The gate drive circuit according to claim 1, wherein: The clock signal includes a plurality of clock pulses, the clock pulses include a setting pulse, and a start time of the setting pulse is aligned with a start time of an effective level of the scanning signal; The start time of the inactive level of the control signal is after the end time of the setting pulse.

4. The gate driving circuit according to claim 3, wherein: The end time of the inactive level of the control signal is after the end time of the active level of the scanning signal.

5. The gate driving circuit according to claim 1, wherein: The shift register includes an i-th stage shift register and a j-th stage shift register, i and j are positive integers, and i is less than j; The control end of the isolation unit in the i-th stage shift register is electrically connected to the third node of the j-th stage shift register.

6. The gate driving circuit according to claim 5, wherein: The input end of the first input unit in the j-th stage shift register is electrically connected to the i-th stage shift register.

7. The gate driving circuit according to claim 5, wherein: The plurality of shift registers include at least one dummy register and a plurality of scanning shift registers, the first-stage shift register to the M-th-stage shift register are the scanning shift registers, and M is greater than or equal to j; The control end of the isolation unit in the M-th stage shift register is electrically connected to the third node of the dummy register.

8. The gate driving circuit according to claim 1, wherein: The isolation unit includes an isolation transistor, a first electrode of the isolation transistor is electrically connected to the first node, a second electrode of the isolation transistor is electrically connected to the second node, and a gate of the isolation transistor receives the control signal.

9. The gate driving circuit according to claim 1, wherein: The shift register further includes a first switching transistor and a first turn-off unit; The first electrode of the first switching transistor is electrically connected to the second node; The control end of the first turn-off unit is electrically connected to the second node, the first end of the first turn-off unit is electrically connected to the second electrode of the first switch transistor, and the second end of the first turn-off unit is electrically connected to the first voltage end.

10. The gate driving circuit according to claim 9, wherein: The shift register further includes a second switching transistor; The gates of the first switching transistor and the second switching transistor are electrically connected to the third node, the first electrode of the second switching transistor is electrically connected to the second electrode of the first switching transistor, the second electrode of the second switching transistor is electrically connected to a second voltage terminal, and the second voltage terminal and the first voltage terminal provide different fixed voltages.

11. The gate driving circuit according to claim 9, wherein: The first turn-off unit includes a first turn-off transistor, a gate of the first turn-off transistor is electrically connected to the second node, a first electrode of the first turn-off transistor is electrically connected to the second electrode of the first switching transistor, and the second electrode of the first turn-off transistor is electrically connected to the first voltage terminal.

12. The gate driving circuit according to claim 1, wherein: An input end of the second input unit receives the clock signal; The shift register further includes a third switch transistor, a gate of the third switch transistor is electrically connected to the input end of the first input unit, and a first electrode of the third switch transistor is electrically connected to the control end of the second input unit.

13. The gate driving circuit according to claim 12, wherein: The shift register further includes a second shut-off unit; The control end of the second shutoff unit is electrically connected to the control end of the second input unit, the first end of the second shutoff unit is electrically connected to the second electrode of the third switch transistor, and the second end of the second shutoff unit is electrically connected to the first voltage end.

14. The gate driving circuit according to claim 13, wherein: The shift register further includes a fourth switching transistor; The gate of the fourth switching transistor is electrically connected to the input end of the first input unit, the first electrode of the fourth switching transistor is electrically connected to the second electrode of the third switching transistor, the second electrode of the fourth switching transistor is electrically connected to the second voltage end, and the second voltage end and the first voltage end provide different fixed voltages.

15. The gate driving circuit according to claim 13, wherein: The second turn-off unit includes a second turn-off transistor, a gate of the second turn-off transistor is electrically connected to the control end of the second input unit, a first electrode of the second turn-off transistor is electrically connected to the second electrode of the third switching transistor, and a second electrode of the second turn-off transistor is electrically connected to the first voltage end.

16. The gate driving circuit according to claim 1, wherein: The shift register further includes a fifth switching transistor and a third turn-off unit; The gate of the fifth switch transistor is electrically connected to the control terminal of the second input unit, the first electrode of the fifth switch transistor is electrically connected to the third node, and the second electrode of the fifth switch transistor is electrically connected to the output terminal of the second input unit; The control end of the third turn-off unit is electrically connected to the third node, the first end of the third turn-off unit is electrically connected to the second electrode of the fifth switch transistor, and the second end of the third turn-off unit is electrically connected to the first voltage end.

17. The gate driving circuit according to claim 16, wherein: The third turn-off unit includes a third turn-off transistor, a gate of the third turn-off transistor is electrically connected to the third node, a first electrode of the third turn-off transistor is electrically connected to the second electrode of the fifth switch transistor, and a second electrode of the third turn-off transistor is electrically connected to the first voltage end.

18. The gate driving circuit according to claim 1, wherein: The shift register includes a second voltage terminal, the second voltage terminal includes a first sub-voltage terminal and a second sub-voltage terminal, and the voltage of the first sub-voltage terminal is less than or equal to the voltage of the second sub-voltage terminal; The second output unit includes an output transistor, a gate of the output transistor is electrically connected to the third node, a first electrode of the output transistor is electrically connected to the second sub-voltage terminal, and a second electrode of the output transistor is electrically connected to the output signal terminal; The shift register further includes a reset transistor, a gate of the reset transistor is electrically connected to the first node, a first electrode of the reset transistor is electrically connected to the third node, and a second electrode of the reset transistor is electrically connected to the first sub-voltage terminal.

19. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 18.

20. A display device, characterized in that: The display panel according to claim 19 is included.

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