Signal repairing circuit, signal repairing method and display panel

Abstract

The invention discloses a signal repairing circuit, a signal repairing method and a display panel, and belongs to the technical field of display. The signal repairing circuit comprises at least two signal sending modules, compensation modules, input lines and output lines, the number of the signal sending modules is at least two, the input lines and the output lines are arranged in pairs, and a pair of input lines and output lines is correspondingly arranged between each signal sending module and a signal receiving module; when the signal receiving module receives the signal of one signal sending module abnormally, the other signal output modules sending the normal signal are used for transmitting the normal signal to the compensation module through the input line; and the compensation module is used for compensating a normal signal and transmitting a compensated compensation signal to the signal receiving module through an output line. Thus, when the output signal of the signal sending module on one side is abnormal, the normal signal on the other side can be compensated through the compensation module and then input into the display area, and abnormal display of the product is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a signal repair circuit, a signal repair method, and a display panel. Background Art

[0002] During the manufacturing process of display panels, various defective panels will be produced due to poor process, among which the defects related to the gate driver less (GDL) circuit account for a higher proportion. GDL defects will cause abnormal output of the row scan signal, which will be reflected as dark horizontal lines on the screen. To address this problem, the existing technology can only downgrade or directly scrap products with such problems. Therefore, these defective products cannot contribute economic benefits to the company, resulting in a decrease in production yield and an inability to further reduce production costs. Summary of the Invention

[0003] The embodiments of the present application provide a signal repair circuit, a signal repair method, and a display panel to solve the technical problem of display abnormality caused by GDL abnormality.

[0004] According to one aspect of an embodiment of the present application, a signal repair circuit is provided, including: a signal sending module, a compensation module, an input line and an output line, wherein there are at least two signal sending modules, and the input line and the output line are arranged in pairs, the signal sending module is used to connect with the signal receiving module in the display area, the input line and the output line are both connected to the compensation module, and a pair of the input line and the output line are correspondingly arranged between each of the signal sending modules and the signal receiving module; when the signal receiving module receives an abnormal signal from one of the signal sending modules, the other signal output modules that send normal signals are used to transmit the normal signal to the compensation module through the input line; the compensation module is used to compensate for the normal signal and transmit the compensated signal to the signal receiving module through the output line.

[0005] In one possible embodiment, the compensation module includes: a comparator; a first input end of the comparator is connected to the input line for inputting the normal signal; a second input end of the comparator is used to input a reference signal; an output end of the comparator is connected to the output line for outputting a high level when the voltage of the normal signal is greater than the voltage of the reference signal, and outputting a low level when the voltage of the normal signal is less than the voltage of the reference signal.

[0006] In one possible embodiment, the compensation module further includes: a first variable resistor and a second variable resistor; the input line is connected to the first input end through the first variable resistor, and / or the signal line for transmitting the reference signal is connected to the second input end through the second variable resistor.

[0007] In one possible embodiment, the compensation module further includes: an N-type metal-oxide-semiconductor field-effect transistor (NMOS) transistor and a gating unit; the output end of the comparator is connected to the gate of the NMOS transistor; the source of the NMOS transistor is connected to the output line; the drain of the NMOS transistor is connected to the gating unit, and the gating unit is used to select a target signal matching the target location of the anomaly and input it into the drain, so that the falling edge of the signal output by the source is consistent with the falling edge of the target signal.

[0008] In a possible implementation, the compensation module further includes: a third variable resistor; and the source of the NMOS transistor is connected to the output line via the third variable resistor.

[0009] In one possible embodiment, the compensation module further includes: an impedance matching unit, the impedance matching unit including: an input port, a plurality of resistor and capacitor modules connected in series with the input port, and a plurality of rows of transmission channels connected in parallel; the input port is connected to the source of the NMOS transistor, the transmission channel is connected to the output line, and a row of the transmission channel is connected between every two adjacent resistor and capacitor modules; each row of the transmission channels includes at least one target transistor connected in series; the gate of the target transistor is used to input a target control signal, and the target control signal is used to control a row of target transmission channels in the plurality of rows of transmission channels to be turned on, so that the signal output from the source passes through at least one resistor and capacitor module between the target transmission channel and the input port, and is then transmitted to the output line through the target transmission channel; wherein the position of the target transmission channel in the plurality of rows of transmission channels matches the target position where the abnormality occurs.

[0010] In one possible embodiment, the target control signal includes: multiple first control signals and multiple second control signals, the first control signals and the second control signals are the same in number, and each second control signal is an inverted signal of a first control signal; the gate of each of the target transistors is used to input a first control signal or a second control signal; based on different combinations of the multiple first control signals and the multiple second control signals, a target transmission channel is controlled to be turned on.

[0011] According to a second aspect of an embodiment of the present application, a signal repair method is also provided, which is applied to the signal repair circuit described in any one of the first aspects above, and the method includes: detecting whether there is an abnormality in the signal reception of the signal receiving module; in response to an abnormality in the signal reception of the signal receiving module, determining the target position where the abnormality is located and the target row where the target position is located; disconnecting the connection between the signal sending module and the signal receiving module on both sides of the target row, connecting the signal sending module and the input line on the opposite side of the target position of the target row to transmit the normal signal to the compensation module; and connecting the output lines on both sides of the target row to the signal receiving module, so that the compensation signal output by the compensation module is transmitted to the signal receiving module via the output lines on both sides of the target row.

[0012] In one possible embodiment, the compensation module further includes: an impedance matching unit; after connecting the output lines on both sides of the target row to the signal receiving module, the method further includes: determining a position of a target transmission channel among multiple rows of transmission channels of the impedance matching unit based on the target row; the position of the target transmission channel matches the target row; and adjusting a target control signal based on the position of the target transmission channel to control all target transistors in the target transmission channel to conduct through the target control signal.

[0013] According to a third aspect of the embodiments of the present application, a display panel is also provided, comprising: a display area and a non-display area, the non-display area being arranged around the display area, the display area being provided with sub-pixels arranged in an array, the non-display area being provided with a signal repair circuit, and the signal repair circuit being the signal repair circuit described in any one of the aforementioned first aspects; the signal sending module being a gate driving circuit, the gate driving circuit being arranged in the non-display areas on both sides of the display area, the signal receiving module being the sub-pixel of the display panel, the compensation module being arranged in the non-display area below the display area, and the input line and the output line being arranged between the gate driving circuit and the sub-pixel.

[0014] The embodiments of the present application propose a signal repair circuit, a signal repair method, and a display panel. The signal repair circuit includes: a signal sending module, a compensation module, an input line, and an output line. There are at least two signal sending modules, and the input line and the output line are arranged in pairs. The signal sending module is used to connect with the signal receiving module in the display area, and the input line and the output line are both connected to the compensation module. A pair of the input line and the output line is correspondingly arranged between each signal sending module and the signal receiving module; when the signal receiving module receives an abnormal signal from one of the signal sending modules, the other signal output modules that send normal signals are used to transmit the normal signal to the compensation module through the input line; the compensation module is used to compensate for the normal signal and transmit the compensated signal to the signal receiving module through the output line. In this way, for bilaterally driven display products, when the signal sending module on one side outputs an abnormal signal, the normal signal output from the other side is introduced into the compensation module through the input line and the output line for compensation. The compensated normal signal is transmitted to the signal receiving module in the display area through the output lines on both sides for display operation. This can eliminate the delay in signal transmission, avoid uneven display caused by differences in signals on both sides, and avoid problems such as abnormal screen display caused by abnormal signals input into the display area, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 This is a schematic diagram of the structure of a signal repair circuit provided in an embodiment of the present application;

[0017] Figure 2 This is a schematic structural diagram of a compensation module provided in an embodiment of the present application;

[0018] Figure 3 This is a schematic structural diagram of a compensation module provided in an embodiment of the present application;

[0019] Figure 4 This is a schematic structural diagram of a compensation module provided in an embodiment of the present application;

[0020] Figure 5 This is a schematic structural diagram of a gating unit provided in an embodiment of the present application;

[0021] Figure 6 This is a schematic structural diagram of a compensation module provided in an embodiment of the present application;

[0022] Figure 7This is a schematic structural diagram of an impedance matching unit provided in an embodiment of the present application;

[0023] Figure 8 This is a signal transmission schematic diagram of an impedance matching unit provided in an embodiment of the present application;

[0024] Figure 9 This is a flow chart of a signal repair method provided in an embodiment of the present application;

[0025] Figure 10 is a structural diagram of a display panel provided in an embodiment of the present application;

[0026] Figure 11 This is a structural diagram of a compensation module provided in an embodiment of the present application.

[0027] Description of Reference Numerals

[0028] 1. Signal sending module; 2. Compensation module; 3. Input line; 4. Output line; 5. Signal receiving module; 21. Comparator; 22. First variable resistor; 23. Second variable resistor; 24. NMOS transistor; 25. Selection unit; 26. Switch circuit; 27. Third variable resistor; 28. Impedance matching unit; 281. Input port; 282. Resistor and capacitor module; 283. Transmission channel; 284. Target transistor. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] This embodiment provides a signal repair circuit. Figure 1 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 1 As shown, the signal repair circuit may include: a signal sending module 1, a compensation module 2, an input line 3 and an output line 4, wherein there are at least two signal sending modules 1, and the input line 3 and the output line 4 are arranged in pairs. The signal sending module 1 is used to connect to the signal receiving module 5 in the display area, and the input line 3 and the output line 4 are both connected to the compensation module 2. A pair of the input line 3 and the output line 4 is correspondingly arranged between each of the signal sending modules 1 and the signal receiving module 5;

[0032] When the signal receiving module 5 receives an abnormal signal from the signal sending module 1, the other signal output modules that send normal signals are used to transmit the normal signals to the compensation module 2 through the input line 3;

[0033] The compensation module 2 is used to compensate the normal signal and transmit the compensated signal to the signal receiving module 5 through the output line 4 .

[0034] In this embodiment, the signal repair circuit can be applied to a display device such as a display panel. For example, the display panel is a bilaterally driven panel, and there are signal sending modules 1 on both the left and right sides of the display area for providing a driving signal to the display area. The signal sending module 1 can be a gate drive circuit. The compensation module 2 can be arranged in a printed circuit board assembly (PCBA), for example, in a non-display area of the display panel. The signal sending module 1 and a pair of input lines 3 and output lines 4 can be respectively arranged on both sides of the display area, i.e., the active area (AA) of the display panel, for example, there is an input line 3 and an output line 4 on the first side and the second side. When the first side is the left side, the second side is the right side; when the first side is the right side, the second side is the left side.

[0035] In one embodiment, the gate driver circuit may be a gate driver less (GDL) circuit, which may be located in a gate driver integrated (GOA) area on an array substrate. For example, each row of the display corresponds to a GOA unit, and a GOA unit corresponds to one or more GDL circuits.

[0036] In one embodiment, when the signal receiving module 5 receives a signal abnormally from one of the signal sending modules 1, the signal receiving module 5 may refer to the signal output by the signal sending module 1 when the signal receiving module 5 receives a signal abnormally from the signal sending module 1 on one side. The signal output module that sends a normal signal may refer to the signal output module that sends a normal signal on the other side. For example, when the signal abnormality occurs in the signal of the signal sending module 1 on the first side, the signal output module that sends a normal signal is the signal sending module 1 on the second side.

[0037] In one embodiment, the signal output module on the other side that sends a normal signal may refer to a signal output module on the other side of the same row as the abnormal signal sending module 1 .

[0038] In one embodiment, the other signal output modules that send normal signals are used to transmit the normal signals to the compensation module 2 through the input line 3, which may refer to the other signal output modules that send normal signals being connected to the input line 3 and being used to transmit the normal signals to the compensation module 2 through the input line 3.

[0039] In one embodiment, the signal transmitting module 1 is connected to the signal receiving module 5 in the display area, which may mean that the signal transmitting module 1 is connected to the signal receiving module 5 in the display area via a scan line. The scan line can be connected together with the input line 3 at the output end of the signal transmitting module 1. The scan line is used to transmit the signal output by the signal transmitting module 1 to the display area of the display panel for display operation. Exemplarily, the GOA area where the signal transmitting module 1 is located can be located on the left and / or right side of the display area.

[0040] In one embodiment, when the signal output by the signal sending module 1 is normal, the input lines 3 on both sides of the display area are disconnected from the signal sending module 1, and the output lines 4 on both sides are disconnected from the scan lines. The normal signal output by the signal sending module 1 is transmitted to the display area through the scan lines for display operation.

[0041] When the signal receiving module 5 receives a signal from the signal sending module 1 abnormally, for example, when the signal output by the signal sending module 1 on the first side is abnormal, the connection between the signal sending modules 1 on both sides of the target row where the abnormality is located and the scan line is disconnected, and the connection between the input line 3 on the second side and the output end of the signal sending module 1 is turned on, so as to transmit the normal signal output by the signal sending module 1 on the second side of the target row to the compensation module 2; the connection between the output lines 4 on both sides and the scan lines is turned on, and the compensation module 2 transmits the compensated compensation signal to the scan line through the output lines 4 on both sides, so as to transmit it to the signal receiving module 5.

[0042] Here, the target row where the abnormality occurs may refer to the target row where the signal sending module 1 where the abnormality occurs is located, for example, the nth row, etc., where n is a positive integer.

[0043] In one embodiment, the output line 4 can be connected to the scanning line through a variable resistor in series. The variable resistor can be a sliding rheostat. The compensated signal can be adjusted by adjusting the variable resistor. For example, it can be adjusted according to the position of the signal sending module 1 where the abnormality occurs, so as to facilitate the matching of the compensated signal with the position where the abnormality occurs, so that the display of the row where the abnormality occurs is consistent with the display of the surrounding rows, thereby reducing uneven brightness.

[0044] In one embodiment, the compensation module 2 can output a compensated signal by comparing the normal signal with a reference signal, wherein the reference signal can be a predetermined high-level signal VGH. The compensated signal is high when the voltage of the normal signal is greater than the reference signal, and is low when the voltage of the normal signal is less than the reference signal.

[0045] In one embodiment, the input line 3 can be connected to the output ends of one or more signal sending modules 1 on the side where the input line 3 is located. For example, an input line 3 on the left side of the display area is connected to the output ends of all signal sending modules 1 located on the left side of the display area, and / or, an input line 3 on the right side of the display area is connected to the output ends of all signal sending modules 1 located on the right side of the display area, thereby reducing the wiring and achieving signal repair of all signal sending modules 1 through one line.

[0046] In this way, for a bilaterally driven display product, when the signal sending module 1 on one side outputs an abnormal signal, the normal signal output from the other side is introduced into the compensation module 2 for compensation. The compensated normal signal is transmitted to the scan line through the output lines 4 on both sides for display operation. This can eliminate the delay in signal transmission, avoid uneven display caused by differences in signals on both sides, and avoid problems such as abnormal screen display caused by abnormal signals input into the scan line display, thereby improving product yield.

[0047] This embodiment provides a signal repair circuit. Figure 2 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 2 As shown, the compensation module 2 in the signal repair circuit may include: a comparator 21;

[0048] The first input end of the comparator 21 is connected to the input line 3 for inputting the normal signal; the second input end of the comparator 21 is used to input the reference signal; the output end of the comparator 21 is connected to the output line 4 for outputting a high level when the voltage of the normal signal is greater than the voltage of the reference signal, and outputting a low level when the voltage of the normal signal is less than the voltage of the reference signal.

[0049] In one embodiment, the comparator 21 may be an operational amplifier (OP), wherein the first input terminal may be a positive input terminal (+IN), and the second input terminal may be a negative input terminal (-IN). The reference signal may be a DC signal generated based on a predetermined high level VGH, for example, the reference signal Vref may be obtained by dividing the predetermined high level signal.

[0050] Here, the first input terminal of the comparator 21 is connected to the input lines 3 on both sides, for receiving a normal signal transmitted by any one of the input lines 3. The output terminal (OUT) of the comparator 21 is connected to the output lines 4 on both sides, for simultaneously transmitting the compensated signal to the output lines 4 on both sides for transmission to the signal receiving module 5.

[0051] In one embodiment, the signal line transmitting the reference signal is connected to the second input terminal and can be grounded via a voltage divider resistor, thereby preventing the compensated signal output based on the excessive VGH voltage of the reference signal from affecting the display effect.

[0052] In one embodiment, the normal signal Gn-in is input to the positive input terminal, and the reference signal Vref is input to the negative input terminal. The comparator 21 compares the voltage values of the reference signal and the normal signal, and outputs a high level when the voltage of the normal signal is greater than or equal to the voltage of the reference signal, and outputs a low level when the voltage of the normal signal is less than the voltage of the reference signal.

[0053] Because of the RC impedance of the wiring, the normal signal output by signal transmission module 1 under normal conditions should be a square wave. By comparing it with a reference signal based on a predetermined high level, comparator 21 outputs a high level when the normal signal is above the predetermined high level, and a low level when the normal signal is below the predetermined high level. The output of the output terminal is a standard square wave, consistent with the normal signal output by signal transmission module 1 under normal conditions. This eliminates the attenuation of the normal signal when it is transmitted to compensation module 2, reducing the impact of attenuation on the display.

[0054] This embodiment provides a signal repair circuit. Figure 3 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 3 As shown, the compensation module 2 in the signal repair circuit further includes: a first variable resistor 22 and a second variable resistor 23;

[0055] The input line 3 is connected to the first input end via a first variable resistor 22 , namely R1 , and / or the signal line for transmitting the reference signal is connected to the second input end via a second variable resistor 23 , namely R2 .

[0056] In one embodiment, the first variable resistor 22 may be connected in series between the first input terminal and the input line 3 . For example, the first variable resistor 22 may be a sliding resistor.

[0057] In one embodiment, the maximum resistance and resistance adjustment of the first variable resistor 22 can be determined according to the voltage value of at least one of the reference signal and the normal signal, so that the input normal signal matches the circuit.

[0058] In this way, the input normal signal is isolated from the DC reference signal by connecting a variable resistor in series, so as to prevent the DC signal from affecting the pulse waveform of the abnormal signal and thus affecting the normal output of the repaired signal.

[0059] In one embodiment, the second variable resistor 23 can be connected in series between the second input terminal and the signal line transmitting the reference signal. For example, the second variable resistor 23 can be a sliding resistor, and the signal line transmitting the reference signal can be a signal line connected to a predetermined high-level VGH signal.

[0060] In one embodiment, the second variable resistor 23 is used to divide the VGH voltage to obtain a reference signal. For example, the maximum resistance or resistance adjustment of the second variable resistor 23 can be determined according to the voltage value of at least one of the reference signal and the normal signal to be obtained.

[0061] In one embodiment, the maximum resistance or resistance adjustment of the second variable resistor 23 can also be determined according to the type of display panel and / or the position of the abnormal signal sending module 1. For example, the position of the abnormal signal sending module 1 can refer to the target position of the abnormal signal sending module 1 and the target row where the target position is located, such as the nth row.

[0062] In one embodiment, the signal line transmitting the reference signal is connected to the second input terminal and can also be grounded through a voltage-dividing resistor, thereby improving the voltage-dividing effect based on the second variable resistor 23 and the voltage-dividing resistor, and also preventing the repaired signal output due to excessive reference signal voltage from affecting the display effect.

[0063] In this way, the trigger point can be adjusted by means of resistor voltage division, so that the reference signal can be flexibly adjusted to meet the needs of different models and different abnormal locations.

[0064] This embodiment provides a signal repair circuit. Figure 4 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 4 As shown, the compensation module 2 in the signal repair circuit further includes: an NMOS transistor 24 and a gating unit 25;

[0065] The output end of the comparator 21 is connected to the gate of the NMOS transistor 24; the source of the NMOS transistor 24 is connected to the output line 4; the drain of the NMOS transistor 24 is connected to the gating unit 25, and the gating unit 25 is used to select a target signal matching the target position where the abnormality is located and input it into the drain, so that the falling edge of the signal output by the source is consistent with the falling edge of the target signal.

[0066] In this embodiment, the NMOS transistor 24 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS).

[0067] In one embodiment, the signal output from the output end of the comparator 21 is used as a signal to drive the gate of the NMOS transistor 24. At this time, the signal output by the comparator 21 is delayed compared with the original normal signal, that is, the falling edge of the signal output by the comparator 21 will be later than the falling edge of the original normal signal. At this time, if the signal output by the comparator 21 is directly transmitted to the display area, the late falling edge will cause the signal to mischarge the display of the next row, affecting the normal display effect.

[0068] Therefore, the drain of the NMOS transistor 24 inputs a target signal that matches the location of the abnormality through the selection unit 25, wherein the target signal can be a target clock signal, that is, the clock signal (CLK) used in the signal sending module 1 where the abnormality occurs. Then, when the signal output by the comparator 21, that is, the gate is high, the NMOS transistor 24 is turned on, the source and drain are turned on, and the signal waveform output by the source will be pulled to a high level. The falling edge of the target clock signal is consistent with the falling edge of the original normal signal output by the signal sending module 1. When the waveform of the target clock signal input by the drain falls, the source output signal will follow the falling edge of the signal input by the drain, so that the signal output by the source of the NMOS transistor 24 maintains the same falling moment as the original input normal signal, eliminating the delay caused by the compensation module 2 on the normal signal, and avoiding the mischarging of the next line of display due to the falling edge delay.

[0069] In one embodiment, Figure 5 As shown, the gating unit 25 may include a predetermined number of switch circuits 26 , each switch circuit 26 is configured to input a clock signal, and different switch circuits 26 input different clock signals.

[0070] In one embodiment, the predetermined number may be equal to the number of clock signals corresponding to the display area in the display panel where the signal sending module 1 is located. Here, the number of clock signals may refer to the number of clock signals used in one clock cycle.

[0071] For example, the number of clock signals corresponding to the display area is 8, that is, when the above-mentioned signal repair circuit is applied to an 8CLK product, the selection unit 25 includes 8 switching circuits 26. After determining the target clock signal that matches the target row where the abnormality is located, the switching circuit 26 corresponding to the target clock signal is turned on, while the switching circuits 26 corresponding to other clock signals remain disconnected, thereby transmitting the target clock signal to the drain of the NMOS transistor 24.

[0072] In one embodiment, each clock signal is connected to the drain of the NMOS transistor 24 through a switch circuit 26. For example, the first clock signal CLK1 is connected to the drain through the first switch circuit, the second clock signal CLK2 is connected to the drain through the second switch circuit, the third clock signal CLK3 is connected to the drain through the third switch circuit...CLK8 is connected to the drain through the eighth switch circuit, and so on. If it is determined that the target clock signal matching the row where the abnormality is located is CLK8, the eighth switch circuit is turned on to transmit CLK8 to the drain.

[0073] In one embodiment, the target location of the anomaly may refer to the target row where the abnormal signal sending module 1 is located. For example, the target clock signal may be determined based on the target row where the abnormal signal sending module 1 is located, the number of clock signals corresponding to the display area, and the clock signal corresponding to the first row of the display area.

[0074] In one embodiment, a switch circuit 26 includes a controllable switch, which can determine the corresponding target clock signal according to the target row where the abnormal signal sending module 1 is located, and control the switch circuit 26 where the target clock signal is located to be turned on through the controllable switch so that the target clock signal is input to the drain.

[0075] In this way, for the signal sending module 1 with abnormalities at different positions, its corresponding clock signal can be selected as the drain input of the NMOS transistor 24, so that the signal output from the source of the NMOS transistor 24 maintains the same falling time as the original input normal signal, eliminating the delay caused by the compensation module 2 to the normal signal, and avoiding mischarging of the next line of display due to the falling edge delay.

[0076] This embodiment provides a signal repair circuit. Figure 6 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 6 As shown, the compensation module 2 in the signal repair circuit further includes: a third variable resistor 27 , namely R3 ; the source of the NMOS transistor 24 is connected to the output line 4 through the third variable resistor 27 .

[0077] Here, connecting the output lines 4 refers to connecting the output lines 4 on both sides of the display area.

[0078] In one embodiment, the third variable resistor 27 may be a sliding resistor. The maximum resistance value and resistance adjustment of the third variable resistor 27 may be determined based on the target location of the abnormality, for example, based on the display effects of other rows adjacent to the target row where the abnormal signal sending module 1 is located. Here, the display effect may include display brightness, display color, etc.

[0079] In one embodiment, the output line 4 is connected to the signal receiving module 5 and may be grounded via a filter capacitor to filter out high-frequency noise and reduce noise interference.

[0080] In this way, by adding a variable resistor to adjust the wiring impedance, the compensated signal matches the display effect of the rows around the abnormal signal sending module 1, avoiding uneven display brightness and reducing inconsistent display brightness with adjacent positions.

[0081] Because the output lines enter from above the display area, the impedance matching requirements required for compensation vary depending on where the anomaly is located within the display area. Manually adjusting the impedance using the third variable resistor has drawbacks such as poor accuracy and the potential for electrostatic damage.

[0082] Therefore, this embodiment provides a signal repair circuit. Figure 7 This is a schematic diagram of the structure of a signal repair circuit provided by an embodiment of the present application. Figure 7 As shown, the compensation module 2 further includes: an impedance matching unit 28, the impedance matching unit 28 includes: an input port 281, a plurality of resistor and capacitor modules 282 connected in series with the input port 281, and a plurality of transmission channels 283 connected in parallel;

[0083] The input port 281 is connected to the source of the NMOS transistor 24, the transmission channel 283 is connected to the output line 4, and a row of the transmission channels 283 is connected between every two adjacent resistor and capacitor modules 282; each row of the transmission channels 283 includes at least one target transistor 284 connected in series;

[0084] The gate of the target transistor 284 is used to input a target control signal, and the target control signal is used to control a row of target transmission channels among the multiple rows of transmission channels 283 to be turned on, so as to transmit the signal output by the source to the output line 4 through the target transmission channel after passing through at least one resistor and capacitor module 282 between the target transmission channel and the input port 281;

[0085] The position of the target transmission channel in the multi-row transmission channels 283 matches the target position where the abnormality occurs.

[0086] Here, the multiple rows of transmission channels 283 can be arranged in multiple rows along the horizontal direction, and the multiple resistor and capacitor modules 282, i.e., RC modules, can be arranged in a column along the vertical direction with the input port 281, with a row of transmission channels 283 connected between every two adjacent resistor and capacitor modules 282.

[0087] In one embodiment, the resistor-capacitor module 282 includes a resistor and a capacitor, the resistor and the capacitor are connected in parallel, and one end of the capacitor is grounded.

[0088] In one embodiment, the number of the resistor and capacitor modules 282 is the same as the number of the transmission channels 283 , for example, both are 8.

[0089] In one embodiment, each row of transmission channels 283 may include one or more target transistors 284 . For example, multiple rows of transmission channels 283 may include the same number of target transistors 284 , and target transistors 284 included in different transmission channels 283 may be controlled by different target control signals.

[0090] In one embodiment, the target transistor 284 may be an NMOS transistor, or a P-type metal-oxide-semiconductor field-effect transistor (PMOS). For example, the target transistor 284 is a PMOS transistor, and when the target control signal is low, the target transistor 284 is turned on, and when the target control signal is high, the target transistor 284 is turned off.

[0091] In one embodiment, when an abnormality occurs at a target position, that is, during the compensation process of a normal signal, only one target transmission channel is turned on, that is, the signal output from the source of the NMOS transistor 24 is transmitted to the output line 4 only through one target transmission channel.

[0092] In one embodiment, different transmission channels 283 and input ports 281 have different numbers of resistor and capacitor modules 282 connected in series. A transmission channel 283 located lower than the input port 281 has more resistor and capacitor modules 282 connected in series.

[0093] For example, one resistor and capacitor module C1R1 is connected in series between the first row of transmission channels 283 and the input port 281. Two resistor and capacitor modules C1R1 and C2R2 are connected in series between the second row of transmission channels 283 and the input port 281. Eight resistor and capacitor modules C1R1, C2R2, through C8R8 are connected in series between the eighth row of transmission channels 283 and the input port 281. The greater the number of resistor and capacitor modules 282 connected in series between a transmission channel 283 and the input port 281, the greater the impedance corresponding to that transmission channel 283.

[0094] In one embodiment, the position of the target transmission channel in the multi-row transmission channel 283 matches the target position where the exception occurs, which may refer to the position of the target transmission channel in the multi-row transmission channel 283 corresponding to the position of the target row where the exception occurs in the display area.

[0095] For example, the target row is located at the top in the display area, and the selected target transmission channel is also located at the top in the multi-row transmission channels, such as selecting the 1st row or the 2nd row; the target row is located in the middle, and the selected target transmission channel is also located in the middle in the multi-row transmission channels, such as selecting the 4th row; the target row is located in the bottom of the display area, and the selected target transmission channel is also located at the bottom in the multi-row transmission channels, such as selecting the 7th row or the 8th row.

[0096] In this way, based on the relative position of the abnormality in the display area, a target transmission channel that matches the position is selected. When the impedance matching requirements required for different abnormal positions are different, the impedances provided by the resistance and capacitance modules corresponding to different target transmission channels are different, thereby achieving accurate and flexible impedance matching, improving accuracy, and avoiding low accuracy and electrostatic damage caused by manual adjustment of variable resistors.

[0097] In some embodiments, the target control signal includes: a plurality of first control signals and a plurality of second control signals, the first control signals and the second control signals are the same in number, and each second control signal is an inverted signal of a first control signal;

[0098] The gate of each target transistor 284 is used to input a first control signal or a second control signal; based on different combinations of the multiple first control signals and the multiple second control signals, a target transmission channel is controlled to be turned on.

[0099] Here, controlling a target transmission channel to be turned on may refer to controlling all target transistors 284 in a target transmission channel to be turned on. A first control signal or a second control signal may be input to multiple target transistors 284 located in the same column, and the multiple target transistors 284 located in the same column may be located in different multiple transmission channels 283.

[0100] For example, Figure 7 and 8 As shown, there are three first control signals and three second control signals. The first control signal includes D2, D1 and D0, and the second control signal includes the inverted signal of D2. The inverted signal of D1 and the inverted signal of D0 C1R1, C2R2 . . . C8R8 are the first to eighth resistor-capacitor modules 282 , respectively. GN-IN is the input signal, ie, the signal output from the source of the NMOS transistor 24 . GN-OUT is the signal output to the output line 4 .

[0101] In one embodiment, different combinations may refer to different phase combinations. By controlling the phase combinations of multiple first control signals, multiple second control signals can be controlled simultaneously. Each combination of multiple first control signals only corresponds to one transmission channel 283 being turned on.

[0102] For example, when the target position or target row where the abnormality occurs corresponds to the middle of the display area, the phases of D2, D1 and D0 are controlled to be 1, 0 and 0 respectively, and the second control signals are 0, 1 and 1 respectively. Figure 8 As shown, when the target transistor 284 is a PMOS transistor, only all target transistors 284 in the fourth transmission channel of the multi-row transmission channel 283 are turned on, that is, the fourth transmission channel is turned on as the target transmission channel, and at least one target transistor 284 in the remaining transmission channels is turned off, that is, the remaining transmission channels remain closed. At this time, the source output signal of the NMOS transistor 24 is transmitted to the output line 4 through the first four resistor and capacitor modules via the fourth transmission channel.

[0103] In this way, by controlling the phase of the first control signal, the switching control of all target transistors can be achieved, and then by combining different combinations of the first control signal, the switching control of different row transmission channels can be accurately achieved, thereby further improving the accuracy and convenience of channel selection control.

[0104] This embodiment provides a signal repair method. Figure 9 FIG. 1 is a flow chart of a signal repair method provided in an embodiment of the present application. Figure 9 As shown, the method applied to the signal repair circuit described in any of the above embodiments includes:

[0105] S10: Detect whether the signal receiving module 5 has any abnormality in signal reception;

[0106] S20: In response to an abnormality in the signal reception of the signal receiving module 5, determining a target position where the abnormality is located and a target row where the target position is located;

[0107] S30: Disconnect the connection between the signal sending module 1 and the signal receiving module 5 on both sides of the target row, connect the signal sending module 1 and the input line 3 on the opposite side of the target position of the target row to transmit the normal signal to the compensation module 2; and connect the output lines 4 on both sides of the target row to the signal receiving module 5, so that the compensation signal output by the compensation module 2 is transmitted to the signal receiving module 5 via the output lines 4 on both sides of the target row.

[0108] In one embodiment, detecting whether the signal reception by the signal receiving module 5 is abnormal may include: detecting whether the signal received by the signal receiving module 5 is abnormal. The received signal may refer to a signal output by the signal sending module 1, such as a driving signal output to the display area for display via a scan line.

[0109] In one embodiment, detecting whether signal reception by the signal receiving module 5 is abnormal may include: detecting a display function corresponding to the signal receiving module 5; and determining whether signal reception by the signal receiving module 5 is abnormal based on the display function corresponding to the signal receiving module 5. For example, the display function may include at least one of display brightness, display color, and whether the display flickers.

[0110] The detection of whether the signal receiving module 5 has abnormal signal reception, such as detecting the display function corresponding to the signal receiving module 5 , can be done by visual observation or by machine detection, such as OM machine detection.

[0111] In one embodiment, detecting whether the signal reception of the signal receiving module 5 is abnormal may include detecting whether at least one of the parameters of the signal received by the signal receiving module 5 , such as the voltage value, frequency, and phase, is abnormal.

[0112] In one embodiment, detecting whether the signal receiving module 5 has abnormal signal reception may further include detecting whether the current and / or components in the signal sending module 1 have abnormal signal reception.

[0113] In one embodiment, the signal reception abnormality of the signal receiving module 5 may refer to the signal reception abnormality of the signal receiving module 5 on one side, for example, the signal reception abnormality on the first side, that is, the signal sending module 1 on the first side has an abnormality.

[0114] In one embodiment, determining the target position where the abnormality is located and the target row where the target position is located may include: determining the target position where the abnormality occurs and the target row where the target position is located. For example, the target position where the signal sending module 1 is located may refer to the target position corresponding to the GOA unit where the signal sending module 1 is located.

[0115] Here, the target position where the abnormality is located and the target row where the target position is located can be determined by the machine display, for example, the target row where the target position is located is determined according to the row number displayed by the machine.

[0116] In one embodiment, the signal transmitting module 1 is connected to the signal receiving module 5 via a scan line. Disconnecting the connection between the signal transmitting module 1 and the signal receiving module 5 on both sides of the target row may include disconnecting the connection between the signal transmitting module 1 and the scan line on both sides of the target row. By disconnecting the connection between the signal transmitting module 1 and the signal receiving module 5 on both sides of the row where the abnormality occurs, it is possible to prevent a difference between the compensated signal input to the scan line from the first side and the normal signal input to the scan line from the second side when an abnormality occurs on the first side of the same row, thereby preventing uneven brightness on the left and right sides of the displayed image.

[0117] In one embodiment, the signal sending module 1 on the opposite side of the target position of the target row may refer to the signal sending module 1 corresponding to the target row on the other side of the side where the target position is located. For example, the target position is located on the first side, and the opposite side refers to the second side. That is, when the abnormal signal sending module 1 is located on the first side, connecting the signal sending module 1 on the opposite side of the target position of the target row and the input line 3 may refer to connecting the signal sending module 1 on the second side of the target row and the input line 3.

[0118] In one embodiment, after step S30, the method may further include: in response to detecting that the abnormal signal transmitting module 1 has returned to normal, disconnecting the output end of the signal transmitting module 1 on the second side of the target row from the input line 3 on the second side, disconnecting the output lines 4 on both sides from the signal receiving module 5, and connecting the signal transmitting module 1 on both sides of the target row to the signal receiving module 5, for example, by laser or other means.

[0119] Here, connecting the output lines 4 on both sides of the target row to the signal receiving module 5 may refer to connecting the output lines 4 on both sides of the target row to the scan lines, for example, by laser or other means. Transmitting the normal signal to the compensation module 2 may refer to transmitting the normal signal output by the signal sending module 1 on the second side of the target row to the compensation module 2 for compensation.

[0120] In this way, when the output signal of one side's signal transmission module 1 is abnormal, its connection with the display area is cut off, preventing the abnormal signal from being directly input into the display area for display, which may cause display abnormality. At the same time, the connection between the other side's signal transmission module and the display area is cut off, which can also prevent the compensated normal signal and the other side's normal signal from being input into the display area, which may cause display abnormality. After the normal signal is input into the compensation module 2, the compensated signal is transmitted to the display area via the output lines 4 on both sides, eliminating the delay and attenuation of the normal signal during transmission from one side to the other, thereby correcting the display abnormality.

[0121] In some embodiments, the compensation module 2 further includes: an impedance matching unit 28;

[0122] After step S30, the method may further include:

[0123] Determine a position of a target transmission channel in the multiple rows of transmission channels 283 of the impedance matching unit 28 based on the target row; the position of the target transmission channel matches the target row;

[0124] The target control signal is adjusted based on the position of the target transmission channel to control all the target transistors 284 in the target transmission channel to be turned on by the target control signal.

[0125] In one embodiment, determining the position of the target transmission channel in the multiple rows of transmission channels 283 of the impedance matching unit 28 based on the target row may include: determining the position of the target transmission channel in the multiple rows of transmission channels 283 of the impedance matching unit 28 based on the position of the target row in the display area. Matching the position of the target transmission channel with the target row may include: matching the position of the target transmission channel in the multiple rows of transmission channels 283 with the position of the target row in the display area.

[0126] For example, the position of the target transmission channel matches the target row, which may mean that when the corresponding position of the target row in the display area is located at the upper part, the target transmission channel is located at the upper part of the multi-row transmission channel 283; when the corresponding position of the target row in the display area is located in the middle part, the target transmission channel is located in the middle part of the multi-row transmission channel 283; when the corresponding position of the target row in the display area is located at the lower part, the target transmission channel is located at the lower part of the multi-row transmission channel 283.

[0127] In one embodiment, the position of the target transmission channel matches the target row, that is, the number of resistor and capacitor modules 282 connected in series between the target transmission channel and the input port 281 matches the target row, that is, the impedance between the target transmission channel and the input port 281 matches the target row. The lower the target row is in the display area, or the longer the path required for the output line 4 to transmit to the location where the abnormality occurs, the lower the target transmission channel is in the multiple rows of transmission channels 283, that is, the greater the number of resistor and capacitor modules 282 connected in series between the target transmission channel and the input port 281, and the greater the impedance between the target transmission channel and the input port 281.

[0128] In one embodiment, adjusting the target control signal based on the position of the target transmission channel may refer to adjusting the phases of multiple first control signals based on the position of the target transmission channel, where the second control signal is an inverted signal of the first control signal. Controlling the conduction of multiple target transistors in the target transmission channel using the target control signal may refer to controlling all target transistors 284 in the target transmission channel to be conducted using the first control signal and the second control signal, and controlling the conduction of target transistors 284 in transmission channels other than the target transmission channel.

[0129] In this way, based on the relative position of the abnormality in the display area, a target transmission channel that matches the position is selected. When the impedance matching requirements required for different abnormal positions are different, the impedances provided by the resistance and capacitance modules corresponding to different target transmission channels are different, thereby achieving accurate and flexible impedance matching, improving accuracy, and avoiding low accuracy and electrostatic damage caused by manual adjustment of variable resistors.

[0130] In some embodiments, step S10 may include:

[0131] Determine whether the display function corresponding to the signal receiving module 5 is abnormal;

[0132] In response to the display function being abnormal, it is determined that the signal reception of the signal receiving module 5 is abnormal.

[0133] Determining whether an abnormality occurs in the display function corresponding to the signal receiving module 5 may refer to determining whether an abnormality occurs in at least one of the display brightness, display color, and display flickering corresponding to the signal receiving module 5 .

[0134] In one embodiment, an abnormality in the display function may refer to a decrease in the display brightness of at least one row corresponding to the signal receiving module 5, or the appearance of at least one dark line on the display screen corresponding to the signal receiving module 5. At this time, it can be determined that an abnormality has occurred in the display function corresponding to the signal receiving module 5.

[0135] In one embodiment, determining whether the display function corresponding to the signal receiving module 5 is abnormal may refer to determining whether the display function corresponding to the signal receiving module 5 is abnormal by visual observation or by machine display.

[0136] In this way, it is possible to more intuitively and accurately determine whether there is an abnormality in the signal received by the signal receiving module 5 based on the display situation, and it is also convenient to locate the position and line number where the abnormality occurs.

[0137] In some embodiments, determining the target location where the anomaly is located and the target row where the target location is located in step S20 may include:

[0138] determining a target location where the abnormality is located based on the location of the display function abnormality;

[0139] The target row where the target position is located is determined based on the row label corresponding to the target position.

[0140] In one embodiment, determining the target location of the abnormality based on the location of the display function abnormality may include: determining the target location of the abnormality and the side of the target location based on the location of the display function abnormality. The target location of the abnormality may refer to the location of the signal transmission module 1 where the abnormality occurred. For example, determining that the signal transmission module 1 where the abnormality occurred is located on the first side based on the location of the dark line.

[0141] In one embodiment, determining the target row of the target position based on the row label corresponding to the target position may include: determining the row label corresponding to the target position by a machine; and determining the target row of the target position based on the row label. Here, the row label may refer to a number recorded on the machine for each row, and the row label may indicate the row number of the corresponding row, for example, a positive integer.

[0142] In this way, the abnormal position can be quickly located by displaying it, and then the number of the row where the abnormality occurs can be quickly and accurately located in combination with the row number, thereby facilitating accurate cutting off of the output connection of the row to the display area, and connecting the signal transmission modules on both sides of the row to the input line 3.

[0143] In some embodiments, disconnecting the signal sending modules 1 and the signal receiving modules 5 on both sides of the target row and connecting the signal sending modules 1 on the opposite side of the target position of the target row to the input line 3 in step S30 may include:

[0144] The connection between the signal sending module 1 and the signal receiving module 5 on both sides of the target row is disconnected by laser, and the signal sending module 1 and the input line 3 on the opposite side of the target position of the target row are connected by laser.

[0145] In this way, physical disconnection and connection are achieved through laser, which improves the stability of disconnection and connection establishment, and avoids abnormal signal transmission caused by disconnection or unstable connection, which in turn causes display abnormality.

[0146] In some embodiments, the compensation module 2 includes a comparator 21, an NMOS transistor 24, and a switch circuit 26; after step S20, the method may further include:

[0147] Determine a target signal corresponding to the signal sending module 1 based on the target row;

[0148] The gating unit 25 is controlled to transmit the target signal to the drain of the NMOS transistor 24 so that the falling edge of the signal output from the source of the NMOS transistor 24 is consistent with the falling edge of the target signal.

[0149] In one embodiment, the target signal corresponding to the signal sending module 1 may refer to a target signal that matches the target location where the anomaly is located, such as a target clock signal that matches the target row, that is, the target clock signal used by the signal sending module 1 where the anomaly occurred. For example, the target signal is a target clock signal determined from a predetermined number of clock signals used by the display panel where the signal sending module 1 where the anomaly occurred is located.

[0150] In one embodiment, determining the target signal corresponding to the signal sending module 1 based on the target row may refer to determining the corresponding target clock signal based on the target row, the number of clock signals corresponding to the display area, and the clock signal corresponding to the first row of the display area.

[0151] For example, the target row where the anomaly is located is row 100, the number of clock signals corresponding to the display area is 8, the clock signal corresponding to the first row of the display area is the 5th clock signal, namely CLK5, and the display area is scanned downward in turn based on the 8 clock signals scanning row by row. Then, based on the remainder of the number of target rows divided by the number of clock signals, namely 100 / 8=12 remainder 4, it can be determined that the target clock signal corresponding to the target row is the 8th clock signal, namely CLK8.

[0152] In one embodiment, the first input end of the comparator 21 is connected to the input lines 3 on both sides, for inputting the normal signal on either side; the second input end of the comparator 21 is used to input the reference signal; the output end of the comparator 21 is connected to the output lines 4 on both sides, for outputting a high level when the voltage of the normal signal is greater than the voltage of the reference signal, and outputting a low level when the voltage of the normal signal is less than the voltage of the reference signal.

[0153] In one embodiment, the output end of the comparator 21 is connected to the gate of the NMOS transistor 24, and the source of the NMOS transistor 24 is connected to the output line 4; the drain of the NMOS transistor 24 is connected to the gating unit 25, and the gating unit 25 is used to select the target signal matching the target row where the exception is located to input the drain, so that the falling edge of the signal output by the source is consistent with the falling edge of the target signal.

[0154] In one embodiment, the gating unit 25 may include a predetermined number of switch circuits 26 , each switch circuit 26 is configured to input a clock signal, and different switch circuits 26 input different clock signals.

[0155] In one embodiment, controlling the gating unit 25 to input the target signal may include controlling the switch circuit 26 corresponding to the target clock signal to be turned on, while keeping the other switch circuits 26 turned off. For example, for a display panel with eight clock signals (8CLK), when the target clock signal is CLK3, the switch circuit 263 corresponding to CLK3 is turned on, while the other seven switch circuits 26 are turned off. CLK3 can then be input to the drain of the NMOS transistor 24.

[0156] In one embodiment, controlling the switch circuit 26 corresponding to the target clock signal to be turned on may include: controlling the switch circuit 26 corresponding to the target clock signal to be turned on by using a controllable switch in the switch circuit 26 .

[0157] In this way, the clock signal corresponding to the abnormal position is selectively input through the selection unit 25, so that the falling edge of the output compensated signal can be consistent with the falling edge of the original normal signal of the row where the abnormality is located, avoiding the delay of the falling edge of the signal causing the next row to be incorrectly charged and resulting in a deviation in the display effect.

[0158] In some embodiments, determining the target signal corresponding to the signal sending module 1 based on the target row includes:

[0159] Based on the number of clock signals corresponding to the display area and the target row, the target clock signal corresponding to the signal sending module 1 is determined.

[0160] In one embodiment, determining the target clock signal corresponding to the signal sending module 1 based on the number of clock signals corresponding to the display area and the target row may include: determining the target clock signal corresponding to the signal sending module 1 based on the number of clock signals corresponding to the display area, the number of the target rows, and the clock signal corresponding to the first row of the display area. Here, the clock signal corresponding to the first row may refer to the clock signal corresponding to the first scan line, the first row may refer to the first row from top to bottom in the display area, and the first bar may refer to the first bar from top to bottom in the display area.

[0161] In one embodiment, determining the target clock signal corresponding to the signal transmitting module 1 based on the number of clock signals corresponding to the display area, the number of the target row, and the clock signal corresponding to the first row of the display area can include: determining the remainder of dividing the number of the target row by the number of clock signals corresponding to the display area; and determining the target clock signal corresponding to the signal transmitting module 1 based on this remainder and the clock signal corresponding to the first row of the display area. In this way, determining the target clock signal corresponding to the target row from all clock signals based on the number of the row where the abnormality occurs and the number of clock signals corresponding to the display area can further improve the accuracy of determining the target clock signal and better avoid display abnormalities caused by incorrectly charging the next row.

[0162] In some embodiments, the compensation module 2 further includes a third variable resistor 27; after step S30, the method may further include:

[0163] Based on the display conditions of other rows adjacent to the target row, the third variable resistor 27 is adjusted to adjust the compensation signal.

[0164] In one embodiment, the source of the NMOS transistor 24 is connected to the output lines 4 on both sides via a third variable resistor 27. The third variable resistor 27 may be a sliding resistor, and adjusting the third variable resistor 27 may refer to adjusting the resistance value of the third variable resistor 27, for example, by moving a slider of the sliding resistor.

[0165] In one embodiment, the display conditions of other rows adjacent to the target row may refer to the display brightness or display color of other rows adjacent to the target row, or the voltage value of the normal signal output by the signal sending module 1 corresponding to other rows.

[0166] In one embodiment, adjusting the compensation signal may refer to adjusting the voltage value of the compensation signal to adjust the display effect corresponding to the target row where the abnormal signal sending module 1 is located. Here, the display effect may include display brightness or display color.

[0167] In this way, by adding a variable resistor to adjust the wiring impedance, the compensated signal matches the display of the rows around the abnormal signal sending module 1, avoiding the situation where the target row and the surrounding rows display uneven brightness after the signal is input into the display area.

[0168] An embodiment of the present application also provides a display panel, which may include: a display area and a non-display area, the non-display area is arranged around the display area, the display area is provided with sub-pixels arranged in an array, the non-display area is provided with a signal repair circuit, and the signal repair circuit is the signal repair circuit described in any one or more of the aforementioned embodiments; the signal sending module 1 is a gate driving circuit, the gate driving circuit is arranged in the non-display areas on both sides of the display area, the signal receiving module 5 is the sub-pixel of the display panel, the compensation module 2 is arranged in the non-display area below the display area, and the input line 3 and the output line 4 are arranged between the gate driving circuit and the sub-pixel.

[0169] Here, the display panel is driven on both sides. The signal repair circuit has a pair of input lines 3 and output lines 4 in the non-display areas on either side of the display area. The gate drive circuit is also located in the non-display areas on both sides of the display area. If a gate drive circuit anomaly occurs on the first side of the display area of the display panel, the gate drive circuit on both sides of the target row experiencing the anomaly can be disconnected from the scan lines. The gate drive circuit on the second side can be connected to the input lines 3, and the output lines 4 on both sides can be connected to the scan lines.

[0170] In one embodiment, the input line 3 and the output line 4 are located in the M1 layer of the display panel, ie, the metal layer 1 (metal1, M1).

[0171] In one embodiment, a pair of input lines 3 and output lines 4 on one side can be located within the GOA area on that side. The compensation module 2 in the signal repair circuit can be located within the display panel's PCBA. The display area and PCBA can be connected via output lines 4, such as output lines 4 connecting scan lines. The PCBA can be located in a non-display area below the display area.

[0172] As a possible implementation, a signal repair circuit is provided, wherein two lines (one input line + one output line) are added on the left and right sides of the surface. The input line Gn serves as the PCBA input source. Because the product is driven on both sides, in order to solve the left or right side defects that occur in actual production, Gn lines need to be reserved on both sides. Similarly, the output line Gout line is the final signal generated after the PCBA end is repaired, and it is the transmission path that needs to be sent to the display area scan line. The schematic diagram of the display panel is shown as follows. Figure 10 As shown, taking the abnormality on the right side of the 100th scan line as an example, first you need to Figure 10 The line connecting the scanning line and the gate drive circuit at A in the middle is disconnected (the reason for disconnecting the abnormal side is to prevent abnormal signals from entering the display area and interfering with the normal opening of the TFT. If the normal side is not disconnected, it will cause the normal Gn on the left and the repaired or compensated Gn on the right to have a slight difference in waveform, resulting in uneven brightness on the left and right, which is prone to gradual changes in brightness. Therefore, both sides are disconnected, and the repaired Gn is sent to the display area, i.e., the AA area, through the Gout lines on both sides at the same time, so that there will be no uneven brightness). Then Figure 10 At point B in the middle, a laser connects the scan line to Gn and Gout. The normal signal on the left enters the compensation module in the PCBA via the Gn trace. Due to the trace resistance and capacitance (RC), the normal Gn output is a square wave. By the time it reaches the PCBA through Gn, the waveform has been delayed and attenuated.

[0173] Ideally, Gn is a standard square wave, which decays into a blue waveform when it reaches the PCBA end, causing the current row to be mistakenly charged with the next row of data. Therefore, the Gn collected by the PCBA end needs to be processed, such as Figure 11As shown. The normal signal collected by the PCBA end is input as Gn_in to the +IN pole of OP. The first variable resistor R1 is connected in series in the middle to isolate Gn_in from the reference signal Vref. Otherwise, the DC of Vref will affect the pulse waveform of Gn_in and thus affect the normal output of GOA. Vref is used as the -IN pole input of OP. The trigger point can be adjusted by the VGH resistor divider. For example, a second variable resistor R2 is connected to adapt to the different abnormal position requirements of different models. OP is used as a comparator. When the input level of the first input terminal +IN of OP is higher than the second input terminal -IN, the output terminal OUT outputs VGH. When the +IN input is lower than -IN, a predetermined low level VGL is output, thereby obtaining a standard square wave.

[0174] Compared with the ideal waveform, the waveform output by OP is almost the same, but there is a μs delay, so it still cannot be sent back directly to the surface, and there will be mischarging. At this time, the OP output signal Gn_out is connected to the gate G of the NMOS transistor Q1 as the switching signal of the MOS, and the drain D is connected to the clock signal CLK. Taking the 8CLK model as an example, CLK1 to CLK8 are the 8 clock signals used. The panel scans downward in turn in 8CLK row-by-row scanning. Assuming that the first scan line in the AA area starts with CLK5, the second is CLK6, the third CLK7 and so on. Therefore, a dip switch is made at the D pole for selection. Different CLKs are selected to connect to the D pole according to the different abnormal positions. Taking the 100th row as an example, 100 / 8=12 with a remainder of 4, so the CLK corresponding to the 100th row is CLK8.

[0175] When the gate G is high, the MOS turns on, the source and drain conduct, and the source S waveform is pulled to a high level. When the drain waveform CLK falls, G is at a high potential, the MOS conducts, and the source S waveform follows the drain falling, achieving the purpose of early shutdown and solving the problem of incorrect charging. The final source waveform is then adjusted by a third variable resistor, the sliding resistor. If the source waveform is directly fed into the surface without a sliding resistor, it will cause the charging to be too good and form a bright line. Therefore, a sliding resistor, the third variable resistor R3, is required to adjust the trace resistance to match the different abnormal locations, and adjust the waveform difference so that the abnormal scan line display is consistent with the surrounding rows.

[0176] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0177] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the scope of protection of the present application.

[0178] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A signal repair circuit, characterized in that: include: a signal sending module, a compensation module, an input line, and an output line, wherein there are at least two signal sending modules, the input line and the output line are arranged in pairs, the signal sending module is used to connect to the signal receiving module in the display area, the input line and the output line are both connected to the compensation module, and a pair of the input line and the output line is correspondingly arranged between each signal sending module and the signal receiving module; When the signal receiving module receives an abnormal signal from one of the signal sending modules, the signal output modules that send normal signals are configured to transmit the normal signals to the compensation module through the input line; The compensation module is used to compensate the normal signal and transmit the compensated signal to the signal receiving module through the output line.

2. The circuit according to claim 1, wherein: The compensation module includes a comparator; The first input terminal of the comparator is connected to the input line for inputting the normal signal; the second input terminal of the comparator is used to input the reference signal; the output terminal of the comparator is connected to the output line for outputting a high level when the voltage of the normal signal is greater than the voltage of the reference signal, and outputting a low level when the voltage of the normal signal is less than the voltage of the reference signal.

3. The circuit according to claim 2, characterized in that The compensation module further includes: a first variable resistor and a second variable resistor; The input line is connected to the first input end via a first variable resistor, and / or the signal line for transmitting the reference signal is connected to the second input end via a second variable resistor.

4. The circuit according to claim 2, characterized in that The compensation module further includes: an NMOS transistor and a gating unit; The output end of the comparator is connected to the gate of the NMOS transistor; the source of the NMOS transistor is connected to the output line; the drain of the NMOS transistor is connected to a gating unit, and the gating unit is used to select a target signal matching the target position where the abnormality is located and input it into the drain, so that the falling edge of the signal output by the source is consistent with the falling edge of the target signal.

5. The circuit according to claim 4, characterized in that The compensation module further includes: a third variable resistor; The source of the NMOS transistor is connected to the output line through the third variable resistor.

6. The circuit according to claim 4, characterized in that The compensation module further includes: an impedance matching unit, the impedance matching unit including: an input port, a plurality of resistor and capacitor modules connected in series with the input port, and a plurality of transmission channels connected in parallel; The input port is connected to the source of the NMOS transistor, the transmission channel is connected to the output line, and a row of the transmission channels is connected between every two adjacent resistor and capacitor modules; each row of the transmission channels includes at least one target transistor connected in series; The gate of the target transistor is used to input a target control signal, and the target control signal is used to control a row of target transmission channels among the multiple rows of transmission channels to be turned on, so as to transmit the signal output by the source to the output line through the target transmission channel after passing through at least one resistor and capacitor module between the target transmission channel and the input port; The position of the target transmission channel in the plurality of rows of transmission channels matches the target position where the anomaly occurs.

7. The circuit according to claim 6, characterized in that The target control signal includes: a plurality of first control signals and a plurality of second control signals, wherein the number of the first control signals is the same as the number of the second control signals, and each second control signal is an inverted signal of a first control signal; The gate of each target transistor is used to input a first control signal or a second control signal; based on different combinations of the multiple first control signals and the multiple second control signals, a target transmission channel is controlled to be turned on.

8. A signal repair method, applied to the signal repair circuit according to any one of claims 1 to 7, characterized in that: The method comprises: Detecting whether the signal receiving module has any abnormality in signal reception; In response to an abnormality in signal reception by the signal receiving module, determining a target position where the abnormality is located and a target row where the target position is located; Disconnect the connection between the signal sending module and the signal receiving module on both sides of the target row, connect the signal sending module on the opposite side of the target position of the target row and the input line to transmit the normal signal to the compensation module; and connect the output lines on both sides of the target row to the signal receiving module, so that the compensation signal output by the compensation module is transmitted to the signal receiving module via the output lines on both sides of the target row.

9. The signal repair method according to claim 8, characterized in that: The compensation module further includes: an impedance matching unit; After connecting the output lines on both sides of the target row to the signal receiving module, the method further includes: Determining a position of a target transmission channel among multiple rows of transmission channels of the impedance matching unit based on the target row; the position of the target transmission channel matches the target row; A target control signal is adjusted based on the position of the target transmission channel, so as to control all target transistors in the target transmission channel to be turned on by the target control signal.

10. A display panel, characterized in that: include: a display area and a non-display area, the non-display area is arranged around the display area, the display area is provided with sub-pixels arranged in an array, the non-display area is provided with a signal repair circuit, and the signal repair circuit is the signal repair circuit according to any one of claims 1 to 7; the signal sending module is a gate driving circuit, the gate driving circuit is arranged in the non-display areas on both sides of the display area, the signal receiving module is the sub-pixel of the display panel, the compensation module is arranged in the non-display area below the display area, and the input line and the output line are arranged between the gate driving circuit and the sub-pixel.

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