Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a pixel circuit, a light-emitting element and a first switch unit, the pixel circuit comprises a first node and a light-emitting control transistor, and the first node is electrically connected with the anode of the light-emitting element; a first electrode of the light-emitting control transistor is electrically connected with the first node, and a grid electrode of the light-emitting control transistor receives a first light-emitting control scanning signal; a first end of the first switch unit is electrically connected with a first node, a second end of the first switch unit is electrically connected with a first voltage end, and a control end of the first switch unit receives a control signal; the time period of the effective level of the control signal overlaps the time period of the effective level of the first light-emitting control scanning signal. The first switch unit corresponding to the abnormal pixel circuit is controlled to be switched on through the control signal so as to control the light-emitting element connected with the first switch unit not to emit light. Therefore, the light-emitting element connected with the abnormal pixel circuit is prevented from abnormally emitting light, and the problems of display crosstalk or bright and dark lines and the like are avoided.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, the production of display panels of any shape often requires laser cutting to create a fixed-size display area. During the cutting process, light-emitting components near the cut line are susceptible to electrostatic damage or the high temperatures of the laser cutting process, causing them to fail to operate according to timing instructions. This can lead to crosstalk or bright / dark lines on the display panel, impacting the panel's yield. Summary of the Invention

[0003] The present invention provides a display panel and a display device, which solve the problems of abnormal pixel circuits in the display panel, which cause display crosstalk or bright and dark lines.

[0004] In a first aspect, an embodiment of the present invention provides a device characterized by comprising a pixel circuit, a light-emitting element, and a first switching unit;

[0005] The pixel circuit includes a first node and a light emitting control transistor, the first node is electrically connected to the anode of the light emitting element; a first electrode of the light emitting control transistor is electrically connected to the first node, and a gate of the light emitting control transistor receives a first light emitting control scanning signal;

[0006] A first terminal of the first switch unit is electrically connected to the first node, a second terminal of the first switch unit is electrically connected to a first voltage terminal, and a control terminal of the first switch unit receives a control signal;

[0007] A period during which the control signal is at an effective level overlaps a period during which the first light emitting control scanning signal is at an effective level.

[0008] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided in the first aspect.

[0009] The display panel provided by an embodiment of the present invention includes a first switch unit, and the first switch unit is connected to the anode of the light-emitting element. In the light-emitting stage of the light-emitting element, the effective level of the control signal controls the first switch unit to be turned on, and the voltage of the first voltage terminal is written to the first node, that is, the voltage of the first voltage terminal is written to the anode of the light-emitting element, and the light-emitting element is controlled not to emit light, thereby avoiding the abnormal light-emitting element connected to the abnormal pixel circuit from emitting light abnormally. That is to say, in the light-emitting stage of the light-emitting element, the first switch unit corresponding to the abnormal pixel circuit is controlled to be turned on by the control signal to control the light-emitting element connected thereto not to emit light. In this way, the light-emitting element connected to the abnormal pixel circuit is avoided from emitting light abnormally, thereby avoiding problems such as display crosstalk or bright and dark lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram of a display area cut of a display panel provided by the related art;

[0011] Figure 2 is a schematic diagram of a display panel provided by the present invention;

[0012] Figure 3 This is a schematic structural diagram of a pixel circuit of a display panel provided by the present invention;

[0013] Figure 4 yes Figure 3 A driving timing diagram of a pixel circuit of a display panel is provided;

[0014] Figure 5 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0015] Figure 6 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0016] Figure 7 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0017] Figure 8 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0018] Figure 9 is a schematic diagram of another display panel provided by the present invention;

[0019] Figure 10 This is a schematic structural diagram of a first pixel circuit of a display panel provided by the present invention;

[0020] Figure 11 is a structural schematic diagram of a second pixel circuit of a display panel provided by the present invention;

[0021] Figure 12 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0022] Figure 13 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0023] Figure 14 is a schematic diagram of another display panel provided by the present invention;

[0024] Figure 15 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0025] Figure 16 is a schematic diagram of another display panel provided by the present invention;

[0026] Figure 17 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0027] Figure 18 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0028] Figure 19 This is a driving timing diagram of a pixel circuit of another display panel provided by the present invention;

[0029] Figure 20 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0030] Figure 21 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0031] Figure 22 It is a structural schematic diagram of a pixel circuit of another display panel provided by the present invention;

[0032] Figure 23 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0034] Figure 1 This is a schematic diagram of the structure of a display panel provided by the related technology, refer to Figure 1 As shown, a plurality of signal lines M are provided in the display area AA of the display panel 100. Figure 1As shown by the AA' cutting line, the cutting of the display area AA will inevitably cut part of the pixel unit a or part of the signal line M. As an improved cutting method, such as cutting along Figure 1 As shown by the BB' cutting line in the figure, the cutting is performed along the edge of the complete pixel unit a. However, during the laser random cutting process, the accumulated high temperature of the laser cutting can easily cause the metal material in the signal line M to melt, forming conductive foreign matter. In short, the light-emitting components near the cutting line are susceptible to electrostatic damage or the high temperature of the laser cutting, and may not function properly according to the timing instructions. The display panel may experience display crosstalk or bright and dark lines, affecting the display panel's yield.

[0035] In order to solve the above technical problems, an embodiment of the present invention provides a display panel. Figure 2 is a schematic diagram of a display panel provided by the present invention, Figure 3 is a structural diagram of a pixel circuit of a display panel provided by the present invention, Figure 4 yes Figure 3 A driving timing diagram of a pixel circuit of a display panel is provided, referring to Figure 2-Figure 4 The display panel 200 includes a pixel circuit 10, a light-emitting element 20, and a first switch unit T. The pixel circuit 10 includes a first node N1 and a light-emitting control transistor M6. The first node N1 can be a physical connection point or a virtual connection point, and the virtual connection point refers to a connection point introduced for the convenience of description. The first node N1 is electrically connected to the anode of the light-emitting element 20. The first electrode of the light-emitting control transistor M6 is electrically connected to the first node N1, and the gate of the light-emitting control transistor M6 receives a first light-emitting control scan signal EM1. The first end of the first switch unit T is electrically connected to the first node N1, that is, the first end of the first switch unit T is electrically connected to the anode of the light-emitting element 20. The second end of the first switch unit T is electrically connected to the first voltage terminal SL, and the control end of the first switch unit T receives a control signal S3. The period during which the control signal S3 is at an active level overlaps with the period during which the first light-emitting control scan signal EM1 is at an active level.

[0036] The active level of the control signal S3 is a voltage in the control signal S3 used to turn on the first switch unit T. The inactive level of the control signal S3 is a voltage in the control signal S3 used to turn off the first switch unit T. The active level of the first light-emitting control scanning signal EM1 is a voltage in the first light-emitting control scanning signal EM1 used to turn on the light-emitting control transistor M6, and the inactive level of the first light-emitting control scanning signal EM1 is a voltage in the first light-emitting control scanning signal EM1 used to turn off the light-emitting control transistor M6.

[0037] Figure 3 In the example, the light emitting control transistor M6 is a PMOS transistor, but the invention is not limited thereto. Figure 3and Figure 4 , the active level of the first light-emitting control scanning signal EM1 is low. The period during which the first light-emitting control scanning signal EM1 is active is the light-emitting phase of the light-emitting element 20. During the light-emitting phase of the light-emitting element 20, the active level of the first light-emitting control scanning signal EM1 controls the conduction of the light-emitting control transistor M6, providing a driving voltage or a driving current to the anode of the light-emitting element 20, thereby controlling the brightness of the light-emitting element 20.

[0038] In the related art, in order to avoid affecting the normal light emitting process of the light emitting element 20 , a reset voltage such as a voltage written into the first node N1 to reset the anode of the light emitting element 20 is set before the light emitting stage of the light emitting element 20 .

[0039] In the embodiment of the present application, the period of time when the control signal S3 is at an effective level overlaps with the period of time when the first light-emitting control scanning signal EM1 is at an effective level. In the light-emitting stage of the light-emitting element 20, the effective level of the control signal S3 controls the first switch unit T to be turned on, and the voltage of the first voltage terminal SL is written to the first node N1, that is, the voltage of the first voltage terminal SL is written to the anode of the light-emitting element 20, controlling the light-emitting element 20 not to emit light, thereby avoiding abnormal light emission of the light-emitting element 20 connected to the abnormal pixel circuit 10, thereby avoiding problems such as display crosstalk or bright and dark lines. Figure 2 In the figure, an abnormal pixel circuit 10 is indicated by pattern filling.

[0040] In other embodiments, the light emitting control transistor M6 may also be an NMOS transistor, and the active level of the control signal S3 is a high level.

[0041] Illustratively, the light-emitting element 20 includes an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), a light-emitting diode (LED), etc. The pixel circuit 10 can have a circuit structure of 2T1C, 4T1C, 7T1C, 7T2C, 8T1C, 8T2C, 13T2C, etc.

[0042] Figure 5 is a structural diagram of a pixel circuit of another display panel provided by the present invention, Figure 6 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention, referring to Figure 5 and Figure 6The pixel circuit 10 further includes a driving transistor M3 and a power write transistor M1. The first electrode of the driving transistor M3 is electrically connected to the second electrode of the emission control transistor M6. The second electrode of the driving transistor M3 is electrically connected to the first electrode of the power write transistor M1. The gate of the power write transistor M1 receives a second emission control scan signal EM2. The first emission control scan signal EM1 is at an active level during a first emission control period P01, and the second emission control scan signal EM2 is at an active level during a second emission control period P02. The first emission control period P01, the second emission control period P02, and the period during which the control signal S3 is at an active level overlap.

[0043] In the embodiment of the present application, a first light-emission control scan signal EM1 is used to control the on / off switching of the light-emission control transistor M6, and a second light-emission control scan signal EM2 is used to control the on / off switching of the power supply write transistor M1. The overlap period between the first light-emission control period P01 and the second light-emission control period P02 is the third light-emission control period P03. It will be appreciated that during the third light-emission control period P03, the power supply write transistor M1 is turned on, the light-emission control transistor M6 is turned on, and a drive voltage or current is supplied to the anode of the light-emitting element 20. The third light-emission control period P03 is the light-emitting phase of the light-emitting element 20. The period during which the control signal S3 is at an active level overlaps with the third light-emission control period P03. Therefore, during the light-emission phase of the light-emitting element 20, the active level of the control signal S3 controls the first switch unit T to conduct, writing the voltage of the first voltage terminal SL to the anode of the light-emitting element 20, thereby preventing the light-emitting element 20 from emitting light. This prevents the light-emitting element 20 connected to the abnormal pixel circuit 10 from emitting light abnormally.

[0044] For example, in combination Figure 3 and Figure 4 As shown, the display phase of the pixel circuit 10 may include an initialization phase, a data writing phase, and a light-emitting phase. In the initialization phase, the first scan signal Sc1 provides a low-level signal, turning on the first reset transistors M5 and M7, writing the reset voltage RST to the first node N1 and the second node N2, and resetting the anode of the light-emitting element 20 and the gate of the driving transistor M3. In the data writing phase, the second scan signal Sc2 provides a low-level signal, turning on the data writing transistor M2 and the threshold compensation transistor M4, and writing the data signal Data to the second node N2 via the driving transistor M3 and the threshold compensation transistor M4. In the light-emitting phase, the first light-emitting control scan signal EM1 provides a low-level signal, controlling the power writing transistor M1 and the light-emitting control transistor M6 to turn on, transmitting the driving voltage or driving current generated by the driving transistor M3 to the light-emitting element 20, causing the light-emitting element 20 to emit light.

[0045] For example, in combination Figure 5 and Figure 6 As shown, in the light-emitting stage, the first light-emitting control scanning signal EM1 and the second light-emitting control scanning signal EM2 provide low-level signals, controlling the power writing transistor M1 and the light-emitting control transistor M6 to be turned on, and the driving voltage or current generated by the driving transistor M3 is transmitted to the light-emitting element 20, and the light-emitting element 20 emits light.

[0046] For example, refer to Figure 3-Figure 6 , taking the pixel circuit 10 as a 7T1C circuit as an example, the pixel circuit 10 further includes a capacitor C1. A first plate of the capacitor C1 is connected to the second node N2, and a second plate of the capacitor C1 is connected to the power supply voltage signal line VDD. A second electrode of the power write transistor M1 is connected to the power supply voltage signal line VDD.

[0047] Figure 7 is a structural diagram of a pixel circuit of another display panel provided by the present invention, Figure 8 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention, referring to Figure 7 and Figure 8 The pixel circuit 10 includes an amplitude adjustment module PAM and a pulse width modulation module PWM. The amplitude adjustment module PAM includes a light-emission control transistor M6 and a driving transistor M3. The first electrode of the driving transistor M3 is electrically connected to the second electrode of the light-emission control transistor M6. The input end of the pulse width modulation module PWM receives a sweep signal Sweep, and the output end of the pulse width modulation module PWM is electrically connected to the gate of the driving transistor M3. The effective level of the sweep signal Sweep is within the period of the first light-emission control scan signal EM1. The effective level of the control signal S3 overlaps with the effective level of the sweep signal Sweep.

[0048] like Figure 8As shown, the active level of the sweep signal Sweep controls the pulse width modulation module PWM to be turned off, preventing the off voltage provided by the pulse width modulation module PWM from being applied to the second node N2. The inactive level of the sweep signal Sweep controls the pulse width modulation module PWM to be turned on, preventing the off voltage provided by the pulse width modulation module PWM from being applied to the second node N2. In one example, the voltage of the sweep signal Sweep gradually decreases. The period during which the sweep signal Sweep maintains an active level is the fourth light-emitting control period P04. During this period, the voltage of the sweep signal Sweep is high, the pulse width modulation module PWM is turned off, and the off voltage cannot be applied to the second node N2, thus unaffecting the voltage at the gate of the driving transistor M3. The fourth light-emitting control period P04 falls within the period during which the first light-emitting control scan signal EM1 maintains an active level. The first light-emitting control scan signal EM1 controls the light-emitting control transistor M6 to conduct, supplying a driving voltage or current to the anode of the light-emitting element 20, thereby controlling the light-emitting element 20 to emit light.

[0049] During the period following the fourth light-emitting control period P04, the voltage of the sweep signal Sweep is low, the pulse width modulation module PWM is turned on, and the off voltage is applied to the second node N2, turning off the driving transistor M3. The driving voltage or driving current cannot be provided to the anode of the light-emitting element 20, and the light-emitting element 20 no longer emits light. The fourth light-emitting control period P04 is the light-emitting phase of the light-emitting element 20. The period during which the control signal S3 is at an effective level overlaps with the fourth light-emitting control period P04. Therefore, during the light-emitting phase of the light-emitting element 20, the effective level of the control signal S3 controls the first switch unit T to turn on, writes the voltage of the first voltage terminal SL to the anode of the light-emitting element 20, and controls the light-emitting element 20 to not emit light, thereby preventing the light-emitting element 20 connected to the abnormal pixel circuit 10 from emitting light abnormally.

[0050] Based on the above embodiments, Figure 3 and Figure 5 As shown, the cathode of the light-emitting element 20 is electrically connected to the second voltage terminal VSS; the voltage of the first voltage terminal SL is less than or equal to the voltage of the second voltage terminal VSS. In the embodiment of the present application, during the light-emitting phase of the light-emitting element 20, the active level of the control signal S3 controls the first switch unit T to conduct, causing the voltage of the first voltage terminal SL to be written to the first node N1. The voltage of the first voltage terminal SL is less than or equal to the voltage of the second voltage terminal VSS, so that the difference between the anode voltage and the cathode voltage of the light-emitting element 20 is less than the turn-on voltage of the light-emitting element 20, and the light-emitting element 10 is controlled to be non-luminous. The second voltage terminal VSS can also be understood as a common power signal terminal.

[0051] Figure 9Schematic diagram of another display panel provided by the present invention. Figure 9 The light emitting element 20 is partially shown, but the light emitting element 20 connected to the pixel circuit 10 is not shown. Figure 9 As shown, the display panel 200 further includes a plurality of control signal lines S and a plurality of input signal lines L. The control signal lines S transmit control signals S3. The plurality of control signal lines S are arranged along a first direction X, and the plurality of input signal lines L are arranged along a second direction Y. The first direction X intersects the second direction Y. Along the first direction X, a plurality of first voltage terminals SL are electrically connected to the same input signal line L. The input signal line L provides a voltage signal to the first voltage terminal SL electrically connected thereto. Figure 9 Only one input signal line L is shown electrically connected to multiple first voltage terminals SL. Along the second direction Y, the control terminals of multiple first switch units T are electrically connected to the same control signal line S, and the control signal line S provides a control signal S3 to the control terminals of the first switch units T electrically connected thereto. In the embodiment of the present application, the second terminals of the first switch units T connected to multiple pixel circuits 10 in the same row are connected to the same input signal line L, and the control terminals of the first switch units T connected to multiple pixel circuits 10 in the same column are connected to the same control signal line S. When the effective level of the control signal S3 provided by the control signal line S controls the first switch unit T to be turned on, the voltage provided by the input signal line L is transmitted to the first node N1 through the turned-on first switch unit T. Addressing and independent control of the independent first switch units T are achieved through the control signal line S and the input signal line L.

[0052] Exemplarily, the plurality of control signal lines S extend along the second direction Y and are arranged along the first direction X, and the plurality of input signal lines L extend along the first direction X and are arranged along the second direction Y. In other embodiments, the plurality of control signal lines S extend along the first direction X and are arranged along the second direction Y, and the plurality of input signal lines L extend along the second direction Y and are arranged along the first direction X.

[0053] Figure 10 is a structural diagram of a first pixel circuit of a display panel provided by the present invention, Figure 11 is a structural diagram of a second pixel circuit of a display panel provided by the present invention, Figure 12 This is a schematic diagram of the structure of a pixel circuit of another display panel provided by the present invention, referring to Figures 9-12The display panel also includes a plurality of light-emitting control signal lines and a plurality of scan signal lines Scan. The light-emitting control signal lines transmit a first light-emitting control scan signal EM1. The scan signal line Scan transmits a scan signal. The scan signal includes a first scan signal Sc1 and a second scan signal Sc2. In one example, the scan signal transmitted by the scan signal line Scan serves as the second scan signal Sc2 of the pixel circuit 10 of the current row, and the data written into the transistor M2 and the threshold compensation transistor M4 in the pixel circuit 10 of the current row are turned on. At the same time, the scan signal transmitted by the scan signal line Scan serves as the first scan signal Sc1 of the pixel circuit 10 of the next row, and the first reset transistor M5 and the second reset transistor M7 in the pixel circuit 10 of the next row are turned on. The plurality of light-emitting control signal lines extend along the first direction X and are arranged along the second direction Y, and the plurality of scan signal lines Scan extend along the first direction X and are arranged along the second direction Y.

[0054] Exemplarily, the display panel may further include a first gate drive circuit for providing a light-emitting control signal, and the shift register in the first gate drive circuit may be forward cascaded and / or reverse cascaded. The first gate drive circuit may be located in the display area AA or in the non-display area. The display panel may further include a second gate drive circuit for providing a scan signal, and the shift register in the second gate drive circuit may be forward cascaded and / or reverse cascaded. The second gate drive circuit may be located in the display area AA or in the non-display area.

[0055] Figure 13 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention, referring to Figures 9-13 The pixel circuit 10 includes a first pixel circuit 41 and a second pixel circuit 42, which are arranged along a second direction Y. The first switch unit T connected to the first pixel circuit 41 is a first pixel switch unit T41, and the first switch unit T connected to the second pixel circuit 42 is a second pixel switch unit T42. The input signal lines L include a first input signal line SL2 and a second input signal line SL3. The first input signal line SL2 is electrically connected to the first pixel switch unit T41, and the second input signal line SL3 is electrically connected to the second pixel switch unit T42. The voltage on the first input signal line SL2 is different from the voltage on the second input signal line SL3.

[0056] As an example, a first pixel circuit 41 and a second pixel circuit 42 exist in the same column of pixel circuits 10. The first pixel switch unit T41 and the second pixel switch unit T42 are connected to the same control signal line S. Thus, due to the difference between the voltage on the first input signal line SL2 and the voltage on the second input signal line SL3, the first pixel switch unit T41 electrically connected to the abnormal first pixel circuit 41 is controlled to be turned on, and the voltage on the first input signal line SL2 is transmitted to the first node N1 of the first pixel circuit 41, thereby controlling the light-emitting element 20 connected to the abnormal first pixel circuit 41 to not emit light. The second pixel switch unit T42 electrically connected to the normal second pixel circuit 42 is controlled to be turned off, without affecting the normal operation of the second pixel circuit 42 or the normal light-emitting process of the light-emitting element 20 connected to the second pixel circuit 42.

[0057] On the basis of the above embodiments, continue to refer to Figure 9 , the display panel 200 includes a first edge W1 extending along a first direction X, and at least part of the control signal line S extends to the first edge W1. Along the second direction Y, the first input signal line SL2 is located between the first edge W1 and the second input signal line SL3. In an embodiment of the present application, along the second direction Y, the first input signal line SL2 is located on a side of the second input signal line SL3 away from the center of the display panel 200. The first input signal line SL2 is closer to the first edge W1 than the second input signal line SL3. The first edge W1 can be the edge of the anisotropic cutting area, and the area closer to the first edge W1 is prone to abnormal pixel circuits 10. In one example, an abnormality occurs in the pixel circuit 10 electrically connected to the first input signal line SL2, while an abnormality does not occur in the pixel circuit 10 electrically connected to the second input signal line SL3.

[0058] Combine Figures 9-13 , the light-emitting element 20 includes a first light-emitting element 21 and a second light-emitting element 22. The first light-emitting element 21 is electrically connected to the first pixel circuit 41, and the second light-emitting element 22 is electrically connected to the second pixel circuit 42. The period in which the control signal S3 is at an effective level overlaps with the light-emitting period of the second light-emitting element 22. The first pixel circuit 41 connected to the first light-emitting element 21 is an abnormal pixel circuit 10, and the second pixel circuit 42 connected to the second light-emitting element 22 is a normal pixel circuit 10. The second light-emitting element 22 emits light normally. During the period in which the control signal S3 is at an effective level, the effective level of the control signal S3 controls the first pixel circuit 41 to not operate, and the first light-emitting element 21 does not emit light. Therefore, when the second light-emitting element 22 emits light normally, the effective level of the control signal S3 controls the first light-emitting element 21 electrically connected to the abnormal first pixel circuit 41 to not emit light.

[0059] Exemplarily, the light control signal lines include a first light control signal line EM12 and a second light control signal line EM13, and the scan signal lines Scan include a second scan signal line Scan2, a third scan signal line Scan3, and a fourth scan signal line Scan4. The control signal lines S include a first control signal line S32. The control terminals of the first pixel switch unit T41 and the second pixel switch unit T42 are electrically connected to the first control signal line S32. For example, the abnormal first pixel circuit 41 is pixel circuit b2, and the second pixel circuit 42 is pixel circuit c2. The period during which the first light control scan signal EM1 transmitted on the first light control signal line EM12 is at an active level is the fifth light control period P05. During the fifth light control period P05, the first control signal line S32 transmits an active level of the control signal S3. The active level of the control signal S3 controls the first light-emitting element 21 to not emit light. The sixth light control period P06 is the light-emitting period during which the second light-emitting element 22 emits light. In the sixth light emitting control period P06, the second pixel switch unit T42 is turned off, and the voltage provided by the second input signal line SL3 cannot be written to the anode of the second light emitting element 22. The second light emitting element 22 can emit light normally. In this way, the light emitting element 20 is individually controlled.

[0060] For example, if the first pixel switch unit T41 includes a PMOS transistor, the first pixel switch unit T41 is turned on when the gate-source voltage difference of the PMOS transistor is greater than the threshold voltage, and is turned off when the gate-source voltage difference of the PMOS transistor is less than the threshold voltage.

[0061] On the basis of the above embodiments, continue to refer to Figures 9-13 , the display panel 200 includes a first edge W1 extending along the first direction X, and at least part of the control signal line S extends to the first edge W1. Figure 9 In the second direction Y, the first light-emitting element 21 is located between the first edge W1 and the second light-emitting element 22. The voltage on the first input signal line SL2 is lower than the voltage on the second input signal line SL3. Therefore, the difference between the voltages on the first control signal line S32 and the first input signal line SL2 can turn on the first pixel switch unit T41, while the difference between the voltages on the first control signal line S32 and the second input signal line SL3 cannot turn on the second pixel switch unit T42, which remains off.

[0062] Figure 14 is a schematic diagram of another display panel provided by the present invention, Figure 15 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention. Based on the above embodiment, Figure 9 、 Figure 13-15Based on the above embodiment, the pixel circuit 10 includes a third pixel circuit 43 and a fourth pixel circuit 44. The third pixel circuit 43 and the fourth pixel circuit 44 are arranged along the first direction X. The first switch unit T connected to the third pixel circuit 43 is a third pixel switch unit T43, and the first switch unit T connected to the fourth pixel circuit 44 is a fourth pixel switch unit T44. The control signal line S includes a first control signal line S32 and a second control signal line S33. The first control signal line S32 is electrically connected to the third pixel switch unit T43, and the second control signal line S33 is electrically connected to the fourth pixel switch unit T44. The voltage on the first control signal line S32 is different from the voltage on the second control signal line S33.

[0063] As an example, a third pixel circuit 43 and a fourth pixel circuit 44 exist in the same row of pixel circuits 10, and the third pixel circuit 43 and the fourth pixel circuit 44 are connected to the same input signal line L. Thus, by controlling the voltage on the first control signal line S32 to be different from the voltage on the second control signal line S33, the third pixel switch unit T43 electrically connected to the abnormal third pixel circuit 43 is controlled to be turned on, the voltage on the first input signal line SL2 is transmitted to the first node N1 of the third pixel circuit 43, and the light-emitting element 20 connected to the abnormal third pixel circuit 43 is controlled not to emit light. The fourth pixel switch unit T44 electrically connected to the normal fourth pixel circuit 44 is controlled to be turned off, without affecting the normal operation of the fourth pixel circuit 44 or the normal light-emitting process of the light-emitting element 20 connected to the fourth pixel circuit 44.

[0064] For example, the abnormal third pixel circuit 43 is pixel circuit b2, and the fourth pixel circuit 44 is pixel circuit b3. The control terminal of the third pixel switch unit T43 is electrically connected to the first control signal line S32. The control terminal of the fourth pixel switch unit T44 is electrically connected to the second control signal line S33. The period during which the first light-emission control scanning signal EM1 transmitted on the first light-emission control signal line EM12 is at an active level is the fifth light-emission control period P05. During the fifth light-emission control period P05, the first control signal line S32 transmits an active level of the control signal S3. The active level of the control signal S3 controls the light-emitting element 20 connected to the abnormal third pixel circuit 43 to not emit light. During the fifth light-emission control period P05, the second control signal line S33 transmits an inactive level of the control signal S3. The inactive level of the control signal S3 controls the fourth pixel switch unit T44 to turn off, without affecting the normal operation of the fourth pixel circuit 44.

[0065] Exemplarily, the inactive level of the control signal S3 is a high level, and the active level of the control signal S3 is a low level. In other embodiments, the inactive level of the control signal S3 is a low level, and the active level of the control signal S3 is a high level.

[0066] Exemplarily, the first pixel circuit 41 and the third pixel circuit 43 are pixel circuit b2, and the first pixel circuit 41 and the third pixel circuit 43 are the same pixel circuit 10. In other embodiments, the first pixel circuit 41 and the third pixel circuit 43 may be different pixel circuits 10. For example, the third pixel circuit 43 is pixel circuit b3, and the fourth pixel circuit 44 is pixel circuit b4.

[0067] On the basis of the above embodiments, continue to refer to Figure 9 The display panel 200 includes a second edge W2 extending in the second direction Y, and at least a portion of the input signal line L extends to the second edge W2. Along the first direction X, the first control signal line S32 is located between the second edge W2 and the second control signal line S33. The first control signal line S32 is closer to the second edge W2 than the second control signal line S33. The second edge W2 may be the edge of the anisotropic cutting area. The area closer to the second edge W2 is more likely to have abnormal pixel circuits 10. In one example, the pixel circuit 10 electrically connected to the first control signal line S32 experiences an abnormality, while the pixel circuit 10 electrically connected to the second control signal line S33 does not experience an abnormality.

[0068] Based on the above embodiments, Figure 13-15 The period during which the first control signal line S32 transmits the control signal S3 at an active level overlaps with the period during which the plurality of first light emission control scanning signals EM1 are at an active level. The period during which the first control signal line S32 transmits the control signal S3 at an active level overlaps with the period during which the second control signal line S33 transmits the control signal at an inactive level.

[0069] In one example, in the display phase following the detection phase, the control signal S3 transmitted on each control signal line S has a fixed voltage. For example, the first control signal line S32 transmits the effective level of the control signal S3, and the second control signal line S33 transmits the ineffective level of the control signal S3. In the display phase, the plurality of scan signal lines Scan scan row by row and illuminate the light-emitting elements 20 row by row. The detection phase will be described later. In the display phase, the first control signal line S32 continuously controls the abnormal pixel circuit b2 to be turned off, and the second control signal line S33 continuously does not affect the normal operation process of the pixel circuit b3.

[0070] Based on the above embodiments, Figure 9 、 Figure 13-15 As shown, the input signal lines L include a first input signal line SL2 and a second input signal line SL3. The effective level voltage of the transmission control signal on the first control signal line S32 is between the voltage on the first input signal line SL2 and the voltage on the second input signal line SL3.

[0071] In the embodiment of the present application, taking the example of the first switch unit T including a PMOS transistor, the voltage at the effective level of the control signal transmitted on the first control signal line S32 is lower than the voltage on the first input signal line SL2. The voltage at the effective level of the control signal transmitted on the first control signal line S32 is higher than the voltage on the second input signal line SL3. In other embodiments, taking the example of the first switch unit T including an NMOS transistor, the voltage at the effective level of the control signal transmitted on the first control signal line S32 is higher than the voltage on the first input signal line SL2. The voltage at the effective level of the control signal transmitted on the first control signal line S32 is lower than the voltage on the second input signal line SL3.

[0072] Figure 16 is a schematic diagram of another display panel provided by the present invention, Figure 17 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention, referring to Figure 16 and Figure 17 The pixel circuit 10 includes a fifth pixel circuit 45 and a sixth pixel circuit 46, which are arranged along the second direction Y. The first switch unit T connected to the fifth pixel circuit 45 is a fifth pixel switch unit T45, and the first switch unit T connected to the sixth pixel circuit 46 is a sixth pixel switch unit T46. The input signal lines L include a third input signal line SL4 and a fourth input signal line SL5. The third input signal line SL4 is electrically connected to the fifth pixel switch unit T45, and the fourth input signal line SL5 is electrically connected to the sixth pixel switch unit T46. The voltage on the third input signal line SL4 includes a fixed voltage, and a floating voltage is applied to the fourth input signal line SL5.

[0073] As an example, a fifth pixel circuit 45 and a sixth pixel circuit 46 are present in the same column of pixel circuits 10. The fifth pixel switch unit T45 and the sixth pixel switch unit T46 are connected to the same control signal line S32. Thus, the fixed voltage on the third input signal line SL4 controls the fifth pixel switch unit T45 electrically connected to the abnormal fifth pixel circuit 45 to turn on. The voltage on the third input signal line SL4 is transmitted to the first node N1 of the fifth pixel circuit 45, thereby controlling the light-emitting element 20 connected to the abnormal fifth pixel circuit 45 to not emit light. Even if the sixth pixel switch unit T46 electrically connected to the normal sixth pixel circuit 46 is turned on, because the fourth input signal line SL5 is floating and no fixed voltage is applied to the fourth input signal line SL5, the normal operation of the sixth pixel circuit 46 is not affected, nor is the normal light-emitting process of the light-emitting element 20 connected to the sixth pixel circuit 46 affected.

[0074] For example, refer to Figure 12 、 Figure 16 and Figure 17 , the light-emitting control signal line includes a third light-emitting control signal line EM14, and the scan signal line Scan includes a fifth scan signal line Scan5. The control end of the first pixel switch unit T41 and the control end of the second pixel switch unit T42 are electrically connected to the first control signal line S32. Taking the abnormal fifth pixel circuit 45 as pixel circuit b2 and the sixth pixel circuit 46 as pixel circuit d2 as an example, the period during which the first light-emitting control scan signal EM1 transmitted on the first light-emitting control signal line EM12 is at an effective level is the fifth light-emitting control period P05. During the fifth light-emitting control period P05, the first control signal line S32 transmits an effective level of the control signal S3. The effective level of the control signal S3 controls the light-emitting element 20 connected to the pixel circuit b2 not to emit light. The period during which the first light-emitting control scan signal EM1 transmitted on the third light-emitting control signal line EM14 is at an effective level is the seventh light-emitting control period P07. During the seventh light-emission control period P07, the sixth pixel switch unit T46 is turned on. However, no additional voltage is written to the anode of the second light-emitting element 22, and no additional voltage affects the normal voltage of the anode of the second light-emitting element 22. The second light-emitting element 22 can emit light normally. In this way, the individual control of the light-emitting element 20 is achieved.

[0075] Exemplarily, the first pixel circuit 41 and the fifth pixel circuit 45 are pixel circuit b2, and the first pixel circuit 41 and the fifth pixel circuit 45 are the same pixel circuit 10. The first input signal line SL2 and the third input signal line SL4 are the same input signal line L. In other embodiments, the first pixel circuit 41 and the fifth pixel circuit 45 may be different pixel circuits 10. For example, the fifth pixel circuit 45 is pixel circuit c2, and the sixth pixel circuit 46 is pixel circuit d2. The first input signal line SL2 and the third input signal line SL4 are different input signal lines L.

[0076] Floating voltage refers to the indeterminate or high-impedance voltage state present at a point in a circuit because it is not directly grounded or connected to a fixed reference potential (such as the positive or negative pole of a power supply) through a low-impedance path.

[0077] Optionally, refer to Figure 16 and Figure 17 , a period during which the floating voltage is applied to the fourth input signal line SL5 overlaps with a period during which the control signal S3 is at an effective level.

[0078] In one example, in the display phase following the detection phase, the input signal transmitted on the third input signal line SL4 has a fixed voltage. The input signal lines L other than the third input signal line SL4 are connected to the normal pixel circuit 10, and the input signal lines L other than the third input signal line SL4 are floating. In the display phase, the third input signal line SL4 continuously writes the voltage transmitted thereon to the first node N1 of the abnormal pixel circuit b2, controlling the light-emitting element 20 electrically connected to the abnormal pixel circuit b2 not to emit light. The input signal lines L other than the third input signal line SL4 do not write an additional voltage to the first node N1 in the normal pixel circuit 10, and do not affect the light-emitting process of the light-emitting element 20 electrically connected to the normal pixel circuit 10.

[0079] Figure 18 This is a schematic diagram of the structure of another pixel circuit of a display panel provided by the present invention. Figure 19 The pixel circuit 10 further includes a resistor R, a first end of the resistor R being electrically connected to the first node N1, and a second end of the resistor R being electrically connected to the first end of the first switch unit T. In the embodiment of the present application, by providing the resistor R in the circuit between the first switch unit T and the anode of the light-emitting element 20, coupling current writing can be reduced, thereby preventing the light-emitting element 20 connected to an abnormal pixel circuit 10 from emitting light, thereby improving the stability of the overall circuit.

[0080] Figure 19 This is another driving timing diagram of the pixel circuit of the display panel provided by the present invention. Based on the above embodiment, reference is made to Figure 2 、 Figure 3 and Figure 19 The same first light emission control scanning signal EM1 includes an active level in the first period P21 and an inactive level in the second period P22. The same control signal S3 includes an active level in the third period P23 and an inactive level in the fourth period P24. The first period P21 overlaps with the third period P23, and the second period P22 overlaps with the fourth period P24.

[0081] As an example, in the first period P21, the power writing transistor M1 and the light-emitting control transistor M6 are turned on, and the driving voltage or driving current generated by the driving transistor M3 is transmitted to the light-emitting element 20, and the light-emitting element 20 emits light; in the second period P22, the power writing transistor M1 and the light-emitting control transistor M6 are turned off, and the light-emitting element 20 does not emit light.

[0082] For example, the active level of the first light-emitting control scanning signal EM1 is low, and the inactive level is high. The active level of the control signal S3 is low, and the inactive level is high. During the overlap of the first period P21 and the third period P23, the first switch unit T is turned on, and the voltage on the first voltage terminal SL is transmitted to the first node N1 of the pixel circuit 10, thereby controlling the light-emitting element 20 connected to the abnormal pixel circuit 10 to not emit light. During the overlap of the second period P22 and the fourth period P24, the first switch unit T is turned off, which does not affect the normal operation of the pixel circuit 10 or the normal light-emitting process of the light-emitting element 20 connected to the pixel circuit 10, and the light-emitting element 20 emits light. In this way, the problem of abnormal light-emitting of the light-emitting element 20 when the power writing transistor M1 and the light-emitting control transistor M6 are turned off can be solved.

[0083] Based on the above embodiments, Figure 2 、 Figure 3 、 Figure 9 and Figure 16 The first switch unit T includes a first switch transistor T1. A first electrode of the first switch transistor T1 is electrically connected to the first node N1, a second electrode of the first switch transistor T1 is electrically connected to the first voltage terminal SL, and a gate of the first switch transistor T1 receives a control signal S3.

[0084] As an example, the first switch unit T uses a first switch transistor T1. The first switch transistor T1 can be a PMOS transistor or an NMOS transistor.

[0085] For example, taking the first switching transistor T1 as a PMOS transistor, for an abnormal pixel circuit 10, during the light-emitting phase, the active-level voltage of the control signal S3 controls the first switching transistor T1 to be turned on, and the voltage on the input signal line L is written to the anode of the light-emitting element 20, causing the light-emitting element 20 to not emit light, thereby preventing the light-emitting element 20 connected to the abnormal pixel circuit 10 from emitting light abnormally. For a normal pixel circuit 10, during the light-emitting phase, the inactive-level voltage of the control signal S3 controls the first switching transistor T1 to be turned off, and the first light-emission control scanning signal EM1 provides a low-level signal, controlling the power writing transistor M1 and the light-emission control transistor M6 to be turned on. The driving voltage or driving current generated by the driving transistor M3 is transmitted to the light-emitting element 20, causing the light-emitting element 20 to emit light.

[0086] Figure 20 This is a schematic diagram of the structure of a pixel circuit of another display panel provided by the present invention, referring to Figure 2 、 Figure 20 The first voltage terminal SL is electrically connected to the cathode of the light emitting element 20 .

[0087] As an example, the cathode of the light-emitting element 20 is electrically connected to the second voltage terminal VSS, and the first voltage terminal SL is connected to the cathode of the light-emitting element 20. The second voltage terminal VSS is reused as the first voltage terminal SL. This eliminates the need for an input signal line L, thereby reducing at least one signal line. Furthermore, there is no need to adaptively design the value of the low voltage at the first voltage terminal SL that can prevent the light-emitting element 20 from emitting light, thereby simplifying the drive timing design.

[0088] For example, the first switch unit T employs a first switching transistor T1, which is a PMOS transistor. The gate of the first switching transistor T1 is connected to the control signal S3, the first electrode of the first switching transistor T1 is connected to the anode of the light-emitting element 20, and the second electrode of the first switching transistor T1 is connected to the cathode of the light-emitting element 20. For an abnormal pixel circuit 10, the active level of the control signal S3 is low, the first switching transistor T1 is turned on, and the anode and cathode of the light-emitting element 20 are short-circuited. The light-emitting element 20 does not emit light.

[0089] Figure 21 This is a schematic diagram of the structure of another pixel circuit of a display panel provided by the present invention. Figure 21 The display panel 200 further includes a detection unit JT, and the detection unit JT is electrically connected to the first node N1.

[0090] As an example, during the detection phase of the pixel circuit 10, electrical signals such as the voltage or current of the first node N1 are transmitted to the detection unit JT, and the external detection circuit analyzes the electrical signals to determine whether the working state of the pixel circuit 10 is normal. In this way, before the light-emitting element 20 is transferred to the array substrate, it is possible to detect whether the pixel circuit 10 on the array substrate has abnormal conditions such as open circuit, short circuit or thin film transistor failure. The present application performs detection by connecting the detection unit JT to the first node N1, replacing the existing visual detection. This avoids the situation where the array substrate needs to be scrapped due to problems, and can only be discarded together with the light-emitting elements transferred to the array substrate. This solves the problem of waste of light-emitting elements and also reduces production costs.

[0091] Based on the above embodiments, Figure 21 The detection unit JT includes a detection transistor T2, a first electrode of the detection transistor T2 is electrically connected to the first node N1, a second electrode of the detection transistor T2 is electrically connected to the detection circuit terminal JC, and a gate of the detection transistor T2 is electrically connected to the detection control signal terminal S4.

[0092] As an example, the detection transistor T2 can be a PMOS transistor or an NMOS transistor. The active level on the detection control signal terminal S4 is a voltage for turning on the detection transistor T2. The inactive level on the detection control signal terminal S4 is a voltage for turning off the detection transistor T2.

[0093] Illustratively, in the detection phase of the pixel circuit 10 , the active level on the detection control signal terminal S4 controls the detection transistor T2 to be turned on, and an electrical signal such as the voltage or current of the first node N1 is transmitted to the detection circuit terminal JC.

[0094] On the basis of the above embodiments, continue to refer to Figure 3 The first switch unit T is multiplexed as the detection unit JT. During the detection phase, the first switch unit T is turned on, providing the voltage of the first node N1 to the first voltage terminal SL, which is then multiplexed as the detection circuit terminal JC. This circuit structure design can reduce detection signal lines and simplify pixel circuit design and drive timing design.

[0095] For example, during the detection phase of the pixel circuit 10, the active level of the control signal S3 controls the first switch unit T to conduct, and an electrical signal, such as the voltage or current at the first node N1, is transmitted to the first voltage terminal SL. The external detection circuit analyzes the electrical signal to determine whether the pixel circuit 10 is operating normally. During the light-emitting phase of the light-emitting element 20, the active level of the control signal S3 controls the first switch unit T to conduct, and the voltage at the first voltage terminal SL is written to the anode of the light-emitting element 20, thereby controlling the light-emitting element 20 connected to the abnormal pixel circuit 10 to not emit light.

[0096] Figure 22 This is a schematic diagram of the structure of another pixel circuit of a display panel provided by the present invention. Figure 22 The display panel also includes a second switch unit T3, a first end of the second switch unit T3 is electrically connected to the cathode of the light emitting element 20, a second end of the second switch unit T3 is electrically connected to the first voltage end SL, and a control end of the second switch unit T3 is electrically connected to the control end of the first switch unit T.

[0097] As an example, the cathode of the light-emitting element 20 is connected to the second switch unit T3. When the second switch unit T3 is turned on, the voltage on the first voltage terminal SL is written to the cathode of the light-emitting element 20. This can prevent the cathode voltage of the light-emitting element 20 from being greater than the anode voltage when the cathode of the light-emitting element 20 is short-circuited with the high-voltage power supply voltage signal line VDD, thereby preventing the light-emitting element 20 from burning out.

[0098] Illustratively, during the light-emitting stage of the light-emitting element 20, the effective level of the control signal S3 controls the first switch unit T and the second switch unit T3 to be turned on at the same time, and the voltage on the first voltage terminal SL is simultaneously written to the anode and cathode of the light-emitting element 20, so that the light-emitting element 20 connected to the pixel circuit 10 that cannot work normally after cutting remains in a normally closed state.

[0099] On the basis of the above embodiments, continue to refer to Figure 22 The second switch unit T3 includes a second switch transistor T30. A first electrode of the second switch transistor T30 is electrically connected to the cathode of the light emitting element 20, a second electrode of the second switch transistor T30 is electrically connected to the first voltage terminal SL, and a gate of the second switch transistor T30 is electrically connected to the control terminal of the first switch unit T.

[0100] As an example, the first switch unit T and the second switch unit T3 both use a transistor, and the first switch unit T and the second switch unit T3 are controlled to be turned on or off by the same control signal S3, which is conducive to reducing the control timing. The anode and cathode of the light-emitting element 20 are written with low voltage at the same time, and the light-emitting element 20 connected to the abnormal pixel circuit remains in a normally closed state.

[0101] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 23 Schematic diagram of a display device provided by an embodiment of the present invention. Figure 23 As shown, the display device 300 includes any of the display panels 200 provided in the above embodiments. Therefore, the display device 300 also has the beneficial effects of the display panel 200 in the above embodiments. The similarities can be understood by referring to the above explanation of the display panel 300, which will not be repeated below.

[0102] The display device 300 provided by the embodiment of the present invention can be Figure 23 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, electronic paper display devices, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0103] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: comprising a pixel circuit, a light-emitting element and a first switching unit; The pixel circuit includes a first node and a light emitting control transistor, the first node is electrically connected to the anode of the light emitting element; a first electrode of the light emitting control transistor is electrically connected to the first node, and a gate of the light emitting control transistor receives a first light emitting control scanning signal; A first terminal of the first switch unit is electrically connected to the first node, a second terminal of the first switch unit is electrically connected to a first voltage terminal, and a control terminal of the first switch unit receives a control signal; A period during which the control signal is at an effective level overlaps a period during which the first light emitting control scanning signal is at an effective level.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a driving transistor and a power writing transistor, wherein a first electrode of the driving transistor is electrically connected to a second electrode of the light emission control transistor, a second electrode of the driving transistor is electrically connected to a first electrode of the power writing transistor, and a gate of the power writing transistor receives a second light emission control scanning signal; A period in which the control signal is at an effective level, a period in which the first light emitting control scanning signal is at an effective level, and a period in which the second light emitting control scanning signal is at an effective level overlap.

3. The display panel according to claim 1, wherein: The pixel circuit includes an amplitude adjustment module and a pulse width modulation module, the amplitude adjustment module includes the light emitting control transistor and the driving transistor, and the first electrode of the driving transistor is electrically connected to the second electrode of the light emitting control transistor; The input end of the pulse width modulation module receives the frequency sweep signal, and the output end of the pulse width modulation module is electrically connected to the gate of the driving transistor; The effective level of the frequency sweep signal is within a period of time when the first light emitting control scanning signal has an effective level, and the period of time when the control signal has an effective level overlaps with the period of time when the frequency sweep signal has an effective level.

4. The display panel according to claim 1, wherein: The cathode of the light emitting element is electrically connected to the second voltage terminal; The voltage of the first voltage terminal is less than or equal to the voltage of the second voltage terminal.

5. The display panel according to claim 1, wherein: The system further comprises a plurality of control signal lines and a plurality of input signal lines, wherein the control signal lines transmit the control signals, the plurality of control signal lines are arranged along a first direction, and the plurality of input signal lines are arranged along a second direction, wherein the first direction intersects the second direction; Along the first direction, a plurality of the first voltage terminals are electrically connected to the same input signal line, and along the second direction, a plurality of the control terminals of the first switch units are electrically connected to the same control signal line.

6. The display panel according to claim 5, wherein: The pixel circuit includes a first pixel circuit and a second pixel circuit, the first pixel circuit and the second pixel circuit are arranged along the second direction; the first switch unit connected to the first pixel circuit is a first pixel switch unit, and the first switch unit connected to the second pixel circuit is a second pixel switch unit; The input signal line includes a first input signal line and a second input signal line, the first input signal line is electrically connected to the first pixel switch unit, and the second input signal line is electrically connected to the second pixel switch unit; The voltage on the first input signal line is different from the voltage on the second input signal line.

7. The display panel according to claim 6, wherein: The display panel includes a first edge extending along the first direction, and at least part of the control signal line extends to the first edge; Along the second direction, the first input signal line is located between the first edge and the second input signal line.

8. The display panel according to claim 6, wherein: The light-emitting element includes a first light-emitting element and a second light-emitting element, the first light-emitting element is electrically connected to the first pixel circuit, and the second light-emitting element is electrically connected to the second pixel circuit; The period during which the control signal is at an effective level overlaps with the light-emitting period of the second light-emitting element.

9. The display panel according to claim 8, wherein: The display panel includes a first edge extending along the first direction, and at least part of the control signal line extends to the first edge; Along the second direction, the first light-emitting element is located between the first edge and the second light-emitting element; The voltage on the first input signal line is lower than the voltage on the second input signal line.

10. The display panel according to claim 5, wherein: The pixel circuit includes a third pixel circuit and a fourth pixel circuit, and the third pixel circuit and the fourth pixel circuit are arranged along the first direction; the first switch unit connected to the third pixel circuit is a third pixel switch unit, and the first switch unit connected to the fourth pixel circuit is a fourth pixel switch unit; The control signal line includes a first control signal line and a second control signal line, the first control signal line is electrically connected to the third pixel switch unit, and the second control signal line is electrically connected to the fourth pixel switch unit; The voltage on the first control signal line is different from the voltage on the second control signal line.

11. The display panel according to claim 10, wherein: The display panel includes a second edge extending along the second direction, and at least part of the input signal line extends to the second edge; Along the first direction, the first control signal line is located between the second edge and the second control signal line.

12. The display panel according to claim 10, wherein: The period during which the effective level of the control signal is transmitted on the first control signal line overlaps with the period during which the effective levels of the plurality of first light-emitting control scanning signals are transmitted; A time period during which the effective level of the control signal is transmitted on the first control signal line overlaps with a time period during which the ineffective level of the control signal is transmitted on the second control signal line.

13. The display panel according to claim 12, wherein: The input signal line includes a first input signal line and a second input signal line; The voltage of the effective level of the transmission control signal on the first control signal line is between the voltage on the first input signal line and the voltage on the second input signal line.

14. The display panel according to claim 5, wherein: The pixel circuit includes a fifth pixel circuit and a sixth pixel circuit, and the fifth pixel circuit and the sixth pixel circuit are arranged along the second direction; the first switch unit connected to the fifth pixel circuit is a fifth pixel switch unit, and the first switch unit connected to the sixth pixel circuit is a sixth pixel switch unit; The input signal line includes a third input signal line and a fourth input signal line, the third input signal line is electrically connected to the fifth pixel switch unit, and the fourth input signal line is electrically connected to the sixth pixel switch unit; The voltage on the third input signal line includes a fixed voltage, and a floating voltage is applied to the fourth input signal line.

15. The display panel according to claim 14, wherein: A period during which the floating voltage is applied to the fourth input signal line overlaps with a period during which the control signal is at an active level.

16. The display panel according to claim 15, wherein: A resistor is further included, wherein a first end of the resistor is electrically connected to the first node, and a second end of the resistor is electrically connected to the first end of the first switch unit.

17. The display panel according to claim 1, wherein: The same first light emitting control scanning signal includes a valid level in the first time period and includes an invalid level in the second time period; The same control signal includes a valid level in the third period and an invalid level in the fourth period; The first time period overlaps with the third time period, and the second time period overlaps with the fourth time period.

18. The display panel according to claim 1, wherein The first switching unit includes a first switching transistor; A first electrode of the first switch transistor is electrically connected to the first node, a second electrode of the first switch transistor is electrically connected to the first voltage terminal, and a gate of the first switch transistor receives the control signal.

19. The display panel according to claim 1, wherein The first voltage terminal is electrically connected to the cathode of the light emitting element.

20. The display panel according to claim 1, wherein The system further includes a detection unit electrically connected to the first node.

21. The display panel according to claim 20, wherein: The detection unit includes a detection transistor, a first electrode of the detection transistor is electrically connected to the first node, a second electrode of the detection transistor is electrically connected to the detection circuit terminal, and a gate of the detection transistor is electrically connected to the detection control signal terminal.

22. The display panel according to claim 20, wherein: The first switch unit is multiplexed as the detection unit; In the detection phase, the first switch unit is turned on to provide the voltage of the first node to the first voltage terminal, and the first voltage terminal is multiplexed as a detection circuit terminal.

23. The display panel according to claim 1, wherein It also includes a second switch unit, a first end of the second switch unit is electrically connected to the cathode of the light-emitting element, a second end of the second switch unit is electrically connected to the first voltage end, and a control end of the second switch unit is electrically connected to the control end of the first switch unit.

24. The display panel according to claim 23, wherein: The second switching unit includes a second switching transistor; The first electrode of the second switch transistor is electrically connected to the cathode of the light emitting element, the second electrode of the second switch transistor is electrically connected to the first voltage terminal, and the gate of the second switch transistor is electrically connected to the control terminal of the first switch unit.

25. The display panel according to claim 1, wherein The light emitting element includes an inorganic light emitting diode.

26. A display device, characterized in that: A display panel comprising any one of claims 1-25.

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