Gate drive circuit, panel drive circuit and display device

Abstract

The invention relates to a gate drive circuit, a panel drive circuit and a display device, and the gate drive circuit comprises an input switch module, an output module, a control module, a self-pull-down module, a pull-down maintenance module and a resistor module, the first end of the resistor module is electrically connected with the control end of the self-pull-down module and the control end of the control module, and the second end of the resistor module is electrically connected with the control end of the self-pull-down module. The first end of the self-pull-down module is electrically connected with the input switch module, the second end of the resistor module is electrically connected with a first node, and the first node is a node connected with the output end of the self-pull-down module, the control end of the pull-down maintaining module and the second end of the resistor module. According to the gate drive circuit, the automatic pull-down function is realized, and the circuit structure is simplified, so that the problems of complicated circuit structure and high manufacturing cost caused by the fact that the gate drive circuit adopts a reverse circuit consisting of four MOS (Metal Oxide Semiconductor) tubes to realize the pull-down function in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a gate driving circuit, a panel driving circuit and a display device. Background Art

[0002] With the rapid development of display technology, the gate on array (GOA) driving circuit has become one of the core technologies of liquid crystal display (LCD) panels due to its advantages of being integrated on the panel array substrate and saving peripheral driving chips.

[0003] In existing GOA drive circuits, the pull-down function is usually implemented by a reverse circuit consisting of four metal-oxide-semiconductor (MOS) transistors. This results in a complex circuit structure and a large number of components, increasing the complexity of panel design and manufacturing costs. Summary of the Invention

[0004] In view of this, the present application provides a gate drive circuit, a panel drive circuit and a display device, which realize autonomous pull-down by simplifying the circuit structure, thereby solving the problems of complex circuit structure and high manufacturing cost in the existing related technology caused by the gate drive circuit using a reverse circuit composed of 4 MOS tubes to realize the pull-down function.

[0005] In a first aspect, an embodiment of the present application provides a gate drive circuit, comprising: an input switch module, an output module, a control module, a self-pull-down module, a pull-down maintaining module, and a resistance module;

[0006] The first end of the resistor module is electrically connected to the control end of the self-pull-down module and the control end of the control module, and the second end of the resistor module is electrically connected to a first node, which is a node where the output end of the self-pull-down module, the control end of the pull-down maintaining module, and the second end of the resistor module are connected;

[0007] The input switch module is configured to transmit the first signal output by the first signal terminal to the control node under the control of the first signal terminal;

[0008] The control module is configured to transmit the first power signal provided by the first power terminal to the control node under the control of the second signal terminal;

[0009] The output module is configured to output a gate drive signal based on a clock signal provided by a clock signal terminal under the control of the control node;

[0010] The self-pull-down module is configured to transmit the second power signal provided by the second power terminal to the first node under the control of the second signal terminal;

[0011] The pull-down maintaining module is used to transmit the first power signal provided by the first power end to the control node and the output end of the output module under the control of the first node.

[0012] Optionally, the pull-down module includes a pull-down transistor, a control terminal of the pull-down transistor is electrically connected to the second signal terminal, a first terminal of the pull-down transistor is electrically connected to the second power terminal, and a second terminal of the pull-down transistor is electrically connected to the first node;

[0013] The resistance module includes a first resistor, a first end of the first resistor is electrically connected to the control end of the pull-down transistor, and a second end of the first resistor is electrically connected to the first node.

[0014] Optionally, the control module includes a control transistor, a first end of the control transistor is electrically connected to the control node, a second end of the control transistor is electrically connected to the first power supply end, and a control end of the control transistor is electrically connected to the second signal end, and the on-state voltage of the pull-down transistor is less than the on-state voltage of the control transistor.

[0015] Optionally, the pull-down maintaining module includes a first pull-down maintaining transistor and a second pull-down maintaining transistor;

[0016] The first pull-down holding transistor is configured to transmit the first power signal provided by the first power terminal to the control node under the control of the first node;

[0017] The second pull-down holding transistor is configured to transmit the first power signal provided by the first power terminal to the output terminal of the output module under the control of the first node.

[0018] Optionally, the output module includes an output transistor and a first capacitor; the control node is a node where the second end of the input switch module is connected to the first end of the control module, the first end of the first capacitor, the first output end of the pull-down maintenance module, and the control end of the output transistor; the second end of the first capacitor is electrically connected to the output end of the output transistor, and the gate drive signal is used to drive the liquid crystal drive circuit of the display area to display.

[0019] Optionally, the output module includes an output transistor, in which an integrated capacitor is integrated. The output transistor is specifically used to output the gate drive signal based on the clock signal and the voltage signal provided by the integrated capacitor under the control of the control node.

[0020] Optionally, the gate drive circuit further includes: a reset module; the reset module is configured to transmit a reset signal provided by the reset signal terminal to the output terminal of the output module under the control of the second signal terminal.

[0021] In a second aspect, an embodiment of the present application provides a panel driving circuit, comprising: N cascaded gate driving circuit units, and each gate driving circuit unit comprises a gate driving circuit as described in any one of the first aspects, wherein N is an integer greater than 1.

[0022] Optionally, among the N gate driving circuit units, the first signal end of the first gate driving circuit unit is used to receive a frame start signal, and the first signal end of the Nth gate driving circuit unit is connected to the output end of its adjacent upper-level gate driving circuit unit.

[0023] Optionally, the panel driving circuit further includes: a pixel array, wherein the pixel array includes N rows of pixel units connected to the gate driving circuit units in a one-to-one correspondence.

[0024] Optionally, each of the pixel units in the pixel array includes a liquid crystal driving transistor, and a control end of the liquid crystal driving transistor in each row is electrically connected to an output end of the gate driving circuit unit to which it is connected.

[0025] Optionally, each of the pixel units further includes a liquid crystal capacitor;

[0026] In the same pixel unit, the first end of the liquid crystal capacitor is electrically connected to the second end of the liquid crystal driving transistor, the second end of the liquid crystal capacitor is electrically connected to the first common power supply end in the pixel array, and the first end of the driving transistor is electrically connected to the data line in the pixel array.

[0027] In a third aspect, an embodiment of the present application provides a display device, comprising a panel driving circuit as described in any one of the second aspects.

[0028] In summary, the gate drive circuit, panel drive circuit and display device provided in the embodiments of the present application realize an autonomous pull-down function through an input switch module, an output module, a self-pull-down module, a pull-down maintenance module and a resistance module. Compared with the solution of the existing related technology that uses a reverse circuit composed of four MOS tubes to realize the pull-down function, the embodiments of the present application can effectively simplify the circuit structure and reduce costs, and solve the problems of complex circuit structure and high manufacturing cost in the existing related technology caused by the gate drive circuit using a reverse circuit composed of four MOS tubes to realize the pull-down function. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0032] Figure 1 A schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of the circuit structure of a gate drive circuit provided in an optional embodiment of the present application;

[0034] Figure 3 A schematic diagram of the circuit structure of a gate drive circuit provided in another optional embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of an output transistor provided as an example of this application;

[0036] Figure 5 A schematic diagram of a panel driving circuit provided in an optional embodiment of the present application;

[0037] Figure 6 A driving timing diagram of a gate driving circuit provided as an example of the present application;

[0038] Figure 7 A schematic diagram of a panel driving circuit provided as an example of the present application;

[0039] Figure 8 A schematic structural diagram of a display device provided as an example of the present application.

[0040] Among them, 110 is an input switch module, 120 is an output module, 130 is a control module, 140 is a pull-down module, 150 is a pull-down maintenance module, 160 is a resistance module, 170 is a reset module, 700 is a display device, 710 is a panel drive circuit, 711 is a mainboard power supply module 711, T1 is an input switch transistor, T2 is an output transistor, T3 is a control transistor, T4 is a pull-down transistor, T5 is a first pull-down maintenance transistor, T6 is a second pull-down maintenance transistor, T7 is a reset transistor, and Q is a control transistor. point, N1 is a first node, STV is a first signal terminal, CK is a clock signal terminal, CK1 is a first clock signal provided by the clock signal terminal, CK2 is a first clock signal provided by the clock signal terminal, CKn is an output terminal of the output transistor or the output module, CKn+1 is a second signal terminal, VGH is a second power supply terminal, VSSQ is a first power supply terminal, VSSG is a reset signal terminal, R1 is a first resistor, C1 is a first capacitor, DATA1, DATA2 and DATA3 are data signal terminals connected to the column drive transistors in the display area. DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0043] Figure 1A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application. The gate drive circuit provided in this embodiment may specifically include: an input switch module 110, an output module 120, a control module 130, a pull-down module 140, a pull-down maintaining module 150, and a resistor module 160; the first end of the resistor module 160 is electrically connected to the control end of the pull-down module 140 and the control end of the control module 130, and the second end of the resistor module 160 is electrically connected to a first node N1, and the first node N1 is a node where the output end of the pull-down module 140, the control end of the pull-down maintaining module 150, and the second end of the resistor module 160 are connected; the input switch module 110 is used to transmit the first signal output from the first signal terminal STV under the control of the first signal terminal STV to the control node Q; the control module 130 is used to transmit the first power signal provided by the first power terminal VSSQ to the control node Q under the control of the second signal terminal CKn+1; the output module 120 is used to output a gate drive signal based on the clock signal provided by the clock signal terminal CK under the control of the control node Q; the self-pull-down module 140 is used to transmit the second power signal provided by the second power terminal TGH to the first node N1 under the control of the second signal terminal CKn+1; the pull-down maintenance module 150 is used to transmit the first power signal provided by the first power terminal VSSQ to the control node Q and the output terminal CKn of the output module 120 under the control of the first node N1.

[0044] Specifically, the gate drive circuit provided in the embodiment of the present application transmits the first signal output from the first signal terminal STV to the control node Q through the input switch module 110 under the control of the first signal terminal STV, and transmits the first power signal provided by the first power terminal VSSQ to the control node Q through the control module 130 under the control of the second signal terminal CKn+1, so that the output module 120 can output the gate drive signal based on the clock signal provided by the clock signal terminal CK under the control of the control node Q, so as to drive the liquid crystal drive circuit of the display area through the gate drive signal to realize liquid crystal driving; and, through the self-pull-down module 140 under the control of the second signal terminal CKn+1, transmits the second power signal provided by the second power terminal TGH to the first node N1, so that the pull-up maintenance module transmits the first power signal provided by the first power terminal VSSQ to the control node Q and the output terminal CKn of the output module 120 under the control of the first node N1, so as to continuously pull down the potential of the control node Q and the output terminal CKn of the output module 120 through the first power signal, thereby realizing the autonomous pull-down function.

[0045] It can be seen that the gate drive circuit provided by the embodiment of the present application realizes the autonomous pull-down function through the coordinated action of the input switch module 110, the output module 120, the self-pull-down module 140, the pull-down maintenance module 150 and the resistance module 160, eliminating the reverse circuit composed of four MOS tubes used in the existing related technology, which can effectively simplify the circuit structure and reduce costs, thereby solving the problems of complex circuit structure and high manufacturing cost in the existing related technology caused by the gate drive circuit using a reverse circuit composed of four MOS tubes to realize the pull-down function.

[0046] It should be noted that the gate drive signal in the embodiment of the present application is used to drive the liquid crystal drive circuit in the display area for display; the first power supply signal can be used as a gate-off signal, which can specifically be used to disconnect the output of the output module 120. For example, when the output module 120 includes an output transistor T2, the first power supply signal can be a low-level signal provided by the first power supply terminal VSSQ, so that the potential of the control node Q is lowered by the low-level signal, so that the output transistor T2 is cut off and disconnected, thereby turning off the output of the output module 120.

[0047] In some optional embodiments of the present application, transistors can be used to implement the functions of the input switch module 110, the output module 120, the control module 130, the pull-down module 140, and the pull-down maintenance module 150 in the embodiment of the present application. Figure 2 As shown, an input switch transistor T1 can be used to implement the input switch module 110, an output transistor T2 can be used to implement the module of the output module 120, a control transistor T3 can be used to implement the module of the control module 130, and a pull-down transistor T4 can be used to implement the function of the self-pull-down module 140. The embodiments of the present application are not limited to this.

[0048] Optionally, the self-pull-down module 140 in the embodiment of the present application includes a pull-down transistor T4, the control end of the pull-down transistor T4 is electrically connected to the second signal end CKn+1, the first end of the pull-down transistor T4 is electrically connected to the second power supply end TGH, and the second end of the pull-down transistor is electrically connected to the first node N1, so that the pull-down transistor T4 can transmit the second power supply signal provided by the second power supply end TGH to the first node N1 under the control of the second signal end CKn+1 to realize the power of the self-pull-down module 140.

[0049] Optionally, the resistance module 160 in the embodiment of the present application includes a first resistor R1, the first end of the first resistor R1 is electrically connected to the control end of the pull-down transistor T4, and the second end of the first resistor R1 is electrically connected to the first node, so that the gate drive circuit can, through the pull-down maintenance module 150, under the control of the first node N1, continuously pull down the potential of the control node Q and the potential of the output end CKn of the output module 120 through the first power supply signal provided by the first power supply end VSSQ, thereby causing the potential of the control node Q and the potential of the output end CKn of the output module 120 to be continuously pulled down to the level corresponding to the first power supply signal.

[0050] Optionally, the control module 130 in the embodiment of the present application includes a control transistor T3, a first end of the control transistor T3 is electrically connected to the control node Q, a second end of the control transistor T3 is electrically connected to the first power supply terminal VSSQ, and the control end of the control transistor T3 is electrically connected to the second signal terminal CKn+1, so that the control transistor T3 can transmit the first power signal provided by the first power supply terminal VSSQ to the control node Q under the control of the second signal terminal CKn+1, and the turn-on voltage of the pull-down transistor T4 is lower than the turn-on voltage of the control transistor T3, so that the second power signal provided by the second power supply terminal TGH can be transmitted to the first node N1 through the turned-on pull-down transistor T4, thereby enabling the pull-down maintaining module 150 to transmit the first power signal provided by the first power supply terminal VSSQ to the control node Q and the output terminal CKn of the output module 120 under the control of the first node N1, so as to maintain the continuous pull-down of the control node Q and the output terminal CKn of the output module 120, thereby ensuring that the liquid crystal driving circuit in the display area can display normally.

[0051] Optionally, the pull-down maintaining module 150 in the embodiment of the present application includes a first pull-down maintaining transistor T5 and a second pull-down maintaining transistor T6; the first pull-down maintaining transistor T5 is used to transmit the first power supply signal provided by the first power supply terminal VSSQ to the control node Q under the control of the first node N1; the second pull-down maintaining transistor T6 is used to transmit the first power supply signal provided by the first power supply terminal VSSQ to the output terminal CKn of the output module 120 under the control of the first node N1.

[0052] The following is an example of an embodiment of the present application in which the input switch module 110 includes an input switch transistor T1, the output module 120 includes an output transistor T2, the control module 130 includes a control transistor T3, the pull-down module 140 includes a pull-down transistor T4, the pull-down maintenance module 150 includes two pull-down maintenance transistors, and the resistance module 160 includes a first resistor R1, to illustrate the embodiment of the present application. However, it should be noted that the implementation of the present application may have the features described below, but the following description does not constitute a limitation on the scope of protection of the embodiment of the present application.

[0053] As an example of the present application, when the pull-down maintenance module 150 includes two pull-down maintenance transistors, one of the pull-down maintenance crystals can be used as the first pull-down maintenance transistor T5 for maintaining the control node Q1 to be pulled down, and the other pull-down maintenance crystal can be used as the second pull-down maintenance transistor T6 for maintaining the output terminal CKn of the output transistor T2 to be pulled down.

[0054] like Figure 2 As shown, in the case where the gate drive circuit specifically includes: an input switch transistor T1, an output transistor T2, a control transistor T3, a pull-down transistor T4, a first pull-down maintenance transistor T5, a second pull-down maintenance transistor T6 and a first resistor R1, a first end of the first resistor R1 is electrically connected to the control end of the pull-down transistor T4 and the control end of the control transistor T3, a second end of the first resistor R1 is electrically connected to a first node N1, and the first node N1 is a node where the output end of the pull-down transistor T4, the control end of the first pull-down maintenance transistor T5 and the control end of the second pull-down maintenance transistor T6 are connected; the input switch transistor T1 is used to transmit the first signal output by the first signal terminal STV to the control node Q under the control of the first signal terminal STV; the control transistor T3 is used to transmit the first signal output by the first signal terminal STV to the control node Q under the control of the second signal terminal STV; The output transistor T2 is configured to output a gate drive signal based on the clock signal provided by the clock signal terminal CK under the control of the control node Q; the pull-down transistor T4 is configured to transmit the second power signal provided by the second power terminal TGH to the first node N1 under the control of the second signal terminal CKn+1; the first pull-down maintenance transistor T5 is configured to transmit the first power signal provided by the first power terminal VSSQ to the control node Q under the control of the first node N1; the second pull-down maintenance transistor T6 is configured to transmit the first power signal provided by the first power terminal VSSQ to the output terminal CKn of the output transistor T2 under the control of the first node N1.

[0055] In a specific implementation, the gate drive circuit provided in the embodiment of the present application can transmit the first signal output from the first signal terminal STV to the control node Q through the input switch transistor T1 under the control of the first signal terminal STV, and transmit the first power supply signal provided by the first power supply terminal VSSQ to the control node Q through the control transistor T3 under the control of the second signal terminal CKn+1, so that the output transistor T2 can output the gate drive signal based on the clock signal provided by the clock signal terminal CK under the control of the control node Q, so as to drive the liquid crystal drive circuit of the display area through the gate drive signal to realize liquid crystal drive; and, through the pull-down transistor T4 in the second Under the control of the signal terminal CKn+1, the second power supply signal provided by the second power supply terminal TGH is transmitted to the first node N1, so that the first pull-down maintenance transistor T5, under the control of the first node N1, transmits the first power supply signal provided by the first power supply terminal VSSQ to the control node Q, so as to continuously pull down the potential of the control node Q through the first power supply signal, and, under the control of the first node N1, the second pull-down maintenance transistor T6 transmits the first power supply signal provided by the first power supply terminal VSSQ to the output terminal CKn of the output transistor T2, so as to continuously pull down the potential of the output terminal CKn of the output transistor T2 through the first power supply signal, thereby realizing the autonomous pull-down function.

[0056] It can be seen that the gate drive circuit provided by the embodiment of the present application realizes an autonomous pull-down function through the synergistic effect of the output transistor T2, the pull-down transistor T4, the first pull-down maintaining transistor T5, the second pull-down maintaining transistor T6 and the first resistor R1, eliminating the reverse circuit composed of four MOS tubes used in the existing related technology, which can effectively simplify the circuit structure and reduce costs, thereby solving the problems of complex circuit structure and high manufacturing cost in the existing related technology caused by the gate drive circuit using a reverse circuit composed of four MOS tubes to realize the pull-down function.

[0057] It should be noted that the gate drive signal in the embodiment of the present application is used to drive the liquid crystal drive circuit in the display area to display; the first power supply signal can be used as a gate-off signal, specifically for disconnecting the output transistor T2, such as the first power supply signal can be a low-level signal provided by the first power supply terminal VSSQ, so as to lower the potential of the control node Q through the low-level signal, so that the output transistor T2 is disconnected.

[0058] Of course, the gate drive circuit in the embodiment of the present application may include not only the input switch transistor T1, the output transistor T2, the control transistor T3, the pull-down transistor T4, the first pull-down maintaining transistor T5, the second pull-down maintaining transistor T6 and the first resistor R1, but may also include other functional devices and modules, such as a reset module 170, a charging capacitor, etc., and this embodiment does not limit this.

[0059] In some optional embodiments of the present application, the output module 120 includes an output transistor T2 and a first capacitor; Figure 3 As shown, the control node Q is a node connecting the second end of the input switch transistor T1, the first end of the control transistor T3, the first end of the first capacitor C1, the first end of the first pull-down maintenance transistor T5, the first end of the second pull-down maintenance transistor T6, and the control end of the output transistor T2; the second end of the first capacitor C1 is electrically connected to the output end CKn of the output transistor T2, so that electric energy can be stored through the first capacitor C1, thereby extending the on time of the output transistor T2 and ensuring normal display of the display area.

[0060] It can be seen that one end of the first capacitor C1 in the embodiment of the present application is connected to the control end of the output transistor T2, and the other end is electrically connected to the output end CKn of the output transistor T2, so that the first capacitor C1 can be used as a charging capacitor to store electrical energy through the charging capacitor and extend the opening time of the output transistor T2.

[0061] In one embodiment of the present application, an energy storage switch transistor with an integrated capacitor can be used as the output transistor T2 in the gate drive circuit, so that the output transistor T2 can store electrical energy through the integrated capacitor inside it, such as adding a TFT capacitor to the traditional thin film transistor (TFT) structure. Figure 4 As shown, the TFT capacitor is used as an integrated capacitor integrated in the energy storage switching transistor, and the energy storage switching transistor can be used as the output transistor T2 in the gate drive circuit, so that the open time of the output transistor T2 is extended by the integrated capacitor in the output transistor T2, so that the output transistor T2 can output the gate drive signal based on the clock signal provided by the clock signal terminal CK and the voltage signal provided by the integrated capacitor under the control of the control node Q, thereby reducing the cost of the drive circuit.

[0062] It should be noted that the traditional TFT structure mainly forms a gate layer GATA, an insulating layer and a semiconductor layer in sequence on a glass substrate, and forms an ohmic contact layer and a source metal at one end of the semiconductor layer, and an ohmic contact layer and a drain metal at the other end of the semiconductor layer, so that the TFT can be used as a switch tube in the GOA gate drive circuit.

[0063] In some optional embodiments of the present application, the output transistor T2 is integrated with an integrated capacitor, and the output transistor T2 is specifically configured to output the gate drive signal based on the clock signal provided by the clock signal terminal CK and the voltage signal provided by the integrated capacitor under the control of the control node Q. Specifically, Figure 5As shown, the gate of the input switch transistor T1 serves as the control terminal of the input switch transistor T1 and is electrically connected to the first terminal of the input switch transistor T1 and the first signal terminal STV, so that the input switch transistor T1 can transmit the first signal output by the first signal terminal STV to the control node Q under the control of the first signal terminal STV, and the control node Q is a node where the second terminal of the input switch transistor T1 is connected to the first terminal of the control transistor T3 and the output transistor T2, so that the output transistor T2 can output a gate drive signal to the liquid crystal drive circuit of the display area through the output terminal CKn of the output transistor T2 based on the clock signal provided by the clock signal terminal CK and the voltage signal provided by the integrated capacitor under the control of the control node Q, thereby realizing liquid crystal display.

[0064] In some optional embodiments of the present application, the gate drive circuit provided in the embodiment of the present application may further include: a reset module 170; Figure 5 As shown, a first terminal of the reset module 170 is electrically connected to the output terminal CKn of the output module 120, a second terminal of the reset module 170 is electrically connected to the reset signal terminal VSSG, and a control terminal of the reset module 170 is electrically connected to the second signal terminal CKn+1, so that the reset module 170 can transmit the reset signal provided by the reset signal terminal VSSG to the output terminal CKn of the output module 120 under the control of the second signal terminal CKn+1, so as to shut down the output of the output module 120. The reset module 170 is configured to transmit the reset signal provided by the reset signal terminal to the output terminal of the output module 120 under the control of the second signal terminal.

[0065] In some optional embodiments of the present application, a reset transistor can be used to implement the function of the reset module 170, and the embodiments of the present application are not limited to this. For example, when the reset module 170 includes a reset transistor T7, the reset transistor T7 is used to transmit the reset signal provided by the reset signal terminal VSSG to the output terminal CKn of the output transistor T2 under the control of the second signal terminal CKn+1, so as to reset the output terminal CKn of the output transistor T2 through the reset signal. Specifically, Figure 5 As shown, the first end of the reset transistor T7 is electrically connected to the output terminal CKn of the output transistor T2, the second end of the reset transistor T7 is electrically connected to the reset signal terminal VSSG, and the gate of the reset transistor T7 is electrically connected to the second signal terminal CKn+1, that is, the gate of the reset transistor T7 serves as the control terminal of the reset transistor T7, so that the reset transistor T7 can transmit the reset signal provided by the reset signal terminal VSSG to the output terminal CKn of the output transistor T2 under the control of the second signal terminal CKn+1, so as to reset the output end of the transistor T2, that is, turn off the output of the output transistor T2, thereby ensuring normal display of the display area.

[0066] In some optional embodiments of the present application, the reset signal provided by the reset signal terminal VSSG and the first power supply signal provided by the first power supply terminal VSSQ can both be low-level signals, so that the low-level signal provided by the reset signal terminal VSSG can be transmitted to the output terminal CKn of the output transistor T2 as the first power supply signal, thereby resetting the output terminal CKn of the output transistor T2; and the low-level signal provided by the first power supply terminal VSSQ can be transmitted to the control node Q through the first pull-down maintenance transistor T5 as the first power supply signal, so that the control node Q is continuously pulled down to a low-level potential when the first pull-down maintenance transistor T5 is turned on, and the first power supply signal can be transmitted to the output terminal CKn of the output transistor T2 through the second pull-down maintenance transistor T6 to maintain the potential of the output terminal CKn of the output transistor T2 being pulled down, that is, the output terminal of the transistor T2 is continuously pulled down to a low-level potential when the second pull-down maintenance transistor T6 is turned on.

[0067] As an example of the present application, when the input switch transistor T1, the output transistor T2, the control transistor T3, the pull-down transistor T4, the first pull-down maintaining transistor T5, the second pull-down maintaining transistor T6 and the reset transistor T7 are all high-level conductive TFTs, the first power supply signal provided by the first power supply terminal VSSQ and the reset signal Reset provided by the reset signal terminal VSSG are both low-level signals, and the second power supply signal provided by the second power supply terminal VGH is a high-level signal. In the charging stage, as Figure 6 As shown, when the first signal outputted by the first signal terminal STV is a high level signal, the input switch transistor T1 is turned on, as shown in FIG. Figure 7 As shown, the high-level signal provided by the first signal terminal STV is transmitted to the control node Q, raising the potential of the control node Q and charging the first capacitor C1. The circuit waits for the first clock signal CK1 provided by the clock signal terminal CK to be pulled high. The first capacitor C1 maintains the output transistor T2 on, causing the gate drive signal output by the output terminal CKn of the output transistor T2 to be high. At this time, the data signal terminal DATA outputs a digital signal, and the liquid crystal charging time is CT. Because the control signal provided by the second signal terminal CKn+1 is the gate drive signal output by the next-level gate drive circuit, when the output terminal CKn of the output transistor T2 is output, the control signal output by the second signal terminal CKn+1 is a low-level signal, turning off the control transistor T3, the first pull-down sustaining transistor T5, the second pull-down sustaining transistor T6, and the reset transistor T7.

[0068] Specifically, after the gate drive signal output from the output terminal CKn of the output transistor T2 is output to the lower gate drive circuit, that is, in the stage of stage transmission and pull-down, taking the first gate drive circuit and the second gate drive circuit in the cascade gate drive circuit as an example, after the input switch transistor T21 in the second gate drive circuit receives the gate drive signal output from the first gate drive circuit through the output terminal CKn of the output transistor T2, the input switch transistor T21 in the second gate drive circuit is turned on, and the charging capacitor C2 in the second gate drive circuit is charged, so that the output transistor T22 in the second gate drive circuit is turned on, thereby being able to pass The output transistor T22 of the second gate drive circuit outputs a high-level signal as the control signal required to be provided by the second signal terminal CKn+1 of the first gate drive circuit, and since the second signal terminal CKn+2 in the second gate drive circuit is the gate drive signal output by the next-level gate drive circuit corresponding to the second gate drive circuit, the control signal provided by the second signal terminal CKn+2 in the second gate drive circuit is a low-level signal, so that the control transistor T23, the first pull-down maintenance transistor T25, the second pull-down maintenance transistor T26 and the reset transistor T27 in the second gate drive circuit are all turned off.

[0069] When the output transistor T22 of the second gate drive circuit outputs a high-level signal, the control transistor T3, the pull-down transistor T4, and the reset transistor T7 in the first gate drive circuit are turned on, so that the low-level signal provided by the first power supply terminal VSSQ is transmitted to the control node Q. The low-level signal provided by the first power supply terminal VSSQ pulls down the potential of the control node Q. The reset signal provided by the reset signal terminal VSSG is transmitted to the output terminal of the output transistor T2, so that the potential of the output terminal CKn of the output transistor T2 of the first gate drive circuit is pulled down to CKn. That is, the potential of both the control node Q and the output terminal CKn of the output transistor T2 are pulled down. Furthermore, the second power supply signal provided by the second power supply terminal TGH is transmitted to the first node N1 through the turned-on pull-down transistor T4, so that the first pull-down sustain transistor T5 and the second pull-down sustain transistor T6 are turned on. Due to the presence of the first resistor R1, the pull-down transistor T4, the first pull-down sustain transistor T5, and the second pull-down sustain transistor T6 can be continuously turned on, so as to continuously pull down the potential of the control node Q and the output terminal CKn of the output transistor T2. Specifically, after the pull-down transistor T4 transmits the second power supply signal provided by the second power supply terminal TGH to the first node N1, the first pull-down sustaining transistor T5 is turned on under the control of the first node N1. Thus, the low-level signal provided by the first power supply terminal VSSQ can be transmitted to the control node Q via the turned-on first pull-down sustaining transistor T5, thereby continuously pulling down the potential of the control node Q. Furthermore, the second pull-down sustaining transistor T6 is turned on under the control of the first node N1. Thus, the low-level signal provided by the first power supply terminal VSSQ can be transmitted to the output terminal CKn of the output transistor T2 via the turned-on second pull-down sustaining transistor T6, thereby continuously pulling down the potential of the output terminal CKn of the output transistor T2, thereby achieving an autonomous pull-down function of the gate drive circuit. The turn-on voltage of the pull-down transistor T4 is lower than the turn-on voltage of the control transistor.

[0070] As can be seen, the embodiment of the present application achieves an autonomous pull-down function of the gate drive circuit through the coordinated action of the output transistor, the pull-down transistor, the first pull-down holding transistor, the second pull-down holding transistor, and the first resistor. Compared to the prior art solution that uses a reverse circuit composed of four MOS transistors to achieve the pull-down function, the embodiment of the present application uses a pull-down transistor, the first pull-down holding transistor, the second pull-down holding transistor, and the first resistor to achieve an autonomous pull-down unit. By replacing the reverse circuit composed of four MOS transistors in the prior art with the autonomous pull-down unit, the circuit structure can be effectively simplified and costs can be reduced.

[0071] Furthermore, an embodiment of the present application also provides a panel driving circuit, which includes: N cascaded gate driving circuit units, and each gate driving circuit unit includes the gate driving circuit provided by any embodiment of the present application, wherein N is an integer greater than 1.

[0072] Optionally, in the N gate driving circuit units of the embodiment of the present application, the first signal terminal of the first gate driving circuit unit is used to receive a frame start signal, and the first signal terminal of the Nth gate driving circuit unit is connected to the output terminal of the adjacent upper-level gate driving circuit unit. Figure 7 As shown, the first signal terminal STV of the first gate drive circuit unit is used to receive a frame start signal, so that the received frame start signal is transmitted to the control node Q through the input switch transistor T1 in the first gate drive circuit unit under the control of the first signal terminal STV, so that the output transistor T2 in the first gate drive circuit unit can output a gate drive signal based on the first clock signal CK1 provided by the clock signal terminal CK under the control of the control node Q, and the output terminal CKn of the output transistor T2 in the first gate drive circuit unit serves as the output terminal of the first gate drive circuit unit and the first signal terminal of the next-stage gate drive circuit unit adjacent to it, that is, the first signal terminal of the second gate drive circuit unit and the output terminal of the first gate drive circuit unit, so that the second gate drive circuit unit can receive the gate drive signal output by the output terminal of the first gate drive circuit unit, and then can output the gate drive signal required to be output by the second gate drive circuit unit through the output terminal of the second gate drive circuit unit based on the second clock signal CK2 provided by the clock signal terminal CK, and transmit it to the second signal terminal CKn+1 of the first gate drive circuit unit, so as to feed back the output of the second gate drive circuit unit to the first gate drive circuit unit, and turn off the output of the first gate drive circuit unit.

[0073] The panel driving circuit in the embodiment of the present application further includes: a pixel array, which can be arranged in the display area, and the pixel array includes N rows of pixel units connected to the gate driving circuit units in a one-to-one correspondence.

[0074] In some optional embodiments of the present application, each of the pixel units in the pixel array includes a liquid crystal driving transistor, and the control end of each row of the liquid crystal driving transistors is electrically connected to the output end of the gate driving circuit to which it is connected, so that the gate driving circuit unit can output a gate driving signal to the row of liquid crystal driving transistors to which it is connected, thereby realizing liquid crystal driving.

[0075] For example, Figure 7As shown, the output end of the first gate driving circuit unit is electrically connected to the gate of the first row of liquid crystal driving transistors of the pixel array in the display area, so that the first gate driving circuit unit can control the first row of liquid crystal driving transistors by the gate driving signal output by the output end CKn; the output end of the second gate driving circuit unit is electrically connected to the gate of the second row of liquid crystal driving transistors of the pixel array, so that the second gate driving circuit unit can control the second row of liquid crystal driving transistors by the gate driving signal output by the output end CKn+1... and so on, the output end of the Nth gate driving circuit unit is electrically connected to the gate of the Nth row of liquid crystal driving transistors of the pixel array, so that the Nth gate driving circuit unit can control the Nth row of liquid crystal driving transistors by the gate driving signal output by the output end CKn+(N-1).

[0076] In some optional embodiments of the present application, each of the pixel units may further include a liquid crystal capacitor Cs; in the same pixel unit, the first end of the liquid crystal capacitor Cs is electrically connected to the second end of the liquid crystal driving transistor T0, the second end of the liquid crystal capacitor Cs is electrically connected to the first common power supply terminal V1 in the pixel array, and the first end of the driving transistor T0 is electrically connected to the data line in the pixel array.

[0077] Optionally, each of the pixel units further includes a storage capacitor Cf; in the same pixel unit, one end of the storage capacitor Cf is electrically connected to the first end of the liquid crystal capacitor Cs and the second end of the liquid crystal driving transistor T0, and the other end of the storage capacitor Cf is electrically connected to the second common power supply terminal V2 in the pixel array.

[0078] Furthermore, embodiments of the present application also provide a display device comprising the panel driver circuit provided in embodiments of the present application. Optionally, the display device provided in embodiments of the present application may include other functional modules in addition to the panel driver circuit, such as a motherboard power supply module for controlling the power supply to the panel driver circuit. Since the principles for solving the problem of this display device are similar to those of the aforementioned panel driver circuit, the repeated parts will not be repeated here.

[0079] For example, Figure 8 As shown, the display device 700 includes: a panel driving circuit 710 and a mainboard power supply module 711, wherein the mainboard power supply module 711 is used to control the power supply to the panel driving circuit 710; wherein, the panel driving circuit 710 can be any panel driving circuit provided in the embodiments of the present application, and specifically can include the display driving unit provided in any embodiment of the present application.

[0080] In a specific implementation, the display device 700 can be a display panel, or can be a display device with a display screen such as a monitor, mobile phone, TV, laptop computer, electronic paper, digital photo frame, navigator, etc., and this application does not impose specific restrictions on this.

[0081] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0082] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, or of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiment.

[0083] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0084] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A gate drive circuit, characterized in that: include: Input switch module, output module, control module, self-pull-down module, pull-down maintenance module and resistance module; The first end of the resistor module is electrically connected to the control end of the self-pull-down module and the control end of the control module, and the second end of the resistor module is electrically connected to a first node, which is a node where the output end of the self-pull-down module, the control end of the pull-down maintaining module, and the second end of the resistor module are connected; The input switch module is configured to transmit the first signal output by the first signal terminal to the control node under the control of the first signal terminal; The control module is configured to transmit the first power signal provided by the first power terminal to the control node under the control of the second signal terminal; The output module is configured to output a gate drive signal based on a clock signal provided by a clock signal terminal under the control of the control node; The self-pull-down module is configured to transmit the second power signal provided by the second power terminal to the first node under the control of the second signal terminal; The pull-down maintaining module is used to transmit the first power signal provided by the first power end to the control node and the output end of the output module under the control of the first node.

2. The gate drive circuit according to claim 1, wherein: The self-pull-down module includes a pull-down transistor, a control terminal of the pull-down transistor is electrically connected to the second signal terminal, a first terminal of the pull-down transistor is electrically connected to the second power terminal, and a second terminal of the pull-down transistor is electrically connected to the first node; The resistance module includes a first resistor, a first end of the first resistor is electrically connected to the control end of the pull-down transistor, and a second end of the first resistor is electrically connected to the first node.

3. The gate drive circuit according to claim 2, wherein: The control module includes a control transistor, a first end of the control transistor is electrically connected to the control node, a second end of the control transistor is electrically connected to the first power supply end, and a control end of the control transistor is electrically connected to the second signal end, and a turn-on voltage of the pull-down transistor is less than the turn-on voltage of the control transistor.

4. The gate drive circuit according to claim 1, wherein: The pull-down maintenance module includes a first pull-down maintenance transistor and a second pull-down maintenance transistor; The first pull-down holding transistor is configured to transmit the first power signal provided by the first power terminal to the control node under the control of the first node; The second pull-down holding transistor is configured to transmit the first power signal provided by the first power terminal to the output terminal of the output module under the control of the first node.

5. The gate driving circuit according to claim 1, wherein: The output module includes an output transistor and a first capacitor; The control node is a node where the second end of the input switch module is connected to the first end of the control module, the first end of the first capacitor, the first output end of the pull-down holding module, and the control end of the output transistor; The second end of the first capacitor is electrically connected to the output end of the output transistor, and the gate drive signal is used to drive the liquid crystal drive circuit in the display area to perform display.

6. The gate driving circuit according to claim 1, wherein: The output module includes an output transistor, in which an integrated capacitor is integrated. The output transistor is specifically configured to output the gate drive signal based on the clock signal and a voltage signal provided by the integrated capacitor under the control of the control node.

7. The gate drive circuit according to any one of claims 1 to 3, characterized in that: The gate drive circuit further includes: a reset module; The reset module is configured to transmit the reset signal provided by the reset signal terminal to the output terminal of the output module under the control of the second signal terminal.

8. A panel driving circuit, characterized in that: The invention comprises: N cascaded gate driving circuit units, and each of the gate driving circuit units comprises the gate driving circuit according to any one of claims 1 to 7, wherein N is an integer greater than 1.

9. The panel driving circuit according to claim 8, wherein: Also includes: A pixel array comprising N rows of pixel units connected in a one-to-one correspondence with the gate driving circuit units; Among the N gate driving circuit units, the first signal end of the first gate driving circuit unit is used to receive a frame start signal, and the first signal end of the Nth gate driving circuit unit is connected to the output end of the adjacent upper-level gate driving circuit unit.

10. A display device, characterized in that: include: A panel driving circuit as claimed in any one of claims 8 to 9.

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