Drive module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device. The driving module includes a data driving module, a voltage regulating module, a polarity partition detection module, and an input control module. The first signal line and the second signal line are both connected to the data driving unit. The polarity partition detection module is connected to the first signal line and the second signal line. The voltage regulating module can lower, maintain, or increase the voltage passing through it. The first voltage regulating module is connected to the first signal line, the second voltage regulating module is connected to the second signal line, and the input control module is connected to the polarity partition detection module. In a polarity symmetric mode, the input control module controls at least one voltage regulating module to lower the data voltage, and the voltage regulating module that outputs the lowered data voltage alternates row by row. By lowering the brightness of the green pixel column on one side of the pixel column at the junction through the voltage regulating module, color deviation can be improved or eliminated, thereby improving the display quality of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] When an LCD displays a picture, the pixel electrodes on one side of the array substrate and the common electrodes on the opposite substrate form a liquid crystal capacitor (LCC), which drives the deflection of the liquid crystal molecules, controlling the brightness of each sub-pixel to achieve the image display. If a single electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may become polarized, resulting in a decrease in display quality and even damage to the liquid crystal material. By inverting the polarity and alternating the direction of the electric field, polarization of the liquid crystal molecules can be effectively avoided.

[0003] Data lines provide data voltage to pixel electrodes. Polarity reversal can cause the data voltage to be greater or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode can offset the data voltage, causing crosstalk and affecting the LCD's display quality. LCDs can be divided into multiple display areas. Providing symmetrical polarity in adjacent display areas can offset coupling and thus improve or eliminate lateral crosstalk.

[0004] However, the polarity of adjacent display areas is symmetrical, and the pixel columns at the junction are always all positive or all negative, which will not change. The area where the column is located will produce color deviation, affecting the display quality of the liquid crystal display. Summary of the Invention

[0005] The purpose of this application is to provide a driving module and a display device to improve or eliminate color deviation and enhance the display quality of a liquid crystal display.

[0006] In order to achieve the above objectives, the present application provides a driving module, including a data driving module, and the driving module further includes:

[0007] a polarity partition detection module connected to the first signal line and the second signal line, wherein the first signal line and the second signal line are both connected to the data driving module;

[0008] a voltage regulating module capable of lowering, maintaining, or raising the voltage passing through it, the voltage regulating module comprising a first voltage regulating module and a second voltage regulating module, the first voltage regulating module being connected to the first signal line and a data line of a pixel column with the same polarity in a polarity symmetric mode of the display panel, and the second voltage regulating module being connected to the second signal line and another data line of the pixel column with the same polarity;

[0009] An input control module is connected to the polarity partition detection module. In a normal polarity mode, the data voltage of the first signal line and the data voltage of the second signal line have opposite polarities, and the input control module controls the first voltage regulation module and the second voltage regulation module to output the data voltage. In a polarity symmetric mode, the data voltage of the first signal line and the data voltage of the second signal line have the same polarity, and the input control module controls at least one of the voltage regulation modules to lower the data voltage. The voltage regulation module that outputs the lowered data voltage alternates row by row or outputs the lowered data voltage alternately row by row.

[0010] Optionally, in the polarity symmetric mode, the input control module controls one of the voltage regulating modules to lower the data voltage, and the voltage regulating module that outputs the lowered data voltage is alternated row by row;

[0011] The voltage regulating module includes a voltage regulating unit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, and an operational amplifier, wherein the first end of the first transistor and the first end of the second transistor are input ends of the voltage regulating unit, the input end of the voltage regulating unit of the first voltage regulating module is connected to the first signal line, and the input end of the voltage regulating unit of the second voltage regulating module is connected to the second signal line;

[0012] The second end of the first transistor is connected to the non-inverting input terminal of the operational amplifier via a first resistor, the second end of the second transistor is connected to the inverting input terminal of the operational amplifier, the second resistor is connected to the non-inverting input terminal and the ground terminal, the first end of the third transistor is connected to the non-inverting input terminal via the third resistor, the first end of the fourth transistor is connected to the inverting input terminal, and the second end of the third transistor, the second end of the fourth transistor, and the output terminal of the operational amplifier are connected to serve as the output terminal of the voltage regulating unit;

[0013] The control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor are control ends of the voltage regulating unit, and the control ends of the voltage regulating unit are connected to the input control module;

[0014] The first transistor and the fourth transistor of the first voltage regulating module and the second transistor and the third transistor of the second voltage regulating module are N-type transistors, and the second transistor and the third transistor of the first voltage regulating module and the first transistor and the fourth transistor of the second voltage regulating module are P-type transistors.

[0015] Optionally, the input control module includes a fifth transistor, a sixth transistor, a seventh transistor and a signal generator, the control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are all connected to the polarity partition detection module, the first end of the fifth transistor is connected to a first power supply, the first power supply outputs a high-level signal, the second end of the fifth transistor is connected to the control end of the voltage regulation unit of the first voltage regulation module, the first end of the sixth transistor is connected to a second power supply, the second power supply outputs a low-level signal, the second end of the sixth transistor is connected to the control end of the voltage regulation unit of the second voltage regulation module, the signal generator is connected to a frame start signal line, the signal generator can output a high-level signal and a low-level signal alternating row by row according to a scanning frequency controlled by the frame start signal line signal, the first end of the seventh transistor is connected to the signal generator, and the second end of the seventh transistor is connected to the control end of the voltage regulation unit;

[0016] The fifth transistor and the sixth transistor are N-type transistors, and the seventh transistor is a P-type transistor, or the fifth transistor and the sixth transistor are P-type transistors, and the seventh transistor is an N-type transistor.

[0017] Optionally, in the polarity symmetry mode, the input control module controls one of the voltage regulation modules to lower the data voltage and controls another of the voltage regulation modules to increase the data voltage, and the voltage regulation module that outputs the data voltage after lowering it and the voltage regulation module that outputs the data voltage after increasing it are alternated row by row.

[0018] Optionally, the voltage regulating module includes a voltage regulating unit and a selection unit, an input end of the selection unit of the first voltage regulating module is connected to the first signal line, an input end of the selection unit of the second voltage regulating module is connected to the second signal line, and an output end of the selection unit is connected to the voltage regulating unit;

[0019] The input control module can control the selection unit to connect the first signal line and the second signal line to the corresponding data line directly or indirectly through the voltage adjustment unit. The voltage adjustment unit can lower or increase the voltage passing through it.

[0020] Optionally, the voltage regulating unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and an operational amplifier, and the first end of the first transistor and the first end of the second transistor are input ends of the voltage regulating unit;

[0021] The second end of the first transistor is connected to the non-inverting input terminal of the operational amplifier through a first resistor, the second end of the second transistor is connected to the inverting input terminal of the operational amplifier, the second resistor is connected to the non-inverting input terminal and the ground terminal, the first end of the third transistor is connected to the non-inverting input terminal through the third resistor, the second end of the third transistor is connected to the output terminal of the operational amplifier, the first end of the fourth transistor is connected to the inverting input terminal, the second end of the fourth transistor is connected to the output terminal of the operational amplifier through the fourth resistor, the fifth resistor is connected to the ground terminal and the second end of the fourth transistor, and the output terminal of the operational amplifier is the output terminal of the voltage regulating unit;

[0022] The control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor are control ends of the voltage regulating unit, and the control ends of the voltage regulating unit are connected to the input control module;

[0023] The first transistor and the fourth transistor of the first voltage regulating module and the second transistor and the third transistor of the second voltage regulating module are P-type transistors, and the second transistor and the third transistor of the first voltage regulating module and the first transistor and the fourth transistor of the second voltage regulating module are N-type transistors.

[0024] Optionally, the selection unit includes an eighth transistor and a ninth transistor, the first end of the eighth transistor and the first end of the ninth transistor are input ends of the selection unit, the second end of the eighth transistor is directly connected to the data line, the second end of the ninth transistor is connected to the data line through the voltage adjustment unit, the control end of the eighth transistor and the control end of the ninth transistor are control ends of the selection unit, and one of the eighth transistor and the ninth transistor is a P-type transistor and the other is an N-type transistor.

[0025] Optionally, the input control module includes a fifth transistor, a sixth transistor, a seventh transistor and a signal generator, and the control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are all connected to the polarity partition detection module;

[0026] The eighth transistor is a P-type transistor and the ninth transistor is an N-type transistor, a first end of the fifth transistor is connected to a first power supply, the first power supply outputs a high-level signal, a second end of the fifth transistor is connected to the control end of the selection unit, a first end of the sixth transistor is connected to a second power supply, the second power supply outputs a low-level signal, and a second end of the sixth transistor is connected to the control end of the selection unit;

[0027] The signal generator is connected to the frame start signal line, and the signal generator can output a high level signal and a low level signal alternately line by line according to a scanning frequency controlled by a signal of the frame start signal line. The first end of the seventh transistor is connected to the signal generator, and the second end of the seventh transistor is connected to the control end of the voltage adjustment unit.

[0028] The fifth transistor and the seventh transistor are N-type transistors, and the sixth transistor is a P-type transistor, or the fifth transistor and the seventh transistor are P-type transistors, and the sixth transistor is an N-type transistor.

[0029] Optionally, the polarity partition detection module includes an XOR gate circuit or an XNOR gate circuit.

[0030] The present application also provides a display device, comprising:

[0031] The driving module;

[0032] The display panel is connected to the driving module.

[0033] The driving module and display device disclosed in this application have the following beneficial effects:

[0034] In the present application, the driving module includes a data driving module, a voltage regulating module, a polarity partition detection module, and an input control module. The data driving module is used to provide a data voltage. The first and second signal lines are both connected to the data driving unit and are used to output the data voltage provided by the data driving module to the display panel. The polarity partition detection module is connected to the first and second signal lines. The voltage regulating module is capable of lowering, maintaining, or raising the voltage passing through it. The first voltage regulating module is connected to the first signal line, the second voltage regulating module is connected to the second signal line, and the input control module is connected to the polarity partition detection module. In a polarity symmetric mode, the input control module controls at least one voltage regulating module to lower the data voltage. The voltage regulating module that outputs the lowered data voltage alternates row by row or outputs the lowered data voltage alternately row by row. By lowering the brightness of the green pixel column on one side of the pixel column at the junction by the voltage regulating module, color shift can be improved or eliminated, thereby enhancing the display quality of the display panel.

[0035] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0038] Figure 1 It is a structural diagram of the driving module in Example 1 of the present application.

[0039] Figure 2 It is a structural diagram of the display panel in Example 1 of the present application.

[0040] Figure 3 This is a schematic diagram of the data voltage reduction of the green sub-pixel in the first embodiment of the present application.

[0041] Figure 4 This is a schematic diagram of the data voltage reduction of the blue and green sub-pixels in the first embodiment of the present application.

[0042] Figure 5 It is a structural diagram of the voltage regulation module in Example 1 of the present application.

[0043] Figure 6 It is a structural diagram of the XNOR gate circuit in Example 1 of the present application.

[0044] Figure 7 It is a structural diagram of the driving module in Example 2 of the present application.

[0045] Figure 8 This is a schematic diagram of the data voltage reduction of all sub-pixels in the blue and green columns in the second embodiment of the present application.

[0046] Figure 9 It is a structural diagram of the driving module in Example 3 of the present application.

[0047] Figure 10 This is a schematic diagram of the data voltage increase of the red sub-pixel in the third embodiment of the present application.

[0048] Figure 11 This is a structural diagram of the voltage regulation unit in Example 3 of the present application.

[0049] Figure 12 It is a structural diagram of the display device in Example 4 of the present application.

[0050] Description of reference numerals:

[0051] 100, display panel; 101, first display area; 102, second display area; 110, sub-pixel;

[0052] 200, driving module; 201, first transistor; 202, second transistor; 203, third transistor; 204, fourth transistor; 205, eighth transistor; 206, ninth transistor; 211, first resistor; 212, second resistor; 213, third resistor; 214, fourth resistor; 215, fifth resistor; 216, operational amplifier;

[0053] 220, first voltage regulation module; 230, second voltage regulation module; 221, voltage regulation unit; 222, selection unit; 240, polarity partition detection module; 241, tenth transistor; 242, eleventh transistor; 243, twelfth transistor; 244, thirteenth transistor; 250, input control module; 251, fifth transistor; 252, sixth transistor; 253, seventh transistor; 254, signal generator; 261, first signal line; 262, second signal line; 263, third signal line; 264, fourth signal line; 271, first power supply; 272, second power supply; 280, third voltage regulation module; 290, fourth voltage regulation module. DETAILED DESCRIPTION

[0054] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0055] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0056] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0057] Example 1

[0058] See also Figure 2As shown, the display panel 100 includes a plurality of sub-pixels 110 arranged in an array, with each column of sub-pixels 110 being arranged between two data lines. The sub-pixels 110 in odd-numbered rows are connected to the data line on their left, and the sub-pixels 110 in even-numbered rows are connected to the data line on their right. The reverse is also possible, that is, the sub-pixels 110 in odd-numbered rows are connected to the data line on their right, and the sub-pixels 110 in even-numbered rows are connected to the data line on their left.

[0059] The display panel 100 can be divided into multiple display areas, including an adjacent first display area 101 and a second display area 102. The number of data lines in the first display area 101 and the second display area 102 is equal. The first display area 101 includes data line 1, data line 2, ..., data line n-1, data line n arranged in sequence from left to right, and the second display area 102 includes data line n+1, data line n+2, etc. arranged in sequence from left to right, where n is an integer greater than 1.

[0060] In the normal polarity mode, the data voltages on the data lines of the entire display panel 100 alternate between positive and negative polarity, i.e., "-+-+". In the polarity symmetry mode, the polarity of the data voltages on adjacent display areas is symmetrical: the data voltage polarity on the data lines of the first display area 101 on the left is "+-+-", while the data voltage polarity on the data lines of the second display area 102 on the right is "-+-+". Switching the display panel 100 to the polarity symmetry mode, i.e., symmetric polarity on adjacent display areas, can offset coupling, thereby improving or eliminating lateral crosstalk.

[0061] However, adjacent display areas have symmetrical polarity, and the pixel columns at the intersection are always completely positive or completely negative, which does not change. The overall color of the column is lighter, and the area where the column is located will experience color shift, affecting the display quality of the display panel 100. For example, if the pixel column at the intersection is composed of red (R) sub-pixels 110, the area where the column is located will be cyan or light blue.

[0062] In order to improve or eliminate color deviation, the present application provides a driving module 200 for driving the display panel 100. Figure 1 As shown, the driving module 200 includes a data driving module, a voltage regulating module, a polarity partition detection module 240, and an input control module 250. The data driving module is used to provide a data voltage V. The first signal line 261 and the second signal line 262 are both connected to the data driving module to output the data voltage provided by the data driving module to the display panel 100. For example, the first signal line 261 provides a data voltage for data line n, and the second signal line 262 provides a data voltage for data line n+1.

[0063] It should be understood that the polarity of the data voltage can be positive or negative. When the data voltage is greater than the common electrode voltage, the data voltage is positive, and when the data voltage is less than the common electrode voltage, the data voltage is negative. By inverting the polarity of the data voltage, and thus alternating the direction of the electric field that drives the liquid crystal, polarization of the liquid crystal molecules can be effectively avoided.

[0064] The polarity partition detection module 240 is connected to the first signal line 261 and the second signal line 262. In the polarity symmetric mode, when the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have the same polarity, the polarity partition detection module 240 outputs a high-level signal. In the normal polarity mode, when the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have different polarities, the polarity partition detection module 240 outputs a low-level signal. Conversely, the polarity partition detection module 240 also outputs a low-level signal when the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have the same polarity, and outputs a high-level signal when the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have different polarities.

[0065] The voltage regulation module can lower, maintain, or increase the voltage passing through it. The increased data voltage is recorded as V+, and the lowered data voltage is recorded as V-. The voltage regulation module includes a first voltage regulation module 220 and a second voltage regulation module 230. The first voltage regulation module 220 is connected to the first signal line 261 and a data line of a pixel column with the same polarity in the display panel 100 in a polarity symmetric mode. The second voltage regulation module 230 is connected to the second signal line 262 and another data line of the pixel column with the same polarity. For example, the first voltage regulation module 220 is connected to data line n, and the second voltage regulation module 230 is connected to data line n+1.

[0066] The input control module 250 is connected to the polarity partition detection module 240. In the normal polarity mode, the data voltage of the first signal line 261 and the data voltage of the second signal line 262 have opposite polarities, and the input control module 250 controls the first voltage regulation module 220 and the second voltage regulation module 230 to output the data voltage V; in the polarity symmetric mode, the data voltage of the first signal line 261 and the data voltage of the second signal line 262 have the same polarity, and the input control module 250 controls at least one voltage regulation module to lower the data voltage, and the voltage regulation module that outputs the lowered data voltage alternates row by row or the voltage regulation module that outputs the lowered data voltage outputs the lowered data voltage alternately row by row.

[0067] The data driving module can be packaged in one chip, the voltage regulating module, the polarity partition detection module 240 and the input control module 250 can be packaged in one chip, or the entire driving module 200 can be packaged in one chip. The specific packaging method can be determined according to the situation.

[0068] When the drive module 200 is working:

[0069] In the normal polarity mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are opposite, the polarity partition detection module 240 outputs a low-level signal to the input control module 250, and the input control module 250 controls the first voltage regulation module 220 and the second voltage regulation module 230 to output the data voltage V.

[0070] In the polarity symmetry mode, the data voltage polarity of the first signal line 261 and the second signal line 262 is the same, the input control module 250 controls a voltage regulating module to lower the data voltage, and the voltage regulating module that outputs the lowered data voltage outputs the lowered data voltage in alternate rows. For example, when scanning the first row, the first voltage regulating module 220 outputs the data voltage V, and the second voltage regulating module 230 outputs the data voltage V-; when scanning the second row, the first voltage regulating module 220 outputs the data voltage V, and the second voltage regulating module 230 outputs the data voltage V; when scanning the third row, the first voltage regulating module 220 outputs the data voltage V, and the second voltage regulating module 230 outputs the data voltage V-; when scanning the fourth row, the first voltage regulating module 220 outputs the data voltage V, and the second voltage regulating module 230 outputs the data voltage V. And so on, the brightness of half of the sub-pixels 110 in the green (G) pixel column to the right of the pixel column at the junction of the display panel 100 is reduced, as shown in FIG. Figure 3 shown.

[0071] In the polarity symmetry mode, the data voltage polarity of the first signal line 261 and the second signal line 262 is the same, the input control module 250 controls a voltage regulation module to lower the data voltage, and the voltage regulation module that outputs the lowered data voltage alternates row by row. For example, when scanning the first row, the first voltage regulation module 220 outputs the data voltage V, and the second voltage regulation module 230 outputs the data voltage V-; when scanning the second row, the first voltage regulation module 220 outputs the data voltage V-, and the second voltage regulation module 230 outputs the data voltage V; when scanning the third row, the first voltage regulation module 220 outputs the data voltage V, and the second voltage regulation module 230 outputs the data voltage V-; when scanning the fourth row, the first voltage regulation module 220 outputs the data voltage V-, and the second voltage regulation module 230 outputs the data voltage V. And so on, the brightness of half of the sub-pixels 110 in the blue (B) pixel column on the left side of the pixel column at the junction of the display panel 100 is reduced, and the brightness of half of the sub-pixels 110 in the green (G) pixel column on the right side is reduced, as shown in FIG. Figure 4shown.

[0072] The human eye sensory contribution values ​​of the red, green and blue sub-pixels 110 are different. The human eye sensory contribution value of the red sub-pixel 110 is approximately 30%, the human eye sensory contribution value of the green sub-pixel 110 is approximately 60%, and the human eye sensory contribution value of the blue sub-pixel 110 is approximately 10%. The human eye sensory contribution value of the green sub-pixel 110 is significantly higher than the human eye sensory contribution value of the blue sub-pixel 110. Therefore, reducing the brightness of the green sub-pixel 110 can significantly improve color deviation.

[0073] In this embodiment, the driving module 200 includes a data driving module, a voltage regulating module, a polarity partition detection module 240 and an input control module 250. The data driving module is used to provide a data voltage. The first signal line 261 and the second signal line 262 are both connected to the data driving unit and are used to output the data voltage provided by the data driving module to the display panel 100. The polarity partition detection module 240 is connected to the first signal line 261 and the second signal line 262. The voltage regulating module can lower, maintain or increase the voltage passing through it. The first voltage regulating module 220 is connected to the first signal line 261, the second voltage regulating module 230 is connected to the second signal line 262, and the input control module 250 is connected to the polarity partition detection module 240. In the polarity symmetric mode, the input control module 250 controls at least one voltage regulating module to lower the data voltage. The voltage regulating module that outputs the lowered data voltage alternates row by row, or the voltage regulating module that outputs the lowered data voltage outputs the lowered data voltage every other row. By lowering the brightness of the green pixel column on one side of the pixel column at the junction by the voltage regulating module, the color shift can be improved or eliminated, thereby enhancing the display quality of the display panel 100 .

[0074] In some embodiments, in the polarity symmetric mode, the input control module 250 controls one voltage regulating module to lower the data voltage, and the voltage regulating module that outputs the lowered data voltage alternates row by row.

[0075] See also Figure 5 As shown, the voltage regulation module includes a voltage regulation unit 221. The voltage regulation unit 221 includes a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a first resistor 211, a second resistor 212, a third resistor 213, and an operational amplifier 216. The first end of the first transistor 201 and the first end of the second transistor 202 serve as inputs of the voltage regulation unit 221. The input of the voltage regulation unit 221 of the first voltage regulation module 220 is connected to the first signal line 261, and the input of the voltage regulation unit 221 of the second voltage regulation module 230 is connected to the second signal line 262.

[0076] The second end of the first transistor 201 is connected to the non-inverting input of the operational amplifier 216 via the first resistor 211, and the second end of the second transistor 202 is connected to the inverting input of the operational amplifier 216. The second resistor 212 is connected between the non-inverting input of the operational amplifier 216 and the ground. The first end of the third transistor 203 is connected to the non-inverting input of the operational amplifier 216 via the third resistor 213, and the first end of the fourth transistor 204 is connected to the inverting input of the operational amplifier 216. The second end of the third transistor 203, the second end of the fourth transistor 204, and the output of the operational amplifier 216 are connected to serve as the output of the voltage regulating unit 221. The output of the voltage regulating unit 221 of the first voltage regulating module 220 is connected to the data line n, and the output of the voltage regulating unit 221 of the second voltage regulating module 230 is connected to the data line n+1.

[0077] The control ends of the first transistor 201 , the second transistor 202 , the third transistor 203 and the fourth transistor 204 are control ends of the voltage regulating unit 221 , and the control ends of the voltage regulating unit 221 are connected to the input control module 250 .

[0078] Among them, the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 are N-type transistors, and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the first voltage regulating module 220 and the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the second voltage regulating module 230 are P-type transistors.

[0079] When the driving module 200 is working in the polarity symmetry mode:

[0080] When scanning the first row, the input control module 250 outputs a control signal that is a high-level signal. The first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 are turned on. The voltage regulating unit 221 functions as a voltage follower circuit and directly outputs the input data voltage V. The second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 are turned on. The voltage regulating unit 221 functions as a negative feedback circuit and adjusts the input data voltage V down to the data voltage V- for output.

[0081] When scanning the second row, the input control module 250 outputs a control signal that is a low-level signal, the second transistor 202 and the third transistor 203 of the voltage regulation unit 221 of the first voltage regulation module 220 are turned on, and the voltage regulation unit 221 acts as a negative feedback circuit. The voltage regulation unit 221 adjusts the input data voltage V down to the data voltage V-output, and the first transistor 201 and the fourth transistor 204 of the voltage regulation unit 221 of the second voltage regulation module 230 are turned on. The voltage regulation unit 221 acts as a voltage follower circuit, and the voltage regulation unit 221 directly outputs the input data voltage V.

[0082] The input control module 250 controls a voltage regulating module to lower the data voltage through the voltage regulating unit 221 , and the voltage regulating modules that output the lowered data voltage are alternated row by row. The voltage regulating unit 221 has a simple structure, which can reduce the manufacturing cost of the driving module 200 .

[0083] It should be noted that if the input control module 250 outputs a control signal as a low-level signal when scanning the first row, and the input control module 250 outputs a control signal as a high-level signal when scanning the second row, the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 may also be P-type transistors, and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the first voltage regulating module 220 and the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the second voltage regulating module 230 may also be N-type transistors.

[0084] In some embodiments, the input control module 250 includes a fifth transistor 251, a sixth transistor 252, a seventh transistor 253, and a signal generator 254. The control terminals of the fifth transistor 251, the sixth transistor 252, and the seventh transistor 253 are all connected to the polarity partition detection module 240. A first terminal of the fifth transistor 251 is connected to a first power supply 271, which outputs a high-level signal. A second terminal of the fifth transistor 251 is connected to a control terminal of the voltage regulating unit 221 of the first voltage regulating module 220. A first terminal of the sixth transistor 252 is connected to a second power supply 272, which outputs a low-level signal. A second terminal of the sixth transistor 252 is connected to a control terminal of the voltage regulating unit 221 of the second voltage regulating module 230.

[0085] Signal generator 254 is connected to the frame start signal line (STV). Signal generator 254 can output alternating high and low signals on a row-by-row basis, based on the scanning frequency controlled by the frame start signal line. In other words, the switching frequency of the high and low signals of signal generator 254 matches the refresh rate of the display panel 100, and the duration of both the high and low signals is the time required to scan a single row. A first terminal of the seventh transistor 253 is connected to signal generator 254, and a second terminal of the seventh transistor 253 is connected to the control terminals of the two voltage adjustment units 221. The fifth and sixth transistors 251 and 252 are P-type transistors, while the seventh transistor 253 is an N-type transistor.

[0086] When the drive module 200 is working:

[0087] In the normal polarity mode, the data voltage of the first signal line 261 and the data voltage of the second signal line 262 have different polarities, the polarity partition detection module 240 outputs a low-level signal, the fifth transistor 251 and the sixth transistor 252 are turned on, and the seventh transistor 253 is turned off. The high-level signal output by the first power supply 271 controls the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 to turn on, and the voltage regulating unit 221 of the first voltage regulating module 220 directly outputs the input data voltage V. The second power supply 272 outputs a low-level signal to control the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the second voltage regulating module 230 to turn on, and the voltage regulating unit 221 of the second voltage regulating module 230 directly outputs the input data voltage V.

[0088] In the polarity symmetric mode, the data voltage of the first signal line 261 and the data voltage of the second signal line 262 have the same polarity, the polarity partition detection module 240 outputs a high-level signal, the fifth transistor 251 and the sixth transistor 252 are turned off, and the seventh transistor 253 is turned on. The voltage adjustment units 221 of the two voltage adjustment modules are controlled by the high-level signal and the low-level signal output by the signal generator 254, which alternate row by row.

[0089] Input control module 250 includes a fifth transistor 251, a sixth transistor 252, and a seventh transistor 253. These three transistors control the two voltage regulator modules, resulting in a simple structure. Input control module 250 also includes a signal generator 254. The signal from signal generator 254 alternates according to the scanning frequency controlled by the frame start signal line signal, ensuring that the alternating control signal is synchronized with the scanning frequency.

[0090] It should be noted that the fifth transistor 251 and the sixth transistor 252 may also be N-type transistors, and the seventh transistor 253 may also be a P-type transistor. It is only necessary to adjust the control signal output by the polarity partition detection module 240 .

[0091] In some embodiments, the polarity partition detection module 240 includes an XOR gate circuit or an XOR gate circuit. When the polarity partition detection module 240 is an XOR gate circuit, if the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have the same polarity, the XOR gate circuit outputs a low-level signal; if the data voltage on the first signal line 261 and the data voltage on the second signal line 262 have different polarities, the XOR gate circuit outputs a high-level signal.

[0092] When polarity partition detection module 240 is an X-OR gate circuit, if the data voltage on first signal line 261 and the data voltage on second signal line 262 have the same polarity, the X-OR gate circuit outputs a high-level signal. If the data voltage on first signal line 261 and the data voltage on second signal line 262 have different polarities, the X-OR gate circuit outputs a low-level signal. This application has been described using the X-OR gate circuit as an example. The control principle is the same when polarity partition detection module 240 is an X-OR gate circuit, so this will not be further described.

[0093] The polarity partition detection module 240 includes an XOR gate circuit or an XOR gate circuit. The XOR gate circuit or the XOR gate circuit compares the polarity of the data voltage of the first signal line 261 with the polarity of the data voltage of the second signal line 262 to determine whether the driving module 200 is in the normal polarity mode or the polarity symmetric mode. The structure of the polarity partition detection module 240 is simple, which can reduce the manufacturing cost of the driving module 200.

[0094] In some embodiments, see Figure 6 As shown, the XNOR gate circuit includes a tenth transistor 241, an eleventh transistor 242, a twelfth transistor 243 and a thirteenth transistor 244, the tenth transistor 241 and the twelfth transistor 243 are N-type transistors, and the eleventh transistor 242 and the thirteenth transistor 244 are P-type transistors.

[0095] The control terminals of the eleventh transistor 242 and the thirteenth transistor 244 are both connected to the first signal line 261, and the control terminals of the tenth transistor 241 and the twelfth transistor 243 are both connected to the second signal line 262. A first terminal of the twelfth transistor 243 is connected to the first power supply 271, which outputs a high-level signal, and a second terminal of the twelfth transistor 243 is connected to the connection node A. A first terminal of the thirteenth transistor 244 is connected to the first power supply 271, and a second terminal of the thirteenth transistor 244 is connected to the connection node A. A first terminal of the eleventh transistor 242 is connected to the connection node A, a second terminal of the eleventh transistor 242 is connected to the first terminal of the tenth transistor 241, and a second terminal of the tenth transistor 241 is connected to ground. The first signal line 261 and the second signal line 262 serve as the two input terminals of an exclusive-OR gate circuit, and the connection node A serves as the output terminal of the exclusive-OR gate circuit.

[0096] When the data voltages of the first signal line 261 and the second signal line 262 are both negative, the eleventh transistor 242 and the thirteenth transistor 244 are turned on, the tenth transistor 241 and the twelfth transistor 243 are turned off, and the XNOR gate circuit outputs a high level signal;

[0097] When the data voltage of the first signal line 261 is negative and the data voltage of the second signal line 262 is positive, the tenth transistor 241, the eleventh transistor 242, the twelfth transistor 243 and the thirteenth transistor 244 are all turned on, and the XOR gate circuit outputs a low level signal;

[0098] When the data voltage of the first signal line 261 is positive and the data voltage of the second signal line 262 is negative, the tenth transistor 241, the eleventh transistor 242, the twelfth transistor 243 and the thirteenth transistor 244 are all turned off, and the XOR gate circuit outputs a low level signal;

[0099] When the data voltages of the first signal line 261 and the second signal line 262 are both positive, the eleventh transistor 242 and the thirteenth transistor 244 are turned off, the tenth transistor 241 and the twelfth transistor 243 are turned on, and the XNOR gate circuit outputs a high level signal.

[0100] Example 2

[0101] The difference between the second embodiment and the first embodiment is that, based on the driving module 200 of the first embodiment, the driving module 200 of the second embodiment further includes a third voltage regulating module 280 and a fourth voltage regulating module 290 .

[0102] See also Figure 7 and Figure 8As shown, the third voltage regulating module 280 connects the data line n-1 and the third signal line 263, and the fourth voltage regulating module 290 connects the data line n+2 and the fourth signal line 264. The ends of the third signal line 263 and the fourth signal line 264, which are away from the voltage regulating modules, are both connected to the data driving module. The structure and control method of the third voltage regulating module 280 are the same as those of the second voltage regulating module 230, and the structure and control method of the fourth voltage regulating module 290 are the same as those of the first voltage regulating module 220.

[0103] When the drive module 200 is working:

[0104] In the normal polarity mode, the third voltage regulating module 280 and the fourth voltage regulating module 290 both directly output the received data voltage V;

[0105] In the polarity symmetric mode, when scanning the first row, the third voltage regulation module 280 adjusts the input data voltage V down to the data voltage V-output, and the fourth voltage regulation module 290 directly outputs the input data voltage V; when scanning the second row, the third voltage regulation module 280 directly outputs the input data voltage V, and the fourth voltage regulation module 290 adjusts the input data voltage V down to the data voltage V-output.

[0106] The brightness of all sub-pixels 110 in each pixel column on both sides of the boundary pixel column (red pixel column) is reduced, which can further improve or eliminate color shift and enhance the display quality of the display panel 100 .

[0107] It should be noted that the brightness of the sub-pixels 110 on the right side of the data line n-1 and the left side of the data line n+2 can be selectively reduced through the third voltage adjustment module 280 and the fourth voltage adjustment module 290, but is not limited to this. The brightness of all sub-pixels 110 controlled by the data line n-1 and the data line n+2 can also be reduced in the polarity symmetry mode, depending on the specific situation.

[0108] Example 3

[0109] The main difference between the third embodiment and the first embodiment is that the structure of the voltage regulating module is different.

[0110] See also Figure 9 As shown, in the polarity symmetric mode, the input control module 250 controls one voltage regulating module to lower the data voltage and controls another voltage regulating module to increase the data voltage, and the voltage regulating module that outputs the lowered data voltage and the voltage regulating module that outputs the increased data voltage are alternated row by row.

[0111] When the drive module 200 is working:

[0112] In the normal polarity mode, the data voltage polarities of the first signal line 261 and the second signal line 262 are opposite, the polarity partition detection module 240 outputs a low-level signal to the input control module 250, and the input control module 250 controls the first voltage regulation module 220 and the second voltage regulation module 230 to output the data voltage V.

[0113] In polarity symmetry mode, the data voltage polarity of the first signal line 261 and the second signal line 262 is the same. The input control module 250 controls one voltage regulator module to lower the data voltage and controls the other voltage regulator module to increase the data voltage. The voltage regulator module that outputs the lowered data voltage and the voltage regulator module that outputs the higher data voltage alternate on a row-by-row basis. For example, when scanning the first row, the first voltage regulator module 220 outputs a data voltage V+ and the second voltage regulator module 230 outputs a data voltage V-. When scanning the second row, the first voltage regulator module 220 outputs a data voltage V- and the second voltage regulator module 230 outputs a data voltage V+. When scanning the third row, the first voltage regulator module 220 outputs a data voltage V+ and the second voltage regulator module 230 outputs a data voltage V-. When scanning the fourth row, the first voltage regulator module 220 outputs a data voltage V- and the second voltage regulator module 230 outputs a data voltage V+. By analogy, the brightness of half of the sub-pixels 110 in the blue (B) pixel column on the left side of the pixel column at the junction of the display panel 100 is reduced, and the brightness of half of the sub-pixels 110 in the green (G) pixel column on the right side is reduced, while the brightness of all the red sub-pixels 110 in the pixel column at the junction is increased. Figure 10 shown.

[0114] In the polarity symmetric mode, the pixel columns at the junction are always all positive or all negative, and this situation does not change. The overall color of the red pixel column is lighter. Increasing the data voltage of the red pixel column can further improve or eliminate the color deviation, thereby improving the display quality of the display panel 100.

[0115] In some embodiments, the voltage regulation module includes a voltage regulation unit 221 and a selection unit 222, the input end of the selection unit 222 of the first voltage regulation module 220 is connected to the first signal line 261, the input end of the selection unit 222 of the second voltage regulation module 230 is connected to the second signal line 262, and the output end of the selection unit 222 is connected to the voltage regulation unit 221.

[0116] The input control module 250 can control the selection unit 222 to connect the first signal line 261 and the second signal line 262 to the corresponding data lines directly or indirectly through the voltage adjustment unit 221 . The voltage adjustment unit 221 can adjust the voltage passing through it downward or upward.

[0117] By selecting whether to adjust the data voltage through the selection unit 222, the structure of the voltage adjustment module is simpler.

[0118] It should be noted that the brightness of half of the sub-pixels 110 in the blue (B) pixel column to the left of the pixel column at the junction of the display panel 100 can be reduced, but the present invention is not limited to this. Since the voltage adjustment unit 221 can increase the voltage passing through it, the driving module 200 can also selectively reduce or increase the brightness of the blue sub-pixels 110 according to the color shift of the display panel 100, thereby increasing the color shift adjustment range.

[0119] In some embodiments, see Figure 11 As shown, the voltage regulating unit 221 includes a first transistor 201, a second transistor 202, a third transistor 203, a fourth transistor 204, a first resistor 211, a second resistor 212, a third resistor 213, a fourth resistor 214, a fifth resistor 215, and an operational amplifier 216. The first end of the first transistor 201 and the first end of the second transistor 202 serve as input ends of the voltage regulating unit 221.

[0120] The second end of the first transistor 201 is connected to the non-inverting input terminal of the operational amplifier 216 via the first resistor 211, and the second end of the second transistor 202 is connected to the inverting input terminal of the operational amplifier 216. The second resistor 212 is connected between the non-inverting input terminal of the operational amplifier 216 and the ground terminal. The first end of the third transistor 203 is connected to the non-inverting input terminal of the operational amplifier 216 via the third resistor 213, and the first end of the fourth transistor 204 is connected to the inverting input terminal of the operational amplifier 216. The second end of the fourth transistor 204 is connected to the output terminal of the operational amplifier 216 via the fourth resistor 214. The fifth resistor 215 is connected to the ground terminal and the second end of the fourth transistor 204. The output terminal of the operational amplifier 216 serves as the output terminal of the voltage regulating unit 221.

[0121] The control ends of the first transistor 201 , the second transistor 202 , the third transistor 203 and the fourth transistor 204 are control ends of the voltage regulating unit 221 , and the control ends of the voltage regulating unit 221 are connected to the input control module 250 .

[0122] Among them, the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 are N-type transistors, and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the first voltage regulating module 220 and the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the second voltage regulating module 230 are P-type transistors.

[0123] When the driving module 200 is working in the polarity symmetry mode:

[0124] When scanning the first row, the input control module 250 outputs a control signal that is a high-level signal. The first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 are turned on. The voltage regulating unit 221 functions as a positive feedback circuit and directly outputs the input data voltage V+. The second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 are turned on. The voltage regulating unit 221 functions as a negative feedback circuit and adjusts the input data voltage V down to the data voltage V- for output.

[0125] When scanning the second row, the input control module 250 outputs a control signal that is a low-level signal, the second transistor 202 and the third transistor 203 of the voltage regulation unit 221 of the first voltage regulation module 220 are turned on, and the voltage regulation unit 221 acts as a negative feedback circuit. The voltage regulation unit 221 adjusts the input data voltage V down to the data voltage V- and outputs it. The first transistor 201 and the fourth transistor 204 of the voltage regulation unit 221 of the second voltage regulation module 230 are turned on. The voltage regulation unit 221 acts as a positive feedback circuit. The voltage regulation unit 221 directly outputs the input data voltage V+.

[0126] The input control module 250 controls one voltage regulating module to lower the data voltage and controls another voltage regulating module to increase the data voltage through the voltage regulating unit 221. The voltage regulating module that outputs the lowered data voltage and the voltage regulating module that outputs the increased data voltage are alternated row by row. The voltage regulating unit 221 has a simple structure and can reduce the manufacturing cost of the driving module 200.

[0127] It should be noted that if the input control module 250 outputs a control signal as a low-level signal when scanning the first row, and the input control module 250 outputs a control signal as a high-level signal when scanning the second row, the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the first voltage regulating module 220 and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the second voltage regulating module 230 may also be P-type transistors, and the second transistor 202 and the third transistor 203 of the voltage regulating unit 221 of the first voltage regulating module 220 and the first transistor 201 and the fourth transistor 204 of the voltage regulating unit 221 of the second voltage regulating module 230 may also be N-type transistors.

[0128] In some embodiments, the selection unit 222 includes an eighth transistor 205 and a ninth transistor 206, the first end of the eighth transistor 205 and the first end of the ninth transistor 206 are input ends of the selection unit 222, the second end of the eighth transistor 205 is directly connected to the data line, the second end of the ninth transistor 206 is connected to the data line through the voltage adjustment unit 221, and the control end of the eighth transistor 205 and the control end of the ninth transistor 206 are control ends of the selection unit 222.

[0129] One of the eighth transistor 205 and the ninth transistor 206 is a P-type transistor and the other is an N-type transistor. If the polarity partition detection module 240 outputs a high-level signal in the polarity symmetric mode and a low-level signal in the normal polarity mode, the eighth transistor 205 is a P-type transistor and the ninth transistor 206 is an N-type transistor. If the polarity partition detection module 240 outputs a low-level signal in the polarity symmetric mode and a high-level signal in the normal polarity mode, the eighth transistor 205 is an N-type transistor and the ninth transistor 206 is a P-type transistor.

[0130] The selection unit 222 is composed of two transistors, which has a simple structure and can reduce the manufacturing cost of the driving module 200 .

[0131] It should be noted that the driving module 200 can adopt a combination of embodiment two and embodiment three, that is, the first voltage regulation module 220 and the second voltage regulation module 230 adopt the solution disclosed in embodiment three, and the third voltage regulation module 280 and the fourth voltage regulation module 290 adopt the solution disclosed in embodiment one.

[0132] In some embodiments, the input control module 250 includes a fifth transistor 251, a sixth transistor 252, a seventh transistor 253, and a signal generator 254. The control terminals of the fifth transistor 251, the sixth transistor 252, and the seventh transistor 253 are all connected to the polarity partition detection module 240.

[0133] The eighth transistor 205 is a P-type transistor and the ninth transistor 206 is an N-type transistor. The first end of the fifth transistor 251 is connected to the first power supply 271, which outputs a high-level signal. The second end of the fifth transistor 251 is connected to the control end of the selection unit 222. The first end of the sixth transistor 252 is connected to the second power supply 272, which outputs a low-level signal. The second end of the sixth transistor 252 is connected to the control end of the selection unit 222.

[0134] The signal generator 254 is connected to the frame start signal line. The signal generator 254 can output high-level signals and low-level signals alternating line by line according to the scanning frequency controlled by the frame start signal line signal. The first end of the seventh transistor 253 is connected to the signal generator 254, and the second end of the seventh transistor 253 is connected to the control end of the voltage adjustment unit 221.

[0135] The fifth transistor 251 and the seventh transistor 253 are N-type transistors, and the sixth transistor 252 is a P-type transistor. If the polarity symmetric mode is used, the polarity partition detection module 240 outputs a low-level signal. If the polarity partition detection module 240 outputs a high-level signal in the normal polarity mode, the fifth transistor 251 and the seventh transistor 253 may also be P-type transistors, and the sixth transistor 252 may also be an N-type transistor.

[0136] The input control module 250 includes a fifth transistor 251 , a sixth transistor 252 and a seventh transistor 253 . The control of the two voltage regulating modules is achieved through three transistors. The structure of the input control module 250 is simple.

[0137] It should be noted that the fifth transistor 251, the sixth transistor 252 and the seventh transistor 253 can also be N-type transistors. In the normal polarity mode, the polarity partition detection module 240 outputs a low-level signal, the fifth transistor 251 and the sixth transistor 252 are turned on, and the high-level signal of the power supply is written to control the two voltage adjustment units 221 to output the data voltage V.

[0138] Example 4

[0139] This application provides a display device, see Figure 12 As shown, the display device includes a driving module 200 and a display panel 100 . The display panel 100 is connected to the driving module 200 . The driving module 200 includes the driving modules 200 disclosed in the first to third embodiments.

[0140] The driving module 200 includes a data driving module, a voltage regulating module, a polarity partition detection module 240 and an input control module 250. The data driving module is used to provide a data voltage. The first signal line 261 and the second signal line 262 are both connected to the data driving unit and are used to output the data voltage provided by the data driving module to the display panel 100. The polarity partition detection module 240 is connected to the first signal line 261 and the second signal line 262. The voltage regulating module can lower, maintain or increase the voltage passing through it. The first voltage regulating module 220 is connected to the first signal line 261, the second voltage regulating module 230 is connected to the second signal line 262, and the input control module 250 is connected to the polarity partition detection module 240. In the polarity symmetric mode, the input control module 250 controls at least one voltage regulating module to lower the data voltage. The voltage regulating module that outputs the lowered data voltage alternates row by row, or the voltage regulating module that outputs the lowered data voltage outputs the lowered data voltage every other row. By lowering the brightness of the green pixel column on one side of the boundary pixel column through the voltage regulating module, color shift can be improved or eliminated, thereby enhancing the display quality of the display panel 100 and the display device.

[0141] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0142] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0143] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0144] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A driving module, comprising a data driving module, characterized in that: The driving module further includes: a polarity partition detection module connected to the first signal line and the second signal line, wherein the first signal line and the second signal line are both connected to the data driving module; a voltage regulating module capable of lowering, maintaining, or raising the voltage passing through it, the voltage regulating module comprising a first voltage regulating module and a second voltage regulating module, the first voltage regulating module being connected to the first signal line and a data line of a pixel column with the same polarity in a polarity symmetric mode of the display panel, and the second voltage regulating module being connected to the second signal line and another data line of the pixel column with the same polarity; an input control module connected to the polarity partition detection module; in a normal polarity mode, the data voltage of the first signal line and the data voltage of the second signal line have opposite polarities, and the input control module controls the first voltage regulating module and the second voltage regulating module to output the data voltage; in a polarity symmetric mode, the data voltage of the first signal line and the data voltage of the second signal line have the same polarity, and when scanning the same row, the input control module controls at least one of the voltage regulating modules to lower the data voltage; The first voltage regulating module outputs the lowered data voltage when scanning even rows or odd rows, and the second voltage regulating module outputs the lowered data voltage when scanning odd rows or even rows; or one of the first voltage regulating module and the second voltage regulating module outputs the lowered data voltage when scanning odd rows or even rows.

2. The driving module according to claim 1, characterized in that: In the polarity symmetric mode, when scanning the same row, the input control module controls one of the voltage regulating modules to lower the data voltage, and the first voltage regulating module outputs the lowered data voltage when scanning the even rows, and the second voltage regulating module outputs the lowered data voltage when scanning the odd rows; The voltage regulating module includes a voltage regulating unit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, and an operational amplifier, wherein the first end of the first transistor and the first end of the second transistor are input ends of the voltage regulating unit, the input end of the voltage regulating unit of the first voltage regulating module is connected to the first signal line, and the input end of the voltage regulating unit of the second voltage regulating module is connected to the second signal line; The second end of the first transistor is connected to the non-inverting input terminal of the operational amplifier via a first resistor, the second end of the second transistor is connected to the inverting input terminal of the operational amplifier, the second resistor is connected to the non-inverting input terminal and the ground terminal, the first end of the third transistor is connected to the non-inverting input terminal via the third resistor, the first end of the fourth transistor is connected to the inverting input terminal, and the second end of the third transistor, the second end of the fourth transistor, and the output terminal of the operational amplifier are connected to serve as the output terminal of the voltage regulating unit; The control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor are control ends of the voltage regulating unit, and the control ends of the voltage regulating unit are connected to the input control module; The first transistor and the fourth transistor of the first voltage regulating module and the second transistor and the third transistor of the second voltage regulating module are N-type transistors, and the second transistor and the third transistor of the first voltage regulating module and the first transistor and the fourth transistor of the second voltage regulating module are P-type transistors.

3. The driving module according to claim 2, characterized in that: The input control module includes a fifth transistor, a sixth transistor, a seventh transistor and a signal generator. The control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are all connected to the polarity partition detection module. The first end of the fifth transistor is connected to a first power supply, which outputs a high-level signal. The second end of the fifth transistor is connected to the control end of the voltage regulation unit of the first voltage regulation module. The first end of the sixth transistor is connected to a second power supply, which outputs a low-level signal. The second end of the sixth transistor is connected to the control end of the voltage regulation unit of the second voltage regulation module. The signal generator is connected to a frame start signal line and can output a high-level signal and a low-level signal alternating row by row according to a scanning frequency controlled by the frame start signal line signal. The first end of the seventh transistor is connected to the signal generator, and the second end of the seventh transistor is connected to the control end of the voltage regulation unit. The fifth transistor and the sixth transistor are N-type transistors, and the seventh transistor is a P-type transistor, or the fifth transistor and the sixth transistor are P-type transistors, and the seventh transistor is an N-type transistor.

4. The driving module according to claim 1, wherein: In the polarity symmetric mode, the input control module controls one of the voltage regulation modules to lower the data voltage and controls another of the voltage regulation modules to increase the data voltage, and the voltage regulation modules that output the lowered data voltage and the voltage regulation modules that output the increased data voltage are alternated row by row.

5. The driving module according to claim 4, characterized in that: The voltage regulating module includes a voltage regulating unit and a selection unit, wherein the input end of the selection unit of the first voltage regulating module is connected to the first signal line, the input end of the selection unit of the second voltage regulating module is connected to the second signal line, and the output end of the selection unit is connected to the voltage regulating unit; The input control module can control the selection unit to connect the first signal line and the second signal line to the corresponding data line directly or indirectly through the voltage adjustment unit. The voltage adjustment unit can lower or increase the voltage passing through it.

6. The driving module according to claim 5, characterized in that: The voltage regulating unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and an operational amplifier, wherein the first end of the first transistor and the first end of the second transistor are input ends of the voltage regulating unit; The second end of the first transistor is connected to the non-inverting input terminal of the operational amplifier through a first resistor, the second end of the second transistor is connected to the inverting input terminal of the operational amplifier, the second resistor is connected to the non-inverting input terminal and the ground terminal, the first end of the third transistor is connected to the non-inverting input terminal through the third resistor, the second end of the third transistor is connected to the output terminal of the operational amplifier, the first end of the fourth transistor is connected to the inverting input terminal, the second end of the fourth transistor is connected to the output terminal of the operational amplifier through the fourth resistor, the fifth resistor is connected to the ground terminal and the second end of the fourth transistor, and the output terminal of the operational amplifier is the output terminal of the voltage regulating unit; The control end of the first transistor, the control end of the second transistor, the control end of the third transistor, and the control end of the fourth transistor are control ends of the voltage regulating unit, and the control ends of the voltage regulating unit are connected to the input control module; The first transistor and the fourth transistor of the first voltage regulating module and the second transistor and the third transistor of the second voltage regulating module are P-type transistors, and the second transistor and the third transistor of the first voltage regulating module and the first transistor and the fourth transistor of the second voltage regulating module are N-type transistors.

7. The driving module according to claim 6, characterized in that: The selection unit includes an eighth transistor and a ninth transistor, the first end of the eighth transistor and the first end of the ninth transistor are input ends of the selection unit, the second end of the eighth transistor is directly connected to the data line, the second end of the ninth transistor is connected to the data line through the voltage adjustment unit, the control end of the eighth transistor and the control end of the ninth transistor are control ends of the selection unit, and one of the eighth transistor and the ninth transistor is a P-type transistor and the other is an N-type transistor.

8. The driving module according to claim 7, characterized in that: The input control module includes a fifth transistor, a sixth transistor, a seventh transistor and a signal generator, wherein the control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor are all connected to the polarity partition detection module; The eighth transistor is a P-type transistor and the ninth transistor is an N-type transistor, a first end of the fifth transistor is connected to a first power supply, the first power supply outputs a high-level signal, a second end of the fifth transistor is connected to the control end of the selection unit, a first end of the sixth transistor is connected to a second power supply, the second power supply outputs a low-level signal, and a second end of the sixth transistor is connected to the control end of the selection unit; The signal generator is connected to the frame start signal line, and the signal generator can output a high level signal and a low level signal alternately line by line according to a scanning frequency controlled by a signal of the frame start signal line. The first end of the seventh transistor is connected to the signal generator, and the second end of the seventh transistor is connected to the control end of the voltage adjustment unit. The fifth transistor and the seventh transistor are N-type transistors, and the sixth transistor is a P-type transistor, or the fifth transistor and the seventh transistor are P-type transistors, and the sixth transistor is an N-type transistor.

9. The driving module according to claim 1, characterized in that: The polarity partition detection module includes an XOR gate circuit or an XNOR gate circuit.

10. A display device, characterized in that: include: The drive module according to any one of claims 1 to 9; The display panel is connected to the driving module.

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