Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The present application relates to a semiconductor device comprising: a device structure in a semiconductor body having a first load terminal on a first side of the semiconductor body; a lower insulating layer on a first side of the semiconductor body; a conductor line in the lowermost metallization layer of the first side of the semiconductor body; a load pad in the uppermost metallization layer of the first side of the semiconductor body; the uppermost metallization layer includes a copper layer and the lowermost metallization layer includes a tungsten layer, wherein the conductor lines are arranged in trenches in the lower insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and to a method for manufacturing the same. Background Art

[0002] A semiconductor device may include a device structure in a semiconductor body that can be contacted via metallization located on a first side of the semiconductor body. The metallization can include a load pad for contact formation, such as a source pad in the case of a FET. The device structure can include a load terminal on the first side of the semiconductor body, such as a source region of a FET. It can also include a control terminal, such as a gate electrode, on the first side of the semiconductor body. Summary of the Invention

[0003] Examples of the present application relate to a semiconductor device.

[0004] In the embodiment of claim 1, a semiconductor device includes: a lower insulating layer located on a first side of a semiconductor body; a conductor line located in a lowermost metallization layer on the first side of the semiconductor body; and a load pad located in an uppermost metallization layer on the first side of the semiconductor body. The lowermost metallization layer includes a tungsten layer, and the uppermost metallization layer includes a copper layer, for example, for contact formation by wire bonding and / or soldering. The conductor line formed in the lowermost metallization layer is arranged in an opening or trench in the lower insulating layer, for example, embedded in the lower insulating layer.

[0005] Conductor lines can improve the lateral distribution of control signals (e.g., gate signals) and avoid interruption of load pads. Embedding the conductor lines in the lower insulating layer can reduce the topology of, for example, the imide layer on the uppermost metallization layer and / or the passivation layer (see below for details). This reduced topology can, for example, have advantages in subsequent handling steps (e.g., mounting and / or contacting steps).

[0006] Embodiments and features are provided throughout this disclosure, which relates to apparatus and device aspects, but also to method and use aspects. If, for example, a device manufactured in a certain manner is described, this also discloses the corresponding manufacturing process, and vice versa. Generally speaking, the present application provides a semiconductor device having, in addition to an uppermost metallization layer, a lowermost metallization layer, wherein conductor lines (e.g., for control / gate signal amplification) formed in the lowermost metallization layer are embedded in a lower insulating layer.

[0007] Although the embedded conductor line or the lowermost metallization layer is a different layer, for example deposited in a subsequent process step, the embedded conductor line or the lowermost metallization layer can be arranged at the same vertical height as the lower insulating layer, for example, in a common lateral plane. The respective layers can be structured, for example, the conductor line is formed in the lowermost metallization layer and the trench is formed in the lower insulating layer, so that at least where the conductor line is embedded in the lower insulating layer, the lowermost metallization layer and the lower insulating layer can be arranged at the same vertical height. In other words, the respective layer refers to a material layer that can only partially cover the first side of the semiconductor body, so that the different layers can be arranged in a common horizontal plane (vice versa, the term layer will not refer to a horizontal plane that completely covers the first side of the semiconductor body). In summary, the lowermost metallization layer and the lower insulating layer deposited in different process steps differ in their respective materials and do not necessarily differ in their vertical position on the first side of the semiconductor body or in their vertical distance relative to the first side of the semiconductor body.

[0008] For example, the embedded conductor line can be laterally surrounded in the lower insulating layer in a lateral direction perpendicular to the length direction of the conductor line. The conductor line can, for example, extend continuously (e.g., without interruption) from under the control pad next to the load pad to under the load pad, for example, from under the gate pad to under the source pad. Its length direction can, for example, be parallel to the underlying control or gate electrode, for example, to improve control signal distribution along the gate electrode.

[0009] Generally, in this disclosure, "below" and "above" refer to a vertical direction perpendicular to the lateral direction, where "below" means closer to the semiconductor body, and "above" means at a greater distance relative to the semiconductor body (this applies to a stack on the semiconductor body). In the vertical direction, the trench in the lower insulating layer can completely penetrate the lower insulating layer, for example, extending between the upper and lower ends of the lower insulating layer. The lower insulating layer can be, for example, doped or undoped silicon oxide.

[0010] The bottom metallization layer (in which the conductor lines are formed) can include a tungsten layer, which can be the sole layer of the bottom metallization layer or a sublayer in a layer stack. For example, a tungsten layer can have advantages in terms of corrosion or mechanical rigidity compared to an aluminum layer. The bottom metallization layer can include one or more metal barrier layers below the tungsten layer, such as at least one of titanium, titanium nitride, or titanium tungsten layers. The barrier layer can have a thickness of at least 5 nm and no more than 50 nm, 30 nm, or 15 nm, and / or the tungsten layer can have a thickness of at least 100 nm or at least 130 nm, with a possible upper limit being, for example, no more than 300 nm or 200 nm.

[0011] The top metallization layer (in which the load pads and, for example, the control pads may be formed) can, for example, have a thickness of at least 3 μm, 4 μm, or 5 μm (a possible upper limit is, for example, 20 μm or 15 μm). It may include a copper layer, which may be the only layer of the top metallization layer or a sublayer in a layer stack. The top metallization layer can further include a metal barrier layer and / or a metal adhesion layer below the copper layer, as will be described in more detail below.

[0012] The semiconductor device may be a power device, for example having a breakdown voltage of at least 10 V, 20 V or 30 V, with a possible upper limit of, for example, not more than 800 V, 600 V, 400 V or 200 V. For example, in the case of a FET, it can have a source region and a drain region as well as a body region. The source region can be a first load terminal on a first side of the semiconductor body, wherein the drain region (second load terminal) can also be arranged on the first side or on a vertically opposite second side of the semiconductor body. Independently of these details, a load pad formed in the uppermost metallization layer can be connected to the first load terminal of the device structure, which can, for example, be a source plate connected to the source region.

[0013] In an embodiment, the embedded conductor line is flush with the lower insulating layer. In other words, the upper end of the conductor line and the upper end of the lower insulating layer are arranged at the same vertical height. After filling the trench with the metal material of the lower metallization layer, a planarization step can be applied, wherein the upper side of the conductor line is then located in the same plane as the upper side of the lower insulating layer, for example. As discussed above, the layers differ in their respective materials and, due to the respective structuring (conductor line versus trench), in their lateral extension and shape, but they can be arranged at the same vertical position (conductor line embedded in the lower insulating layer).

[0014] In an embodiment, the device includes an upper insulating layer on a lower insulating layer. With respect to the vertical direction, the upper insulating layer can be adjacent to the lower insulating layer, for example, deposited directly on the lower insulating layer. The upper insulating layer is disposed below the uppermost metallization layer (e.g., excluding the opening / interconnect), for example, below a load pad formed in the uppermost metallization layer.

[0015] In one embodiment, the upper insulating layer is made of a harder material than the lower insulating layer. The upper insulating layer can serve as a hard passivation for the device, for example, to protect or seal the device structure, for example, from ion diffusion. In other words, the hard passivation can be integrated below the load pad / topmost metallization layer. For example, in combination with a lower insulating layer made of silicon oxide, the upper insulating layer can be made of silicon nitride.

[0016] In an embodiment, the upper insulating layer is locally penetrated by a vertical load interconnect, which provides an electrical connection between the load pad and the first load terminal of the device structure (e.g., between the source pad and the source region). The vertical load interconnect can be formed in the topmost metallization layer, for example, filled by a layer or sublayer (layer stack) of the topmost metallization system. In other words, the same metal barrier layer and / or metal adhesion layer and / or copper layer deposited for the load pad can fill or form the vertical load interconnect. This also applies to the vertical control interconnect, which can connect the control pad (e.g., gate pad) next to the load pad in the topmost metallization layer to the conductor line below.

[0017] In one embodiment, a lower load interconnect extends through the lower insulating layer and connects the first load pad to the first load terminal of the device structure. Specifically, the lower load interconnect can be connected vertically between the vertical load interconnect and the first load terminal. The lower load interconnect can be made of the same metal material as the conductor line, for example, including a tungsten layer and optionally an underlying barrier layer. In other words, the lower load interconnect and the conductor line can be fabricated in the same process step or steps.

[0018] In an embodiment, the conductor line below the load pad is completely covered by the upper insulating layer. Alternatively or additionally, the conductor line may be completely covered by the upper insulating layer laterally between the load pad and the control pad (e.g., gate pad). In the case where the conductor line is completely covered, the upper insulating layer is not interrupted, for example, above the conductor line. It may be interrupted laterally to the side, for example, where a vertical load interconnect is formed.

[0019] In an embodiment, the bottommost metallization layer and the topmost metallization layer are the only metallization layers located on the first side of the semiconductor body. Each of the two metallization layers may comprise different metal sublayers, but no further metal layer isolated from the topmost and bottommost metallization layers will be arranged in between. In other words, the front metallization consists of two metallization layers (that is, the bottommost and topmost metallization layers). The vertical load interconnect can be directly connected to the lower load interconnect, and / or the vertical control interconnect can be directly connected to the conductor line, and / or the lower load interconnect can be directly connected to the load terminal, and / or the conductor line can be directly connected to the control electrode, such as the gate electrode. In any case, the metallization can be provided on the second side of the semiconductor body, that is, the back side metallization.

[0020] As described above, the topmost metallization layer may include a barrier layer below the copper layer, wherein the barrier layer may, for example, include titanium nitride and / or tungsten (e.g., a TiN layer+W layer), among other elements. In an embodiment, the barrier layer is retracted inwardly in the lateral direction, with the lateral edges of the barrier layer being covered by the copper layer. The lateral spacing between this lateral edge of the barrier layer and the lateral edge of the copper layer, as seen in a vertical cross-section, for example, perpendicular to the lateral edge of the barrier layer, may be at least 1 μm or 2 μm (a possible upper limit is, for example, 25 μm, 15 μm, or 10 μm). If an adhesive layer is provided between the barrier layer and the copper layer, the barrier layer may also be retracted inwardly in the lateral direction with respect to the adhesive layer. In other words, the respective lateral edges of the adhesive layer and the copper layer may be arranged in substantially the same lateral position, with the barrier layer retracted inwardly and surrounded laterally by the adhesive and / or copper layer. Considering the top metallization layer as a whole, this may, for example, allow for defined lateral edges.

[0021] In an embodiment, the device structure has a second load terminal on a second side of the semiconductor body. This can be, for example, a drain region (see above), with the device structure having its source region on a first side and its drain region on a second side of the semiconductor body. Between them, a body region including a channel region can be arranged, with a gate electrode capacitively coupled to the body region via a gate dielectric. The source and drain regions can be made of a first doping type, and the body region can be made of a second doping type, where the first type is, for example, n-type and the second type is p-type.

[0022] In an embodiment, a device or device structure comprises a gate electrode in a trench extending from a first side into the semiconductor body and having an elongated lateral extension. Alternatively or in addition, the device or device structure may comprise a field electrode in a trench extending from the first side into the semiconductor body and having an elongated lateral extension. Separate trenches may be provided for the gate electrode and the field electrode, or the gate electrode and the field electrode may be arranged in a common trench. Regardless of the details, the field electrode may be arranged next to a drift region of the device structure, for example, the drift region being made of the same doping type but having a lower doping concentration than the drain region.

[0023] In an embodiment, a conductor line is stacked above the gate electrode, for example, extending parallel to an elongated trench having the gate electrode. The gate electrode and the conductor line may be made of different materials, for example, the gate electrode may be made of polysilicon. The upper conductor line may be formed directly adjacent to the gate electrode, for example, to improve lateral gate signal distribution along the gate electrode.

[0024] In an embodiment, a method of manufacturing a semiconductor device (e.g., a device as claimed in one of the device claims) is provided. The method may include:

[0025] i) forming a lower insulating layer on the first side of the semiconductor body;

[0026] ii) etching a trench into the lower insulating layer;

[0027] iii) Filling the trench with tungsten material.

[0028] With regard to possible details of the device, reference is made to the present disclosure as a whole.

[0029] Before the tungsten material is deposited, a barrier layer may be formed, for example, covering the bottom of the trench. The tungsten material may be deposited in excess, for example, extending above and covering the upper side of the lower insulating layer. The excess tungsten material may be removed by planarization, for example, by chemical mechanical polishing (CMP), for example, together with the barrier layer located on the surface of the lower insulating layer. As a result, the conductor line may be flush in the lower insulating layer.

[0030] In an embodiment, the conductor line and the lower load interconnect that may later connect the load pad to the first load terminal are fabricated simultaneously. Using tungsten material deposition for the conductor line, possibly in conjunction with a previous barrier layer deposition, the conductor line can be formed and the lower load interconnect can also be formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In the following, a semiconductor device and a method for manufacturing the same are explained in more detail by means of exemplary embodiments.In different combinations, individual features can also be relevant for the present disclosure.

[0032] Figure 1 A semiconductor device is shown in cross-sectional view;

[0033] Figure 2 In vertical Figure 1 The sectional plane of the drawing plane is shown Figure 1 a part of a device;

[0034] Figure 3 Further details of the semiconductor device are shown in cross-sectional views;

[0035] Figure 4 showing a detailed view of the lateral edge of the uppermost metallization layer having a copper layer;

[0036] Figure 5 Summarize some manufacturing steps in a flow chart;

[0037] Figure 6a -f illustrates some of the manufacturing steps in more detail. DETAILED DESCRIPTION

[0038] Figure 1The semiconductor device 10 is shown in a cross-sectional view. It comprises a device structure 20 in a semiconductor body 30, which has a first load terminal 21 on a first side 30.1 and a second load terminal 25 on a second side 30.2 of the semiconductor body 30. The load terminals 21, 25 are only schematically shown. Figure 1 For further details of the device structure 20, refer to Figure 3 .

[0039] On the first side 30.1 of the semiconductor body 30, a lower insulating layer 40 is arranged, which in the example shown is made of silicon oxide. Conductor lines 65 are embedded in the lower insulating layer 40, that is, arranged in trenches 45 in the lower insulating layer 40. The conductor lines 65 are flush in the lower insulating layer 40, which can be obtained in a planarization step (see in detail). Figure 6d / e). Conductor line 65 is formed in a lowermost metallization layer 60, which is at least partially embedded in lower insulating layer 40 (arranged at the same vertical position, as discussed above). Lowermost metallization layer 60 includes a tungsten layer 160 and an underlying barrier layer 162, such as a titanium nitride layer (or a TiN+W layer stack). In the example shown, barrier layer 162 has a thickness of approximately 10 nm, and tungsten layer 160 has a thickness of approximately 150 nm.

[0040] The upper insulating layer 50 is placed on the lower insulating layer 40 and covers the conductor line 65. Compared to the lower insulating layer 40, the upper insulating layer 50 is made of a harder material, in this example, silicon nitride. On the upper insulating layer 50, the uppermost metallization layer 70 is arranged. It includes a copper layer 170, which in this example has a thickness of about 7 μm. Below, further layers are arranged (not cited here), see more details. Figure 4 In the top metallization layer 70, a load pad 75 is formed, which can be a source pad. The load pad 75 can be covered by a passivation layer 80 and / or an imide layer 90, with the center portion of the load pad 75 remaining open for contact formation in the back-end-of-line (BOL) process.

[0041] Vertical load interconnect 56 penetrates upper insulating layer 50 and connects load pad 75 to first load terminal 21. Corresponding opening 57 in upper insulating layer 50 is filled with uppermost metallization layer 70, which forms vertical load interconnect 56. Below, opening 47 in lower insulating layer 40 is filled with the stack of lowermost metallization layer 60, that is, with barrier layer 162 and tungsten layer 160.

[0042] Below the conductor line 65, the gate electrode 115 is arranged in the trench 215. Perpendicular to the plane of the drawing, it has an elongated lateral extension, parallel to which the conductor line 65 extends. This is illustrated in more detail in Figure 2 middle, Figure 2 Shown perpendicular to Figure 1 1 and 1 . The cross section of the drawing plane is shown in FIG. 1 (see AA for illustration). In the active area of device structure 20, for example, below load pad 75, conductor line 65 is stacked on gate electrode 115 and extends parallel thereto. Gate electrode 115 ends below load pad 75, and conductor line 65 forms an electrical connection to control pad 78 next to load pad 75.

[0043] Under load pad 75 and between load pad 75 and control pad 78, conductor line 65 is covered by upper insulating layer 50. Conductor line 65 is connected to control pad 78 via vertical control interconnect 58 below control pad 78.

[0044] Figure 3 The device structure 20 is shown in more detail. Generally, in this disclosure, similar reference numerals refer to similar elements or elements with similar functions, and reference is also made to the description of other figures. Figure 3 In the case of the FET illustrated in FIG, a first load terminal 21 is a source region 22 at a first side 30.1 of a semiconductor body 30. A second load terminal 25 is a drain region 26 at a vertically opposite second side 30.2, wherein the body region 23 is arranged in the middle, optionally in combination with a drift region 24. In the example shown, the source region 22, the drift region 24, and the drain region 25 are n-doped, and the body region 23 is p-doped.

[0045] The lowermost and uppermost metallization layers 60, 70 and the corresponding interconnects are only schematically shown. Figure 3 The lower load interconnect 46 and the vertical load interconnect 56 connect the load pad 75 (eg, source plate) to the source region 22. Similar interconnect structures may be provided for connecting the load pad 75 to the field electrode (not shown here) in the trench next to the drift region.

[0046] Figure 4The topmost metallization layer 70 is shown in detail. In addition to the copper layer 170, it also includes an adhesion layer 171 and a barrier layer 172 below. Adhesion layer 171 can also be a copper layer, for example, sputter-deposited, as opposed to copper layer 170, which is deposited from a bath. Barrier layer 172 can be a titanium nitride layer. Barrier layer 172 is laterally set back relative to copper layer 170 and adhesion layer 171. Lateral edges 172a of barrier layer 172 can be covered within the stack, for example, laterally and vertically. In this example, a vertical distance 185 between lateral edges 172a of barrier layer 172 and lateral edges 171a of adhesion layer 171 and / or lateral edges 170a of copper layer 170 is approximately 10 μm.

[0047] Figure 5 Some manufacturing steps are summarized in a flow chart.The method may include forming 301 a lower insulating layer on a first side of the semiconductor body, etching 302 trenches into the lower insulating layer, and filling 303 the trenches with a tungsten material.

[0048] Figure 6a -f illustrates some of the manufacturing steps in more detail. Figure 6a A semiconductor body 30 is shown in which the device structure 20 has been formed (eg, doped regions and gate trenches). A lower insulating layer 40 is then formed on a first side 30.1 of the semiconductor body 30 by depositing silicon oxide 140, see Figure 6b .exist Figure 6c In the step shown in , trenches 45 (for conductor lines) and openings 47 (for lower load interconnects) have been etched into the lower insulating layer 40. For this etching step, a structured mask can be provided on the lower insulating layer 40, which is not shown in detail here.

[0049] Figure 6d The structure is shown after deposition of the lowermost metallization layer 60 , where only tungsten material 260 is shown (the thin barrier layer below is not shown). Tungsten material 260 fills trenches 45 and openings 47 , with excess tungsten material 260 . 1 covering the upper side of lower insulating layer 40 .

[0050] Figure 6e The structure is shown after planarization (that is, after removing excess tungsten material from the upper side of the lower insulating layer 40 by chemical mechanical polishing). Likewise, the lower metallization layer 60 (e.g., conductor line 65 and lower load interconnect 46) is embedded in the lower insulating layer 40. Subsequently, the upper insulating layer 50 can be formed by depositing silicon nitride 150, see Figure 6f In a subsequent step not shown here, the silicon nitride 150 can be opened locally in order to later form contacts with the uppermost metallization layer, see Figure 1-3 Make a comparison.

[0051] The embodiments and features of the present application can be summarized in the form of the following examples:

[0052] 1. A semiconductor device (10), comprising:

[0053] A device structure (20) located in a semiconductor body (30) having a first load terminal (21) on a first side (30.1) of the semiconductor body (30);

[0054] a lower insulating layer (40) located on the first side (30.1) of the semiconductor body (30);

[0055] a conductor line (65) located in the lowermost metallization layer (60) of the first side (30.1) of the semiconductor body (30);

[0056] a load pad (75) located in the uppermost metallization layer (70) of the first side (30.1) of the semiconductor body (30);

[0057] The uppermost metallization layer (70) comprises a copper layer (170), and the lowermost metallization layer (60) comprises a tungsten layer (160),

[0058] The conductor line (65) is arranged in a groove (45) in the lower insulating layer (40).

[0059] 2. The semiconductor device (10) of Example 1, wherein the conductor line (65) is flush in the lower insulating layer (40).

[0060] 3. The semiconductor device (10) according to example 1 or 2, comprising:

[0061] An upper insulating layer (50) is located on the lower insulating layer (40).

[0062] 4. In the semiconductor device (10) of Example 3, the upper insulating layer (50) is made of a harder material than the lower insulating layer (40).

[0063] 5. In the semiconductor device (10) of Example 3 or 4, the upper insulating layer (50) is partially penetrated by a vertical load interconnect (56), the vertical load interconnect (56) providing an electrical connection between the load pad (75) and the first load terminal (21), the vertical load interconnect (56) being formed in the uppermost metallization layer (70).

[0064] 6. In the semiconductor device (10) of Example 5, the vertical load interconnect (56) is connected to the first load terminal (21) via a lower load interconnect (46), wherein the lower load interconnect (46) passes through the lower insulating layer (40) and is made of the same tungsten layer (160) as the conductor line (65).

[0065] 7. A semiconductor device (10) as described in any one of Examples 3 to 6, wherein the conductor line (65) is completely covered by the upper insulating layer (50) below the load pad (75) and / or laterally between the load pad (75) and the control pad (78).

[0066] 8. The semiconductor device (10) of any one of the preceding examples, wherein the lowermost metallization layer (60) and the uppermost metallization layer (70) are the only metallization layers at the first side (30.1) of the semiconductor body (30).

[0067] 9. The semiconductor device (10) of any one of the preceding examples, wherein the uppermost metallization layer comprises a barrier layer (172) below the copper layer (170), wherein the barrier layer (172) is laterally retracted inwardly, and a lateral edge (172a) of the barrier layer (172) is covered by the copper layer (170).

[0068] 10. The semiconductor device (10) of any one of the preceding examples, the device structure (20) having a second load terminal (25) on a second side (30.2) of the semiconductor body (30) vertically opposite the first side (30.1).

[0069] 11. A semiconductor device (10) as described in any of the preceding examples, wherein the device structure (20) has a gate electrode (115) and / or a field electrode arranged in a trench (215), the trench (215) extending from the first side (30.1) into the semiconductor body (30) and having an elongated lateral extension.

[0070] 12. The semiconductor device (10) of Example 11, wherein the conductor line (65) extends parallel to the trench (215) and parallel to the gate electrode (115) disposed in the trench (215), and the conductor line (65) is stacked above the gate electrode (115).

[0071] 13. A method of manufacturing a semiconductor device (10), comprising:

[0072] i.) forming (301) a lower insulating layer (40) on a first side (30.1) of the semiconductor body (30);

[0073] ii.) etching (302) a trench (45) into the lower insulating layer (40);

[0074] iii.) Filling (303) the trench (45) with tungsten material (260).

[0075] 14. The method for manufacturing the semiconductor device (10) according to Example 2 according to Example 13, wherein in step iii.), the tungsten material (260) is deposited excessively, and the excess tungsten material (260.1) is subsequently removed by planarization.

[0076] 15. The method of example 13 or 14 for manufacturing the semiconductor device (10) of example 6, wherein the lower load interconnect (46) and the conductor line (65) are made simultaneously.

Claims

1. A semiconductor device (10), comprising: A device structure (20) located in a semiconductor body (30) having a first load terminal (21) on a first side (30.1) of the semiconductor body (30); a lower insulating layer (40) located on the first side (30.1) of the semiconductor body (30); a conductor line (65) located in the lowermost metallization layer (60) of the first side (30.1) of the semiconductor body (30); a load pad (75) located in the uppermost metallization layer (70) of the first side (30.1) of the semiconductor body (30); The uppermost metallization layer (70) comprises a copper layer (170), and the lowermost metallization layer (60) comprises a tungsten layer (160), The conductor line (65) is arranged in a groove (45) in the lower insulating layer (40).

2. The semiconductor device (10) according to claim 1, wherein the conductor line (65) is flush in the lower insulating layer (40).

3. The semiconductor device (10) according to claim 1 or 2, comprising: An upper insulating layer (50) is located on the lower insulating layer (40).

4. The semiconductor device (10) according to claim 3, wherein the upper insulating layer (50) is made of a harder material than the lower insulating layer (40).

5. A semiconductor device (10) as claimed in claim 3 or 4, wherein the upper insulating layer (50) is locally penetrated by a vertical load interconnect (56), the vertical load interconnect (56) providing an electrical connection between the load pad (75) and the first load terminal (21), the vertical load interconnect (56) being formed in the uppermost metallization layer (70).

6. The semiconductor device (10) of claim 5, wherein the vertical load interconnect (56) is connected to the first load terminal (21) via a lower load interconnect (46), wherein the lower load interconnect (46) passes through the lower insulating layer (40) and is made of the same tungsten layer (160) as the conductor line (65).

7. A semiconductor device (10) as claimed in any one of claims 3 to 6, wherein the conductor line (65) is completely covered by the upper insulating layer (50) below the load pad (75) and / or laterally between the load pad (75) and the control pad (78).

8. The semiconductor device (10) of any one of the preceding claims, wherein the lowermost metallization layer (60) and the uppermost metallization layer (70) are the only metallization layers at the first side (30.1) of the semiconductor body (30).

9. The semiconductor device (10) of any one of the preceding claims, the uppermost metallization layer comprising a barrier layer (172) below the copper layer (170), wherein the barrier layer (172) is set back laterally inwards, lateral edges (172a) of the barrier layer (172) being covered by the copper layer (170).

10. The semiconductor device (10) according to any one of the preceding claims, the device structure (20) having a second load terminal (25) on a second side (30.2) of the semiconductor body (30) vertically opposite the first side (30.1).

11. The semiconductor device (10) as claimed in claim 1 , wherein the device structure (20) has a gate electrode (115) and / or a field electrode arranged in a trench (215), the trench (215) extending from the first side (30.1) into the semiconductor body (30) and having an elongated lateral extension.

12. The semiconductor device (10) of claim 11, wherein the conductor line (65) extends parallel to the trench (215) and parallel to a gate electrode (115) disposed in the trench (215), the conductor line (65) being stacked above the gate electrode (115).

13. A method of manufacturing a semiconductor device (10), comprising: i.) forming (301) a lower insulating layer (40) on a first side (30.1) of the semiconductor body (30); ii.) etching (302) a trench (45) into the lower insulating layer (40); iii.) Filling (303) the trench (45) with tungsten material (260).

14. The method for manufacturing a semiconductor device (10) according to claim 2, wherein in step iii.), the tungsten material (260) is deposited in excess, the excess tungsten material (260.1) being subsequently removed by planarization.

15. The method for manufacturing the semiconductor device (10) according to claim 6 according to claim 13 or 14, wherein the lower load interconnect (46) and the conductor line (65) are made simultaneously.

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