A circuit and method for preventing malfunction of power secondary equipment

Abstract

This invention discloses a circuit and method for preventing malfunction of secondary power equipment, relating to the field of power protection technology. A global monitoring layer acquires the power system's safety thresholds. A real-time response layer collects the power system's DC grounding current and AC inrush voltage waveforms, and detects transient currents in relay (TJR) coils. A dynamic coordination layer receives the power system voltage waveforms and relay (TJR) coil transient currents. Based on the safety thresholds sent by the global monitoring layer, it dynamically adjusts resistance and capacitance parameters to optimize the filter frequency response. This protection method utilizes a programmable capacitor array and a digital potentiometer. Using an FPGA to calculate the optimal resistance and capacitance combination, the filter parameters can be adaptively adjusted based on grid interference, improving the bypass capability of high-frequency signals and rapidly triggering the bypass mechanism to prevent relay malfunctions and enhance power system reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of power protection, and in particular to a circuit and method for preventing malfunction of power secondary equipment. Background Art

[0002] One of the most direct hazards of AC leakage into DC and DC system grounding is the possibility of causing false operation of relay protection devices, that is, the protection tripping is erroneously initiated when there is no actual fault in the primary equipment of the power system. The correct operation of relay protection devices is crucial to maintaining the stability of the power system. False operation can cause unnecessary power outages, threatening the safe operation of the power grid and the reliability of power supply.

[0003] The existing technology has the following defects:

[0004] 1. When relays switch, they generate transient currents that can cause malfunctions. Existing technologies lack the ability to accurately monitor and bypass these transient currents. Traditional methods may use simple time delay mechanisms to avoid malfunctions, but this approach cannot distinguish between true fault signals and transient interference signals and may still cause malfunctions.

[0005] 2. Existing power systems mostly use passive filtering or simple hardware circuits (such as fixed capacitors and resistors) for anti-interference design. This approach cannot be optimized for different types of high-frequency interference signals. For example, when AC interference signals occur, the response speed of traditional filtering circuits is slow, which may cause relays to malfunction and affect the normal operation of equipment in the power system. Summary of the Invention

[0006] The purpose of the present invention is to provide a circuit and method for preventing malfunction of power secondary equipment. The circuit and method use a programmable capacitor array and a digital potentiometer to calculate the optimal resistance-capacitance combination through FPGA, so that the filter parameters can be adaptively adjusted according to the grid interference situation, the bypass capability of high-frequency signals can be improved, and the bypass mechanism can be quickly triggered to prevent relay malfunction and improve the reliability of the power system.

[0007] In order to achieve the above object, the present invention provides the following technical solution: a method for preventing malfunction of power secondary equipment, the protection method comprising the following steps:

[0008] The global monitoring layer obtains the safety threshold of the power system, communicates with the dynamic coordination layer through the CAN bus, and sends global parameter instructions;

[0009] The real-time response layer collects the voltage waveform of the power system and detects the transient current of the relay coil before transmitting it to the dynamic coordination layer;

[0010] The dynamic coordination layer receives the power system voltage waveform and the transient current of the relay coil, and optimizes the filter frequency response by dynamically adjusting the resistance and capacitance parameters based on the safety threshold sent by the global monitoring layer.

[0011] In a preferred embodiment, the dynamic coordination layer receives the power system voltage waveform and the transient current of the relay coil, dynamically adjusts the resistance and capacitance parameters based on the safety threshold sent by the global monitoring layer, and optimizes the filter frequency response, including the following steps:

[0012] The dynamic coordination layer continuously receives signal data from the real-time response layer through the communication interface. The signal data includes the current DC or AC voltage waveform, AC inrush frequency characteristics, and the transient current waveform of the relay coil.

[0013] After determining the current interference type, the preset interference model is retrieved, the frequency range of the current interference is compared, the resistance and capacitance time constants required for the optimal filter response range are calculated, and the corresponding resistance and capacitance adjustment values ​​are output to form the target response curve;

[0014] Send instructions to the digital potentiometer through the FPGA to adjust the internal resistance setting of the digital potentiometer, and send control commands to the programmable capacitor array. The programmable capacitor array selects the capacitor combination according to the control commands;

[0015] The dynamically adjusted RC network acts on the front end of the detection circuit or the relay control loop. The FPGA transmits the currently used RC time constant and filter response effect information back to the global monitoring layer and the real-time response layer. The global monitoring layer updates the security policy based on the RC time constant and filter response effect. The real-time response layer adjusts the next round of sampling strategy and trigger judgment criteria based on the RC time constant and filter response effect.

[0016] In a preferred embodiment, the RC time constant required for the optimal filter response interval is calculated, and the corresponding resistance and capacitance adjustment amounts are output to form a target response curve, specifically:

[0017] Time constant of RC filter The relationship with resistance R and capacitance C is: , select the cutoff frequency as the upper limit of the interference frequency, calculate the corresponding time constant, and the cutoff frequency calculation expression is: , then the calculation expressions of resistance and capacitance are: , where The cut-off frequency is calculated by adjusting the resistance and capacitance values ​​as needed through the digital potentiometer and programmable capacitor array, and the target response curve is optimized through gain control and filter bandwidth adjustment.

[0018] In a preferred embodiment, the digital potentiometer and the programmable capacitor array are used to adjust the resistance and capacitance values ​​as needed to calculate the corresponding adjustment amount, including the following steps:

[0019] The resistance adjustment amount is obtained by subtracting the current resistance from the target resistance. Assume that the total resistance range of the digital potentiometer is , calculate the digital code corresponding to adjusting the resistance to the required value, the expression is: , where is the required resistance value, is the digital potentiometer resolution, It is the control code corresponding to the resistance adjustment amount of the digital potentiometer;

[0020] The capacitance adjustment amount is obtained by subtracting the current capacitance from the target capacitance. Assume that the capacitance range of the programmable capacitor array is , calculate the digital code corresponding to adjusting the capacitance to the required value, the expression is: , where is the required capacitance value, is the programmable capacitor array resolution, It is the control code corresponding to the capacitance adjustment amount of the programmable capacitor array.

[0021] In a preferred embodiment, the real-time response layer collects the voltage waveform of the power system and detects the transient current of the relay coil and transmits it to the dynamic coordination layer, including the following steps:

[0022] The real-time response layer forms a basic detection circuit by connecting a parallel non-polarized capacitor group and a series resistor. The basic detection circuit is connected to the relay coil loop to sense the transient current characteristics generated by the relay when it is turned on and off.

[0023] The Hall current sensor detects the current flowing through the ground loop or relay loop in the power system in real time, outputs an analog current signal, and then enters the ADS8688 analog-to-digital conversion chip to simultaneously collect the DC ground current, the AC waveform of the incoming current, and the current change of the relay coil at the switching moment.

[0024] During the triggering of the relay coil, the sampling circuit will detect the instantaneous current mutation; if the amplitude of the detected current mutation exceeds the set threshold, it is determined that the relay coil is in an energized or abnormally energized state.

[0025] In a preferred embodiment, the real-time response layer forms a basic detection circuit by connecting a non-polar capacitor group C1-C4 in parallel with resistors R2-R3 in series. The non-polar capacitor group C1-C4 is used to bypass high-frequency interference signals, and the resistors R2-R3 are used for current limiting and voltage division.

[0026] The Hall sensor is based on the principle of magnetic field induction. When AC intrusion, instantaneous induced current, or grounding anomaly occurs in the system, the Hall sensor obtains the corresponding current waveform.

[0027] In a preferred embodiment, the global monitoring layer obtains the safety threshold of the power system, communicates with the dynamic coordination layer via the CAN bus and sends a global parameter instruction, including the following steps:

[0028] The global monitoring layer is connected to the power system nodes, including the DC bus and AC power supply lines. By introducing a voltage sampling circuit, the voltage signal in the power system is introduced into the voltage / frequency detection chip;

[0029] The voltage / frequency detection chip is used to process the sampled analog voltage signal and calculate the effective value and AC frequency component of the analog voltage signal respectively;

[0030] The voltage / frequency detection chip determines whether the DC voltage is within the rated range and identifies whether there are abnormal AC frequency components in the AC signal. When the AC frequency exceeds the frequency threshold or the DC voltage is not within the rated range, it is immediately marked as a risk state.

[0031] In a preferred embodiment, after the voltage / frequency detection chip outputs an analog RMS voltage signal, it is buffered by an operational amplifier and interfaced with an ADC, and the value is read by a microcontroller. The microcontroller has built-in threshold judgment logic, which compares the collected voltage and frequency values ​​with built-in safety threshold parameters to determine whether it is in an abnormal state;

[0032] If the sampled data exceeds the set safety threshold, the microcontroller generates a corresponding global parameter instruction. The instruction content includes the current detected voltage and frequency values, the degree of deviation from the safety threshold, the recommended adjustment direction, the event timestamp, and the signal source identification.

[0033] The microcontroller encapsulates the global parameter instructions into CAN frames through the configured CAN bus interface and sends them to the dynamic coordination layer in the system.

[0034] In a preferred embodiment, a voltage / frequency detection chip is used to process the sampled analog voltage signal, and the effective value and AC frequency component of the analog voltage signal are calculated respectively, including the following steps:

[0035] The input analog voltage signal is connected to the voltage / frequency detection chip. The chip first rectifies and integrates the signal. The effective value calculation formula is: , where is a valid value, is the waveform period, is the function of input voltage changing with time, and , where is the peak value of the voltage, is the AC frequency, For time, is the initial phase angle;

[0036] The microcontroller uses the zero-crossing detection method combined with the timer to complete the frequency extraction, identify the zero-crossing point where the waveform changes from negative to positive or from positive to negative, and record the time difference between two consecutive rising or falling edges. , the period calculation expression is: , then the AC frequency calculation expression is: , where is the AC frequency, is the nth zero-crossing timestamp, The n+1th zero-crossing timestamp.

[0037] A power secondary equipment anti-malfunction protection circuit includes a sampling module, a detection module and a regulation module;

[0038] Sampling module: obtains the safety threshold of the power system through the voltage / frequency detection chip, outputs the digital signal to the microcontroller, communicates with the regulation module through the CAN bus and sends global parameter instructions;

[0039] Detection module: This module uses a Hall current sensor and ADC to collect the DC ground current and AC inrush voltage waveforms of the power system. A parallel non-polarized capacitor bank and a series resistor form a basic circuit to detect the transient current of the relay coil.

[0040] Regulation module: Receives the power system voltage waveform and relay coil transient current, uses digital potentiometers and programmable capacitor arrays, and dynamically adjusts resistance and capacitance parameters based on the safety thresholds sent by the global monitoring layer. It configures the FPGA to execute an adaptive algorithm to calculate the optimal resistance and capacitance combination, and then optimizes the filter frequency response.

[0041] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0042] This invention uses a global monitoring layer to obtain the power system's safety thresholds. The real-time response layer collects the power system's DC grounding current and AC inrush voltage waveforms, and detects transient currents in relay (TJR) coils. The dynamic coordination layer receives the power system voltage waveform and relay (TJR) coil transient currents. It then dynamically adjusts the resistance and capacitance parameters based on the safety thresholds transmitted by the global monitoring layer to optimize the filter frequency response. This protection method utilizes a programmable capacitor array and digital potentiometers. Using an FPGA to calculate the optimal resistance and capacitance combination, the filter parameters can be adaptively adjusted based on grid interference, improving the bypass capability of high-frequency signals and rapidly triggering the bypass mechanism to prevent relay malfunction and enhance power system reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments described in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0044] Figure 1 Flow chart of the method of the present invention.

[0045] Figure 2 This is a schematic diagram of the circuit module of the present invention.

[0046] Figure 3 This is a schematic diagram of the installation and wiring of the anti-tamper module of the present invention.

[0047] Figure 4 This is the circuit module mind map of the present invention. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0049] Example 1: Please refer to Figure 1 and Figure 3 As shown, the present embodiment provides a method for protecting secondary power equipment from malfunction, the method comprising the following steps:

[0050] The global monitoring layer obtains the safety threshold of the power system, communicates with the dynamic coordination layer through the CAN bus and sends global parameter instructions. The real-time response layer collects the voltage waveform of the power system, detects the transient current of the relay coil, and transmits it to the dynamic coordination layer. The dynamic coordination layer receives the power system voltage waveform and the transient current of the relay coil, and dynamically adjusts the resistance and capacitance parameters based on the safety threshold sent by the global monitoring layer to optimize the filtering frequency response.

[0051] The global monitoring layer obtains safety thresholds for the power system (e.g., a DC bus voltage range of ±10% of the rated value, or an alarm is triggered when the AC inrush frequency exceeds 50 Hz). The global monitoring layer integrates a voltage / frequency detection chip (e.g., the AD736RMS detection chip), outputs digital signals to a microcontroller (STM32 series), communicates with the dynamic coordination layer via the CAN bus, and sends global parameter commands. This includes the following steps:

[0052] The global monitoring layer connects to key nodes in the power system, including the DC bus and AC power lines. By introducing a voltage sampling circuit, the voltage signals in the power system (including the DC bus voltage and AC input signal) are accurately fed into the voltage / frequency detection chip.

[0053] Use a voltage / frequency detection chip (such as the AD736RMS chip) to process the sampled analog voltage signal and calculate its effective value (RMS) and AC frequency component respectively.

[0054] For DC voltage: the voltage / frequency detection chip determines whether it is within the range of ±10% of the rated value.

[0055] For AC signals: The voltage / frequency detection chip identifies whether there are abnormal AC frequency components. When the AC frequency exceeds 50Hz (such as power frequency interference or inductive crosstalk), it is immediately marked as a risk state.

[0056] The voltage / frequency detection chip outputs an analog RMS voltage signal, which is then buffered by an operational amplifier and connected to an ADC (analog-to-digital converter) interface. The value is then read by a microcontroller (such as the STM32 series). The microcontroller has built-in threshold judgment logic that compares the collected voltage and frequency values ​​with built-in safety threshold parameters to determine whether an abnormal state exists.

[0057] Once the sampled data is found to exceed the set safety threshold (such as the DC bus voltage is too high or too low, or the AC frequency is abnormal), the microcontroller (such as the STM32 series) will generate the corresponding global parameter instructions.

[0058] The command content includes: the currently detected voltage and frequency values, the degree of deviation from the safety threshold, the recommended adjustment direction (such as improving the RC bypass capability, strengthening filtering, etc.), as well as the event timestamp and signal source identification. The microcontroller encapsulates the above global parameter commands into CAN frames through the configured CAN bus interface and sends them to the dynamic coordination layer within the system.

[0059] If a serious deviation is detected (such as bus voltage exceeding ±15% or AC frequency exceeding the limit for several seconds), a retransmission mechanism is added to ensure the reliability of information transmission.

[0060] The voltage / frequency detection chip is used to process the sampled analog voltage signal and calculate the effective value and AC frequency component of the analog voltage signal, specifically:

[0061] The input analog voltage signal is connected to the voltage / frequency detection chip. The chip first rectifies and integrates the signal. Taking AD736 as an example, its output voltage is proportional to the true RMS value of the input signal. The RMS calculation formula is as follows: , where is a valid value, is the waveform period (for example, when AC is 50Hz, T=20ms), is the function of input voltage changing with time, and , where is the peak value (maximum amplitude) of the voltage, is the AC frequency (unit: Hz, domestic power grid is usually 50Hz), is the time (unit: seconds), is the initial phase angle (unit: radian, determines the starting point of the waveform).

[0062] The voltage / frequency detection chip itself may not output the frequency directly, so it can be assisted by the microcontroller to perform auxiliary calculations, using the zero-crossing detection method combined with the timer to complete the frequency extraction, identify the zero-crossing point where the waveform changes from negative to positive or from positive to negative, and record the time difference between two consecutive rising or falling edges. , the period calculation expression is: , then the AC frequency calculation expression is: , where is the AC frequency (Hz), is the waveform period (seconds), is the nth zero-crossing timestamp, The n+1th zero-crossing timestamp.

[0063] In this application, the AD736 chip is used to output the RMS analog voltage signal of the input waveform in real time. The operational amplifier is used to buffer and stabilize the signal to prevent voltage drop. The STM32 ADC is used to sample the AD736 output analog voltage signal to obtain the RMS value. The STM32 timer + GPIO is used to detect the zero crossing point of the voltage signal and calculate the frequency.

[0064] After the voltage / frequency detection chip outputs an analog RMS voltage signal, it is buffered by an operational amplifier and interfaced with an ADC. The microcontroller then reads the value. The microcontroller has built-in threshold judgment logic that compares the collected voltage and frequency values ​​with the built-in safety threshold parameters to determine whether it is in an abnormal state. If the sampled data exceeds the set safety threshold, the microcontroller generates a corresponding global parameter instruction. The instruction content includes the current detected voltage and frequency values, the degree of deviation from the safety threshold, the recommended adjustment direction, and the event timestamp and signal source identification. Specifically:

[0065] Connect the analog RMS voltage signal output by the voltage / frequency detection chip (such as AD736) to the input of a precision operational amplifier (such as OPA2333) to construct a unity-gain follower for impedance matching and signal buffering. The output of the operational amplifier is connected to the built-in ADC channel of a microcontroller (such as STM32) to ensure smooth signal input without voltage drop interference. If the system integrates a frequency measurement circuit (such as zero-crossing detection through an STM32 timer), the frequency signal is also synchronously input into the microcontroller logic module.

[0066] The microcontroller periodically triggers the ADC to sample and convert the buffered analog voltage signal to generate numerical RMS voltage data. If the zero-crossing frequency measurement method is used, the STM32 timer records the time interval between adjacent rising / falling edges to obtain the current AC frequency.

[0067] The microcontroller stores a set of safety threshold parameters, such as the ±10% range of the DC bus rated voltage; the AC inrush frequency threshold (e.g., >50Hz triggers an alarm); and the voltage / frequency abnormal drift tolerance. The currently acquired voltage RMS value and frequency value are compared with the corresponding safety thresholds to determine whether they are in an abnormal state or in a critical deviation range. If any parameter (voltage or frequency) exceeds the safety threshold range or is in a critical drift state, the microcontroller automatically triggers the exception handling logic. The generated global parameter instruction should contain the fields shown in Table 1:

[0068] Table 1

[0069]

[0070] The above information is organized into a structured data packet (struct or JSON format can be used) and prepared to be sent to the dynamic coordination layer via the CAN bus. The formatted global parameter instructions are sent to the bus through the microcontroller's built-in CAN controller for the dynamic coordination layer to use for RC parameter adjustment and fault response logic processing.

[0071] The real-time response layer uses a Hall-effect current sensor (ACS712) and a high-speed ADC (ADS8688) to collect the DC ground current and AC inrush voltage waveforms of the power system. A parallel non-polarized capacitor bank (C1-C4) and series resistors (R2-R3) form a basic circuit to detect transient current in the relay (TJR) coil (e.g., >5mA triggers bypass). The circuit includes the following steps:

[0072] The real-time response layer forms a basic detection circuit by connecting a parallel non-polarized capacitor group (C1-C4) and a series resistor (R2-R3). The non-polarized capacitor group C1-C4 is responsible for bypassing high-frequency interference signals and improving voltage signal stability. Resistors R2-R3 are used for current limiting and voltage division to ensure the input safety of the subsequent sampling circuit. This circuit is connected to the relay (TJR) coil loop and can sense the transient current characteristics generated at the moment of its on and off.

[0073] The real-time response layer uses the ACS712 Hall-effect current sensor to detect the current flowing through the ground loop or relay loop in the power system in real time. Based on the principle of magnetic field induction, the Hall-effect sensor has the characteristics of isolated detection, fast response, and sensitivity to both DC and AC. When the system experiences AC inrush, transient induced current, or grounding anomalies, the Hall-effect sensor can accurately obtain the corresponding current waveform.

[0074] After the Hall current sensor outputs the analog current signal, it enters the ADS8688 high-speed analog-to-digital conversion chip. This chip supports multi-channel synchronous sampling, high precision (16-bit), and a wide dynamic input range, making it suitable for capturing millisecond or even microsecond current waveform details.

[0075] The system simultaneously collects: DC ground current (indicating abnormal discharge or insulation degradation); incoming AC waveform (to determine whether there is interference signal above 50Hz); and current changes in the relay (TJR) coil at the moment of switching (to determine whether it is operating stably or experiencing jitter).

[0076] During the triggering of the relay coil, the sampling circuit will detect the instantaneous current mutation; if the amplitude of the detected current mutation exceeds the set threshold (such as 5mA), the system will consider that the relay coil is in an energized or abnormally energized state; this signal will be recorded in real time and used as one of the criteria for the "bypass trigger" event.

[0077] All waveform data collected by the ADC is received and analyzed by a microcontroller (such as STM32) or FPGA (such as Spartan-6);

[0078] The system analyzes the following information within a millisecond time window: whether the current waveform contains high-frequency components above 50Hz, whether there is power frequency coupling interference, whether the ground current is continuously abnormal, and whether the relay current exceeds the set threshold.

[0079] Once a risky behavior is detected (such as ground leakage, voltage inrush, or relay mis-engagement), the system immediately generates an event identifier and related waveform data. This data is sent to the dynamic coordination layer via an internal communication protocol (such as SPI or CAN bus), which further determines whether bypass protection is required, adjusts resistance and capacitance parameters, or reports a system fault.

[0080] During the relay coil triggering period, the sampling circuit will detect the instantaneous current mutation; if the detected current mutation amplitude exceeds the set threshold, it is determined that the relay coil is in the excitation or abnormal excitation state, specifically:

[0081] The current mutation is calculated using the difference method, and the expression is: , where is the current mutation amplitude at the current moment, is the current value sampled at the current moment, is the current value at the previous moment, is the time difference between two samples.

[0082] If the current mutation amplitude is greater than the mutation current judgment threshold (such as 5mA or calibrated by experiments), it is determined to be an excitation / abnormal excitation state.

[0083] The dynamic coordination layer receives the power system voltage waveform and the transient current of the relay (TJR) coil. It dynamically adjusts the resistance and capacitance parameters based on the safety thresholds sent by the global monitoring layer to optimize the filter frequency response (for example, enhancing the capacitor bypass capability for high-frequency interference). The dynamic coordination layer uses a digital potentiometer (AD5272) and a programmable capacitor array (PE64909) to dynamically adjust the resistance and capacitance parameters. It configures an FPGA (Xilinx-Spartan-6) to execute an adaptive algorithm and calculate the optimal resistance and capacitance combination. The following steps are included:

[0084] The dynamic coordination layer continuously receives signal data from the real-time response layer through a communication interface (such as the CAN bus or SPI bus), including: the current DC or AC voltage waveform; the AC inrush frequency characteristics; the transient current waveform of the relay (TJR) coil; all data has high time resolution and meets millisecond-level real-time requirements.

[0085] The "safety threshold instruction packet" sent by the global monitoring layer through the CAN bus contains the following core information: safe voltage range; AC inrush judgment criteria; transient current threshold allowed by the relay; recommended filtering direction (such as: suppressing high frequency, enhancing bypass, limiting adjustment, etc.).

[0086] The FPGA in the dynamic coordination layer is activated as the core computing device. An adaptive resistance-capacitance algorithm is loaded internally and performs the following analysis based on the collected actual voltage waveform spectrum characteristics and transient current amplitude, time width, and other parameters:

[0087] Determine the current interference type (such as high-frequency spikes, low-frequency coupling, or transient fluctuations); retrieve the preset interference model and compare it with the frequency range of the current interference; calculate the resistance-capacitance time constant (RC value) required for the optimal filter response range; and output the corresponding resistance and capacitance adjustment values ​​to form the target response curve (such as low-pass or band-stop characteristics).

[0088] The FPGA sends I²C commands to a digital potentiometer (AD5272) to adjust its internal resistance setting. The digital potentiometer (AD5272) has high precision and fast response, allowing precise resistance control (for example, from hundreds of ohms to thousands of ohms) under varying interference conditions. This adjustment directly affects the time constant of the RC filter loop, thereby changing its responsiveness to signals of a specific frequency.

[0089] The FPGA sends control commands to the PE64909 to select the appropriate capacitor combination (the chip contains multiple switchable capacitor elements). This allows for fine-tuning and graded combination of capacitor capacity, enhancing the circuit's response variability at different frequencies. When high-frequency interference occurs, the system automatically selects a larger capacitor for bypass absorption. If low-frequency interference is detected, the capacitor is reduced to avoid inadvertent suppression of normal signals.

[0090] The dynamically adjusted RC network acts on the front end of the detection circuit or the relay control loop to achieve: enhanced high-frequency interference bypass capability; transient spike voltage suppression; and retention of normal control signal passage. The system dynamically adjusts to adapt to different electromagnetic environments and system disturbance states in real time to avoid false triggering of relay protection actions.

[0091] The FPGA transmits information such as the currently used RC parameters and filter response effects (such as interference attenuation ratio and relay excitation waveform changes) back to the upper layer; the global monitoring layer updates the security policy accordingly, and the real-time response layer can also adjust the next round of sampling strategies and trigger judgment criteria accordingly, realizing multi-layer linkage and closed-loop optimization.

[0092] After determining the current interference type, the preset interference model is retrieved, the frequency range of the current interference is compared, the resistance and capacitance time constants required for the optimal filter response range are calculated, and the corresponding resistance and capacitance adjustment values ​​are output to form the target response curve, specifically:

[0093] The type of interference is determined based on the sampled current or voltage waveform. Interference models can be classified based on frequency range, for example:

[0094] High-frequency interference: The frequency is greater than 1kHz, usually caused by switching power supplies, transient pulses, etc.

[0095] Low-frequency interference: The frequency is between 50Hz and 200Hz, which may be caused by periodic fluctuations of power equipment.

[0096] Broadband noise: The frequency range is wide and there is no obvious pattern.

[0097] The frequency components of the current signal are extracted by Fourier transform (FFT) (this step belongs to the prior art and will not be described in detail in this application) to determine its frequency range.

[0098] To optimize the filter response, calculate the required RC time constant to determine the appropriate resistor and capacitor combination, the RC filter time constant The relationship with resistance R and capacitance C is: , select the cutoff frequency as the upper limit of the interference frequency, calculate the corresponding time constant, and the cutoff frequency calculation expression is: , then the calculation expressions of resistance and capacitance are: , where The cutoff frequency is the upper limit of the interference frequency. The high-frequency portion of the interference in the preset model is usually selected. The resistance and capacitance values ​​are adjusted as needed using a digital potentiometer (such as the AD5272) and a programmable capacitor array (such as the PE64909). The corresponding adjustment amount is calculated: the resistance adjustment is calculated by subtracting the pre-adjustment resistance value from the adjusted resistance value, and the capacitance adjustment is calculated by subtracting the pre-adjustment capacitance value from the adjusted capacitance value. Optimizing the target response curve is typically achieved by reducing interference within the frequency range while preserving system signal integrity. This can be achieved through gain control and filter bandwidth adjustment.

[0099] in:

[0100] Resistor and capacitor values ​​are adjusted using digital potentiometers (such as the AD5272) and programmable capacitor arrays (such as the PE64909). The system calculates the appropriate adjustment based on the desired resistor and capacitor values. In this system, the adjusted resistor and capacitor values ​​are typically set based on design objectives (such as the filter's cutoff frequency and RC time constant). Assume that the required resistor and capacitor values ​​have been determined for the system (either by querying the data block or manually entering them).

[0101] The resistance adjustment is obtained by subtracting the current resistance from the target resistance. Digital potentiometers (such as the AD5272) use a digital input signal to adjust their resistance. The AD5272 is a 256-level digital potentiometer whose resistance value is determined by a digital code (typically 8 or 10 bits).

[0102] Assumption: The total resistance range of the digital potentiometer is For example, from 10 kΩ to 100 kΩ, the resolution of the digital potentiometer is 256 levels, which means N=256. To adjust the resistance to the required value, calculate the corresponding digital code. The expression is: , where is the required resistance value, is the digital potentiometer resolution, It is the control code corresponding to the resistance adjustment amount of the digital potentiometer.

[0103] The capacitance adjustment amount is obtained by subtracting the current capacitance from the target capacitance. A programmable capacitor array (such as PE64909) can adjust its output capacitance value by controlling specific switches according to the required capacitance value. Assume that the capacitance range of the capacitor array is , and its capacitance can be adjusted by a set of digital control signals. To adjust the capacitance to the required value, calculate the corresponding digital code, the expression is: , where is the required capacitance value, is the programmable capacitor array resolution, It is the control code corresponding to the capacitance adjustment amount of the programmable capacitor array.

[0104] Optimizing the target response curve, especially when reducing interference within the frequency range and maintaining system signal integrity, can be achieved through gain control and filter bandwidth adjustment. The following are the steps to achieve this goal:

[0105] System signal frequency range: This is typically the frequency range we want to preserve. For example, possible system signal frequencies are between 0 Hz and 50 Hz.

[0106] Interference signal frequency range: The frequency range in which interference signals may exist. Interference signals usually appear in a range higher than the system signal frequency, such as 50 Hz to 500 Hz, or even higher.

[0107] By sampling the signal and performing spectrum analysis (e.g., Fast Fourier Transform, FFT), the frequency components of the signal, especially the presence and amplitude of interfering signals, can be analyzed and determined. For example, the following steps can be used:

[0108] Sampling signal: Sample the input signal (which may contain interference components) and perform a fast Fourier transform (FFT) on the signal to obtain the signal spectrum.

[0109] Identify interference frequency components: Based on the spectrum analysis results, identify the frequency range of the interference signal.

[0110] Once the interference frequency and signal frequency are determined, the next step is to design a filter. The main goal is to suppress the interference signal while preserving the system signal. Common methods include low-pass filters, high-pass filters, band-pass filters, or band-stop filters.

[0111] Low-pass filter: used to suppress interference signals above the set cutoff frequency.

[0112] High-pass filter: used to suppress interference signals below the set frequency.

[0113] Bandpass filter: Only allows signals within a certain frequency range to pass through, and is often used in scenarios with specific frequency bandwidth requirements.

[0114] Band-stop filter: suppresses interference signals within a specific frequency band.

[0115] Select filter type: Select the appropriate filter type (low-pass, high-pass, band-pass, or band-stop) according to actual needs.

[0116] Determine the filter's cutoff frequency, typically set to the upper limit of the interfering signal's frequency range. For example, if the interfering signal's frequency range is 50 Hz to 200 Hz, the filter's cutoff frequency might be set at 50 Hz. The filter's bandwidth (BW) controls the filter's selectivity; a wider bandwidth allows a wider range of signal frequencies to pass.

[0117] Gain control is typically used to adjust the signal amplitude to ensure that the signal is not distorted or saturated due to excessive gain, while also preventing the signal from being weakened due to too low a gain. Gain control generally includes the following:

[0118] Adjust the gain coefficient: According to the amplitude of the filter output signal, dynamically adjust the gain coefficient G to control the amplitude of the output signal and keep it in a stable range.

[0119] Gain range selection: The gain coefficient can be adjusted within a preset range. For example, if the amplitude of the filtered signal is too small, the gain coefficient will be increased. If the signal is too large, the gain will be reduced. The gain calculation formula is: , where is the gain coefficient, is the output signal after gain control, For the input signal, optimize the filter bandwidth and gain settings based on the frequency range of the interference signal and system requirements to achieve the best filtering effect: appropriately adjust the filter bandwidth to ensure effective suppression of interference signals while ensuring that the integrity of the system signal is not compromised. For bandpass filters, the bandwidth should cover the frequency range of the system signal and be able to effectively attenuate interference frequencies. For low-pass or high-pass filters, the bandwidth should ensure that the signal frequency range is passed and the interference signal is effectively filtered out. The system output signal can be monitored in real time and the filter response can be adjusted to ensure the optimal filtering effect. The filter performance can be verified through simulation or actual testing, and the filter parameters can be further fine-tuned based on actual conditions.

[0120] Selecting a preset interference model that matches the interference frequency is a key step in power system interference suppression. Based on the measured frequency content, the system can determine the type of interference source and select the most suitable preset interference model for optimization. The following example illustrates how to select and optimize an interference model based on the measured frequency content:

[0121] Assume that the system has successfully measured and analyzed the frequency components of the power system using a voltage / frequency detection chip (such as the AD736), obtaining spectrum information within a certain time period. The measured frequency components may show different frequency peaks. For example:

[0122] Low-frequency interference: Frequency components are between 0 Hz and 50 Hz (for example, 50 Hz power frequency fluctuations, low-frequency noise, etc.).

[0123] High-frequency interference: The frequency component is between 50 Hz and 200 Hz (for example, high-frequency interference introduced by switching power supplies, high-frequency interference generated by industrial control equipment, etc.).

[0124] Ultra-high frequency interference: frequency components above 200 Hz (for example, high-frequency noise caused by electromagnetic compatibility issues).

[0125] The system selects a preset interference model that matches the interference frequency based on the measured frequency components. Common interference types and their corresponding models may be as follows:

[0126] 1) Power frequency interference (50 Hz interference):

[0127] Frequency range: 50 Hz (or 60 Hz). Preset model: Uses a power frequency filter model, such as a bandpass filter or lowpass filter. By adjusting the capacitor or resistor, the 50 Hz filter effect is enhanced to suppress interference from the power lines.

[0128] 2) High-frequency noise generated by switching power supply:

[0129] Frequency range: 50 Hz to 200 Hz (or higher).

[0130] Preset model: High-pass filter model or Band-stop filter model.

[0131] Optimization direction: According to the spectrum of high-frequency interference, adjust the parameters of the capacitor array and digital potentiometer, and optimize the bandwidth of the filter so that it can more effectively suppress the interference generated by the switching power supply.

[0132] 3) Electromagnetic radiation interference:

[0133] Frequency range: Above 200 Hz, possibly approaching the RF (radio frequency) range.

[0134] Preset models: RF filter or low-pass / high-pass filter combination.

[0135] Optimization direction: Through programmable capacitor arrays and digital potentiometers, special optimization is performed for high-frequency interference to ensure that the system can shield or filter out high-frequency electromagnetic radiation.

[0136] Based on the measured interference frequency range, the system selects the most appropriate interference model and optimizes it to achieve the best filtering effect. Assuming that the measured interference frequency components are mainly concentrated around 100 Hz, the system will select the high-frequency noise model generated by the switching power supply.

[0137] The optimization steps include selecting an appropriate filter type (such as a bandstop filter) and adjusting the capacitor and resistor values ​​using a capacitor array and digital potentiometer to ensure sufficient filter attenuation around 100 Hz to effectively suppress noise. Based on the results of spectrum analysis, the resistor and capacitor parameters are dynamically adjusted to better match the target frequency. For example, if the main peak of high-frequency noise occurs at 100 Hz, the filter might use specific resistor and capacitor values ​​to form a bandstop filter specifically designed to suppress frequencies around 100 Hz. By dynamically controlling the resistor and capacitor network, the filter's frequency response is adjusted to achieve optimal attenuation within the target frequency range.

[0138] For example, suppose voltage measurement data in a power system shows a strong interference signal near 60 Hz. The system can identify this as power frequency interference and select a preset power frequency filtering model. The system then optimizes a low-pass filter by adjusting the programmable capacitor array and digital potentiometer to effectively suppress the 60 Hz power frequency interference. By adjusting the resistor and capacitor values, the filter can be tuned to specifically filter the 60 Hz power frequency wave, effectively reducing the impact of power frequency interference.

[0139] The FPGA sends instructions to the digital potentiometer to adjust the internal resistance setting of the digital potentiometer, and sends control commands to the programmable capacitor array. The programmable capacitor array selects the capacitor combination based on the control commands. Specifically:

[0140] 1. FPGA communicates with the digital potentiometer;

[0141] The FPGA calculates the target resistance value based on system requirements (such as filter parameters and interference frequency) and sets the value through the digital potentiometer control interface. Typically, digital potentiometers such as the AD5272 use an SPI interface to communicate with the FPGA.

[0142] The FPGA converts the control instructions into numerical data of the SPI protocol and sends it to the digital potentiometer through the SPI interface to adjust its internal resistance value. The digital potentiometer adjusts its resistance according to the received value.

[0143] PI control signal:

[0144] SCK: clock signal;

[0145] MOSI: Master Output Slave Input (data transmission from FPGA to digital potentiometer);

[0146] CS: Chip select signal, determines the communication between the digital potentiometer and other peripherals;

[0147] MISO: Master Input Slave Output (data fed back to the FPGA by the digital potentiometer).

[0148] After receiving the new resistance setting, the digital potentiometer may return an acknowledgment signal (such as ACK) or the updated resistance value to the FPGA. The FPGA can read this feedback information via SPI to confirm whether the resistance adjustment was successful.

[0149] 2. FPGA communicates with the programmable capacitor array;

[0150] Similar to resistor value adjustment, the FPGA calculates the target capacitance value and determines the required capacitor combination. Programmable capacitor arrays, such as the PE64909, are adjusted using similar control signals and offer a variety of capacitor value combinations. The FPGA calculates the optimal capacitor configuration. The capacitor array may select a capacitor combination based on a programmed address or code value. Typically, the control interface for programmable capacitor arrays also uses SPI or other digital communication protocols. Capacitor combination selection: By controlling specific capacitor selection registers, the FPGA selects the appropriate capacitor combination.

[0151] The FPGA sends control commands to the programmable capacitor array via a control interface (such as SPI) to select the desired capacitance value. The command includes the selected capacitor register address and the corresponding capacitance value. The control signal sent by the FPGA may be as follows:

[0152] SPI control signals:

[0153] SCK: clock signal;

[0154] MOSI: data output (command from FPGA to capacitor array);

[0155] CS: chip select signal (select the corresponding capacitor array device);

[0156] MISO: Feedback signal (capacitor selection confirmation information if there is one).

[0157] After receiving the control command, the programmable capacitor array selects the appropriate capacitor based on the set value and feeds the result back to the FPGA. If necessary, the FPGA can read the capacitor selection status to confirm whether the adjustment was successful.

[0158] The dynamically adjusted RC network acts on the front end of the detection circuit or the relay control loop. The FPGA transmits the currently used RC time constant and filter response effect information back to the global monitoring layer and the real-time response layer. The global monitoring layer updates the security policy based on the RC time constant and filter response effect. The real-time response layer adjusts the next round of sampling strategy and trigger judgment criteria based on the RC time constant and filter response effect. Specifically:

[0159] The filter's response depends primarily on the adjustment of the RC network. The FPGA calculates the filter's response indicators (such as the filter's bandwidth and attenuation) based on the RC time constant and the current system's interference characteristics. The filter's response can be calculated using the following frequency response function or similar methods: , where is the frequency response of the filter, is the angular frequency of the signal, is the signal frequency, is the current RC time constant, Is an imaginary unit.

[0160] The FPGA transmits the calculated current RC time constants and filter response results back to the global monitoring layer and real-time response layer. This feedback process is usually completed through a communication interface (such as CAN bus, SPI, etc.).

[0161] The global monitoring layer receives information about the current RC time constants and filter response from the FPGA and analyzes and evaluates it. It compares this information with the current security thresholds to determine whether security policies need to be updated.

[0162] For example, the global monitoring layer may evaluate the following: whether the current RC network can effectively suppress external interference, whether the filter's frequency response is sufficient to meet the system's safety requirements, and whether further adjustments to safety thresholds or gain settings are needed.

[0163] If the global monitoring layer identifies areas that require optimization or modification, the system will adjust safety policies based on the actual situation. For example, they might adjust voltage or frequency safety thresholds, update alarm triggering conditions (such as increasing voltage fluctuation tolerance), or optimize interference suppression strategies based on filter responses. The global monitoring layer will notify other layers, such as the real-time response layer and the dynamic coordination layer, of these updated global parameter instructions, ensuring timely and accurate system responses.

[0164] After receiving the RC time constant and filter response information from the FPGA, the real-time response layer first evaluates the effectiveness of the current sampling strategy. If the current sampling strategy does not adapt well to the newly adjusted RC network or filter response, it needs to be adjusted.

[0165] The real-time response layer can adjust the sampling strategy based on the current RC time constant and filtering effect, including:

[0166] Sampling frequency: Based on the bandwidth of the filter response, the sampling frequency is dynamically adjusted to ensure that sufficient signal changes can be captured.

[0167] Sampling accuracy: Based on the interference characteristics and the effectiveness of the filter, the sampling accuracy and quantization level are adjusted to ensure that key changes in the signal are accurately captured.

[0168] Sampling timing: The real-time response layer can optimize sampling timing based on the response effect of the adjusted RC network. For example, it can avoid periods of high system interference and select the most suitable sampling window.

[0169] Under the influence of the new RC network, the real-time response layer also needs to adjust its trigger judgment criteria to ensure that the system can correctly identify interference events based on the latest filtering effects. Adjusting the trigger criteria may involve: adjusting the threshold for voltage or current sudden changes, optimizing the trigger delay or response speed based on the filtering effect, and adjusting the relay coil trigger conditions based on the new capacitor or resistor values. The real-time response layer ensures that the system can respond to various interferences in real time and maintains stable operation by flexibly adjusting the sampling strategy and trigger judgment criteria.

[0170] The PGA, as the core processing unit of the dynamic coordination layer, is tasked with: processing sampled waveform data in real time; determining interference characteristics based on safety thresholds; calculating the optimal RC parameter combination; and controlling the digital potentiometer and capacitor array to achieve regulation. The FPGA modular algorithm framework is shown in Table 2:

[0171] Table 2

[0172]

[0173] The schematic flow of FPGA operation logic is as follows:

[0174] [Voltage / current sampling data]→

[0175] [Spectrum Analysis / Feature Extraction]→

[0176] [Interference Identification (High Frequency / Low Frequency / Surge)] →

[0177] [Look up the table + calculate the target RC value] →

[0178] [Control Byte Generation] →

[0179] [Output to AD5272 / PE64909] →

[0180] [Recovery verification of filtering effect].

[0181] Some of the core algorithms used in the FPGA include: Fast Fourier Transform (FFT) for spectrum extraction; transfer function calculation formula for the RC low-pass filter; and adaptive iterative method for trying different RC combinations multiple times to fit the target filter shape.

[0182] In this application, the digital potentiometer / capacitor array control instruction structure includes the digital potentiometer AD5272 (I²C control) and the programmable capacitor array PE64909 (SPI control);

[0183] 1) AD5272 digital potentiometer (I²C controlled);

[0184] Address range: 7-bit I²C address (default: 0101xxx, based on AD0 / AD1 pin configuration)

[0185] The number of adjustable resistance steps: 1024 steps (10-bit control resolution)

[0186] The control command structure is shown in Table 3:

[0187] Table 3

[0188]

[0189] The resistance conversion formula is: Rout = (RDAC value / 1024) × Rtotal value (typically 10kΩ or 20kΩ).

[0190] 2) Programmable capacitor array PE64909 (SPI control);

[0191] Control method: Write a 6-bit control word via SPI to control the on / off state of the 8 internal capacitor units; each bit controls one capacitor unit, and the typical value of the capacitor unit ranges from 0.6pF to 7pF. A high level on each bit indicates enablement. The control command structure is shown in Table 4:

[0192] Table 4

[0193]

[0194] Total capacitance conversion method: Ctotal = C1×b1+C2×b2+C3×b3+...+C6×b6, where bi represents each bit control signal (0 / 1). The RC combination instruction generation example is as follows:

[0195] Assume the target is: resistor value = 5kΩ (AD5272), capacitor value = 4.2pF (PE64909);

[0196] AD5272 control instructions: Calculation steps: 5kΩ / 10kΩ×1024≈512, Command Byte: 00000000, Data-MSB: 00000010, Data-LSB: 00000000.

[0197] PE64909: Enable C1=0.6pF, C3=1.2pF, C5=2.4pF → total 4.2pF, control code: 101010.

[0198] This application uses a global monitoring layer to obtain the power system's safety thresholds. The real-time response layer collects the power system's DC grounding current and AC inrush voltage waveforms, and detects transient currents in relay (TJR) coils. The dynamic coordination layer receives the power system voltage waveform and transient currents in the relay (TJR) coils. It then dynamically adjusts the resistance and capacitance parameters based on the safety thresholds sent by the global monitoring layer to optimize the filter frequency response. This protection method uses a programmable capacitor array and digital potentiometers, and uses an FPGA to calculate the optimal resistance and capacitance combination. This allows the filter parameters to be adaptively adjusted based on grid interference, improving the bypass capability of high-frequency signals and rapidly triggering the bypass mechanism to prevent relay misoperation and improve power system reliability.

[0199] The beneficial effects of this application are:

[0200] 1. When AC flows into the DC system, the AC power flowing through the tripping relay can be bypassed. When DC grounding occurs, the anti-malfunction module can bypass the transient current of the distributed capacitance to prevent the relevant relays (or optocouplers) from malfunctioning, thereby preventing the switch from malfunctioning when AC flows into the DC system and the DC system is grounded.

[0201] 2. It can be directly installed at both ends of the trip relay (TJQ, TJR, TBJ and optocoupler switch, etc.), and the installation does not require the switch to be powered off, making the installation simple and convenient.

[0202] 3. When AC leaks into the DC system or DC grounding occurs, the circuit that starts protection through the long cable and directly trips through the long cable will not malfunction, which can avoid accidents and improve the safety and reliability of the relay protection system.

[0203] Therefore, in summary, by adding appropriate resistor and capacitor elements at both ends of the relay to form the anti-maloperation module, it is possible to effectively prevent the switch from maloperating when AC enters the DC system and the DC system is grounded, thereby achieving the effect of preventing the switch from maloperating when AC enters the DC system and the DC system is grounded.

[0204] Example 2: Please refer to Figure 2 and Figure 4As shown, the power secondary equipment anti-malfunction protection circuit described in this embodiment includes a sampling module, a detection module and an adjustment module;

[0205] Sampling module: This module uses a voltage / frequency detection chip (such as the AD736RMS detection chip) to obtain safety thresholds for the power system (e.g., a DC bus voltage range of ±10% of the rated value, or an alarm triggered when the AC inrush frequency exceeds 50 Hz). It then outputs digital signals to a microcontroller (STM32 series), which then communicates with the regulation module via the CAN bus and sends global parameter commands.

[0206] The detection module uses a Hall current sensor (ACS712) and a high-speed ADC (ADS8688) to collect the DC ground current and AC inrush voltage waveforms of the power system. A parallel non-polarized capacitor bank (C1-C4) and series resistors (R2-R3) form a basic circuit for detecting transient current in the relay (TJR) coil (e.g., >5mA triggers bypass). The power system voltage waveform and relay (TJR) coil transient current are transmitted to the regulation module.

[0207] The regulation module receives the power system voltage waveform and the transient current of the relay (TJR) coil. It uses a digital potentiometer (AD5272) and a programmable capacitor array (PE64909) to dynamically adjust the resistance and capacitance parameters based on the safety thresholds sent by the global monitoring layer. It configures an FPGA (Xilinx-Spartan-6) to execute an adaptive algorithm, calculates the optimal resistance and capacitance combination, and optimizes the filter frequency response (for example, enhancing the capacitor bypass capability for high-frequency interference).

[0208] The following is the electrical connection relationship between the various electronic components in the power secondary equipment anti-malfunction protection circuit:

[0209] Sampling module: The voltage / frequency detection chip (AD736) is connected to the power system bus to collect voltage / frequency data. The output of the voltage / frequency detection chip (AD736) is connected to the ADC input of the microcontroller (STM32 series) for data processing. The microcontroller (STM32 series) sends global parameter instructions to the regulation module through the CAN bus.

[0210] Detection module: The input end of the Hall current sensor (ACS712) is connected in series to the DC bus of the power system to detect ground current. The output end of the Hall current sensor (ACS712) is connected to the high-speed ADC (ADS8688) to achieve high-precision analog signal acquisition. The ADC (ADS8688) is connected to the SPI interface of the microcontroller (STM32 series) to transmit data to the microcontroller. The non-polarized capacitor group (C1-C4) and the series resistor (R2-R3) are connected in parallel to form the relay (TJR) coil detection circuit. The Hall current sensor (ACS712) is connected to the relay (TJR) coil to detect transient current. The data of the detection module is transmitted to the regulation module via SPI for further analysis and adjustment.

[0211] Regulation module: The microcontroller (STM32 series) receives safety thresholds from the global monitoring layer via the CAN bus. The power system voltage waveform and relay coil transient current signal are input into the FPGA (Xilinx-Spartan-6), where an adaptive algorithm is executed. The output of the FPGA (Xilinx-Spartan-6) is connected to a digital potentiometer (AD5272) for adjusting resistance parameters. The output of the FPGA is also connected to a programmable capacitor array (PE64909) for adjusting capacitance parameters. The adjusted resistance and capacitance parameters act on the power system filter circuit to optimize frequency response and improve capacitor bypass capability.

[0212] The circuit obtains the power system safety threshold through the sampling module, the detection module collects key current / voltage data, and the regulation module calculates and dynamically adjusts the resistance and capacitance parameters based on the FPGA to achieve optimized bypass of high-frequency interference and improve the reliability of relay protection.

[0213] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0214] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Obviously, many modifications and variations are possible based on the contents of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for preventing malfunction of power secondary equipment, characterized by: The protection method comprises the following steps: The global monitoring layer obtains the safety threshold of the power system, communicates with the dynamic coordination layer via the CAN bus, and sends global parameter instructions. The instructions include the current detected voltage and frequency values, the degree of deviation from the safety threshold, the recommended adjustment direction, the event timestamp, and the signal source identifier. The real-time response layer collects the voltage waveform of the power system and detects the transient current of the relay coil before transmitting it to the dynamic coordination layer; The dynamic coordination layer receives the power system voltage waveform and the transient current of the relay coil, and dynamically adjusts the resistance and capacitance parameters based on the safety threshold sent by the global monitoring layer to optimize the filter frequency response. The process includes the following steps: The dynamic coordination layer continuously receives signal data from the real-time response layer through the communication interface. The signal data includes the current DC or AC voltage waveform, AC inrush frequency characteristics, and the transient current waveform of the relay coil. After determining the current interference type, the preset interference model is retrieved, the frequency range of the current interference is compared, the resistance and capacitance time constants required for the optimal filter response range are calculated, and the corresponding resistance and capacitance adjustment values ​​are output to form the target response curve; Send instructions to the digital potentiometer through the FPGA to adjust the internal resistance setting of the digital potentiometer, and send control commands to the programmable capacitor array. The programmable capacitor array selects the capacitor combination according to the control commands; The dynamically adjusted RC network acts on the front end of the detection circuit or the relay control loop. The FPGA transmits the currently used RC time constant and filter response effect information back to the global monitoring layer and the real-time response layer. The global monitoring layer updates the security policy based on the RC time constant and filter response effect. The real-time response layer adjusts the next round of sampling strategy and trigger judgment criteria based on the RC time constant and filter response effect.

2. A method for preventing malfunction of power secondary equipment according to claim 1, characterized in that: Calculate the RC time constant required for the optimal filter response range and output the corresponding resistance and capacitance adjustment values ​​to form the target response curve, specifically: Time constant of RC filter The relationship with resistance R and capacitance C is: , select the cutoff frequency as the upper limit of the interference frequency, calculate the corresponding time constant, and the cutoff frequency calculation expression is: , then the calculation expressions of resistance and capacitance are: , where The cut-off frequency is calculated by adjusting the resistance and capacitance values ​​as needed through the digital potentiometer and programmable capacitor array, and the target response curve is optimized through gain control and filter bandwidth adjustment.

3. The method for preventing malfunction of power secondary equipment according to claim 2, characterized in that: The digital potentiometer and the programmable capacitor array are used to adjust the resistance and capacitance values ​​as needed, and the corresponding adjustment amount is calculated, including the following steps: The resistance adjustment amount is obtained by subtracting the current resistance from the target resistance. Assume that the total resistance range of the digital potentiometer is , calculate the digital code corresponding to adjusting the resistance to the required value, the expression is: , where is the required resistance value, is the digital potentiometer resolution, It is the control code corresponding to the resistance adjustment amount of the digital potentiometer; The capacitance adjustment amount is obtained by subtracting the current capacitance from the target capacitance. Assume that the capacitance range of the programmable capacitor array is , calculate the digital code corresponding to adjusting the capacitance to the required value, the expression is: , where is the required capacitance value, is the programmable capacitor array resolution, It is the control code corresponding to the capacitance adjustment amount of the programmable capacitor array.

4. A method for preventing malfunction of power secondary equipment according to claim 3, characterized in that: The real-time response layer collects the voltage waveform of the power system and detects the transient current of the relay coil before transmitting it to the dynamic coordination layer. The following steps are included: The real-time response layer forms a basic detection circuit by connecting a parallel non-polarized capacitor group and a series resistor. The basic detection circuit is connected to the relay coil loop to sense the transient current characteristics generated by the relay when it is turned on and off. The Hall current sensor detects the current flowing through the ground loop or relay loop in the power system in real time, outputs an analog current signal, and then enters the ADS8688 analog-to-digital conversion chip to simultaneously collect the DC ground current, the AC waveform of the incoming current, and the current change of the relay coil at the switching moment. During the triggering of the relay coil, the sampling circuit will detect the instantaneous current mutation; if the amplitude of the detected current mutation exceeds the set threshold, it is determined that the relay coil is in an energized or abnormally energized state.

5. The method for preventing malfunction of power secondary equipment according to claim 4, characterized in that: The real-time response layer forms a basic detection circuit by connecting a non-polarized capacitor group C1-C4 in parallel with resistors R2-R3 in series. The non-polarized capacitor group C1-C4 is used to bypass high-frequency interference signals, and resistors R2-R3 are used for current limiting and voltage division. The Hall sensor is based on the principle of magnetic field induction. When AC intrusion, instantaneous induced current, or grounding anomaly occurs in the system, the Hall sensor obtains the corresponding current waveform.

6. A method for protecting secondary power equipment from malfunction according to claim 5, characterized in that: The global monitoring layer obtains the safety threshold of the power system, communicates with the dynamic coordination layer through the CAN bus and sends global parameter instructions, including the following steps: The global monitoring layer is connected to the power system nodes, including the DC bus and AC power supply lines. By introducing a voltage sampling circuit, the voltage signal in the power system is introduced into the voltage / frequency detection chip; The voltage / frequency detection chip is used to process the sampled analog voltage signal and calculate the effective value and AC frequency component of the analog voltage signal respectively; The voltage / frequency detection chip determines whether the DC voltage is within the rated range and identifies whether there are abnormal AC frequency components in the AC signal. When the AC frequency exceeds the frequency threshold or the DC voltage is not within the rated range, it is immediately marked as a risk state.

7. A method for preventing malfunction of power secondary equipment according to claim 6, characterized in that: After the voltage / frequency detection chip outputs the analog RMS voltage signal, it is buffered by the operational amplifier and interfaced with the ADC. The microcontroller reads the value. The microcontroller has built-in threshold judgment logic, which compares the collected voltage and frequency values ​​with the built-in safety threshold parameters to determine whether it is in an abnormal state. If the sampled data exceeds the set safety threshold, the microcontroller generates the corresponding global parameter instruction; The microcontroller encapsulates the global parameter instructions into CAN frames through the configured CAN bus interface and sends them to the dynamic coordination layer in the system.

8. A method for protecting secondary power equipment from malfunction according to claim 7, characterized in that: The sampled analog voltage signal is processed using a voltage / frequency detection chip to calculate the effective value and AC frequency component of the analog voltage signal, including the following steps: The input analog voltage signal is connected to the voltage / frequency detection chip. The chip first rectifies and integrates the signal. The effective value calculation formula is: , where is a valid value, is the waveform period, is the function of input voltage changing with time, and , where is the peak value of the voltage, is the AC frequency, For time, is the initial phase angle; The microcontroller uses the zero-crossing detection method combined with the timer to complete the frequency extraction, identify the zero-crossing point where the waveform changes from negative to positive or from positive to negative, and record the time difference between two consecutive rising or falling edges. , the period calculation expression is: , then the AC frequency calculation expression is: , where is the AC frequency, is the nth zero-crossing timestamp, The n+1th zero-crossing timestamp.

9. A power secondary equipment anti-malfunction protection circuit, used to implement the protection method according to any one of claims 1 to 8, characterized in that: It includes sampling module, detection module and adjustment module; Sampling module: obtains the safety threshold of the power system through the voltage / frequency detection chip, outputs the digital signal to the microcontroller, communicates with the regulation module through the CAN bus and sends global parameter instructions; Detection module: This module uses a Hall current sensor and ADC to collect the DC ground current and AC inrush voltage waveforms of the power system. A parallel non-polarized capacitor bank and a series resistor form a basic circuit to detect the transient current of the relay coil. Regulation module: Receives the power system voltage waveform and relay coil transient current, uses digital potentiometers and programmable capacitor arrays, and dynamically adjusts resistance and capacitance parameters based on the safety thresholds sent by the global monitoring layer. It configures the FPGA to execute an adaptive algorithm to calculate the optimal resistance and capacitance combination, and then optimizes the filter frequency response.

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