Oscillator-based pulse width detection circuit for preventing metastable state
By introducing orthogonal phase counting and logic judgment into the pulse width detection circuit, the error problem caused by metastable state is solved, and the reliability and accuracy of the circuit are improved.
Patent Information
- Application Number
- CN202510336860.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-08-12
AI Technical Summary
The existing pulse width detection circuit based on gated oscillator is prone to errors in metastable conditions, resulting in reduced circuit reliability.
A multi-phase gated oscillator, sampling path, counting path and error correction coding circuit containing interpolation circuit is used to locate the intervals that may occur in metastable state through orthogonal phase counting and logic judgment, and select the appropriate phase signal for counting to ensure that the counting path results are consistent with the sampling path results and avoid errors caused by metastable state.
It effectively avoids errors caused by metastable state, improves the reliability and accuracy of the circuit, and ensures the accuracy of pulse width detection.
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Figure CN120474524A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor integrated circuit, and more particularly to a pulse width detection circuit. Background Art
[0002] Pulse width detection circuits are widely used in scenarios such as high-speed ADCs (analog-to-digital converters) for time domain quantization, step measurement of delay lines, and digital filters.
[0003] Existing pulse-width detection circuits based on gate-controlled oscillators (GCOs) consist of a multiphase GCO with interpolation circuitry, a sampling path, a counting path, and an error-correction coding circuit. If the gate signal corresponding to a pulse causes the GCO output to enter a metastable state, conflicting results may occur between the subsequent counting and sampling paths. While this is a rare occurrence, it can lead to significant errors in the final pulse-width detection result, reducing circuit reliability.
[0004] See also Figure 1 The multi-phase gated oscillator including the interpolation circuit includes X cross-coupled delay units connected in cascade, each cross-coupled delay unit is used to generate an output signal after processing two input signals with a fixed delay. Generally speaking, X needs to be an even number. Figure 1 An example is given where X=4. The multi-phase gated oscillator including the interpolation circuit is controlled by both reset signal 1 and the pulse width signal to be measured. The pulse width signal to be measured and reset signal 1 cannot arrive at the same time. The standard operating timing of the multi-phase gated oscillator including the interpolation circuit is as follows.
[0005] (1) When a reset signal arrives, each output phase of the multi-phase gated oscillator including the interpolation circuit is reset to an initial state.
[0006] (2) Once the reset signal is turned off, each output phase of the multi-phase gated oscillator including the interpolation circuit remains in the initial state.
[0007] (3) When the pulse width signal to be measured arrives (high level), the multi-phase gated oscillator including the interpolation circuit starts to oscillate. The wider the pulse width signal to be measured, the longer the multi-phase gated oscillator 1 oscillates.
[0008] (4) When the pulse width signal to be measured ends, the multi-phase gated oscillator including the interpolation circuit stops oscillating, and each output phase is in a floating state. The level of each output phase and the number of oscillation cycles when the multi-phase gated oscillator including the interpolation circuit stops oscillating contain information about the pulse width of the pulse width signal to be measured. The subsequent circuit performs a sampling and encoding operation, and after the operation is completed, the timing (1) to (4) are repeated.
[0009] When the multi-phase gated oscillator including the interpolation circuit includes X cross-coupled delay units, there are 4X output phases, that is, Figure 1 The output of a cross-coupled delay unit, out(0), passes through an inverter and becomes pi(0). The output of two cross-coupled delay units, out(0) and out(1), pass through two inverters and are directly connected together to become pi(1). This process is called interpolation.
[0010] See also Figure 2 When X=4, the multiphase gated oscillator including the interpolation circuit has 16 output phases, namely pi(0) to pi(15), and the phase difference between adjacent phases is 22.5 degrees. At any time, the phase difference between the jth phase pi(j) and the j+2Xth phase pi(j+2x) output by the multiphase gated oscillator including the interpolation circuit is 180 degrees (i.e., an anti-phase relationship), and the value range of j is 0≤j≤2x-1.
[0011] When the multi-phase gated oscillator including the interpolation circuit is reset, pi(0) to pi(7) are low level (binary number 0), and pi(8) to pi(15) are high level (binary number 1). When the pulse width signal to be measured arrives, the multi-phase gated oscillator including the interpolation circuit starts to oscillate, which can be intuitively understood as Figure 2 The 16 pointers in the oscillator start to rotate clockwise. When the pulse width signal to be measured ends, the multi-phase gated oscillator including the interpolation circuit stops oscillating.
[0012] At this point, the output of the sampling path is: K is an integer between 0 and 14, and has 15 possible values. A horizontal bar above pi(K) represents negation, or the logical NOT operation. Both the asterisk and the period represent multiplication. The output of the sampling path has 16 possible values.
[0013] At this time, the output of the counting path is: the number of falling edges of pi (15) changing from a high level to a low level during the oscillation process of the multi-phase gated oscillator including the interpolation circuit×16.
[0014] After the error correction coding circuit obtains the outputs of the sampling and counting paths, the output pulse width quantization result is expressed as: (sampling path result + counting path result - 8) × LSB. Here, LSB represents the minimum quantization time unit and is determined by the frequency F of the multi-phase gated oscillator containing the interpolation circuit. LSB = 1 ÷ (F × 16).
[0015] In most cases, the existing pulse width detection circuit can normally quantify the pulse width of the pulse width signal to be measured, but it will make mistakes when the following rare events occur.
[0016] The first error scenario: When the multi-phase gated oscillator including the interpolation circuit stops working, pi (15) becomes a floating node during the transition from a high level to a low level, which means that the output result of pi (15) is in a metastable state. In this case, if the sampling path samples pi (15) as a high level, and the counting path records this transition as a valid falling edge, the quantized pulse width will be offset by +16 LSBs (i.e., 16 more).
[0017] The second error scenario: When the multi-phase gated oscillator containing the interpolation circuit stops working, pi (15) becomes a floating node during the transition from a high level to a low level, which means that the output result of pi (15) is metastable. In this case, if the sampling path samples pi (15) as a low level, but the counting path does not record this transition as a valid falling edge, the quantized result of the pulse width will be offset by -16 LSBs (i.e., 16 less).
[0018] The third error scenario: When the multiphase gated oscillator including the interpolation circuit stops working, pi (15) becomes a floating node during the transition from a low level to a high level. However, due to leakage, pi (15) enters a metastable state and slowly decreases, falsely triggering the counting path and causing an extra count. As a result, the quantized pulse width will be offset by +16 LSBs.
[0019] The fourth error scenario: When the reset signal is turned off and the pulse width signal to be measured has not yet arrived, due to the influence of leakage, pi (15) enters the metastable state and slowly decreases, and the counting path is mistakenly triggered, resulting in an extra count result. Then, the quantization result of the pulse width will have an offset of +16 LSB.
[0020] The pi(15) phase in each of the above cases is only an example. Other phases may also produce metastable states, but they have little impact on the overall performance of the circuit. The phase with the most significant negative impact is pi(4X-1), because it performs calculations in both the sampling path and the counting path.
[0021] If the result deviation problem caused by metastable state in the pulse width detection circuit can be solved, it will play a greater role. Summary of the Invention
[0022] The technical problem to be solved by the present application is: how to overcome the erroneous quantization results caused by the metastable state in the existing pulse width detection circuit based on the gated oscillator.
[0023] In order to solve the above technical problems, the present application proposes an oscillator-based pulse width detection circuit that prevents metastability, comprising: a multi-phase gated oscillator including an interpolation circuit, a sampling path, a counting path, and an error correction coding circuit. The multi-phase gated oscillator including the interpolation circuit is used to output an oscillation signal output containing all phases of the pulse width signal information to be measured; the multi-phase gated oscillator including the interpolation circuit has 4X output phases, namely pi(0), pi(1), ..., pi(4X-1), where X is a positive integer; wherein pi(4X-1) is a key phase; the key phase pi(4X-1) and any one of pi(X-1) or pi(3X-1) orthogonal to the key phase constitute a pair of mutually orthogonal oscillation signal outputs. The sampling path is used to sample all 4X phase oscillation signals output by the multi-phase gated oscillator including the interpolation circuit after it stops working, obtaining 4X sampling results, each sampling result corresponding to the oscillation signal of each output phase; the sampling path uses the two sampling results corresponding to the two phases pi(4X-2) and pi(0) adjacent to the key phase pi(4X-1) as the "sampling result output for determining metastable state". The counting path is used to count the output of the multi-phase gated oscillator including the interpolation circuit; the counting path counts the number of falling edges of the pair of mutually orthogonal oscillation signal outputs, and selects one of the falling edge count results as the counting result output by the counting path according to the sampling result output for determining metastable state; and the counting path obtains a correction signal according to the sampling result output for determining metastable state. The error correction coding circuit is used to encode the sampling results, counting results and correction signals through the encoding clock to obtain the final pulse width quantization result output and clock output.
[0024] Furthermore, in order to locate the interval where the key phase pi (4X-1) may undergo a metastable state, an XOR logic operation is performed on the output results of the two phases pi (4X-2) adjacent to the key phase pi (4X-1) and pi (0) to obtain a selection signal; when the selection signal is at a high level, it indicates that the key phase pi (15) may undergo a metastable state; when the selection signal is at a low level, it indicates that the key phase pi (15) will not undergo a metastable state.
[0025] Furthermore, the key phase pi(4X-1) is a counting phase, and the two phases pi(X-1) or pi(3X-1) that are orthogonal to the key phase pi are both standby counting phases.
[0026] Furthermore, the mutually orthogonal pair of oscillation signal outputs consists of a counting phase and a spare counting phase; when the selection signal is a high level, the counting path selects the falling edge counting result of the spare counting phase as the output counting result; when the selection signal is a low level, the counting path selects the falling edge counting result of the counting phase as the output counting result.
[0027] Furthermore, the counting path is changed to count the number of rising edges of the pair of mutually orthogonal oscillation signal outputs respectively, and according to the sampling result output of determining the metastable state, one of the rising edge counting results is selected as the counting result output by the counting path.
[0028] Furthermore, when the selection signal is at a high level, the counting path generates a correction signal; the correction signal flag= Among them, the horizontal line above pi(4X-2) represents negation, and the period represents multiplication.
[0029] Furthermore, when the correction signal is at a high level, 16 LSBs are subtracted from the final output of the error correction coding circuit; LSB represents the minimum quantization time unit; when the correction signal is at a low level, the final output of the error correction coding circuit is not processed.
[0030] Furthermore, when the correction signal is at a high level, the pulse width quantization result output of the error correction coding circuit = (count result - 1) × 16, the unit is LSB; when the correction signal is at a low level, the pulse width quantization result output of the error correction coding circuit = count result × 16, the unit is LSB.
[0031] Furthermore, after one pulse width detection is completed, the multi-phase gated oscillator including the interpolation circuit is reset when the reset signal 1 arrives, and then the counting path is reset when the reset signal 2 arrives.
[0032] The technical effect achieved by the present application is: innovatively providing an orthogonal phase counting circuit, locating the interval where metastable states may occur through logical judgment, selecting the appropriate phase signal for counting, and ultimately making the results of the counting path consistent with the results of the sampling path, avoiding large errors caused by falling into metastable states and deteriorating circuit performance, thereby solving the shortcomings of the existing technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 The diagram is a structural diagram of an example of an existing multi-phase gated oscillator including an interpolation circuit.
[0034] Figure 2 yes Figure 1 The output phase diagram of an example of a multi-phase gated oscillator including an interpolation circuit is shown.
[0035] Figure 3 This is a schematic diagram of the structure of an oscillator-based pulse width detection circuit for preventing metastable states proposed in this application.
[0036] Figure 4 yes Figure 3 The typical working timing diagram of the pulse width detection circuit is shown in FIG.
[0037] Explanation of the reference numerals in the figure: a multi-phase gated oscillator 1 including an interpolation circuit, a sampling path 2, a counting path 3, and an error correction coding circuit 4. DETAILED DESCRIPTION
[0038] See also Figure 3 The oscillator-based pulse width detection circuit for preventing metastability proposed in this application includes: a multi-phase gated oscillator 1 including an interpolation circuit, a sampling path 2, a counting path 3, and an error correction coding circuit 4.
[0039] The multi-phase gated oscillator 1 including the interpolation circuit is used to provide the subsequent circuit with an oscillation signal output of all phases containing the information of the pulse width signal to be measured, wherein the interpolation circuit is used to double the resolution of the pulse width quantization result. When the multi-phase gated oscillator 1 including the interpolation circuit is mainly composed of X cross-coupled delay units, X is a positive integer, and there are 4X output phases, namely pi(0), pi(1), ..., pi(4X-1). Among them, pi(4X-1) is the key phase. pi(4X-1) and pi(X-1) form a mutually orthogonal relationship, and pi(4X-1) and pi(3X-1) also form a mutually orthogonal relationship. The mutually orthogonal oscillation signals are a subset of the oscillation signals of all phases, one of which is the key phase pi(4X-1), and the other is pi(X-1) or pi(3X-1) that is orthogonal to the key phase pi(4X-1). The key phase pi (4X-1) is a counting phase, and the two phases that are orthogonal to the key phase pi (4X-1) are both standby counting phases.
[0040] The sampling path 2 is used to sample the oscillation signals of all phases output by the multi-phase gated oscillator 1 including the interpolation circuit after it stops working. The sampling path 2 has two inputs and two outputs. The sampling clock is used to sample the oscillator outputs of all phases, and the obtained sampling results are aligned with the sampling clock. When the multi-phase gated oscillator 1 including the interpolation circuit has 4X output phase oscillation signals, the sampling path 2 also outputs 4X sampling results, and each sampling result corresponds to the oscillation signal of each output phase. The "sampling result output for determining metastable state" is a subset of the sampling results. In order to locate the interval where metastable state may occur in the critical phase pi (4X-1), the two sampling results corresponding to the two phases pi (4X-2) and pi (0) adjacent to the critical phase pi (4X-1) are used as the "sampling result output for determining metastable state".
[0041] The counting path 3 is used to count the output of the multi-phase gated oscillator 1 including the interpolation circuit. The counting path 3 has three inputs and two outputs. A pair of mutually orthogonal oscillator outputs (counting phase, a certain spare counting phase) are respectively counted for the number of falling edges (or rising edges) in the counting path 3, and one of the falling edge counting results (or rising edge counting results) is selected as the counting result output by the counting path 3 based on the sampling result output of the metastable state. And a correction signal is obtained based on the sampling result output of the metastable state. Reset signal 2 is used to reset the counting result of the counting path 3 to zero at the end of each conversion cycle. The process of pulse width detection is to periodically convert the input pulse into digital code. A conversion cycle refers to the length of time it takes for the pulse width detection circuit to completely convert the input pulse into digital code.
[0042] The error correction coding circuit 4 is used to encode the sampling results, counting results, and correction signal using an encoding clock to obtain a final pulse width quantization output and a clock output. When the correction signal is at a high level (binary 1), 16 LSBs are subtracted from the final output of the error correction coding circuit 4. When the correction signal is at a low level (binary 0), the final output of the error correction coding circuit 4 is not processed.
[0043] Figure 3 In the pulse width detection circuit shown, an output of sampling path 2, the "metastability determination sampling result output," serves as an input to counting path 3. Counting path 3 performs a logical operation within the circuit, determining whether a metastability state is likely to occur and taking measures to mitigate adverse effects, thereby outputting an accurate count result. An output of counting path 3, the correction signal, serves as an input to error correction encoding circuit 4, which processes the correction signal to produce the final quantized pulse width output.
[0044] For the first, second and third error scenarios, this application innovatively introduces the logic of orthogonal phase counting. First, the circuit needs to locate the interval where metastable states may occur. Taking pi (15) as an example, if pi (14) is high and pi (0) is low in a certain sampling clock cycle, then the sampling clock cycle is the time interval where pi (15) may occur the first and second error scenarios. Similarly, if pi (14) is low and pi (0) is high in a certain sampling clock cycle, then the sampling clock cycle is the time interval where pi (15) may occur the third error scenario. Perform an exclusive OR logic operation on the output results of pi (14) and pi (0) (both represented by binary numbers 0 or 1) to obtain a selection signal sel (also represented by binary numbers 0 or 1). This selection signal sel can be used to locate the time interval where pi (15) may occur metastable states. In summary, in order to locate the interval where the key phase pi (4X-1) may be in a metastable state, the output results of the two phases pi (4X-2) adjacent to the key phase pi (4X-1) and pi (0) are subjected to an XOR logic operation to obtain a selection signal sel. When the selection signal sel is at a high level (binary number 1), it indicates that the key phase pi (15) may be in a metastable state. When the selection signal sel is at a low level (binary number 0), it indicates that the key phase pi (15) will not be in a metastable state. Figure 2 The output phases of the multi-phase gated oscillator 1 including the interpolation circuit can be seen intuitively. It can be found that pi(3) and pi(15) are in an orthogonal relationship, and pi(11) is also in an orthogonal relationship with pi(15). In the time interval when pi(15) may be in a metastable state, pi(3) and pi(11) are both determined high and low levels. Therefore, it is possible to consider having an additional backup counting phase to replace the key phase pi(15) when the first, second, and third error situations may occur, thereby avoiding the quantization error caused by the possible metastable state of pi(15). In summary, in order to avoid the influence of the metastable state of the key phase pi(4X-1), pi(X-1) or pi(3X-1) that has an orthogonal relationship with the key phase pi(4X-1) is used as a backup counting phase.
[0045] Assume that the counting path 3 counts the falling edge of pi (15) (it can be modified to count the rising edge of pi (15) according to actual conditions), and selects pi (11) as the backup counting phase between pi (3) and pi (11). When the selection signal sel is high (binary 1), it indicates that the key phase pi (15) may be in a metastable state, and the counting path 3 selects the falling edge counting result of the backup counting phase pi (11) as the counting result output. When the selection signal sel is low (binary 0), it indicates that the key phase pi (15) will not be in a metastable state, and the counting path 3 selects the falling edge counting result of the key phase pi (15) as the counting result output. In this way, the occurrence of the first, second, and third error situations can be avoided to a certain extent, but it is not enough to completely eliminate the quantization error.
[0046] Considering the first and second error scenarios, when the selection signal sel is high, if pi(15) is sampled as low in sampling path 2, then ideally, counting path 3 should count the last falling edge of pi(15), and the falling edge count of pi(11) is consistent with the ideal situation. If pi(15) is sampled as high in sampling path 2, then ideally, counting path 3 should not count the last falling edge of pi(15). In this case, the number of falling edges of pi(11) will be one more than the ideal situation, and a new correction signal flag can be introduced at this time. The horizontal line above pi(14) indicates negation, i.e., the “not” operation in the logic operation. The dot indicates multiplication. In summary, in order to avoid the possible metastable state of the critical phase pi(4X-1), the correction signal When the correction signal flag is high (binary 1), 16 LSBs are subtracted from the final output of the error correction coding circuit 4. When the correction signal flag is low (binary 0), the error correction coding circuit 4 does not perform any processing.
[0047] Considering the third error situation, when the selection signal sel is at a high level, the falling edge count of the standby counting phase pi (11) is consistent with the ideal situation.
[0048] Considering the fourth error scenario, the circuit timing is adjusted so that the reset signal 2 is turned off after the rising edge of the pulse width signal to be measured arrives. This can avoid accidental counting errors in the reset state.
[0049] To summarize the solutions to the various error scenarios described above, the counting result output by counting path 3 of the present application is as follows: when the selection signal sel is at a low level, the counting result is the number of falling edges of the counting phase pi(4X-1). When the selection signal sel is at a high level, the counting result is the number of falling edges of the backup counting phase pi(X-1) or pi(3X-1).
[0050] The error correction coding circuit 4 receives the output of the preceding circuit and uses a correction signal flag to correct the count result. When the correction signal is high (binary 1), the pulse width quantization result output by the error correction coding circuit 4 = (count result - 1) × 16, in LSBs. When the correction signal is low (binary 0), the pulse width quantization result output by the error correction coding circuit 4 = count result × 16, in LSBs.
[0051] See also Figure 4 ,This is Figure 3 The typical operating timing diagram of the pulse width detection circuit shown in the figure. Starting with the arrival of the pulse width signal to be measured, the multi-phase gated oscillator 1 including the interpolation circuit begins to oscillate. At the end of the pulse width signal to be measured, the output of the multi-phase gated oscillator 1 including the interpolation circuit enters a floating state (a state where metastable conditions may occur). When the rising edge of the sampling clock arrives, sampling path 2 outputs the sampling result of the current cycle. Counting path 3 receives a portion of the sampling result to produce the correct counting result output, while also generating a selection signal sel and a correction signal flag. After the encoding clock arrives, the final pulse width quantization result output and clock output are obtained. Then, the arrival of the reset signal resets the multi-phase gated oscillator 1 including the interpolation circuit. Finally, the arrival of the reset signal resets the counting path 3, and the next cycle conversion process begins.
[0052] The orthogonal phase counting technology proposed in this application completely avoids the influence of metastability on the accuracy of the quantization results of the pulse width detection circuit, and compared with the existing technical solutions, it only adds one more spare counting phase, thereby achieving an improvement in the circuit reliability with very low overhead.
[0053] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.
Claims
1. A pulse width detection circuit based on an oscillator for preventing metastability, characterized in that: include: A multi-phase gated oscillator including an interpolation circuit, a sampling path, a counting path, and an error correction coding circuit; The multi-phase gated oscillator including the interpolation circuit is used to output oscillation signals of all phases including information of the pulse width signal to be measured; the multi-phase gated oscillator including the interpolation circuit has 4X output phases, namely pi(0), pi(1), ..., pi(4X-1), where X is a positive integer; Wherein pi(4X-1) is the critical phase; the critical phase pi(4X-1) and any one of pi(X-1) or pi(3X-1) which is orthogonal to the critical phase form a pair of mutually orthogonal oscillation signal outputs; The sampling path is used to sample all 4X phase oscillation signals output by the multi-phase gated oscillator including the interpolation circuit after the multi-phase gated oscillator stops working, and obtain 4X sampling results, each sampling result corresponding to the oscillation signal of each output phase; the sampling path uses the two sampling results corresponding to the two phases pi(4X-2) and pi(0) adjacent to the key phase pi(4X-1) as "sampling result outputs for determining metastable state"; The counting path is used to count the output of the multi-phase gated oscillator including the interpolation circuit; the counting path respectively counts the number of falling edges of the pair of mutually orthogonal oscillation signal outputs, and selects one of the falling edge count results as the counting result output by the counting path based on the sampling result output of determining the metastable state; and the counting path obtains a correction signal based on the sampling result output of determining the metastable state; The error correction coding circuit is used to encode the sampling result, the counting result and the correction signal through the encoding clock to obtain the final pulse width quantization result output and the clock output.
2. The oscillator-based pulse width detection circuit for preventing metastability according to claim 1, wherein: In order to locate the interval where the key phase pi(4X-1) may be in a metastable state, an XOR logic operation is performed on the output results of the two phases pi(4X-2) adjacent to the key phase pi(4X-1) and pi(0) to obtain a selection signal; when the selection signal is at a high level, it indicates that the key phase pi(15) may be in a metastable state; when the selection signal is at a low level, it indicates that the key phase pi(15) will not be in a metastable state.
3. The oscillator-based pulse width detection circuit for preventing metastability according to claim 2, wherein: The key phase pi(4X-1) is a counting phase, and the two phases pi(X-1) or pi(3X-1) that are orthogonal to the key phase pi are both standby counting phases.
4. The oscillator-based pulse width detection circuit for preventing metastability according to claim 3, wherein: The mutually orthogonal pair of oscillation signal outputs consists of a counting phase and a spare counting phase; when the selection signal is at a high level, the counting path selects the falling edge counting result of the spare counting phase as the output counting result; when the selection signal is at a low level, the counting path selects the falling edge counting result of the counting phase as the output counting result.
5. The oscillator-based pulse width detection circuit for preventing metastability according to claim 1, wherein: The counting path is changed to count the number of rising edges of the pair of mutually orthogonal oscillation signal outputs respectively, and according to the sampling result output of determining the metastable state, one of the rising edge counting results is selected as the counting result output by the counting path.
6. The oscillator-based pulse width detection circuit for preventing metastability according to claim 2, wherein: When the selection signal is high, the counting path generates a correction signal; the correction signal Among them, the horizontal line above pi(4X-2) represents negation, and the period represents multiplication.
7. The oscillator-based pulse width detection circuit for preventing metastability according to claim 6, wherein: When the correction signal is high, the final output of the error correction coding circuit is reduced by 16 LSBs; LSB represents the minimum quantization time unit; when the correction signal is low, the final output of the error correction coding circuit is not processed.
8. The oscillator-based pulse width detection circuit for preventing metastability according to claim 7, wherein: When the correction signal is at a high level, the pulse width quantization result output of the error correction coding circuit = (count result - 1) × 16, the unit is LSB; when the correction signal is at a low level, the pulse width quantization result output of the error correction coding circuit = count result × 16, the unit is LSB.
9. The oscillator-based pulse width detection circuit for preventing metastability according to claim 1, wherein: After one pulse width detection is completed, the multi-phase gated oscillator including the interpolation circuit is reset when the reset signal arrives, and then the counting path is reset when the reset signal arrives.