Phased array agile beam emission queue management device

Abstract

The invention discloses a phased array agile beam transmission queue management device, and belongs to the field of satellite communication. The device comprises an interface module, a data frame processing module, a queue cache module, a storage table module, a cache module, a queue write-in control module and a queue read control module. Under limited hardware storage resources, multi-rate and multi-wave-position combined coverage transmission is realized, and the method has the advantages of stable performance, portability and good expandability.

Description

Technical Field

[0001] The present invention relates to the field of satellite communications, in particular to a phased array agile beam transmission queue management device. Background Art

[0002] Traditional satellite-borne transmitters generally have limited information rate coverage and support a limited number of simultaneous wavelets. With the increasing number of ground users and the maturation of satellite communication technology, the demand for high-throughput, high-speed transmission is increasing. Satellite-borne transmitters need to meet the needs of both high-speed and low-speed users. The increasing maturity of phased array antenna technology allows for the simultaneous support of more simultaneous wavelets and a wider coverage area.

[0003] Currently, the design of multi-rate and multi-wavelength satellite transmitters mostly uses the queue number coverage method to achieve multi-rate and multi-wavelength transmission. However, its system design is relatively complex and requires high FPGA hardware storage resources, which cannot meet the current growing wavelength and rate requirements. Summary of the Invention

[0004] In view of this, the present invention proposes a phased array agile beam transmission queue management device. The present invention adopts dynamic storage linked list queue management technology and a two-level dynamic buffer solution to achieve multi-rate and multi-wavelength combination coverage transmission under limited hardware storage resources.

[0005] The technical solution adopted in the present invention is:

[0006] A phased array agile beam transmission queue management device includes an interface module 1, a data frame processing module 2, a queue buffer module 5, a storage table module 3, a buffer module 4, a queue write control module 6, and a queue read control module 7;

[0007] The interface module 1 receives data from the outside. If the data is a configuration frame, it is sent to the storage table module 3. If the data is a service frame, it is sent to the data frame processing module 2.

[0008] The data frame processing module 2 extracts the destination station address and the corresponding rate file information from the service frame, sends the corresponding relationship between the destination station address and the rate file information to the storage table module 3, and sends the complete service frame to the buffer module 4;

[0009] The storage table module 3 extracts the destination station address and the corresponding wave number information from the configuration frame, and stores the correspondence between the destination station address and the wave number information and the correspondence between the destination station address and the speed file information in two tables respectively;

[0010] The buffer module 4 stores the service frames sent by the data frame processing module 2 in a first-in-first-out manner;

[0011] The queue cache module 5 includes multiple cache queues, monitors the status information of each cache queue, and outputs four levels of thresholds to the queue write control module 6 and the queue read control module 7;

[0012] The queue write control module 6 is used to control the writing of data;

[0013] After receiving the externally input burst frame tail pulse, the queue reading control module 7 determines the queue number to be selected for the next burst data and reads the cached data of the corresponding queue number in the queue cache module 5 .

[0014] Furthermore, the thresholds of the four levels are:

[0015] The first-level threshold is 1600, which is used to determine whether the remaining buffer space in the buffer is less than 1600 bytes;

[0016] The secondary threshold is the rate level, which is used to determine whether the data in the current buffer can send a complete burst of data;

[0017] The third-level threshold is 1, which is used to determine whether the buffer data is empty;

[0018] The fourth level threshold is 2, which is used to determine whether the data storage time in the buffer exceeds 2 seconds.

[0019] Furthermore, the specific working mode of the queue writing control module 6 is as follows:

[0020] The queue write control module 6 notifies the buffer module 4 to send the destination station address of the service frame at the head of the buffer module 4 to the storage table module 3. The storage table module 3 performs a table lookup based on the destination station address and transmits the rate file information and wave position number information obtained from the table lookup to the queue write control module 6; the queue write control module 6 searches the dynamic linked table based on the rate file information and wave position number information. The dynamic linked table stores the correspondence between the combination of the rate file information and the wave position number information and the cache queue in the queue cache module 5. The dynamic linked table is initially empty. If the corresponding cache queue is found, it is determined whether the service frame can be stored in the cache queue at this time based on the first-level threshold provided by the queue cache module 5. If it can, the queue write control module 6 informs the buffer module 4 of the queue number that needs to be stored in the queue cache module 5. , the cache module 4 stores the head business frame into the corresponding cache queue in the queue cache module 5, otherwise, continue to wait until it can be stored in the corresponding cache queue; if the dynamic linked list is searched and no corresponding combination of rate gear information and wave position number information is found, then it is determined whether there is an empty cache queue in the queue cache module 5 according to the three-level threshold provided by the queue cache module 5; if so, the head business frame in the memory module 4 is stored in the empty cache queue, and the combination of rate gear information and wave position number information corresponding to the business frame is added to the dynamic linked list, and a corresponding relationship between the new combination of rate gear information and wave position number information and the cache queue in the queue cache module 5 is established; if there is no empty cache queue, continue to wait until an empty cache queue appears in the queue cache module 5.

[0021] Furthermore, the storage table module 3 has three states: wave number information storage state 3-1, rate gear information storage state 3-2 and table lookup state 3-3;

[0022] In the wave number information storage state 3-1, the configuration frame data of the interface module 1 is parsed, and the destination station address and wave number information are extracted and stored in the first storage table;

[0023] In the rate profile information storage state 3-2, the destination station address and rate profile information provided by the data frame processing module 2 are stored in the second storage table;

[0024] In the table lookup state 3 - 3 , the first storage table and the second storage table are looked up according to the destination station address provided by the buffer module 4 , and the acquired wave number information and rate level information are sent to the queue write control module 6 .

[0025] Furthermore, the buffer module 4 uses the off-chip memory and on-chip memory of the FPGA to form a primary memory for storing the service data before entering the queue buffer; the buffer module 4 includes a first data writing module 4-1, a data table lookup module 4-2 and a data reading module 4-3;

[0026] The first data writing module 4-1 receives the service data from the data frame processing module 2 and stores it in the on-chip memory of the FPGA first. When the on-chip memory reaches the upper limit, it stores it in the off-chip memory;

[0027] The data table lookup module 4-2 reads the destination station address of the service frame header from the on-chip or off-chip memory and outputs it to the storage table module 3 for table lookup;

[0028] The data reading module 4 - 3 receives a read flag from the queue writing control module 6 , and when the read flag is pulled high, reads a complete service frame and outputs it to the corresponding queue number buffer of the queue buffer module 5 .

[0029] Furthermore, the queue buffer module 5 includes a second data writing module 5-1, a queue monitoring module 5-2 and a data output module 5-3;

[0030] The second data writing module 5-1 stores the service data of the buffer module 4 into the corresponding queue buffer according to the queue number provided by the write control module 6;

[0031] The queue monitoring module 5-2 monitors the status parameters of the queue buffer and outputs the four-level threshold value to the queue writing control module 6 and the queue reading control module 7;

[0032] The data output module 5 - 3 reads the data in the corresponding queue buffer according to the burst code block based on the burst enable and queue number sent by the queue reading control module 7 .

[0033] Furthermore, the queue write control module 6 uses a security state machine to sequentially determine queue write judgment conditions, while maintaining a dynamic linked list, maintaining queue wave number and rate gear information; the queue write control module 6 has four states: an initial state 6-1, a first-level judgment state 6-2, a second-level judgment state 6-3, and a threshold judgment state 6-4. The queue write control module 6 also includes a dynamic linked list maintenance module 6-5;

[0034] In the initial state 6-1, the wave position number and speed level information data are received from the storage table module 3, triggering the safety state machine operation switch and entering the first level judgment state 6-2;

[0035] In the first-level judgment state 6-2, the dynamic linked table is queried to determine whether there is an entry with consistent wave position number and rate gear information. If they are consistent, the process proceeds to the threshold judgment state 6-4. If there is no consistent entry, the process proceeds to the second-level judgment state 6-3.

[0036] In the secondary judgment state 6-3, it is determined whether there is an empty queue in the queue buffer. If there is an empty queue, the start writing queue flag signal is pulled high and output to the buffer module 4, the wave bit number and rate level information corresponding to the service frame are stored in the dynamic linked list, and the initial state 6-1 is returned. If there is no empty queue, it waits in the current state until an empty queue buffer appears.

[0037] In the threshold judgment state 6-4, the queue buffer module 5 determines whether it can store the next service data based on the first-level threshold. If the queue buffer storage space has not reached the threshold, the queue write flag signal is pulled high and output to the buffer module 4, and the process returns to the initial state 6-1. If the queue buffer storage space has reached the threshold, the process waits in the current state until the queue buffer is empty.

[0038] The dynamic linked list maintenance module 6-5 contains n table entries, corresponding to the wave position numbers and rate gear information corresponding to the n queue memories; the dynamic linked list maintenance module 6-5 updates the information data of each table entry in real time and transmits the dynamic linked list data to the queue reading control module 7.

[0039] Furthermore, the queue reading control module 7 uses a security state machine to sequentially determine the queue writing judgment conditions, including six states: initial state 7-1, first-level judgment state 7-2, second-level judgment state 7-3, third-level judgment state 7-4, fourth-level judgment state 7-5 and fifth-level judgment state 7-6;

[0040] In the initial state 7-1, after receiving the external input burst frame tail pulse, it enters the first level judgment state 7-2;

[0041] In the first-level judgment state 7-2, it is determined whether the data in the current queue buffer is empty. The current queue buffer refers to the queue number read during the last burst. The default queue buffer at power-on is queue 1. If it is empty, the second-level judgment state 7-3 is entered. If it is not empty, the data in the queue buffer is continued to be read, the wave position number and rate gear information of the queue buffer are retrieved from the dynamic storage linked table and output, and the next burst data pulse is output to the queue buffer module 5 to trigger the data reading of the queue buffer 5, and then the initial state 7-1 is returned.

[0042] In the second-level judgment state 7-3, each queue is judged in turn to see whether it meets the fourth-level threshold condition. If the fourth-level threshold condition is met, the queue data is read, and only one service frame data is read at a time. The wave bit number and rate level information of the queue are output, and the next burst data pulse is output to the queue buffer module 5, and then the initial state 7-1 is returned. If none of the queue buffers meet the fourth-level threshold condition, the third-level judgment state 7-4 is entered.

[0043] In the third-level judgment state 7-4, each queue is judged in turn to see whether it meets the first-level threshold condition. If the first-level threshold condition is met, the queue data is read, the wave position number and rate level information of the queue are output, the next burst data pulse is output to the queue buffer module 5, and then the initial state 7-1 is returned. If none of the queue buffers meet the first-level threshold condition, the fourth-level judgment state 7-5 is entered.

[0044] In the fourth-level judgment state 7-5, each queue is judged in turn to see whether it meets the second-level threshold condition. If the second-level threshold condition is met, the queue data is read, the wave position number and rate level information of the queue are output, and the next burst data pulse is output to the queue buffer module 5, and then the initial state 7-1 is returned. If none of the queue buffers meet the second-level threshold condition, the fifth-level judgment state 7-6 is entered.

[0045] In the five-level judgment state 7-6, each queue is judged in turn whether it meets the third-level threshold condition. If the third-level threshold condition is met, the queue data is read, the wave position number and rate gear information of the queue are output, and the next burst data pulse is output to the queue cache module 5, and then the initial state 7-1 is returned; if none of the queue buffers meet the third-level threshold condition, the idle code of the current queue buffer is continued to be read, and then the initial state 7-1 is returned.

[0046] The beneficial effects of the present invention are:

[0047] 1. The present invention has a dynamic linked list storage technology. By adopting the dynamic linked list storage technology, the queue wave position number and rate gear parameters can be updated in a time-sharing manner. A small number of queues can be used to realize the combination parameters of multiple rate gears and wave position numbers. It has high flexibility and a wide range of applications.

[0048] 2. The present invention adopts dynamic linked list storage technology and uses a small number of queue buffers to realize data storage of multiple speed levels and wave numbers, effectively saving hardware storage resources.

[0049] 3. This invention utilizes a two-level caching technology. The first-level cache utilizes a larger buffer, caching externally transmitted data corresponding to the destination station address. The second-level cache acts as a queue buffer. If the first-level buffer's data wave bit number and rate range information do not meet the second-level queue buffer parameters, the data is stored in the first-level buffer until an empty queue is created, at which point the data is output to that queue. This approach ensures that the transmitter does not experience frame loss and provides excellent stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 2 is a schematic diagram of the principle of a phased array agile beam transmission queue management device in an embodiment of the present invention.

[0051] Figure 22 is a schematic diagram of the principle of the storage table module in an embodiment of the present invention.

[0052] Figure 3 Schematic diagram of the principle of the buffer module in an embodiment of the present invention.

[0053] Figure 4 It is a schematic diagram of the principle of the queue cache module in an embodiment of the present invention.

[0054] Figure 5 It is a schematic diagram of the principle of the queue writing control module in an embodiment of the present invention.

[0055] Figure 6 It is a schematic diagram of the principle of the queue reading control module in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present invention will be described in further detail below with reference to the accompanying drawings.

[0057] A phased array agile beam transmission queue management device, referring to Figure 1 , including an interface module 1, a data frame processing module 2, a storage table module 3, a buffer module 4, a queue buffer module 5, a queue write control module 6 and a queue read control module 7.

[0058] Interface module 1 stores the configuration frame data in storage table module 3 and sends the service frame data to data frame processing module 2. Data frame processing module 2 extracts and stores the service frame information carrying the destination station address and corresponding rate range information in storage table module 3, and stores the destination station address and service frame data of all service frame data in buffer module 4. Buffer module 4 outputs the stored service frame destination station address to storage table module 3 for table lookup. Storage table module 3 receives the configuration frame data from interface module 1, stores the wave number information corresponding to the destination station address, stores the rate range destination station address information from data frame processing module 2, obtains the destination station address of the service frame from the buffer module for table lookup, and sends the corresponding wave number information and rate range information to queue write control module 6. The queue write control module 6 searches the dynamic linked table according to the rate gear and wave number information provided by the storage table module 3, and finds the table entry with the same rate gear and wave number, that is, the corresponding queue buffer. It judges whether the service frame can be stored in the queue at this time according to the first-level threshold provided by the queue buffer module 5. If it meets the requirements, the service frame of the memory module 4 is stored in the queue buffer corresponding to the queue buffer module 5. If it does not meet the requirements, it waits until the queue storage conditions are met and the service frame is stored in the queue buffer corresponding to the queue buffer module 5; if the table lookup result does not have consistent rate gear and wave number information, it judges whether the queue is stored in an empty queue according to the third-level threshold provided by the queue buffer module 5. If there is an empty queue, the service frame of the memory module 4 is stored in the queue, and the rate gear and wave number information corresponding to the service frame are updated in the dynamic linked table. If there is no empty queue, it waits until there is an empty queue, and the service frame of the memory module 4 is stored in the queue corresponding to the queue buffer module 5, and the rate gear and wave number information corresponding to the service frame are updated in the dynamic linked table. The queue buffer module 5 includes n queue buffers, capable of storing service frames with n different combinations of rate levels and wavenumbers. This module receives service frame data from the buffer module 4 and stores it in the corresponding buffer. Based on the queue number and rate level information provided by the queue read control module 7, this module reads buffer data according to the burst code block. The queue buffer module 5 monitors queue buffer status information and outputs four-level thresholds to the queue write control module 6 and queue read control module 7. The queue read control module 7 determines the queue number for the next burst data frame, starting at the end of the previous burst data frame. It uses a five-level judgment process to determine whether the five criteria are met and then reads the corresponding queue data.

[0059] like Figure 2 As shown, the storage table module 3 includes a wave number information storage state 3-1, a rate level information storage state 3-2 and a table lookup state 3-3.

[0060] The wave number information storage state 3-1 parses the configuration frame data of the interface module 1, extracts the destination station address and wave number information and stores them in the storage table 1; the rate gear information storage state 3-2 stores the destination station address and rate gear information provided by the data frame processing module 2 in the storage table 2; the table lookup state 3-3 looks up the two storage tables according to the destination station address provided by the cache module 4, and sends the acquired wave number information and rate gear information to the queue write control module 6.

[0061] like Figure 3 As shown, the buffer module 4 uses the FPGA external memory and the FPGA on-chip memory to form a primary memory for storing the service data before entering the queue buffer. The buffer module 4 includes a data writing module 4-1, a data table lookup module 4-2, and a data reading module 4-3.

[0062] The data write module 4-1 receives the business data from the data frame processing module 2, and stores it in the FPGA on-chip storage first. After the on-chip storage reaches the upper limit, it is stored in the off-chip storage; the data lookup module 4-2 first reads the destination station address of the business frame header in the memory, and outputs it to the storage table module 3 for table lookup; the data read module 4-3 receives the read flag from the queue write control module 6. When the read flag is pulled high, a complete business frame is read and output to the corresponding queue number buffer of the queue cache module 5.

[0063] like Figure 4 As shown, the queue buffer module 5 includes a data writing module 5-1, a queue monitoring module 5-2 and a data output module 5-3.

[0064] The data writing module 5-1 stores the service data of the buffer module 4 into the corresponding queue buffer according to the queue number provided by the write control module 6; the queue monitoring module 5-2 monitors the status parameters of the queue buffer and outputs the four-level threshold to the queue writing control module 6 and the queue reading control module 7; the data output module 5-3 reads the data in the corresponding queue buffer according to the burst code block based on the burst enable and queue number sent by the queue reading control module 7.

[0065] like Figure 5 As shown, the queue write control module 6 uses a secure state machine to sequentially determine queue write conditions, while also maintaining a dynamic linked list, queue wave number, and rate level information. It primarily includes an initial state 6-1, a primary determination state 6-2, a secondary determination state 6-3, a threshold determination state 6-4, and a dynamic linked list maintenance module 6-5.

[0066] Initial state 6-1 receives the wave number and speed level information data from the self-storage table module 3, triggers the safety state machine operation switch, and enters the first-level judgment state 6-2. The first-level judgment state 6-2 queries the dynamic linked table to determine whether there is a table entry with consistent wave number and speed level information. If so, it enters the threshold judgment state 6-4. If not, it enters the second-level judgment state 6-3. The second-level judgment state 6-3 determines whether there is an empty queue in the queue buffer. If there is an empty queue, the start write queue flag signal is pulled high and output to the buffer module 4, and the wave number and speed level information corresponding to the service frame is stored in the dynamic linked table. The process then returns to initial state 6-1. If there is no empty queue, it waits in this state until an empty queue buffer appears, and the above operation is repeated. Threshold determination state 6-4 determines whether the queue buffer can store the next service data based on the first-level threshold input by queue buffer module 5. If the queue buffer storage space has not reached the threshold, the start-write queue flag signal is pulled high and output to buffer module 4, and the process returns to initial state 6-1. If the queue buffer storage space has reached the threshold, the process waits in this state until an empty queue buffer appears, repeating the above operation. Dynamic linked list maintenance module 6-5 contains n entries, corresponding to the wave position number and rate level information of n queue memories, and updates the information data of each entry in real time, transmitting the dynamic linked list data to queue read control module 7.

[0067] like Figure 6 As shown, the queue read control module 7 uses a security state machine to sequentially determine the queue write judgment conditions, which mainly include an initial state 7-1, a first-level judgment state 7-2, a second-level judgment state 7-3, a third-level judgment state 7-4, a fourth-level judgment state 7-5, and a fifth-level judgment state 7-6.

[0068] After receiving the externally input burst frame tail pulse, initial state 7-1 enters level 1 judgment state 7-2. Level 1 judgment state 7-2 determines whether the current queue buffer data is empty. If so, it enters level 2 judgment state 7-3. If not, it continues to read the queue data, outputs the queue's wave position number and rate range information, outputs the next burst data pulse to queue buffer module 5, and returns to initial state 7-1. Level 2 judgment state 7-3 sequentially determines whether the queue meets the fourth-level threshold condition. If so, it prioritizes reading the queue data, outputs the queue's wave position number and rate range information, outputs the next burst data pulse to queue buffer module 5, and returns to initial state 7-1. If none of the queues meet the fourth-level threshold condition, it enters level 3 judgment state 7-4. The third-level judgment state 7-4 determines whether a queue has met the first-level threshold condition. If so, the queue data is preferentially read, the queue's wave number and rate range information are output, and the next burst data pulse is output to the queue buffer module 5, returning to the initial state 7-1. If none of the queues have met the first-level threshold condition, the process proceeds to the fourth-level judgment state 7-5. The fourth-level judgment state 7-5 determines whether a queue has met the second-level threshold condition. If so, the queue data is preferentially read, the queue's wave number and rate range information are output, and the next burst data pulse is output to the queue buffer module 5, returning to the initial state 7-1. If none of the queues have met the second-level threshold condition, the process proceeds to the fifth-level judgment state 7-6. The fifth-level judgment state 7-6 determines whether a queue has met the third-level threshold condition. If so, the queue data is preferentially read, the queue's wave number and rate range information are output, and the next burst data pulse is output to the queue buffer module 5, returning to the initial state 7-1. If none of the queues have met the third-level threshold condition, the process continues to read the idle code in the current queue buffer, returning to the initial state 7-1.

[0069] The brief working principle of the present invention is as follows:

[0070] The interface module 1 stores the configuration frame into the storage table module 3 and sends the service frame data to the data frame processing module 2.

[0071] The data frame processing module 2 extracts and stores the service frame information carrying the destination station address and the corresponding rate file information into the storage table module 3, extracts the destination station address of all service frame data, encapsulates it into the service frame header, and stores the service frame into the buffer module 4.

[0072] The buffer module 4 outputs the stored service frame destination address to the storage table module 3 for table lookup.

[0073] The storage table module 3 sends the wave position number and speed level information obtained by looking up the table to the queue writing control module 6.

[0074] The queue write control module 6 searches the dynamic linked table according to the rate level and wave number information provided by the storage table module 3, and looks for the table entry with the same rate level and wave number, that is, the corresponding queue buffer. According to the four-level threshold judgment condition provided by the queue buffer module 5, the business data of the buffer module 4 is stored in the corresponding queue buffer, and the queue buffer wave number and rate information are updated to the dynamic storage linked table of the queue read control module 7.

[0075] The queue reading control module 7 starts to judge the queue number of the next burst data selection at the end of the previous burst data frame, and judges whether the data in the queue buffer meets the fourth-level threshold conditions according to the five-level judgment criteria. If it is not empty, read the queue data. If none of them meet the conditions, keep reading the idle code of the previous queue.

[0076] In summary, the present invention utilizes dynamic storage linked list technology, adopts a queue management scheme, and uses a queue buffer to control the beam hopping of the phased array antenna for users with different rate levels and different wave position numbers, and the rate level changes burst by burst to provide data transmission for users.

[0077] The present invention is applicable to a phased array agile beam satellite transmitter. On a hardware platform with limited storage resources, it adopts a dynamic storage linked list technology to realize data transmission of multiple rate levels and multiple wave position number combinations, and has the advantages of stable performance, portability and good scalability.

Claims

1. A phased array agile beam transmission queue management device, comprising an interface module (1), a data frame processing module (2), and a queue buffer module (5), characterized in that: It also includes a storage table module (3), a buffer module (4), a queue writing control module (6), and a queue reading control module (7); The interface module (1) receives data from the outside, and if the data is a configuration frame, it sends it to the storage table module (3); if the data is a service frame, it sends it to the data frame processing module (2); The data frame processing module (2) extracts the destination station address and the corresponding speed file information from the service frame, sends the corresponding relationship between the destination station address and the speed file information to the storage table module (3), and sends the complete service frame to the buffer module (4); The storage table module (3) extracts the destination station address and the corresponding wave number information from the configuration frame, and stores the corresponding relationship between the destination station address and the wave number information and the corresponding relationship between the destination station address and the speed level information in two tables respectively; The buffer module (4) stores the service frames sent by the data frame processing module (2) in a first-in-first-out manner; The queue cache module (5) includes multiple cache queues, monitors the status information of each cache queue, and outputs four levels of thresholds to the queue write control module (6) and the queue read control module (7); The queue writing control module (6) is used to control the writing of data; After receiving the externally input burst frame tail pulse, the queue reading control module (7) determines the queue number to be selected for the next burst data and reads the cache data of the corresponding queue number in the queue cache module (5).

2. The phased array agile beam transmission queue management device according to claim 1, characterized in that: The thresholds of the four levels are: The first-level threshold is 1600, which is used to determine whether the remaining buffer space in the buffer is less than 1600 bytes; The secondary threshold is the rate level, which is used to determine whether the data in the current buffer can send a complete burst of data; The third-level threshold is 1, which is used to determine whether the buffer data is empty; The fourth level threshold is 2, which is used to determine whether the data storage time in the buffer exceeds 2 seconds.

3. The phased array agile beam transmission queue management device according to claim 2, characterized in that: The specific working mode of the queue writing control module (6) is: The queue writing control module (6) notifies the buffer module (4) to send the destination station address of the service frame at the head of the buffer module (4) to the storage table module (3). The storage table module (3) performs a table lookup according to the destination station address and transmits the rate file information and wave number information obtained from the table lookup to the queue writing control module (6). The queue writing control module (6) searches the dynamic linked table according to the rate file information and the wave number information. The dynamic linked table stores the corresponding relationship between the combination of the rate file information and the wave number information and the cache queue in the queue buffer module (5). The dynamic linked table is initially empty. If the corresponding cache queue is found, it is determined whether the service frame can be stored in the cache queue according to the first-level threshold provided by the queue buffer module (5). If it can be stored, the queue writing control module (6) notifies the buffer module (4) that it needs to be stored in the queue buffer module (5). ), the buffer module (4) stores the head business frame into the corresponding cache queue in the queue cache module (5); otherwise, it continues to wait until it can be stored in the corresponding cache queue; if the dynamic linked list is searched and no corresponding combination of rate gear information and wave position number information is found, it is judged whether there is an empty cache queue in the queue cache module (5) according to the three-level threshold provided by the queue cache module (5); if so, the head business frame in the memory module (4) is stored in the empty cache queue, and the combination of rate gear information and wave position number information corresponding to the business frame is added to the dynamic linked list, and a corresponding relationship between the new combination of rate gear information and wave position number information and the cache queue in the queue cache module (5) is established; if there is no empty cache queue, it continues to wait until an empty cache queue appears in the queue cache module (5).

4. The phased array agile beam transmission queue management device according to claim 3, characterized in that: The storage table module (3) has three states: a wave number information storage state (3-1), a speed level information storage state (3-2) and a table lookup state (3-3); In the wave number information storage state (3-1), the configuration frame data of the interface module (1) is parsed, and the destination station address and wave number information are extracted and stored in the first storage table; In the rate profile information storage state (3-2), the destination station address and rate profile information provided by the data frame processing module (2) are stored in the second storage table; In the table lookup state (3-3), a table lookup is performed in the first storage table and the second storage table according to the destination station address provided by the buffer module (4), and the acquired wave position number information and rate level information are sent to the queue write control module (6).

5. The phased array agile beam transmission queue management device according to claim 4, characterized in that: The buffer module (4) uses the off-chip memory and on-chip memory of the FPGA to form a first-level memory for storing business data before entering the queue buffer; the buffer module (4) includes a first data writing module (4-1), a data table lookup module (4-2) and a data reading module (4-3); The first data writing module (4-1) receives the service data from the data frame processing module (2), and stores it in the on-chip memory of the FPGA first, and stores it in the off-chip memory after the on-chip memory reaches the upper limit; The data table lookup module (4-2) reads the destination station address of the service frame header from the on-chip or off-chip memory and outputs it to the storage table module (3) for table lookup; The data reading module (4-3) receives a read flag from the queue writing control module (6), and when the read flag is pulled high, reads a complete service frame and outputs it to the corresponding queue number buffer of the queue buffer module (5).

6. The phased array agile beam transmission queue management device according to claim 4, characterized in that: The queue buffer module (5) comprises a second data writing module (5-1), a queue monitoring module (5-2) and a data output module (5-3); The second data writing module (5-1) stores the service data of the buffer module (4) into the corresponding queue buffer according to the queue number provided by the writing control module (6); The queue monitoring module (5-2) monitors the status parameters of the queue buffer and outputs the four-level threshold value to the queue writing control module (6) and the queue reading control module (7); The data output module (5-3) reads the data in the corresponding queue buffer according to the burst code block based on the burst enable and queue number sent by the queue reading control module (7).

7. The phased array agile beam transmission queue management device according to claim 6, characterized in that: The queue writing control module (6) uses a security state machine to sequentially judge the queue writing judgment conditions, and at the same time maintains a dynamic linked list, and maintains the queue wave position number and rate gear information; the queue writing control module (6) has four states: an initial state (6-1), a first-level judgment state (6-2), a second-level judgment state (6-3), and a threshold judgment state (6-4); the queue writing control module (6) also includes a dynamic linked list maintenance module (6-5); In the initial state (6-1), the wave position number and speed level information data are received from the storage table module (3), the safety state machine operation switch is triggered, and the first level judgment state (6-2) is entered; In the first-level judgment state (6-2), the dynamic linked table is queried to determine whether there is an entry with the same wave position number and rate file information. If they are consistent, the process enters the threshold judgment state (6-4). If there is no consistent entry, the process enters the second-level judgment state (6-3). In the secondary judgment state (6-3), it is judged whether there is an empty queue in the queue buffer. If there is an empty queue, the start writing queue flag signal is pulled high and output to the buffer module (4), the wave bit number and rate gear information corresponding to the service frame are stored in the dynamic linked list, and the initial state (6-1) is returned. If there is no empty queue, wait in the current state until an empty queue buffer appears; In the threshold judgment state (6-4), based on the first-level threshold value input by the queue buffer module (5), it is judged whether the queue buffer can store the next business data. If the queue buffer storage space does not reach the threshold value, the start writing queue flag signal is pulled high and output to the buffer module (4), and the initial state (6-1) is returned. If the queue buffer storage space has reached the threshold, wait in the current state until an empty queue buffer appears; The dynamic linked list maintenance module (6-5) includes n entries corresponding to the wave position numbers and rate file information corresponding to the n queue memories; The dynamic linked list maintenance module (6-5) updates the information data of each table item in real time and transmits the dynamic linked list data to the queue reading control module (7).

8. The phased array agile beam transmission queue management device according to claim 7, characterized in that: The queue reading control module (7) uses a security state machine to sequentially judge the queue writing judgment conditions, including six states: initial state (7-1), first-level judgment state (7-2), second-level judgment state (7-3), third-level judgment state (7-4), fourth-level judgment state (7-5) and fifth-level judgment state (7-6); In the initial state (7-1), after receiving the external input burst frame tail pulse, it enters the first-level judgment state (7-2); In the first-level judgment state (7-2), it is judged whether the data in the current queue buffer is empty. The current queue buffer refers to the queue number read during the last burst. The default queue buffer at power-on is queue No.

1. If it is empty, the second-level judgment state (7-3) is entered; if it is not empty, the data in the queue buffer is continued to be read, the wave position number and rate gear information of the queue buffer are queried from the dynamic storage linked table and output, and the next burst data pulse is output to the queue buffer module (5) to trigger the data reading of the queue buffer (5), and then the initial state (7-1) is returned; In the secondary judgment state (7-3), it is judged in turn whether each queue has reached the fourth-level threshold condition. If the fourth-level threshold condition is met, the queue data is read, and only one service frame data is read each time, and the wave position number and rate gear information of the queue are output, and the next burst data pulse is output to the queue buffer module (5), and then the initial state (7-1) is returned. If none of the queue buffers have reached the fourth-level threshold condition, the third-level judgment state (7-4) is entered. In the third-level judgment state (7-4), it is judged in turn whether each queue has reached the first-level threshold condition. If the first-level threshold condition is met, the queue data is read, the wave position number and rate gear information of the queue are output, the next burst data pulse is output to the queue buffer module (5), and then the initial state (7-1) is returned. If none of the queue buffers have reached the first-level threshold condition, the fourth-level judgment state (7-5) is entered. In the fourth-level judgment state (7-5), it is judged in turn whether each queue has reached the second-level threshold condition. If the second-level threshold condition is met, the queue data is read, the wave position number and rate gear information of the queue are output, the next burst data pulse is output to the queue buffer module (5), and then the initial state (7-1) is returned. If none of the queue buffers have reached the second-level threshold condition, the fifth-level judgment state (7-6) is entered. In the five-level judgment state (7-6), it is judged in turn whether each queue has reached the third-level threshold condition. If the third-level threshold condition is met, the queue data is read, the wave position number and rate gear information of the queue are output, the next burst data pulse is output to the queue buffer module (5), and then the initial state (7-1) is returned. If none of the queue buffers have reached the third-level threshold condition, the idle code of the current queue buffer is continued to be read, and then the initial state (7-1) is returned.

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