A bidirectional hysteresis TVS device with ultra-low capacitance and its preparation method

Abstract

The present invention provides a bidirectional hysteresis TVS device with ultra-low capacitance and a preparation method thereof. The bidirectional hysteresis TVS device with ultra-low capacitance is divided into two regions by a P-type substrate and an isolation layer embedded in the P-type substrate. The isolation layer divides the P-type substrate into two regions. One region includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer sequentially deposited on the P-type substrate, wherein the first N-type layer and the second N-type layer each include two laterally arranged regions with different doping concentrations, and the structures of the two regions in the first N-type layer and the second N-type layer are opposite. The other region includes a third N-type layer and a third P-type layer sequentially deposited on the P-type substrate. When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance is obtained by inverting all doping in the P-type substrate. The bidirectional hysteresis TVS device can meet positive / negative bidirectional transient voltage shock requirements while having ultra-low capacitance characteristics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bidirectional hysteresis TVS device with ultra-low capacitance and a preparation method thereof. Background Art

[0002] With the rapid development of 5G communications, the Internet of Things, and high-speed digital interfaces (such as USB4, HDMI 2.1, and Thunderbolt), electronic devices are placing increasingly stringent demands on the high-frequency characteristics and signal integrity of circuit protection components. Transient voltage suppressor (TVS) diodes, as core overvoltage protection components, have become a key factor limiting the performance of high-speed signal transmission.

[0003] Traditional TVS devices mostly utilize planar or mesa-shaped designs. While they offer high surge absorption capabilities, their junction capacitance is typically in the tens to hundreds of picofarads (typically 50pF to 200pF). When used in high-frequency circuits in the GHz range, parasitic capacitance can cause problems such as rising-edge signal distortion, severely impacting the transmission quality of high-speed interfaces like USB3.2 / DP2.0. In applications such as new energy vehicle BMS systems, industrial automation control, and high-precision medical equipment, circuit protection devices must also withstand both positive and negative bidirectional transient voltage surges while maintaining sub-picofarad parasitic capacitance (<0.5pF at 1MHz) in the signal path. Traditional bidirectional TVS devices typically utilize a back-to-back series unidirectional TVS structure. While this structure can achieve bidirectional voltage clamping, it lacks the required ultra-low capacitance.

[0004] Existing technologies also connect and package multiple chips with different characteristics to realize the multifunctional characteristics of the chip. However, this solution has two core defects: one is the matching and stability of each chip, and the other is the large size of the device, which makes it difficult to meet the requirements of micro-packaging. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a bidirectional hysteresis TVS device with ultra-low capacitance and a preparation method thereof, which is intended to meet the positive / negative bidirectional transient voltage impact and have ultra-low capacitance characteristics.

[0006] According to an embodiment of the present invention, a bidirectional hysteresis TVS device with ultra-low capacitance, when the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, includes a P-type substrate and an isolation layer embedded in the P-type substrate, wherein the isolation layer divides the P-type substrate into two regions;

[0007] One region includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer sequentially deposited on the P-type substrate, wherein the first N-type layer includes a first N-type region disposed laterally and a second N-type region with a lower doping concentration than the first N-type region, the second N-type layer includes a third N-type region disposed laterally and a fourth N-type region with a lower doping concentration than the third N-type region, the first N-type region and the fourth N-type region are located on the same side, and the second N-type region and the third N-type region are located on the same side;

[0008] Another region includes a third N-type layer and a third P-type layer sequentially deposited on the P-type substrate;

[0009] When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance can be obtained by inverting all doping in the bidirectional hysteresis TVS device with ultra-low capacitance whose substrate is P-type.

[0010] Furthermore, the total thickness of the first N-type layer, the first P-type layer, the second N-type layer, and the second P-type layer is less than the total thickness of the third N-type layer and the third P-type layer.

[0011] Furthermore, the doping elements of the P-type substrate and the third P-type layer are both boron, and the doping concentration range is 1E18cm -3 ~9E19cm -3 .

[0012] Furthermore, the doping element of the first P-type layer is boron, and the doping concentration range is 1E12cm -3 ~9E14cm -3 .

[0013] Furthermore, the thickness of the first P-type layer is 13 μm to 18 μm.

[0014] Furthermore, the doping element of the second P-type layer is boron, and the doping concentration range is 1E18cm -3 ~9E20cm -3 .

[0015] Furthermore, the first N-type layer and the second N-type layer have the same thickness, the doping element of the first N-type layer and the second N-type layer is phosphorus, the first N-type region and the third N-type region have the same doping concentration and area size, and the second N-type region and the fourth N-type region have the same doping concentration and area size.

[0016] Furthermore, the thickness of the first N-type layer and the second N-type layer are both in the range of 1 μm to 3 μm.

[0017] Furthermore, the doping concentration range of the first N-type region and the third N-type region is 1E17cm -3 ~9E18cm -3 The doping concentration range of the second N-type region and the fourth N-type region is 1E15cm -3 ~9E16cm -3 .

[0018] According to an embodiment of the present invention, a method for preparing a bidirectional hysteresis TVS device with ultra-low capacitance is used to prepare the bidirectional hysteresis TVS device with ultra-low capacitance. The method includes:

[0019] When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, a P-type substrate is provided, and a first N-type epitaxial layer is epitaxially grown on the P-type substrate, and then N+ doping is performed in the first N-type epitaxial layer;

[0020] epitaxially growing a first P-type epitaxial layer on the doped first N-type epitaxial layer;

[0021] epitaxially growing a second N-type epitaxial layer on the first P-type epitaxial layer, and then performing N+ doping in the second N-type epitaxial layer;

[0022] epitaxially growing a second P-type epitaxial layer on the doped second N-type epitaxial layer to obtain an initial epitaxial wafer;

[0023] Etching a trench at a first predetermined position of the initial epitaxial wafer until reaching the P-type substrate, and then depositing an oxide layer in the etched trench, wherein the region formed between the oxide layers includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer sequentially deposited on the P-type substrate;

[0024] Etching a groove at a second predetermined position of the oxide layer until reaching the P-type substrate, and then sequentially depositing a third N-type layer and a third P-type layer in the etched groove;

[0025] When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance can be obtained by inverting all doping in the bidirectional hysteresis TVS device with ultra-low capacitance whose substrate is P-type.

[0026] The beneficial effects of the present invention are:

[0027] The isolation layer is used to divide the P-type substrate into two regions through a P-type substrate and an isolation layer embedded in the P-type substrate; one region includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer with a doping concentration higher than that of the first P-type layer, which are sequentially deposited on the P-type substrate. The first N-type layer and the second N-type layer each include two regions with different doping concentrations arranged laterally, and the structures of the two regions in the first N-type layer and the second N-type layer are opposite. The opposite structures make the current more uniform in the structure. In addition, by adjusting the concentration of the region with high doping concentration in the first N-type layer and the second N-type layer, the depletion layer of the NP junction therein can be penetrated, so that The carriers are accelerated by the electric field in the depletion region to obtain a large current; the other region includes a third N-type layer and a third P-type layer deposited in sequence on a P-type substrate, and the PNP structure mainly plays the role of regulating the withstand voltage of the device; when the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance is obtained by inverting all doping in the substrate of P-type. Specifically, one side region is a structure for achieving ultra-low capacitance and regulating withstand voltage, and the other side region is a structure for achieving hysteresis characteristics and regulating withstand voltage, and the two regions are connected in series, which can make the capacitance of the device smaller or the hysteresis characteristics stronger. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of a bidirectional hysteresis TVS device with ultra-low capacitance provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a process flow for preparing a bidirectional hysteresis TVS device with ultra-low capacitance provided by an embodiment of the present invention.

[0030] Description of main component symbols:

[0031]

[0032] The following specific implementation methods will further illustrate this application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0034] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that to achieve ultra-low capacitance, a PIN structure is required, which uses an epitaxial layer with a higher resistivity and increases the width of the depletion region. However, a higher resistivity means a higher resistance and weaker current flow capacity. A small current can generate a large voltage, which fails to achieve the function of protecting the device. In order to solve the problem of the constraint between low capacitance and weak current flow capacity, the embodiment of the present invention provides a bidirectional hysteresis TVS device with ultra-low capacitance. Please refer to Figure 1 , is a schematic structural diagram of a bidirectional hysteresis TVS device with ultra-low capacitance provided by an embodiment of the present invention. Specifically, when the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, it includes a P-type substrate 1 and an isolation layer 2 embedded in the P-type substrate 1, and the isolation layer 2 divides the P-type substrate 1 into two regions. It can be understood that it includes isolation layers 2 embedded on both sides of the P-type substrate 1 and an isolation layer 2 embedded in the middle of the P-type substrate 1, wherein the isolation layer 2 is an oxide layer, and the width of the isolation layer 2 ranges from 1μm to 2μm. In the embodiment of the present invention, the isolation layer 2 divides the P-type substrate 1 into two regions, and different structures are correspondingly provided in the two regions;

[0037] One region includes a first N-type layer 3, a first P-type layer 4, a second N-type layer 5, and a second P-type layer 6 with a doping concentration higher than that of the first P-type layer 4, which are sequentially deposited on the P-type substrate 1. The first N-type layer 3 includes a first N-type region 31 disposed laterally and a second N-type region 32 with a doping concentration lower than that of the first N-type region 31. The second N-type layer 5 includes a third N-type region 51 disposed laterally and a fourth N-type region 52 with a doping concentration lower than that of the third N-type region 51. The first N-type region 31 and the fourth N-type region 52 are located on the same side, and the second N-type region 32 and the third N-type region 51 are located on the same side. It can be understood that the term "lateral arrangement" refers to a direction perpendicular to the epitaxial growth direction.

[0038] Specifically, the first N-type layer 3 deposited on the P-type substrate 1 includes a half-highly doped first N-type region 31 and a medium-doped second N-type region 32, followed by a thicker low-doped first P-type layer 4. The thickness of the first P-type layer 4 is 13 μm to 18 μm. For example, the thickness of the first P-type layer 4 is 13 μm, 14 μm, 15 μm, 16 μm, 17 μm or 18 μm, but is not limited thereto. The doping element of the first P-type layer 4 is boron, and the doping concentration range is 1E12 cm -3 ~9E14cm -3 , the second N-type layer 5 deposited upward has half of a highly doped third N-type region 51 and a medium-doped fourth N-type region 52. It can be understood that the first N-type layer 3 and the second N-type layer 5 have the same thickness, and the thickness range of the first N-type layer 3 and the second N-type layer 5 is 1μm~3μm. For example, the thickness of the first N-type layer 3 and the second N-type layer 5 is 1μm, 2μm or 3μm, etc., but not limited to this. The doping element of the first N-type layer 3 and the second N-type layer 5 is phosphorus, and the doping concentration and area size of the first N-type region 31 and the third N-type region 51 are the same, and the doping concentration and area size of the second N-type region 32 and the fourth N-type region 52 are the same. It should be noted that the doping concentration range of the first N-type region 31 and the third N-type region 51 is 1E17cm -3 ~9E18cm -3 The doping concentration range of the second N-type region 32 and the fourth N-type region 52 is 1E15cm -3 ~9E16cm -3 .

[0039] The doping concentration regions in the first N-type layer 3 and the second N-type layer 5 are in opposite positions to make the current more uniform in the structure. Above them is the highly doped second P-type layer 6. The thickness of the second P-type layer 6 ranges from 1 μm to 3 μm. The doping element of the second P-type layer 6 is boron, and the doping concentration range is 1E18 cm -3 ~9E20cm -3 .

[0040] The first N-type region 31 and the third N-type region 51, located above and below the first P-type layer 4, are adjusted to appropriate concentrations to allow the depletion layers of the upper and lower NP junctions to penetrate. This allows carriers to be accelerated by the electric field in the depletion region, resulting in a large current. The doping concentration of the second N-type region 32 is lower than that of the first N-type region 31 to facilitate conduction of the PNPN structure. The addition of the second P-type layer 6 creates a symmetrical PNPN structure, further increasing the current flow capacity and placing the device in a low-impedance state, which also exhibits hysteresis characteristics. Furthermore, the first N-type layer 3 forms a PN junction with the P-type substrate 1 and the second P-type layer 6. Regardless of whether a positive or negative voltage is applied above, one PN junction is always reverse biased. A large current only flows through the PN junction after avalanche breakdown. This reverse-biased PN junction also contributes to the device's withstand voltage.

[0041] The other region includes a third N-type layer 7 and a third P-type layer 8 sequentially deposited on the P-type substrate 1. The doping elements of the P-type substrate 1 and the third P-type layer 8 are both boron, and the doping concentration range is 1E18cm -3 ~9E19cm -3 It should be noted that the PNP structure composed of the P-type substrate 1, the third N-type layer 7 and the third P-type layer 8 in this region mainly plays the role of regulating the withstand voltage of the device. Due to the low hole mobility in the PNP structure, when the P-type semiconductor is used as the substrate, the hysteresis characteristics of the entire device are weak.

[0042] It should be noted that the total thickness of the first N-type layer 3 , the first P-type layer 4 , the second N-type layer 5 and the second P-type layer 6 is less than the total thickness of the third N-type layer 7 and the third P-type layer 8 .

[0043] Furthermore, the structures in the left and right regions are both vertically symmetrical, with electrodes 9 provided on both the second P-type layer 6 and the third P-type layer 8, giving the device bidirectional symmetry. The low-capacitance structure on the left and the structure on the right are connected in series, which results in even lower capacitance.

[0044] When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance is obtained by inverting all the doping in the substrate with P-type, that is, the P-type becomes N-type, and the N-type becomes P-type. At this time, the electron mobility in the formed NPN structure is high, so the hysteresis characteristics of the entire device are strong.

[0045] In order to prepare the above-mentioned bidirectional hysteresis TVS device with ultra-low capacitance, the embodiment of the present invention provides a method for preparing a bidirectional hysteresis TVS device with ultra-low capacitance, please refer to Figure 2 , Figure 2A schematic diagram of a process flow for preparing a bidirectional hysteresis TVS device with ultra-low capacitance provided by an embodiment of the present invention. When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, the method specifically includes the following steps:

[0046] S100: providing a P-type substrate 1, and epitaxially growing a first N-type epitaxial layer 30 on the P-type substrate 1, and then performing N+ doping in the first N-type epitaxial layer 30;

[0047] Specifically, the P-type substrate 1 is doped with boron at a concentration of 1E18 cm -3 ~9E19cm -3 The thickness of the grown first N-type epitaxial layer 30 is 1 μm to 3 μm, and the doping concentration is 1E15 cm -3 ~9E16cm -3 On this basis, N+ doping is performed on a portion of the first N-type epitaxial layer 30. The doping element is phosphorus, and the concentration range after doping is 1E17cm -3 ~9E18cm -3 , that is, the first N-type region 31 is obtained.

[0048] S200: epitaxially growing a first P-type epitaxial layer 40 on the doped first N-type epitaxial layer 30;

[0049] The first P-type epitaxial layer 40 with high resistivity is epitaxially grown. The thickness of the first P-type epitaxial layer 40 is 13 μm to 18 μm, and the doping element is boron with a doping concentration range of 1E12 cm -3 ~9E14cm -3 .

[0050] S300: epitaxially growing a second N-type epitaxial layer 50 on the first P-type epitaxial layer 40, and then performing N+ doping in the second N-type epitaxial layer 50;

[0051] It should be noted that the thickness of the second N-type epitaxial layer 50 is 1 μm to 3 μm, and the doping concentration is 1E15 cm -3 ~9E16cm -3 On this basis, N+ doping is performed on a portion of the second N-type epitaxial layer 50. The doping element is phosphorus, and the concentration range after doping is 1E17cm -3 ~9E18cm -3 , that is, the third N-type region 51 is obtained.

[0052] S400: epitaxially growing a second P-type epitaxial layer 60 on the doped second N-type epitaxial layer 50 to obtain an initial epitaxial wafer;

[0053] The doping element of the second P-type epitaxial layer 60 is boron, and the doping concentration range is 1E18cm-3 ~9E20cm -3 The thickness of the second P-type epitaxial layer 60 is in the range of 0.5 μm to 3 μm.

[0054] S500: etching a trench at a first predetermined position of the initial epitaxial wafer until reaching the P-type substrate, and then depositing an oxide layer in the etched trench;

[0055] It can be understood that after etching is completed and the oxide layer is deposited again, the region formed between the oxide layers includes the first N-type layer 3, the first P-type layer 4, the second N-type layer 5, and the second P-type layer 6 sequentially deposited on the P-type substrate, wherein the first N-type layer 3 includes a laterally arranged first N-type region 31 and a second N-type region 32 with a doping concentration lower than that of the first N-type region 31, and the second N-type layer 5 includes a laterally arranged third N-type region 51 and a fourth N-type region 52 with a doping concentration lower than that of the third N-type region 51, and the first N-type region 31 and the fourth N-type region 52 are located on the same side, and the second N-type region 32 and the third N-type region 51 are located on the same side;

[0056] S600 : etching a trench at a second preset position of the oxide layer until reaching the P-type substrate 1 , and then sequentially depositing a third N-type layer 7 and a third P-type layer 8 in the etched trench.

[0057] A trench is etched at a second preset position of the oxide layer until it reaches the P-type substrate 1, thereby obtaining an isolation layer 2 embedded in the P-type substrate 1. Subsequently, a third N-type layer 7 and a third P-type layer 8 are sequentially deposited in the trenches formed between the isolation layers 2, wherein the position of the lower surface of the third N-type layer 7 is lower than the position of the lower surface of the first N-type layer 3, and the position of the lower surface of the third N-type layer 7 differs from the position of the lower surface of the first N-type layer 3 by 0.5 μm to 1 μm.

[0058] Specifically, the thickness of the third N-type layer 7 is in the range of 4 μm to 8 μm. For example, the thickness of the third N-type layer 7 is 4 μm, 5 μm, 6 μm, 7 μm or 8 μm, but not limited thereto. The doping element of the third N-type layer 7 is phosphorus, and the doping concentration range is 1E16 cm -3 ~9E17cm -3 The doping element of the third P-type layer 8 is boron, and the doping concentration range is 1E18cm -3 ~9E19cm -3 The upper surfaces of the third P-type layer 8 , the second P-type layer 6 and the isolation layer 2 are flush.

[0059] Finally, an oxide layer is deposited as a dielectric layer (not shown), CT (through hole) etching is performed at corresponding positions of the third P-type layer 8 and the second P-type layer 6, and then metal aluminum is deposited to form two electrodes 9 of the low-capacitance TVS.

[0060] In some other embodiments of the present invention, when the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance can be obtained by inverting all doping in the above-mentioned bidirectional hysteresis TVS device with ultra-low capacitance whose substrate is P-type.

[0061] The bidirectional hysteresis TVS device with ultra-low capacitance prepared by the above method has the following beneficial effects:

[0062] 1. Meet the requirements of positive / negative bidirectional transient voltage impact and have ultra-low capacitance characteristics;

[0063] 2. It has hysteresis characteristics, which can suppress transient voltage at a lower clamping voltage, helping to release energy in advance and greatly protecting the safety of IC and downstream circuits;

[0064] 3. The strength of the hysteresis characteristic can be selected and adjusted according to the substrate type and doping;

[0065] 4. All functions are integrated on one chip, eliminating multi-chip matching and stability issues. It is small in size and can be packaged in a micro form factor.

[0066] 5. The device electrodes are all on the front of the chip, and there is no need for back-gold processing, which reduces costs and tape-out time.

[0067] The present invention will be further described below with specific embodiments:

[0068] Example 1

[0069] Embodiment 1 of the present invention provides a bidirectional hysteresis TVS device with ultra-low capacitance. When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, the device comprises a P-type substrate and an isolation layer embedded in the P-type substrate, wherein the isolation layer divides the P-type substrate into two regions.

[0070] One region includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer sequentially deposited on the P-type substrate, wherein the first N-type layer includes a first N-type region disposed laterally and a second N-type region with a lower doping concentration than the first N-type region, the second N-type layer includes a third N-type region disposed laterally and a fourth N-type region with a lower doping concentration than the third N-type region, the first N-type region and the fourth N-type region are located on the same side, and the second N-type region and the third N-type region are located on the same side;

[0071] Another region includes a third N-type layer and a third P-type layer sequentially deposited on the P-type substrate;

[0072] Among them, the concentrations of the P-type substrate, the second P-type layer, and the third P-type layer are all 1E18cm-3 The thickness of the first N-type layer and the second N-type layer are both 2 μm, and the concentration of the first N-type region and the third N-type region are both 1E17 cm -3 The concentrations of the second N-type region and the fourth N-type region are both 5E15cm -3 The thickness of the first P-type layer is 15 μm, and the concentration of the first P-type layer is 1E13 cm -3 , the thickness of the third N-type layer is 6μm, and the concentration of the third N-type layer is 5E17cm -3 , the thickness of the second P-type layer is 3 μm, and the thickness of the third P-type layer is 17 μm.

[0073] Example 2

[0074] Example 2 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentration of the third N-type layer is 7E17cm -3 .

[0075] Example 3

[0076] Example 3 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentration of the third N-type layer is 5E16cm -3 .

[0077] Example 4

[0078] Embodiment 4 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Embodiment 1 is that the thickness of the first N-type layer and the second N-type layer are both 1.5 μm, and the thickness of the second P-type layer is 4 μm.

[0079] Example 5

[0080] Embodiment 5 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Embodiment 1 is that the thickness of the first N-type layer and the second N-type layer are both 1 μm, and the thickness of the second P-type layer is 5 μm.

[0081] Example 6

[0082] Embodiment 6 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance, which differs from Embodiment 1 in that the thickness of the first P-type layer is 12 μm, and the thickness of the second P-type layer is 6 μm.

[0083] Example 7

[0084] Example 7 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance, which differs from Example 1 in that the thickness of the first P-type layer is 9 μm, and the thickness of the second P-type layer is 9 μm.

[0085] Example 8

[0086] Example 8 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentration of the first P-type layer is 1E14 cm -3 .

[0087] Example 9

[0088] Example 9 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentration of the first P-type layer is 9E14cm -3 .

[0089] Example 10

[0090] Example 10 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentrations of the second N-type region and the fourth N-type region are both 1E15 cm -3 , the concentration of the third N-type layer is 5E16cm -3 .

[0091] Example 11

[0092] Example 11 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance. The difference from Example 1 is that the concentrations of the second N-type region and the fourth N-type region are both 9E15cm -3 , the concentration of the third N-type layer is 5E16cm -3 .

[0093] Example 12

[0094] Embodiment 12 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance, which differs from Embodiment 1 in that the thickness of the third N-type layer is 4 μm, and the thickness of the third P-type layer is 19 μm.

[0095] Example 13

[0096] Embodiment 13 of the present invention also provides a bidirectional hysteresis TVS device with ultra-low capacitance, which differs from Embodiment 1 in that the thickness of the third N-type layer is 8 μm, and the thickness of the third P-type layer is 15 μm.

[0097] The bidirectional hysteresis TVS devices with ultra-low capacitance in Examples 1 to 13 were tested under the same conditions, and the specific results are as follows:

[0098]

[0099] It can be seen from the above table that in order to obtain an ultra-low capacitance bidirectional hysteresis TVS device, the thickness of the first P-type layer cannot be too thin (please refer to Example 1, Example 6 and Example 7), and the concentration cannot be too high (please refer to Example 1, Example 8 and Example 9); the thickness and concentration of the first N-type region, the second N-type region, the third N-type region and the fourth N-type region will affect the breakdown voltage and hysteresis voltage, and can be adjusted as needed; the concentration (please refer to Example 1, Example 2 and Example 3) and thickness (please refer to Example 1, Example 12 and Example 13) of the third N-type layer will also affect the breakdown voltage and hysteresis voltage, and the breakdown voltage and hysteresis voltage are jointly determined by the devices on the left and right sides.

[0100] In summary, the bidirectional hysteresis TVS device with ultra-low capacitance and the preparation method thereof in the embodiments of the present invention are obtained by a P-type substrate and an isolation layer embedded in the P-type substrate, and the isolation layer divides the P-type substrate into two regions; one region includes a first N-type layer, a first P-type layer, a second N-type layer and a second P-type layer sequentially deposited on the P-type substrate, wherein the first N-type layer and the second N-type layer both include two regions with different doping concentrations arranged laterally, and the structures of the two regions in the first N-type layer and the second N-type layer are opposite; the other region includes a third N-type layer and a third P-type layer sequentially deposited on the P-type substrate; when the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance is obtained by inverting all doping in the P-type substrate, specifically, one side region is a structure for realizing ultra-low capacitance and regulating withstand voltage, and the other side region is a structure for realizing hysteresis characteristics and regulating withstand voltage, and the two regions are connected in series, which can make the capacitance of the device smaller or the hysteresis characteristics stronger.

[0101] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A bidirectional hysteresis TVS device with ultra-low capacitance, characterized in that: When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, the device comprises a P-type substrate and an isolation layer embedded in the P-type substrate, wherein the isolation layer divides the P-type substrate into two regions; One region includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer deposited sequentially from bottom to top on the P-type substrate, wherein the first N-type layer includes a first N-type region disposed laterally and a second N-type region having a lower doping concentration than the first N-type region, the second N-type layer includes a third N-type region disposed laterally and a fourth N-type region having a lower doping concentration than the third N-type region, the first N-type region and the fourth N-type region are located on the same side, and the second N-type region and the third N-type region are located on the same side; Another region includes a third N-type layer and a third P-type layer sequentially deposited from bottom to top on the P-type substrate; When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance can be obtained by inverting all doping in the bidirectional hysteresis TVS device with ultra-low capacitance whose substrate is P-type.

2. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 1, characterized in that: The total thickness of the first N-type layer, the first P-type layer, the second N-type layer, and the second P-type layer is less than the total thickness of the third N-type layer and the third P-type layer.

3. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 2, characterized in that: The doping elements of the P-type substrate and the third P-type layer are both boron, and the doping concentration range is 1E18cm -3 ~9E19cm -3 .

4. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 3, characterized in that: The doping element of the first P-type layer is boron, and the doping concentration range is 1E12cm -3 ~9E14cm -3 .

5. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 4, characterized in that: The thickness of the first P-type layer is 13 μm to 18 μm.

6. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 5, characterized in that: The doping element of the second P-type layer is boron, and the doping concentration range is 1E18cm -3 ~9E20cm -3 .

7. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 6, characterized in that: The first N-type layer and the second N-type layer have the same thickness, the doping elements of the first N-type layer and the second N-type layer are both phosphorus, the first N-type region and the third N-type region have the same doping concentration and area size, and the second N-type region and the fourth N-type region have the same doping concentration and area size.

8. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 7, characterized in that: The thickness of the first N-type layer and the second N-type layer are both in the range of 1 μm to 3 μm.

9. The bidirectional hysteresis TVS device with ultra-low capacitance according to claim 8, characterized in that: The doping concentration range of the first N-type region and the third N-type region is 1E17 cm -3 ~9E18cm -3 The doping concentration range of the second N-type region and the fourth N-type region is 1E15cm -3 ~9E16cm -3 .

10. A method for preparing a bidirectional hysteresis TVS device with ultra-low capacitance, characterized in that: A method for preparing a bidirectional hysteresis TVS device with ultra-low capacitance according to any one of claims 1 to 9, comprising: When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is P-type, a P-type substrate is provided, and a first N-type epitaxial layer is epitaxially grown on the P-type substrate, and then N+ doping is performed in the first N-type epitaxial layer; epitaxially growing a first P-type epitaxial layer on the doped first N-type epitaxial layer; epitaxially growing a second N-type epitaxial layer on the first P-type epitaxial layer, and then performing N+ doping in the second N-type epitaxial layer; epitaxially growing a second P-type epitaxial layer on the doped second N-type epitaxial layer to obtain an initial epitaxial wafer; Etching a trench at a first predetermined position of the initial epitaxial wafer until reaching the P-type substrate, and then depositing an oxide layer in the etched trench, wherein the region formed between the oxide layers includes a first N-type layer, a first P-type layer, a second N-type layer, and a second P-type layer sequentially deposited on the P-type substrate; Etching a groove at a second predetermined position of the oxide layer until reaching the P-type substrate, and then sequentially depositing a third N-type layer and a third P-type layer in the etched groove; When the substrate of the bidirectional hysteresis TVS device with ultra-low capacitance is N-type, the bidirectional hysteresis TVS device with ultra-low capacitance can be obtained by inverting all doping in the bidirectional hysteresis TVS device with ultra-low capacitance whose substrate is P-type.

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