A passivation method of silicon cell, a preparation method of silicon-calcium laminated cell and a device

Abstract

The application relates to a passivation method of a silicon cell piece, which comprises the following steps: placing the silicon cell piece in a reaction cavity, and exposing a to-be-passivated region on the silicon cell piece to the reaction cavity; conveying a gaseous passivation material into the reaction cavity, the passivation material being tri(2,2-dimethylpropyl)aluminum, and the passivation material being input into the reaction cavity through a carrier gas; pulse-conveying an oxygen source into the reaction cavity, the oxygen source and the passivation material interacting to passivate the to-be-passivated region; the oxygen source, the tri(2,2-dimethylpropyl)aluminum and silicon dangling bonds interacting to passivate the dangling bonds and generate aluminum oxide in the passivated region; after the passivation, the silicon cell piece is taken out, annealed and the passivated silicon cell piece is obtained. The method effectively reduces the defect state density of the silicon cell piece, and further improves the cell efficiency. The passivation method in the application can be used not only for passivating the silicon cell piece in a silicon-calcium laminated cell, but also for a crystalline silicon cell or other silicon cell piece products which need to be passivated.

Description

TECHNICAL FIELD

[0001] The present application relates to a passivation method of a silicon cell piece, a preparation method of a silicon-calcium laminated cell and a device, and belongs to the field of new energy. BACKGROUND

[0002] With the continuous growth of global energy demand, solar energy as a clean and renewable energy has attracted widespread attention. At present, crystalline silicon solar cells (including single crystal silicon and polycrystalline silicon) are the mainstream technology in the market, and their photoelectric conversion efficiency has approached the theoretical limit. The highest efficiency of single crystal silicon cell in the laboratory is 26%-27%, and the efficiency of polycrystalline silicon cell is generally between 20%-22%, but in practical application, due to the influence of manufacturing process, material defects and environmental factors, its efficiency is usually lower. In addition, crystalline silicon cells will exhibit a light-induced degradation phenomenon under long-term illumination, which will lead to a gradual decline in performance, limiting their long-term stability and power generation capacity.

[0003] In recent years, perovskite solar cells have become a research hotspot due to their excellent photoelectric performance. The theoretical efficiency of single-junction perovskite cells can reach 31%, and by combining with crystalline silicon cells to form a laminated structure, the theoretical efficiency is expected to break through 45%. Perovskite materials have the advantages of abundant raw materials and low cost, and the preparation cost of its core components (such as metal halides) is much lower than that of high-purity silicon materials. At the same time, perovskite cells can be prepared by solution methods (such as spin coating, inkjet printing, slot coating, etc.), which have simple process, low energy consumption and are suitable for large-area industrial production, significantly reducing the manufacturing cost.

[0004] However, perovskite / crystalline silicon laminated cells still face challenges in practical application. On the silicon-based substrate, the dangling bonds and defect states generated during the cutting process of the silicon cell piece will cause non-radiative recombination of carriers, leading to a decrease in open-circuit voltage (Voc) and fill factor (FF), and thus affecting the overall performance of the cell. Therefore, how to effectively suppress interface recombination and improve carrier collection efficiency has become a key technical problem for improving the efficiency of perovskite / crystalline silicon laminated cells. SUMMARY

[0005] In order to passivate the dangling bonds or defects of the edge of the silicon cell piece, a passivation method of a silicon cell piece is proposed, which effectively reduces the defect state density after passivation, thereby improving the cell efficiency. The passivation method in the present application can not only be used for passivating the silicon cell piece in the silicon-calcium laminated cell, but also can be used for crystalline silicon cells or other silicon cell pieces that need to passivate dangling bonds.

[0006] One of the schemes adopted by the present application is: a passivation method of a silicon cell piece, comprising the following steps

[0007] S01, place the silicon cell piece in a reaction cavity, and expose the to-be-passivated area of the silicon cell piece to the reaction cavity;

[0008] S02 delivering a passivation material into the reaction cavity, the passivation material being tris(2,2-dimethylpropyl)aluminum, the passivation material being delivered into the reaction cavity through a carrier gas;

[0009] S03 delivering an oxygen source into the reaction cavity in a pulse form, the oxygen source and the tris(2,2-dimethylpropyl)aluminum generating aluminum oxide in the region to be passivated;

[0010] S04 repeating S02 and S03 for a set number of times or for a set time;

[0011] S05 taking out the silicon wafer, annealing, and obtaining a passivated silicon wafer.

[0012] As a preferred mode, the passivation material is delivered into the reaction cavity through a carrier gas in a pulse form, the pulse time being 0.05-0.2s, and an inert gas or the carrier gas is used for purging after the pulse is over. The concentration of the aluminum source in the reaction cavity during the pulse is (0.1-0.5)mg / cycle·cm², and the input rate of the aluminum source is (10-50)scem.

[0013] As a preferred mode, the oxygen source is O3 or H2O, and the oxygen source is delivered into the reaction cavity in a pulse form, the pulse time being 0.02-0.1s, and an inert gas or the carrier gas is used for purging after the pulse is over.

[0014] As a preferred mode, step S02 specifically comprises heating tris(2,2-dimethylpropyl)aluminum to 80-100℃ and then delivering it into the reaction cavity, and the tris(2,2-dimethylpropyl)aluminum is adsorbed on the surface of the region to be passivated.

[0015] As a preferred mode, the number of times of repeating step S02 and step S03 is 50-200, and the thickness of the aluminum oxide film generated in the region to be passivated is 5-20nm.

[0016] As a preferred mode, the annealing temperature of step S05 is 0-150℃.

[0017] The second aspect is a device comprising the silicon wafer obtained by the passivation method of the first aspect.

[0018] The third aspect is a method for preparing a silicon-calcium laminated battery, comprising the following steps:

[0019] S01 obtaining a silicon wafer: the silicon wafer is processed by the passivation method of the first aspect;

[0020] S02 Preparing a hole transport layer: depositing a hole transport layer on the silicon wafer, the hole transport layer containing at least one hole transport material, the hole transport layer being deposited by one or more of spin coating, blade coating, printing, magnetron sputtering, evaporation, atomic deposition;

[0021] S03 Preparing a perovskite layer: depositing a perovskite layer on the hole transport layer, the hole transport layer being in direct or indirect contact with the perovskite layer, the indirect contact being through an intermediate layer, the perovskite layer containing at least one perovskite light-absorbing material;

[0022] S04 Preparing an electron transport layer: depositing an electron transport layer on the perovskite layer, the electron transport layer being in direct or indirect contact with the perovskite layer, the indirect contact being through an intermediate layer, the electron transport layer containing at least one electron transport material;

[0023] S05 Preparing an electrode layer.

[0024] As a preferred mode, the hole transport material is MeO-2PACz, and the perovskite light-absorbing material of the perovskite layer is Cs x1 FA x2 MA （1-x1-x2） Pb(I y1 Br （1-y1） )3, 0

[0025] As a preferred mode, the to-be-passivated region of the silicon wafer is a cutting surface produced when the silicon wafer is cut, and the dangling bond is a dangling bond on the cutting surface.

[0026] As a preferred mode, the method for preparing the hole transport layer is:

[0027] a mixing MeO-2PACz with an ethanol solution to obtain a MeO-2PACz solution;

[0028] b spin coating the MeO-2PACz solution on the silicon wafer to obtain a MeO-2PACz hole transport layer.

[0029] The method for preparing the perovskite layer is:

[0030] a dissolving FAI, FABr, MAI, MABr, PbI2, PbBr2, and CsI in N-N dimethylformamide and dimethyl sulfoxide to obtain a precursor solution,

[0031] b heating the precursor solution to completely dissolve to obtain a Cs x1 FA x2 MA （1-x1-x2） Pb(I y1 Br （1-y1） )3 solution;

[0032] c Cs x1 FA x2 MA （1-x1-x2） Pb(I y1 Br （1-y1） )3 solution is spin-coated on the hole transport layer, and toluene is added dropwise when spin-coating to a set time;

[0033] d annealing under nitrogen atmosphere to obtain a perovskite layer.

[0034] The beneficial effects generated by the present application are: the present application uses TDMAP-Al as a passivation material precursor, in which the aluminum atom is surrounded by three tert-butyl groups, the steric hindrance is low, thereby reducing the reaction rate of each ALD cycle, allowing O3 to fully oxidize the aluminum atom center, in addition, the low-temperature reactivity of the material is controllable, and a dense and low-interface-state aluminum oxide layer can be generated under low-temperature conditions, which is suitable for uniform coverage of steep edge structures. DETAILED DESCRIPTION

[0035] The present application will be described in more detail below, but should not be understood as limiting the scope of protection of the present application to the following description. Unless otherwise specified, any range described in the present application includes the end values and any numerical value between the end values and any sub-range formed by the end values or any numerical value. The purity of all raw materials in the present application is not particularly limited, and the present application preferably uses analytical pure. The source and abbreviation of all raw materials in the present application belong to the conventional source and abbreviation in the art, and are clear and explicit in the field of their related use. The skilled person can purchase or prepare them by conventional methods according to the abbreviation and the corresponding use.

[0036] "at least one" means one or more, "a plurality of" means two or more. "And / or" describes the association between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0037] Those skilled in the art will appreciate that the perovskite material can be represented by the general formula [A][B][X]3, wherein [A] is at least one monovalent cation, [B] is at least one divalent cation, and [X] is at least one anion. When the perovskite includes more than one A cation, the different A cations can be distributed in an ordered or disordered manner over the A sites. When the perovskite includes more than one B cation, the different B cations can be distributed in an ordered or disordered manner over the B sites. When the perovskite includes more than one X anion, the different X anions can be distributed in an ordered or disordered manner over the X sites.

[0038] The present application proposes a passivation method for the dangling bonds of a silicon wafer, aiming to reduce the defect state density of the silicon wafer, increase the carrier transport efficiency, and improve the cell efficiency. The proposed passivation method for the silicon wafer is preferably processed in an atomic deposition device, including the following steps: S01 placing the silicon wafer in the reaction cavity of the atomic deposition device and exposing the to-be-passivated area, if the silicon wafer is due to the dangling bonds generated in the cutting process, the to-be-passivated area is the cutting surface; S02 starting the device, and conveying the passivation material tris(2,2-dimethylpropyl) aluminum into the reaction cavity, preferably the passivation material is a powder, mixed with a carrier gas, heated and gasified, and then conveyed to the reaction cavity, the carrier gas is a protective gas, preferably nitrogen, and the passivation material is adsorbed on the surface of the to-be-passivated area to form a monolayer coverage; S03 stopping the conveying of tris(2,2-dimethylpropyl) aluminum, and conveying an oxygen source into the reaction cavity, the oxygen source reacts with the passivation material on the to-be-passivated surface to form aluminum oxide and passivate the dangling bonds; S04 repeating steps S02 and S03 for a certain number of times or until the passivation is completed; S05 taking out the silicon wafer after the passivation is completed, and annealing in a nitrogen atmosphere to obtain the required silicon wafer. The annealing temperature is preferably 100-150℃, and more preferably 140-150℃, which will not destroy the perovskite structure, and will cause the incomplete decomposition of TDMAP-Al to be decomposed again, avoiding the generation of defects.

[0039] As an embodiment, the passivation material is heated to 70-90°C, preferably to 80°C, and then delivered into the reaction cavity for reaction. At this temperature, the vapor pressure of TDMAP-Al in the carrier gas N2 can form a stable gas flow, so as to deliver the mixed gas of the passivation material and the carrier gas into the reaction cavity in the form of pulses, and the pulse time is 0.05-0.2s. In a specific implementation, the pulse time can be set to 0.05s, 0.07s, 0.09s, 0.1s, 0.12s, 0.18s, or 0.2s. After the pulse is over, the inert gas or the carrier gas is introduced to remove the unreacted passivation material. After the purging is completed, the oxygen source is introduced in the form of pulses. The oxygen source in the present application can be O3 or H2O, which is introduced in the form of gas. If O3 is used, 200g / Nm3 of O3 is introduced in the reaction, and the pulse time is 0.02-0.1s. In a specific implementation, the pulse time can be 0.02s, 0.06s, 0.09s, or 0.1s. After the pulse is over, the inert gas or the carrier gas is introduced to remove the by-products, and the purging time is 5-10s, which can be 5s, 6s, 7s, 9s, or 10s. The passivation material and the oxygen source are introduced in cycles to fully passivate the silicon wafer. The reaction process involved in this process is as follows:

[0040] (1) Main reaction: Al(CH2C(CH3)3)3(g)+O3(g)→Al-O*+(CH2C(CH3)3)2O(g)+by-products

[0041] (2) Subsequent O3 pulse further oxidizes Al-O* to Al2O3:

[0042] 2Al-O*+O3→Al2O3+O2(g)

[0043] The overall reaction formula is as follows:

[0044] 2Al(CH2C(CH3)3)3+3O3→Al2O3+6(CH3)2C=CH2↑+3H2↑+O2↑. After multiple cycles, 5-20nm thick Al2O3 is finally generated. After the reaction is over, the silicon wafer is taken out and annealed at 100-150°C to obtain the processed silicon wafer.

[0045] The silicon cell wafer in the application can be used to prepare a silicon cell, a silicon-calcium laminated solar cell, and as a silicon substrate in the silicon-calcium laminated solar cell, which is conducive to reducing the non-radiative recombination of carriers and improving the cell efficiency. The silicon-calcium laminated solar cell can be a two-terminal cell or a four-terminal cell, and the silicon cell is arranged on the light side and the perovskite cell is arranged on the back light side, or the silicon cell is arranged on the back light side and the perovskite cell is arranged on the light side. The silicon cell can be an HJT cell, a PERC cell or a TOPCON cell, and the perovskite cell can be a positive perovskite cell or a negative perovskite cell. The preparation method is described in detail below taking a two-terminal laminated cell as an example. The two-terminal laminated cell takes a silicon cell as a bottom cell and a negative perovskite cell as a top cell.

[0046] The preparation method of the two-terminal laminated cell is as follows:

[0047] S01 Obtaining a silicon cell wafer: cutting a silicon cell wafer of a desired size as needed, and performing passivation using the passivation method of the silicon cell wafer in the application;

[0048] S02 Preparing a hole transport layer: preparing a hole transport layer on the silicon cell wafer, or preparing a hole transport layer after preparing a first intermediate layer, which can be one or more layers such as a tunneling layer, a conductive layer, a modification layer, a passivation layer, etc. The hole transport layer contains one or more hole transport materials, which can or can not contain additives, and the hole transport material can be nickel oxide, copper oxide, SAM material, carbazole material, thiophene material, etc. The deposition method can be one or a combination of spin coating, blade coating, printing, magnetron sputtering, evaporation, and atomic deposition. The preferred preparation method is as follows: a mixing MeO-2PACz with an ethanol solution to obtain a MeO-2PACz solution; b spin coating the MeO-2PACz solution on the silicon cell wafer to obtain a MeO-2PACz hole transport layer;

[0049] S03 Preparation of perovskite layer: prepare perovskite layer on the hole transport layer, or prepare perovskite layer after preparing the second intermediate layer, which can be one or more layers such as one or more of the energy level transition layer, the modification layer, the passivation layer, the light adjustment layer, the perovskite layer contains at least one perovskite material, which generates electrons and holes under light excitation, the electrons are extracted and exported by the electron transport layer, and the holes are extracted and exported by the hole transport layer, the perovskite layer can contain additives in addition to the perovskite material, the perovskite layer can be one or more layers, when the perovskite layer is multiple layers, it can include perovskite layers with different band gaps to improve light absorption, and the preparation method of the perovskite layer can be one or a combination of more than one of spin coating, blade coating, printing, magnetron sputtering, evaporation, and atomic deposition, such as inorganic layer prepared by evaporation and organic layer prepared by spin coating, thereby obtaining a high-quality perovskite layer. The preferred preparation method is: a. Dissolve FAI, FABr, MAI, MABr, PbI2, PbBr2, and CsI in N-N dimethylformamide and dimethyl sulfoxide at a set ratio to obtain a precursor solution; b. Heat the precursor solution to complete dissolution to obtain a Cs x1 FA x2 MA （1-x1-x2） Pb(I y1 Br （1-y1） )3 solution; c. Spin coating the solution on the hole transport layer and adding toluene dropwise when spin coating to a set time; d. Annealing under nitrogen atmosphere to obtain a perovskite layer. Cs x1 FA x2 MA （1-x1-x2） Pb(I y1 Br （1-y1） )3 is preferably Cs 0.1 FA 0.2 MA 0.7 Pb(I 0.76 Br 0.24 )3;

[0050] S04 Preparation of electron transport layer: prepare the electron transport layer on the perovskite layer, or prepare the electron transport layer after preparing the third intermediate layer on the perovskite layer, which can be one or more, such as one or more of the energy level transition layer, the modification layer, the passivation layer, the light adjustment layer, the electron transport layer can contain only one type of electron extraction material, or can contain multiple types of electron extraction materials such as fullerene, PCBM, TiO2, SnO2, etc. The electron transport layer can contain additives in addition to the electron extraction material, and the preparation method of the electron transport layer can be a combination of one or more of spin coating, blade coating, printing, magnetron sputtering, evaporation, and atomic deposition;

[0051] S05 Preparing electrode layer: directly preparing electrode layer on the electron transport layer or preparing electrode layer after preparing the fourth intermediate layer, which can be a single layer or a multi-layer structure such as a hole blocking layer, a light adjusting layer, a modification layer, a passivation layer, etc. The electrode layer is a transparent conductive layer and a metal grid layer, which collects the electrons introduced by the electron transport layer. Example 1

[0052] The passivation method of the silicon wafer in this embodiment is as follows:

[0053] 1. Obtain a silicon wafer

[0054] Cut the silicon wafer into the required size, and ultrasonically clean the cut silicon wafer;

[0055] 2. Load the silicon wafer into the passivation equipment

[0056] The passivation equipment is an ALD equipment (atomic deposition equipment), the silicon wafer is fixed in the reaction cavity of the ALD equipment, and the passivation area of the silicon wafer is exposed, and the passivation area is the cutting surface by default;

[0057] 3. TDMAP-Al pulse stage

[0058] Use tris(2,2-dimethylpropyl)aluminum (TDMAP-Al, Al(CH2CH2C(CH3)2)3) as the passivation material, heat the passivation material to 80°C to vaporize, and then start to transport the carrier gas N2, the pulse time is 0.1s;

[0059] 4. First purging

[0060] After the TDMAP-Al pulse is completed, the unreacted passivation material is removed by purging with N2 for 5s;

[0061] 5. Oxygen source (O3) pulse stage

[0062] Pass O3 (concentration of 200g / Nm³, temperature of 120°C) into the reaction cavity through an ozone generator, the pulse time of this stage is 0.05s;

[0063] 6. Second purging

[0064] After the oxygen source pulse stage is completed, the unreacted passivation material and the by-products generated by the reaction are removed by purging with N2 for 5s;

[0065] 7. Cycle steps 3-6 for a total of 100 times, then end;

[0066] 8. Post-processing: take out the silicon wafer from the reaction cavity and anneal at 150°C for 10 minutes to obtain a stable silicon wafer.

[0067] An ITO tunneling layer is prepared on the passivated silicon wafer, and then a silicon- calcium two-end stacked cell is prepared, in which the silicon cell is the bottom cell and the perovskite cell is the top cell. The preparation method is as follows:

[0068] 1. 1 mg of MeO-2PACz is mixed with 1 mL of ethanol solution to obtain a MeO-2PACz solution of 1 mg / mL. After filtering to remove large particles, the solution is spin-coated on one side of the silicon wafer provided with a tunneling layer at a spin-coating rate of 3300 rpm for 30 s, and then annealed at 120°C for 10 min to obtain a MeO-2PACz hole transport layer with a thickness of about 3 nm;

[0069] 2. Cs 0.1 FA 0.2 MA 0.7 Pb(I 0.76 Br 0.24 )3) solution: 27.5152 mg of FAI, 19.9949 mg of FABr, 120.8172 mg of MAI, 40.3092 mg of MABr, 691.515 mg of PbI2, 36.701 mg of PbBr2, and 41.5696 mg of CsI are dissolved in 0.80 mL of DMF (N-N dimethylformamide) and 0.2 mL of DMSO (dimethyl sulfoxide), heated to 70°C and stirred for 2 hours until completely dissolved, and then filtered using a 0.45 μm filter to remove large particles in the solution to obtain a 1.6 M Cs 0.1 FA 0.2 MA 0.7 Pb(I 0.76 Br 0.24 )3) solution. The prepared Cs 0.1 FA 0.2 MA 0.7 Pb(I 0.76 Br 0.24 )3) solution is spin-coated on the hole transport layer at a spin-coating rate of 3000 rpm for 30 s. At the 10th second of spin-coating, 150 μL of anti-solvent toluene is uniformly added on the film layer, and then annealed at 100°C for 30 min under a nitrogen atmosphere, and then cooled to be ready for use, to form a perovskite layer with a thickness of 450 nm;

[0070] 3. A vacuum evaporation device is used to evaporate C 60 material to form a 20 nm electron transport layer on the perovskite layer;

[0071] 4. Preparation of hole blocking layer: an ALD atomic layer deposition device is used to form a 10 nm hole blocking layer of SnO2 on the electron transport layer by atomic layer deposition;

[0072] 5. Preparation of electrode: ITO layer is evaporated on the surface of the hole blocking layer by thermal evaporation, and then silver electrode is prepared. Example 2

[0073] The difference between the example 1 is the process parameters, and the passivation method of the silicon wafer in the present comparative example is as follows:

[0074] 1. Obtain silicon wafer

[0075] Cut the silicon wafer material into silicon wafer of desired size, and perform ultrasonic cleaning on the cut silicon wafer;

[0076] 2. Load the silicon wafer into the passivation equipment

[0077] The passivation equipment is ALD equipment (atomic deposition equipment), the silicon wafer is fixed in the reaction cavity of the ALD equipment, and the passivation area of the silicon wafer is exposed, and the passivation area is the cutting surface by default;

[0078] 3. TDMAP-Al pulse stage

[0079] Take tris(2,2-dimethylpropyl)aluminum (TDMAP-Al, Al(CH2CH2C(CH3)2)3) as the precursor passivation material, heat it to 100℃ to vaporize, then start to transport the carrier gas N2, and the pulse time is 0.15s;

[0080] 4. First purging

[0081] After the TDMAP-Al pulse is finished, N2 is used to purge for 5s to remove the unreacted precursor;

[0082] 5. Oxygen source (O3) pulse stage

[0083] O3 (concentration of 200g / Nm³, temperature of 120℃) is introduced into the reaction cavity by the ozone generator, and the pulse time of this stage is 0.1s;

[0084] 6. Second purging

[0085] After the oxygen source pulse stage is finished, N2 is used to purge for 7s to remove the unreacted precursor and the by-products produced by the reaction;

[0086] 7. Cycle the steps 3~6 for 150 times, and then end;

[0087] 8. Post-processing: take out the silicon wafer from the reaction cavity, and anneal it at 100℃ for 10 minutes to obtain stable silicon wafer.

[0088] Prepare silicon-calcium stacked cell with the silicon wafer obtained by the above passivation method, and the preparation method of the cell is the same as that of example 1. Example 3

[0089] The difference between Example 3 and Example 1 is the process parameters, and the passivation method of the silicon wafer in the present comparative example is as follows:

[0090] 1. Obtain a silicon wafer

[0091] Cut the silicon wafer material into a silicon wafer of the desired size, and perform ultrasonic cleaning on the cut silicon wafer.

[0092] 2. Load the silicon wafer into a passivation device

[0093] The passivation device is an ALD device (atomic deposition device), the silicon wafer is fixed in the reaction cavity of the ALD device, the passivation area of the silicon wafer is exposed, and the passivation area is the cutting surface by default.

[0094] 3. TDMAP-Al pulse stage

[0095] Use tris(2,2-dimethylpropyl)aluminum (TDMAP-Al, Al(CH2CH2C(CH3)2)3) as the precursor material, heat the precursor material to 95°C to vaporize, and then start to transport the carrier gas N2, the pulse time is 0.2s.

[0096] 4. First purge

[0097] After the TDMAP-Al pulse is completed, use N2 to purge for 5s to remove the unreacted precursor.

[0098] 5. Oxygen source (O3) pulse stage

[0099] Pass O3 (concentration of 200g / Nm³, temperature of 120°C) into the reaction cavity through an ozone generator, the pulse time of this stage is 0.1s.

[0100] 6. Second purge

[0101] After the oxygen source pulse stage is completed, use N2 to purge for 7s to remove the unreacted precursor and the by-products generated by the reaction.

[0102] 7. Repeat steps 3-6 for a total of 100 cycles.

[0103] 8. Post-processing: remove the silicon wafer from the reaction cavity and anneal at 100°C for 10 minutes to obtain a stable silicon wafer.

[0104] Prepare a silicon-calcium stacked cell using the silicon wafer obtained by the above passivation method, and the preparation method of the cell is the same as that of Example 1.

[0105] Comparative Example

[0106] The difference between the example and the comparative example is only in the passivation method of the silicon wafer. In the comparative example, the passivation method of the silicon wafer is as follows:

[0107] 1. Obtain a silicon wafer

[0108] Cut the silicon wafer material into a silicon wafer of a desired size, and perform ultrasonic cleaning on the cut silicon wafer.

[0109] 2. Load the silicon wafer into a passivation device

[0110] The passivation device is an ALD device (atomic deposition device), the silicon wafer is fixed in the reaction cavity of the ALD device, and the passivation area of the silicon wafer is exposed. The passivation area is the cutting surface by default.

[0111] 3. TMA pulse stage

[0112] Take TMA as the precursor material, and start to transport the carrier gas N2 after the precursor material is vaporized at room temperature. The pulse time is 0.1s.

[0113] 4. First purge

[0114] After the TMA pulse is completed, the unreacted precursor is removed by purging with N2 for 5s.

[0115] 5. Oxygen source (H2O) pulse stage

[0116] Vaporized H2O (vaporized after passing through the heating pipe) is introduced into the reaction cavity. The pulse time of this stage is 0.05s.

[0117] 6. Second purge

[0118] After the oxygen source pulse stage is completed, the unreacted precursor and the by-products generated by the reaction are removed by purging with N2 for 5s.

[0119] 7. Repeat steps 3-6 for a total of 100 cycles.

[0120] 8. Post-processing: remove the silicon wafer from the reaction cavity and anneal it at 200°C for 10 minutes to obtain a stable silicon wafer.

[0121] The silicon wafer obtained by the above passivation method is used to prepare a silicon-calcium stacked cell. The preparation method of the cell is the same as that of Example 1.

[0122] Data test:

[0123] The performance parameters of the silicon-calcium tandem cells in Example 1 and the comparative examples are shown in Table 1. It can be seen that the cells passivated by TDMAP-Al-ALD in the example have significantly superior performance in open-circuit voltage Voc (V), fill factor FF (%), short-circuit current Js (mA / cm²) and cell efficiency.

[0124] Table 1 IV test data of the cells in the example and the comparative examples

[0125] Parameters TMA-ALD passivated cell (comparative example) TDMAP-Al-ALD passivated cell (example 1) TDMAP-Al-ALD passivated cell (example 2) TDMAP-Al-ALD passivated cell (example 3) Voc (V) 1.820 1.838 1.825 1.827 FF (%) 81.2 83.4 83.1 82.9 Jsc (mA / cm2) 18.8 19.0 19.0 19.0 Efficiency (%) 27.8 29.1 28.81 28.77

[0126] The C content and the interface density of Al2O3 formed after passivation of the silicon cells in Example 1 and the silicon cells in the comparative examples are shown in Table 2. It can be seen that the interface film layer formed after passivation has optimized quality and presents low defects and high density.

[0127] Table 2 XPS and C-V test (carbon residue and interface state density)

[0128] Indicators TMA process (comparative example) TDMAP-Al process (example 1) TDMAP-Al process (example 2) TDMAP-Al process (example 3) C content (at%) 5.8 0.7 0.68 0.69 Interface state density (eV -1 cm -2 )]]> 5.2×10¹¹ 0.8×10¹¹ 0.87×10¹¹ 0.83×10¹¹

[0129] The interface of the Al2O3 film layer formed in Example 1 and the Al2O3 film layer formed in the comparative examples is observed by SEM, and the uniformity and edge coverage of the film layer are analyzed. The results are shown in Table 3.

[0130] Table 3 Uniformity and edge coverage of the film layer

[0131] Indicators TMA process (comparative example) TDMAP-Al process (example 1) TDMAP-Al process (example 2) TDMAP-Al process (example 3) Surface film thickness (nm) 8.2 ± 2.19 (uneven) 10.5 ± 0.3 (uniform) 10.5 ± 0.3 (uniform) 10.5 ± 0.3 (uniform) Surface coverage ~75% >95% >95% >95%

[0132] The minority carrier lifetime is tested by QSSPC. The results are shown in Table 4.

[0133] Table 4 QSSPC test results

[0134] Region TMA process (comparative example) TDMAP-Al process (example) TDMAP-Al process (example 2) TDMAP-Al process (example 3) Silicon cell center (μs) 185 220 215 210 Silicon cell edge (μs) 48 85 82 80

[0135] It is found by testing that the silicon cells passivated by the TDMAP-Al passivation process in the application have the following advantages:

[0136] 1. The edge passivation performance is significantly improved: the minority carrier lifetime of the silicon cell edge (the average survival time of non-equilibrium minority carriers in a semiconductor from generation to recombination) is increased from 50 μs by TMA process to 85 μs (tested by quasi-steady-state photoconductance decay method), and the surface recombination rate of the carriers is reduced. Under AM1.5G illumination, the open-circuit voltage of the tandem cell is tested, and it is found that the TDMAP-Al passivation process is increased by 15-25 mV.

[0137] 2. Excellent low-temperature annealing performance

[0138] Compared with the TMA passivation process in the comparative example, annealing at a temperature of 200°C or higher is required, while the TDMAP-Al in the example still maintains high reaction efficiency at low temperature (50-150°C), avoiding thermal degradation of the perovskite top layer material. And the mild reaction kinetics of TDMAP-Al and O3 adapt to low-temperature ALD, without the need for high-temperature activation.

[0139] 3. The obtained film layer has low carbon residue, high coverage, low defects and high density

[0140] The tert-butyl group of TDMAP-Al in the example generates volatile isobutene, with extremely low carbon residue. The three methyl groups (-CH3) of TMA are directly bonded to the aluminum (Al) center, and the C-Al bond is weak (~70 kcal / mol), which is easily broken in the ALD reaction, but part of the methyl groups cannot be completely oxidized and removed, resulting in carbon residue. SEM cross-section measurement found that the surface coverage of the silicon wafer after TDMAP-Al passivation was >95%.

[0141] 4. High process stability and repeatability

[0142] At 80°C, the vapor pressure of TDMAP-Al in the example is stably maintained at 0.1 Torr (about 13.3 Pa), while the vapor pressure of TMA in the comparative example is higher than 10 Torr. This characteristic enables controlled vapor delivery during the ALD process, thereby controlling the passivation effect.

[0143] During the oxygen source supply process, the O3 pulse time in the example can be adjusted within the range of 0.02-0.1 s, while the comparative example requires strict control of the oxygen source pulse time, with a control range of ±0.01 s. Exceeding the control range will cause a vertical decline in passivation effect. Therefore, compared with the comparative example, the passivation method of the example has high process stability and repeatability. After 30 batches of experiments, the standard deviation of the efficiency of the battery in the example was <0.3%, while the standard deviation of the efficiency of the battery in the comparative example was as high as 0.8%.

[0144] The above examples are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method of passivating a silicon cell, characterized by: The method comprises the following steps S01 placing a silicon wafer in a reaction cavity, and exposing a to-be-passivated region of the silicon wafer to the reaction cavity; S02 feeding a gaseous passivation material into the reaction cavity, wherein the passivation material is tri(2,2-dimethylpropyl)aluminum, the tri(2,2-dimethylpropyl)aluminum is heated to a set temperature and then fed into the reaction cavity, the tri(2,2-dimethylpropyl)aluminum is adsorbed on the surface of the to-be-passivated region, and the set temperature is 80-100 DEG C; S03 feeding an oxygen source into the reaction cavity in a pulse form, wherein the oxygen source and the passivation material interact to passivate the to-be-passivated region, the oxygen source is O3, the oxygen source is fed into the reaction cavity in a pulse form, the pulse time is 0.02-0.1 s, and an inert gas or a carrier gas is used for purging after the pulse is over; S04 repeating the operations of S02 and S03 for a set number of times or for a set time; S05 taking out the silicon wafer, annealing, and obtaining a passivated silicon wafer.

2. The passivation method according to claim 1, characterized in that: The passivation material is fed into the reaction cavity in a pulse form through a carrier gas, the pulse time is 0.05-0.2 s, and an inert gas or a carrier gas is used for purging after the pulse is over.

3. The passivation method according to claim 1, characterized in that: The number of times of repeating the operation of S02 and S03 is 50-200, and an aluminum oxide film is formed on the to-be-passivated region after passivation, and the thickness of the aluminum oxide film is 5-20 nm.

4. The passivation method according to claim 1, characterized in that: The annealing temperature in S05 is 0-150 DEG C.

5. A solar energy device, characterized by: The method comprises the following steps 6. A method of making a silicon-calcium stacked cell, characterized by: The method comprises the following steps: S01 obtaining a silicon wafer: the silicon wafer is treated by the passivation method according to any one of claims 1-4; S02 preparing a hole transport layer: depositing a hole transport layer on the silicon wafer, wherein the hole transport layer contains at least one hole transport material; S03 preparing a perovskite layer: depositing a perovskite layer on the hole transport layer, wherein the hole transport layer and the perovskite layer are in direct or indirect contact, and the perovskite layer contains at least one perovskite light-absorbing material; S04 preparing an electron transport layer: depositing an electron transport layer on the perovskite layer, wherein the electron transport layer and the perovskite layer are in direct or indirect contact, and the electron transport layer contains at least one electron transport material; S05 preparing an electrode layer.

7. The method of producing a silicon-calcium stacked cell according to claim 6, characterized by: The hole transport material is MeO-2PACz, and the perovskite light-absorbing material is Cs x1 FA x2 MA (1-x1-x2) Pb(I y1 Br (1-y1) )3, 0 < x1 < 1, 0 < x2 < 1, 0 < x1 + x2 < 1, 0 < y1 < 1.

8. The method of producing a silicon-calcium stacked cell according to claim 7, characterized by: The preparation method of the hole transport layer is as follows: a mixing MeO-2PACz and an ethanol solution to obtain a MeO-2PACz solution; b coating the MeO-2PACz solution on the silicon wafer to obtain a MeO-2PACz hole transport layer; The preparation method of the perovskite layer is as follows: a dissolving FAI, FABr, MAI, MABr, PbI2, PbBr2 and CsI in N-N dimethylformamide and dimethyl sulfoxide at a set ratio to obtain a precursor solution; b heating the precursor solution to complete dissolution; c coating the precursor solution on the hole transport layer and adding toluene dropwise for a set time; d annealing under a nitrogen atmosphere to obtain a perovskite layer.