Independent addressing of single and dual wire devices on a shared RFFE bus interface

Abstract

A data communication device coupled to a serial bus has a protocol controller that configures a first plurality of slave devices with device identifiers that are unique within the first plurality of slave devices and configures a second plurality of slave devices with device identifiers that are unique within the second plurality of slave devices. A sequence start condition sent over the serial bus indicates a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. Device identifiers associated with the first plurality of slave devices are used to send first datagrams over the serial bus in the first communication mode and device identifiers associated with the second plurality of slave devices are used to send second datagrams over the serial bus in the second communication mode.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 157,000, filed January 19, 2023, which is assigned to the assignee of this patent application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure relates in general to serial communication, and more specifically to addressing on a shared radio frequency front-end serial bus for devices configured for single-wire communication and devices configured for two-wire communication. Background Technology

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing devices, user interface components, storage devices, and other peripheral components that communicate via a shared data communication bus, which may include a multi-point serial bus or a parallel bus. Commonly known serial interfaces in the industry include inter-integrated circuit (I2C) or inter-system (I2C) interfaces. 2 C) Serial interfaces and their derivatives and alternatives.

[0005] The Mobile Industry Processor Interface (MIPI) Alliance defines standards and protocols for improved Inter-Integrated Circuit (I3C) serial interfaces, Radio Frequency Front-End (RFFE) interfaces, System Power Management Interfaces (SPMIs), and other interfaces. These interfaces can be used to connect, for example, processors, sensors, and other peripheral devices. In some interfaces, multiple host devices are coupled to a serial bus, allowing two or more devices to act as host devices for different types of messages transmitted on the serial bus. The RFFE interface defines a communication interface that can be used to control various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located in a single IC device or distributed across multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the SPMI specification defined by the MIPI Alliance provides a hardware interface that can be implemented between the baseband or application processor and peripheral components. In some implementations, SPMI is deployed to support power management operations within the device.

[0006] As devices become more complex, the demand for input / output pins also increases, necessitating simplified bus architectures and protocols that can coexist with older bus architectures and protocols. Summary of the Invention

[0007] Some aspects of this disclosure relate to systems, apparatuses, methods, and techniques that enable communication with devices coupled to a single-wire link via an interface, while some devices use multiple wires to communicate.

[0008] In various aspects of this disclosure, a method performed at a master device coupled to a serial bus includes: configuring each of a first plurality of slave devices with a unique device identifier within the first plurality of slave devices; configuring each of a second plurality of slave devices with a unique device identifier within the second plurality of slave devices; transmitting a sequence start condition via a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in a clock signal on a clock line of the serial bus; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, transmitting a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, transmitting a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0009] In various aspects of this disclosure, a data communication device includes: an interface circuit adapted to couple the data communication device to two lines of a serial bus; and a protocol controller configured to: configure each of a first plurality of slave devices with a unique device identifier within the first plurality of slave devices; configure each of a second plurality of slave devices with a unique device identifier within the second plurality of slave devices; transmit a sequence start condition via a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in a clock signal on a clock line of the serial bus; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, transmit a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, transmit a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0010] In various aspects of this disclosure, a method performed at a slave device coupled to a serial bus includes: receiving a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition is transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition is transmitted together with embedded clock information in the data signal; responding to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device; and responding to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device.

[0011] In various aspects of this disclosure, an apparatus has interface circuitry adapted to couple the apparatus to two lines of a serial bus, and a processor. The processor is configured to receive from the data lines of the serial bus a first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition is transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receive from the data lines a second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition is transmitted along with embedded clock information in the data signal; respond to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the apparatus; and respond to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the apparatus. Attached Figure Description

[0012] Figure 1 An example is illustrated of a device employing a data link between IC devices, which operates selectively according to one of a plurality of available standards.

[0013] Figure 2 The system architecture of a device employing data links between IC devices is illustrated.

[0014] Figure 3 An example of a device configuration for using multiple RFFE buses to couple various radio frequency front-end devices is shown.

[0015] Figure 4A system in which single-line slave devices and two-line slave devices coexist according to certain aspects disclosed herein is illustrated.

[0016] Figure 5 An example of the sequence start condition defined by the RFFE protocol is shown.

[0017] Figure 6 Examples of transactions performed on a multimode serial bus according to certain aspects disclosed herein are illustrated.

[0018] Figure 7 This is a flowchart illustrating an example of communication in a device coupled to a hybrid bus that couples single-wire slave devices and two-wire slave devices to a master device.

[0019] Figure 8 This illustrates certain aspects of addressing on a hybrid serial bus configured according to certain aspects of this disclosure.

[0020] Figure 9 An example is illustrated of a host device configured to manage communication via a hybrid serial bus, according to certain aspects of this disclosure.

[0021] Figure 10 An example of an erroneous two-line SSC transmitted on a data line of a serial bus configured according to certain aspects of this disclosure is illustrated.

[0022] Figure 11 Examples of datagram structures that can conform to or be compatible with the RFFE protocol are shown.

[0023] Figure 12 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0024] Figure 13 This is a flowchart illustrating a method for data communication at a master device, based on certain aspects disclosed herein.

[0025] Figure 14 Examples of specific hardware implementations of host device apparatus adapted to certain aspects disclosed herein are illustrated.

[0026] Figure 15 This is a flowchart illustrating a method for data communication at a single-line slave device, based on certain aspects disclosed herein.

[0027] Figure 16 Examples of specific hardware implementations of a single-wire slave device adapted to certain aspects disclosed herein are illustrated. Detailed Implementation

[0028] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. Specific details are included to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0029] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0030] Certain aspects of this disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial bus typically operates in a hierarchical manner, as one device controls communication during a transaction. The controlling device may be referred to as a master device, bus master, management device, or another term supported by a standard defining a protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communication during all transactions conducted via the serial bus. In other serial bus configurations, multiple devices may operate as controlling devices for each transaction conducted via the serial bus, and one device may act as the controlling device. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands to one or more receiving devices using address information provided in or with a command. Receiving devices may be referred to as slave devices, client devices, slaves, peripheral devices, or another term supported by a standard defining a protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as a master device, and the associated receiving device will be referred to as a slave device.

[0031] Overview

[0032] Devices comprising multiple SoCs and other IC devices typically employ a shared communication interface, which may include a serial bus or other data communication link for connecting the processor to modems and other peripherals. The serial bus or other data communication link may operate according to one or more defined standards or protocols. For example, a serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that can be configured for half-duplex operation. The increased functionality and operational complexity of devices coupled to a serial bus, and the more stringent timing constraints imposed to support applications, peripherals, and sensors, may lead to greater demands on GPIO and communication link throughput.

[0033] Certain aspects of this disclosure relate to techniques for communication over a single wire by combining data and clock information in the same signal. In one example, the data and clock information can be encoded using pulse width modulation (PWM). In another example, Manchester-coded data carries clock information in each transmitted bit. In one aspect, a master device can be adapted to communicate with some slave devices over a single wire (data only) and with other devices over a two-wire connection (data and clock). The protocol controller can signal the type of communication (single-wire or two-wire) based on the duration of the sequence start condition (SSC) used to initiate a transaction.

[0034] Various aspects of the SSC are defined by the RFFE protocol. The durations of the high and low portions are specified by the protocol, and the rise and fall times of transitions within the SSC are also defined by the protocol. Limitations on the frequency of the clock signal transmitted on the SCLK line of the RFFE bus are also defined by the protocol. In one aspect of this disclosure, the protocol controller can be configured to send modified SSCs to indicate when to transact with a single-wire slave device. In some examples, the protocol controller can send extended-length SSCs to target a single-wire slave device for communication. In some implementations, the protocol controller can send shortened SSCs to target a single-wire slave device for communication. In some instances, the protocol controller can send SSCs with modified rise and fall times to target a single-wire slave device for communication.

[0035] In one example, the host device has interface circuitry adapted to couple the device to two lines of a serial bus; and a protocol controller. The protocol controller can configure a unique device identifier within each of a first plurality of slave devices; configure a unique device identifier within each of a second plurality of slave devices; transmit a sequence start condition via the data lines of the serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in the clock signal on the clock line of the serial bus; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, transmit a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, transmit a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0036] Some aspects disclosed herein can be used to replace or supplement serial bus protocols such as I2C, I3C, SPMI, and / or RFFE protocols, or point-to-point interfaces based on UART or line-multiplexed UART (LM-UART). Some aspects are applicable to serial buses operating in half-duplex or full-duplex mode. Some aspects are applicable to point-to-point interfaces, including UART-based interfaces and line-multiplexed UART (LM-UART) interfaces. In some specific implementations, some aspects disclosed herein can be deployed to support the exchange of Virtual GPIO (VGI) messages. Some aspects are applicable to multipoint interfaces and / or interfaces operating in point-to-point mode.

[0037] Example of a device using a serial data link

[0038] According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0039] Figure 1An example of a device 100 that may employ a data communication bus is illustrated. Device 100 may include a System-on-a-Chip (SoC), processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs or SoCs. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0040] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, floppy disk, or hard disk, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls such as switches or buttons 128, 130 and / or an integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0041] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuitry, counters, timers, control logic units, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0042] Figure 2 Examples include multiple devices 202 and 2220-222 coupled to serial bus 220. N Certain aspects of device 200. Devices 202 and 2220-222 N It can be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. In various specific implementations, devices 202 and 2220-222... N It may include, support, or operate as a modem, signal processing device, display driver, camera, user interface, sensor, sensor controller, media player, transceiver, RFFE device, and / or other such components or devices. In some examples, slave devices 2220-222 N One or more of these may be used to control, manage, or monitor sensor devices. Devices 202 and 2220-222 N Communication between them via serial bus 220 is controlled by master device 202. Some types of buses can support multiple master devices 202.

[0043] In one example, master device 202 may include interface controller 204, which manages access to the serial bus and configures slave devices 2220-222. N The dynamic address and / or clock signal 228 is transmitted on clock line 218 of serial bus 220. Master device 202 may include configuration register 206 or other storage device 224 and other control logic unit 212 configured to process protocols and / or higher-level functions. Control logic unit 212 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Master device 202 includes transceiver 210 and line driver / receiver 214a and 214b. Transceiver 210 may include a receiver, transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 228 provided by clock generation circuitry 208. Other timing clocks 226 may be used by control logic unit 212 and other functions, circuitry, or modules.

[0044] At least one device 2220-222 N The device 2220 can be configured to operate as a slave device on a serial bus 220 and may include circuitry and modules supporting and communicating with one or more sensors that control and measure environmental conditions. In one example, the device 2220 configured to operate as a slave device may provide control functions, modules, or circuitry 232, including circuitry and modules for supporting and communicating with one or more sensors that control and measure environmental conditions. The slave device 2220 may include a configuration register 234 or other storage device 236, control logic unit 242, transceiver 240, and line drivers / receivers 244a and 244b. Control logic unit 242 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 210 may include a receiver, transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 248 provided by clock generation and / or recovery circuitry 246. Clock signal 248 can be derived from the signal received from clock line 218. Other timing clocks 238 can be used by control logic unit 242 and other functions, circuits or modules.

[0045] The serial bus 220 can operate according to RFFE, I2C, I3C, SPMI, or another protocol. At least one device 202, 2220-222 N It can be configured to selectively operate as a master or slave device on serial bus 220. Two or more devices 202, 2220-222 N It can be configured to operate as a master device on serial bus 220.

[0046] In some implementations, the serial bus 220 can operate according to the I3C protocol. Devices communicating using the I3C protocol can coexist on the same serial bus 220 as devices communicating using the I2C protocol. The I3C protocol can support different communication modes, including a Single Data Rate (SDR) mode compatible with the I2C protocol. High Data Rate (HDR) mode provides data transfer rates between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes offer even higher data transfer rates. The I2C protocol can conform to the de facto I2C standard, providing data rates ranging from 100 kilobits per second (kbps) to 3.2 Mbps. In addition to data format and bus control aspects, the I2C and I3C protocols can also define the electrical and timing aspects of signals transmitted on the two-wire serial bus 220. In some aspects, the I2C and I3C protocols can define the DC characteristics affecting certain signal levels associated with the serial bus 220 and / or the AC characteristics affecting certain timing aspects of signals transmitted on the serial bus 220. In some examples, the two-wire serial bus 220 transmits data on data line 216 and clock signals on clock line 218. In some instances, the data may be encoded in the signaling state or in the signaling state transitions between data line 216 and clock line 218.

[0047] Figure 3 Figure 300 illustrates an example configuration of a chipset or device 302 employing multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. In this example, modem 304 includes an RFFE interface 308 that couples modem 304 to a first RFFE bus 330. Modem 304 can communicate with baseband processor 306 and radio frequency IC (RFIC 312) via respective communication links 310, 336, or in some implementations via a shared communication link 310 or 336. The illustrated device 302 can be embodied in one or more of the following: mobile communication devices, mobile phones, mobile computing systems, mobile phones, laptops, tablet computing devices, media players, gaming devices, wearable computing devices, wearable communication devices, electrical appliances, etc.

[0048] In various examples, device 302 may be implemented using one or more baseband processors 306, modems 304, RFICs 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. Device 302 may include other processors, circuitry, modules, and may be configured for various operations and / or different functionalities. Figure 3In the illustrated example, modem 304 is coupled to RF tuner 318 via its RFFE interface 308 and first RFFE bus 330. RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, state machine, and / or processor that configure and control certain aspects of the RF front end. In the illustrated example, RFIC 312 communicates with PA 320 and power tracking module 322 via the first RFFE interface and second RFFE bus 332 in its RFFE interface 314. In the illustrated example, RFIC 312 communicates with switch 324 and one or more LNAs 326, 328 via the second RFFE interface and third RFFE bus 334 in its RFFE interface 316.

[0049] Bus latency can affect the serial bus's ability to process high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor status, device-generated real-time events, and virtualized GPIO. In one example, bus latency can be measured as the time elapsed between a message becoming available for transmission and its delivery. In another example, bus latency can be measured as the time elapsed between a message becoming available for transmission and the start of transmission. Other measurements of bus latency may be used. Bus latency typically includes delays incurred when transmitting higher-priority messages, interrupt handling, the time required to terminate datagrams in progress on the serial bus, the time for sending commands that switch the bus between transmit and receive modes, bus arbitration, and / or command transmission specified by the protocol.

[0050] In one example, a delay-sensitive message carries or includes a coexistence message. Coexistence messages can be sent across multiple system platforms to prevent or reduce collisions between certain types of RFFE devices. RFFE devices that can be the source or body of a coexistence message include, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices that operate concurrently in a manner that generates inter-device RF interference and / or may potentially damage one or more devices. Coexistence management messages can be exchanged between certain devices shared between different radio access technologies, wireless subscriptions, and / or applications. For example, switches 324, LNAs 326, 328, PAs 320, and / or antennas can be shared by two different radio access technologies with different transmit and receive schedules, and damage to LNAs 326, 328, or other devices may occur if a device begins transmitting using one radio access technology and receiving using the other. Devices that can interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that may cause interference or collisions. For example, two modems 304 can exchange CxM messages to manage the operation of shared components. In conventional systems, CxM messages are exchanged using dedicated serial links, each implemented using a two-wire or four-wire Universal Asynchronous Receiver / Transmitter (UART). In multi-radio, multi-application systems, CxM interconnects and other device interconnects can consume a large number of physical input / output (I / O) pins and interconnects, increasing cost and routing complexity.

[0051] Multipoint interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used for communication between multiple devices. Protocols supporting communication over multipoint serial buses define datagram structures for sending command, control, and data payloads. Certain common features are defined for the datagram structures of different protocols, including addressing for selecting devices to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, examples of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0052] Based on certain aspects disclosed herein, a two-wire serial bus can be adapted to operate alternately in conventional two-wire and single-wire modes. In one example, the serial bus can operate according to the RFFE protocol, such that the clock and data lines are used for communication with two-wire slave devices coupled to the serial bus, and the data lines are used for communication with single-wire slave devices coupled to the serial bus in the absence of a clock signal. The master device can use pulse width modulation to encode data sent to the single-wire slave device.

[0053] Figure 4 A system 400 according to certain aspects disclosed herein is illustrated, in which a single-wire slave device 404 and a two-wire slave device 406 can coexist, and in which a master device 402 can communicate with both the single-wire slave device 404 and the two-wire slave device 406. The master device 402 can be located in an RFIC, modem, application processor, or another type of device. The master device 402 is coupled to one or more slave devices 404, 406 via at least an SDATA line 410 of a two-wire serial bus 408, which also has an SCLK line 412. Data can be encoded in a data signal transmitted via the SDATA line 410, and in two-wire communication mode, a receiver can extract the data using a clock signal transmitted via the SCLK line 412. In the illustrated example, the serial bus 408 operates according to the RFFE protocol. In other examples, the serial bus 408 may operate according to another protocol such as the I3C protocol, the SPMI protocol, etc. In the illustrated example, each single-wire slave device 404 and each two-wire slave device 406 are coupled to the SDATA line 410. The single-wire slave device 404 is adapted for single-wire communication mode, while the two-wire slave device 406 is also coupled to the SCLK line 412 to receive clock signals used in two-wire communication mode.

[0054] The host device 402 may include a protocol controller 414, which may be implemented by processing circuitry having a processor, controller, state machine, or other logic components. The protocol controller 414 may be configured to support one or more protocols that can be used to manage the operation of the serial bus 408. In some implementations, the protocol controller 414 is operable to configure one or more slave devices 404, 406. The protocol controller 414 may determine the configuration of the slave devices 404, 406 as designated recipients of data to be transmitted via the serial bus 408, and may accordingly encode the data in a signal to be transmitted via the SDATA line 410. In some instances, a broadcast message for a combination of single-wire slave device 404 and two-wire slave device 406 may be transmitted twice, once in single-wire communication mode and once in two-wire communication mode. The protocol controller 414 may additionally determine whether and / or when a clock signal will be transmitted via the SCLK line 412. In some implementations, the clock signal is suppressed when data is transmitted to one or more single-wire slave devices 404 in single-wire communication mode.

[0055] According to certain aspects disclosed herein, the host device 402 can select between a single-wire slave device 404 and a dual-wire slave device 406 when initiating a transaction. The host device 402 can use different Sequence Start Conditions (SSCs) to precede single-wire and dual-wire transactions. In some implementations, certain interface characteristics of the single-wire slave device 404 and / or the dual-wire slave device 406 can be configurable. For example, the single-wire slave device 404 and / or the dual-wire slave device 406 coupled to the serial bus 408 can match a specified bus capacitor when driving the SDATA line 410 based on a configurable register setting defined as the capacitor specified by the SDATA line 410. In other instances, the specified bus capacitor can be hardwired in the single-wire slave device 404 and / or the dual-wire slave device 406.

[0056] Figure 5 This example illustrates the RFFE sequence start timing 500, including SSC 504 as defined by the RFFE protocol. See also... Figure 4 The serial bus 408 is initially idle, with both the SDATA line 410 and the SCLK line 412 low. The host device 402 can initiate a transaction by sending two bits of SSC 504. The bit time, or the transmission time per bit, can be determined by the frequency of the internal clock 502 used by the host device 402. The internal clock 502 can be selected to control the bit rate of the serial bus 408 during data transmission. SSC 504 consists of a pulse transmitted on the SDATA line 410 while the SCLK line 412 remains low. This pulse consists of a high portion 506 followed by a low portion 508. The address 510 may follow SSC 504. In normal RFFE operation, information bits, including payload data, address, and control bits, are sampled or captured when a clock pulse is provided on the SCLK line 412. No clock pulse is provided during the transmission of SSC 504, and the receiving device recognizes the change in signaling state indication control signaling on SDATA line 410 when SCLK line 412 is held low.

[0057] Various aspects of the SSC 504 are defined by the RFFE protocol, including the duration of the high portion 506 and the low portion 508 of the SSC 504. The rise time (T) of the preamble transition 512... R ) and the fall time (T) of the pulse termination transition 514 FThe frequency of the clock signal transmitted on SCLK line 412 is also defined by the protocol. Limitations on the frequency of the clock signal transmitted on SCLK line 412 may be defined by the design, application, and / or by the specification defining the RFFE protocol. Protocol controller 414 may be configured to transmit a modified SSC indicating when to transact with single-wire slave device 404. In some examples, protocol controller 414 may transmit an extended-length SSC to target single-wire slave device 404 for communication and / or indicate that a transaction will be conducted in single-wire communication mode, wherein the extended-length SSC has a duration longer than the duration of the SSC pulse provided according to the RFFE specification. In some specific implementations, protocol controller 414 may transmit a shortened SSC to target single-wire slave device 404 for transacting, wherein the shortened SSC comprises a pulse with a duration shorter than the duration of the SSC pulse provided according to the RFFE specification. In some instances, protocol controller 414 may transmit an SSC with modified rise and / or fall times to target single-wire slave device 404 for communication.

[0058] In some respects, legacy two-wire datagrams are identified by a standard SSC 504, which indicates that signaling will be provided on both the SDATA line 410 and the SCLK line 412. Single-wire datagrams can be identified by an SSC including a unique pulse timing marker on the SDATA line 410. In one example, the unique pulse timing marker is provided when the SSC pulse has a duration guaranteed to exceed the high portion 506 of the standard SSC 504 (pulse duration). In another example, the unique pulse timing marker includes a modified rise time (T0). R ) and fall time (T F The conversion involves a receiver equipped with slope detection circuitry. In various specific implementations, the modified SSC for a single-wire datagram provides timing and / or control information that configures the receiver for the modulation scheme used on the SDATA line 410. In one example, the modified SSC for a single-wire datagram indicates the duration and / or center point of the bit interval. In some examples, signaling in a clock cycle following the modified SSC indicates the duration and / or center point of the bit interval.

[0059] In various implementations, the voltage level defining the idle state of the bus can be configurable or can be changed depending on the specific implementation. In some examples, SDATA line 410 and SCLK line 412 are at a low voltage (or zero volts) in the idle state, while in other examples, SDATA line 410 and SCLK line 412 are at a high voltage level in the idle state. The voltage level of the idle state can define the voltage level of the pulses transmitted in the pulse width modulated data signal, and / or be used to indicate the direction of data transition in the phase modulated data signal. Figure 5 Generalized examples of systems 520 and 540 operating in different idle states are included. In the first system 520, the master device 522 communicates with the slave device 524 via a serial bus 526, where the idle state is defined by a low voltage level 530, while an activity pulse rises to a higher voltage level 528. The serial bus 526 can be a single-wire bus, a two-wire bus, or a bus with multiple data lines. In some instances, the number of lines in the serial bus 526 is configurable, and the master device 522 and the slave device 524 may have configurable general-purpose input / output (GPIO) pins that can be configured to match the configuration of the serial bus 526. In some implementations, the master device 522 and / or the slave device 524 may have predefined GPIO configurations. In some implementations, the master device 522 may be designed with GPIO pads and / or pins that support operation in single-wire, two-wire, or mixed single-wire / two-wire applications.

[0060] In the second system 540, the master device 542 communicates with the slave device 544 via a serial bus 546, where an idle state is defined by a high voltage level 550, while an active pulse drops to a lower voltage level 548. The serial bus 546 can be a single-wire bus, a two-wire bus, or a bus with multiple data lines. In some instances, the number of lines in the serial bus 546 is configurable, and both the master device 542 and the slave device 544 may have configurable general-purpose input / output (GPIO) pins that can be configured to match the configuration of the serial bus 546. In some implementations, the master device 542 and / or the slave device 544 may have predefined GPIO configurations. In some implementations, the master device 542 may be designed with GPIO pads and / or pins that support operation in single-wire, two-wire, or mixed single-wire / two-wire applications.

[0061] Figure 6Examples of transactions 600 and 620 performed on a multi-mode serial bus are illustrated. In the first transaction 600, a two-wire SSC 608 is sent by the master device. The master device then sends a pulse 610 on the SCLK line 604 indicating and / or distinguishing the data bits on the SDATA line 602. In the first transaction 600, datagrams are sent starting with slave device address bits 612, 614, 616, and 618. The duration of the two-wire SSC 608 is shorter than the duration defined for a single-wire SSC, causing the single-wire slave device 404 to ignore address bits 612, 614, 616, 618 and any subsequent data transmissions until a valid 1-bit SSC 622 is detected. In some specific implementations, the line interface circuitry in the single-wire slave device 404 provides a detection signal 606 indicating whether a single-wire SSC has been detected.

[0062] In the second transaction 620, the single-wire SSC 622 is sent by the master device. The master device then strobes, suppresses, or otherwise avoids sending a pulse in the clock signal transmitted via the SCLK line 604. The master device sends information on the SDATA line 602. In the second transaction 620, the information may begin with the slave device address bit 624. The two-wire slave device 406 can be configured or adapted to ignore the slave address bit 624 when no pulse is provided on the SCLK line 604. When the single-wire SSC 622 has been detected, the line interface circuitry in the single-wire slave device 404 provides a transition to an active state 626 in the detection signal 606.

[0063] A serial bus that couples both single-wire and two-wire slave devices to a master device may be referred to herein as a hybrid bus. Devices coupled to a hybrid bus may implement some combination of hardware and software to dynamically detect the duration of the SSC pulse and thus identify the operating mode of an incoming transaction. Operating modes supported by devices coupled to a hybrid bus may include single-wire and two-wire modes. Devices coupled to a hybrid bus are typically configured to detect the operating mode of each incoming transaction. In one example, devices coupled to a hybrid bus may achieve dynamic transaction detection by measuring the duration (width) of each incoming SSC pulse. The duration of the SSC pulse can typically distinguish between single-wire and two-wire transactions. In one example, dynamic detection is implemented using an internal oscillator or clock generator that operates at a multiple of the RFFE bus clock frequency. In some instances, the internal oscillator or clock generator outputs a clock signal that oscillates at four times (4x) the RFFE bus clock frequency.

[0064] For the purposes of this disclosure, a two-wire transaction is preceded by an SSC pulse lasting one RFFE transmit clock cycle, and a single-wire transaction is preceded by an SSC pulse lasting three or more RFFE transmit clock cycles. A single-wire transaction via the RFFE bus can be processed by a device with single-wire capability. A two-wire transaction via the RFFE bus can be processed by a device with two-wire capability. The transaction can be processed by a device with a unique identifier (“Device ID”) that matches the address field in the command sent in the transaction. A device with a Device ID that does not match the address field in the command sent in the transaction can ignore the ignored command and monitor the data lines for the next incoming command.

[0065] Figure 7 Flowchart 700 is an example of communication in devices coupled to a hybrid bus that couples single-wire slave devices and two-wire slave devices to a master device. For example, Figure 4 The illustrated system 400 includes a single-line slave device 404 and a two-line slave device 406, when using Figure 6 When exemplified by control signaling, they can coexist on the same bus. In some instances, one or more of the two-wire slave devices 406 can be dual-mode devices capable of operating as single-wire slave devices. Dual-mode devices can be configured to dynamically switch between single-wire and two-wire modes based on the detected SSC structure and configuration. That is, a dual-mode device can be configured to communicate using the two-wire protocol when a regular (shorter) SSC is detected, and to communicate using the single-wire protocol when a longer SSC is detected. Dual-mode devices can be lockable in the selected or desired operating mode. In one example, a dual-mode device can be locked in single-wire mode in some cases and in two-wire mode in others. During system integration and / or system configuration, dual-mode devices can be locked or unlocked by the host device or application.

[0066] When a dual-mode device detects the start of an SSC, it can be in idle state 702. In idle state 702, the hybrid bus is idle, or the dual-mode device is waiting for the hybrid bus to become idle and / or remain idle for a minimum duration. Bus management protocols typically define the minimum duration for which the bus idle condition is qualified. The dual-mode device can process the SSC and associated commands, or it can effectively discard commands based on the dual-mode device's operating state. The dual-mode device can discard commands by ignoring the SSC and subsequent datagrams until an idle period is detected on the serial bus. If the dual-mode device is in an unlocked state, it will read the command and respond if the dual-mode device is command-addressed. If the dual-mode device is in a two-wire locked state, it will process the SSC and associated commands when directed to a two-wire device, and will discard the command when directed to a single-wire device. If the dual-mode device is in single-line locked state, when it is redirected to a single-line device, the dual-mode device will process the SSC and associated commands, and when it is redirected to a dual-line device, the dual-mode device will discard the commands.

[0067] Therefore, in block 704, the dual-mode device determines whether it has been locked, and proceeds to block 706 if unlocked, or to block 720 if locked. In block 706, the unlocked dual-mode device enables its clock generator and enables a counter that can be configured to count the cycles of an internal clock signal provided by the clock generator. In block 708, the counter increments in each cycle of the internal clock signal. The internal clock signal may have a frequency that is a multiple of the frequency of the transmitter clock in the host device. For the purposes of this description, the threshold counter value “N” is used to distinguish between single-line SSC and dual-line SSC. In one example, N may correspond to a counter value that has not been reached before the dual-line SSC terminates. In another example, N may correspond to a counter value that has not been exceeded before the dual-line SSC terminates. In block 710 of the illustrated example, after the SSC has terminated, the counter value is compared with N. When the counter value does not exceed N, the dual-mode device proceeds to block 712, and when the counter value exceeds N, the dual-mode device proceeds to block 714. In box 712, the dual-mode device disables its internal clock and participates in a two-wire transaction. In box 714, the dual-mode device uses its internal clock for data decoding purposes and participates in a single-wire transaction. After completing or abandoning a transaction, the dual-mode device can re-enter idle state 702.

[0068] In box 720, the locked dual-mode device determines which mode is locked. When dual-line locking is enabled, the dual-mode device proceeds to box 722, and when single-line locking is enabled, it proceeds to box 724. In box 722, the dual-mode device determines whether an incoming command is routed to the dual-line device based on the duration of the SSC. When an incoming command is routed to the dual-line device, the dual-mode device processes the transaction in box 728 and discards the incoming command routed to the single-line device in box 726. In box 724, the dual-mode device determines whether an incoming command is routed to the single-line device based on the duration of the SSC. When an incoming command is routed to the single-line device, the dual-mode device processes the transaction in box 728 and discards the incoming command routed to the dual-line device in box 726. When discarding the incoming command in box 726 or processing the transaction in box 728, the dual-mode device can re-enter idle state 702.

[0069] According to certain aspects of this disclosure, a host device coupled to a hybrid serial bus can maintain separate addressing schemes for devices configured for two-wire mode transactions and devices configured for single-wire mode transactions. The ability to independently assign addresses for different modes of operation of the hybrid bus provides greater flexibility and increases the number of devices that can access the hybrid bus. In some examples, when the hybrid bus is shared by two-wire and single-wire RFFE devices, using separate addressing schemes can double the number of addressable devices on a single RFFE bus.

[0070] Figure 8 Examples of addressing on a serial bus configured according to certain aspects of this disclosure are illustrated. In a first configuration 800, up to 15 RFFE devices configured for two-wire communication can be coupled to data line 802 and clock line 804 provided by the serial bus. In a second configuration 820, up to 15 RFFE devices configured for single-wire communication can be coupled to data line 822 provided by the serial bus. In both configurations 800 and 820, each RFFE device is configured with a unique device ID, and the host device can maintain a single table associating each RFFE device with its assigned device ID.

[0071] In the third configuration 840, up to 15 RFFE devices configured for two-wire communication can be coupled to data line 842 and clock line 844 provided by a serial bus, and up to 15 RFFE devices configured for single-wire communication can be coupled to data line 842 of the serial bus. In this configuration 840, a device ID assigned to each RFFE device can be assigned to another RFFE device operating in a different mode. The host device can maintain tables for each operating mode. One table associates each RFFE device configured for two-wire operation with its unique assigned device ID among the two-wire RFFE devices, and a second table associates each RFFE device configured for single-wire operation with its unique assigned device ID among the single-wire RFFE devices. In one example, two RFFE devices 846 and 848 sharing the same device ID can be configured to always operate in different operating modes. The two RFFE devices 846 and 848 do not need to have the same assigned device ID.

[0072] In one aspect of this disclosure, the RFFE device 846 configured for two-wire operation can also be configured for single-wire operation. A host device can assign two different addresses to the dual-mode RFFE device 846. For example, the dual-mode RFFE device 846 can be configured with a first device ID for two-wire mode that matches the device ID assigned to the single-wire RFFE device 848, and the dual-mode RFFE device can be configured with a second device ID for single-wire mode that is different from the first device ID. In some instances, the dual-mode RFFE device 846 can be assigned two device IDs with the same value, thereby allowing the dual-mode RFFE device 846 to respond to the same address in both two-wire and single-wire transactions.

[0073] The flexibility provided to host devices by using different addressing schemes for different operating modes can yield many advantages. In one example, a host device maintaining separate addresses for different operating modes, according to certain aspects of this disclosure, can assign a specific 4-bit address for use by a two-wire device, a single-wire device, or both. In another example, a single RFFE device can be assigned different priorities in different operating modes. In the latter example, different priorities can lead to different behaviors and results in the address arbitration process performed in different operating modes. In yet another example, the number of addressable devices that can be coupled to a single RFFE bus can be doubled.

[0074] An RFFE host device configured according to certain aspects of this disclosure can maintain separate address and input / output (I / O) buffer spaces to manage communication with two-wire and single-wire RFFE devices sharing a hybrid RFFE bus. Circuitry within the RFFE host device can provide automatic data traffic routing to and from the two-wire or single-wire buffer spaces on the host based on the communication mode enabled for the hybrid RFFE bus.

[0075] Figure 9 Some features of a host device 900 configured to manage communication over a hybrid serial bus, according to certain aspects of this disclosure, are illustrated. The host device 900 includes a set of two-wire transaction buffers 902 and a set of single-wire transaction buffers 904. A transmit buffer 912a in the two-wire transaction buffer 902 can be configured to provide a data stream to be transmitted in two-wire communication mode. A receive buffer 912b in the two-wire transaction buffer 902 can be configured to receive and / or assemble data received in transactions performed in two-wire communication mode.

[0076] The mode detection logic unit 910 can determine the operating mode. The mode detection logic unit 910 can set the operating mode in response to an SSC signal detected on SDATA 916. In some implementations, the mode detection logic 910 can set the operating mode in response to input or commands from a higher-level communication protocol implemented in the host device. For example, a component of the bus interface can set the two-wire operating mode when it determines that the destination of data provided by the application corresponds to a two-wire device. The two-wire transaction buffer 902 is enabled during the two-wire operating mode, and the path selector circuit 906 is configured to guide the data flow between the two-wire transaction buffer 902 and the circuitry in the transmit and receive circuitry 908 for two-wire transmission. In some implementations, the transmit and receive circuitry 908 can respond to the mode detection logic unit 910 by, for example, enabling driver circuitry to transmit a clock signal via SCLK 918.

[0077] The transmit buffer 914a in the single-wire transaction buffer 904 can be configured to provide a data stream to be transmitted in single-wire communication mode. The receive buffer 914b in the single-wire transaction buffer 904 can be configured to receive and / or assemble data received in transactions performed in single-wire communication mode.

[0078] The mode detection logic unit 910 can set the operating mode in response to an SSC signaling detected on SDATA 916. In some implementations, the mode detection logic 910 can set the operating mode in response to input or commands from a higher-level communication protocol implemented in the host device. For example, a component of the bus interface can set a single-wire operating mode when it determines that the destination of data provided by the application corresponds to a single-wire device. The single-wire transaction buffer 904 is enabled during single-wire operating mode, and the path selector circuit 906 is configured to guide the data flow between the single-wire transaction buffer 904 and the circuitry in the transmit and receive circuitry 908 for single-wire transmission. In some implementations, the transmit and receive circuitry 908 can respond to the mode detection logic unit 910 by, for example, disabling the driver circuitry to prevent the transmission of a clock signal via SCLK 918.

[0079] In some implementations, the transmitting and receiving circuitry 908 may include encoding circuitry that can be used in single-wire mode to provide pulse-width modulated data signals, Manchester-coded data signals, or other encoded signals to be transmitted via SDATA 916.

[0080] The host device 900 may include multiple address tables 922, 924 for identifying devices coupled to the hybrid serial bus. In the illustrated example, a first address table 922 associates a device ID with a corresponding device configurable for operation in two-wire mode, and a second address table 924 associates a device ID with a corresponding device configurable for operation in single-wire mode. One or more devices may be referenced in both address tables 922, 924. Address tables 922, 924 may be dynamically configured during manufacturing, system integration, and system initialization via commands issued by applications and / or by the host device 900. The use of multiple address tables 922, 924 can provide secure dual addressing for those devices that can support both two-wire and single-wire modes. In some implementations, dual-mode devices may have the same or different device IDs for both modes. Dual-mode devices may be configured to dynamically change their operating mode and simultaneously change their active device ID.

[0081] A change in operating mode in the bus interface of a slave device can be triggered by the duration of a Single Serial Scan (SSC) detected on the data lines of the hybrid RFFE bus. Slave devices configured according to certain aspects of this disclosure can be configured to prevent the detection of erroneous SSCs caused by bit sequences transmitted via the data lines of the hybrid RFFE bus in single-wire mode. Slave devices operating in single-wire mode can be configured to ignore significant SSCs that, when the hybrid bus operates in two-wire mode, are not preceded by a bus idle period of more than zero consecutive transmissions of maximum length. Devices operating in two-wire mode are expected to ignore erroneous SSCs when no clock signal is present on the hybrid RFFE bus.

[0082] Figure 10 This is a timing diagram 1000 illustrating a single-line erroneous SSC 1012 transmitted on a serial bus data line configured according to certain aspects of this disclosure. In the illustrated example, the host device initially initiates a two-line transaction by transmitting a two-line SSC 1006 on the SDATA line 1004. A clock signal is provided on the SCLK 1002, starting after the transmission of the two-line SSC 1006. During the transaction, a byte with the value 0x00 is transmitted. Parity bit 1010 provides odd parity, resulting in a 9-bit transmission 1008, where the SDATA line 1004 is low for at least 8 clock cycles before transitioning to a high state. The 8-bit 0x00 transmission satisfies or exceeds the minimum duration specified for a pulse on the SDATA line according to the conventional RFFE protocol to qualify as an SSC. After parity bit 1010, the next 9-bit transmission begins with a bit pattern 1014, which includes at least two bits with a value of "1", followed by a bit with a value of "0". The combined parity bit 1010 and bit pattern 1014 can be considered or referred to as error single-line SSC 1012.

[0083] In some implementations, a single-wire slave device may be configured or adapted, according to certain aspects of this disclosure, to ignore single-wire SSC transmissions on SDATA line 1004, which are not preceded by a predefined number of clock cycles. In one example, the number of clock cycles corresponds to a 10-bit transmission interval in a two-wire datagram. The number of clock cycles may be selected based on specific implementation details and other factors. In one example, the number of cycles may be increased or decreased based on the expected accuracy of the internal clock signal used by the single-wire slave device to measure the duration of idle periods or SSC pulses. In another example, the number of cycles may be increased when certain fields can be transmitted in a two-wire datagram without parity. In yet another example, the number of cycles may be increased when even parity is used in a two-wire datagram.

[0084] Figure 11 Examples of datagrams 1100 and 1120 are shown, which can conform to or be compatible with the standard RFFE protocol and can be transmitted in both single-line and double-line datagrams. Datagrams 1100 and 1120 represent Write commands that can be transmitted in datagrams defined by the RFFE protocol.

[0085] The first datagram 1100 corresponds to a register 0 write command with a limited data payload capacity. Datagram 1100 begins with the transmission of two SSC bits 1102, followed by a slave address 1104 or other device identifier. In the first datagram 1100, slave address 1104 has four bits. Next, an 8-bit command field 1106 is transmitted, where the first bit 1112 is set to indicate that the command is a register 0 write command. Command field 1106 also carries a seven-bit data payload. In the first datagram 1100, command field 1106 may include a parity bit 1108, and may be followed by bus-resident signaling 1110.

[0086] Datagram 1120 represents a generic Write command that can be sent in a datagram defined by the RFFE protocol. Datagram 1120 begins with the transmission of two SSC bits 1122, followed by four bits of address 1124 or another device identifier. Next, an 8-bit command code 1126 is sent. Parity bit 1128 may follow command code 1126. Address field 1130 is sent, which can be 8 bits or 11 bits long (for extended register write commands). Parity bit 1132 may follow address field 1130. One or more data frames 1134 may be sent, each with an accompanying parity bit 1136. Bus residency condition (BPC 1138) terminates datagram 1120. Each of the data frames 1134 may include an 8-bit byte with parity bit 1136.

[0087] Examples of processing circuits and methods

[0088] Figure 12This is a diagram illustrating an example of a hardware implementation of device 1200. In some examples, device 1200 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1202 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1202 may include one or more processors 1204 controlled by some combination of hardware modules and software modules. Examples of processors 1204 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1204 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1216. One or more processors 1204 may be configured by a combination of software modules 1216 loaded during initialization, and may also be configured by loading or unloading one or more software modules 1216 during operation.

[0089] In the illustrated example, processing circuitry 1202 can be implemented using a bus architecture, typically represented by bus 1210. Depending on the specific application of processing circuitry 1202 and overall design constraints, bus 1210 may include any number of interconnect buses and bridges. Bus 1210 links together various circuits including one or more processors 1204 and storage devices 1206. Storage devices 1206 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1210 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuitry. Bus interface 1208 provides an interface between bus 1210 and one or more transceivers 1212a, 1212b. Transceivers 1212a, 1212b may be provided for each networking technology supported by the processing circuitry. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1212a, 1212b. Each transceiver 1212a, 1212b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1212a may be used to couple device 1200 to a multi-wire bus. In another example, transceiver 1212b may be used to connect device 1200 to a radio access network. Depending on the nature of device 1200, a user interface 1218 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1210 either directly or via bus interface 1208.

[0090] Processor 1204 may be responsible for managing bus 1210 and for general processing, which may include executing software stored in a computer-readable medium that may include storage device 1206. In this regard, processing circuitry 1202 (including processor 1204) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1206 may be used to store data manipulated by processor 1204 when executing software, and the software may be configured to implement any of the methods disclosed herein.

[0091] One or more processors 1204 in processing circuitry 1202 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1206 or on an external computer-readable medium. External computer-readable media and / or storage device 1206 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1206 may also include, for example, carrier waves, transmit lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable media and / or storage device 1206 may reside in processing circuitry 1202, in processor 1204, outside of processing circuitry 1202, or distributed across multiple entities including processing circuitry 1202. The computer-readable media and / or storage device 1206 may be embodied in a computer program product. For example, a computer program product may include computer-readable media in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0092] Storage device 1206 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1216. Each software module in software module 1216 may include instructions and data that, when installed or loaded into processing circuitry 1202 and executed by one or more processors 1204, contribute to a runtime image 1214 controlling the operation of one or more processors 1204. Some instructions, when executed, cause processing circuitry 1202 to perform functions according to certain methods, algorithms, and processes described herein.

[0093] Some software modules in software module 1216 may be loaded during the initialization of processing circuitry 1202, and these software modules 1216 may configure processing circuitry 1202 to perform the various functions disclosed herein. For example, some software modules 1216 may configure the internal devices and / or logic circuitry 1222 of processor 1204, and may manage access to external devices such as transceivers 1212a, 1212b, bus interface 1208, user interface 1218, timers, math coprocessors, etc. Software module 1216 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1202. Resources may include memory, processing time, access to transceivers 1212a, 1212b, user interface 1218, etc.

[0094] One or more processors 1204 of the processing circuitry 1202 can be multifunctional, whereby some software modules in software module 1216 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1204 may additionally be adapted to manage background tasks initiated in response to inputs, such as from user interface 1218, transceivers 1212a, 1212b, and device drivers. To support the execution of multiple functions, one or more processors 1204 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1204 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1220 that transfers control of the processors 1204 between different tasks, whereby each task returns control of one or more processors 1204 to the time-sharing program 1220 upon completion of any pending operations and / or in response to inputs such as interrupts. When a task has control over one or more processors 1204, the processing circuitry is effectively dedicated to the purpose addressed by the functions associated with the control task. The time-sharing program 1220 may include an operating system, a main loop for loop-based transfer control, a function to allocate control of one or more processors 1204 according to function priority, and / or an interrupt-driven main loop to provide control of one or more processors 1204 to processing functions in response to external events.

[0095] Methods for optimizing virtual GPIO latency may include parsing the actions of various input sources, including the source of GPIO signal states, parameters, and / or messages to be transmitted. Input sources may include hardware events, configuration data, mask parameters, and register addresses. A packet-specific latency estimator may be employed to estimate the latency of the corresponding packet type based on the parsed parameters. The packet type to be transmitted may be selected based on the minimum latency calculated or determined for the available packet types. The selected packet type may be identified using a command code, which may be provided to the packetizer along with the payload to be transmitted. The command code may also reflect the protocol to be used to transmit the payload. In some implementations, the physical link used to transmit the payload may operate according to different protocols or different variants of one or more protocols. The protocol to be used to transmit the payload may be selected based on the latency associated with various available protocols or protocol variants.

[0096] Figure 13 Flowchart 1300 shows a method that can be performed by a host device coupled to a serial bus. One or more single-wire slave devices and one or more two-wire slave devices can be coupled to the serial bus.

[0097] In block 1302, the host device can configure a unique device identifier for each of the first plurality of slave devices. In block 1304, the host device can configure a unique device identifier for each of the second plurality of slave devices. In block 1306, the host device can transmit a sequence start condition via the data lines of the serial bus, the sequence start condition indicating whether clock pulses will be provided concurrently with the transaction initiated by the sequence start condition in the clock signal on the clock lines of the serial bus. In block 1308, when the sequence start condition indicates that clock pulses will be provided concurrently in the clock signal, the host device can use the device identifier associated with the first plurality of slave devices to send a first datagram to one of the slave devices via the serial bus. In block 1310, when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal, the host device can use the device identifier associated with the second plurality of slave devices to send a second datagram to one of the second plurality of slave devices via the serial bus. In some instances, one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

[0098] In some examples, a dual-mode slave device is included in a first plurality of slave devices and a second plurality of slave devices. The host device may configure a first device identifier to the dual-mode slave device, which is associated with the first plurality of slave devices and used by the dual-mode slave device for communication via the serial bus when a sequence start condition indicates that clock pulses will be provided concurrently in the clock signal. The host device may configure a second device identifier to the dual-mode slave device, which is associated with the second plurality of slave devices and used by the dual-mode slave device for communication via the serial bus when a sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal. In some examples, the first device identifier has the same value as the second device identifier. In some examples, the first device identifier and the second device identifier have different values.

[0099] In some specific implementations, the sequence start condition has a first duration when indicating that clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0100] In some specific implementations, the host device may configure each of the second or more slave devices to ignore the sequence start condition unless there is an idle period preceding the sequence start condition, which has a minimum duration calculated based on the transmission time of the data bytes transmitted via the serial bus.

[0101] Figure 14 This is a simplified example illustration of a hardware implementation of a device 1400 employing processing circuitry 1402. The processing circuitry typically has a controller or processor 1416 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1402 can be implemented using a bus architecture, typically represented by bus 1410. Depending on the specific application of processing circuitry 1402 and overall design constraints, bus 1410 may include any number of interconnect buses and bridges. Bus 1410 links together various circuits including controller or processor 1416, modules or circuits 1404, 1406, and 1408, and processor-readable storage medium 1418. One or more physical layer circuits and / or modules 1414 may be provided to support communication via a communication link implemented using a multi-wire bus 1412, via an antenna or antenna array 1422 (e.g., to a radio access network), etc. Bus 1410 may also link various other circuits such as timing sources, peripheral devices, voltage regulators and power management circuits, which are well known in the art and will therefore not be described further.

[0102] Processor 1416 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1418. The processor-readable storage medium may include non-transitory storage. When executed by processor 1416, the software causes processing circuitry 1402 to perform the various functions described above for any particular device. The processor-readable storage medium can be used to store data manipulated by processor 1416 during software execution. Processing circuitry 1402 also includes at least one of modules 1404, 1406, and 1408. Modules 1404, 1406, and 1408 may be software modules residing in / stored in processor-readable storage medium 1418, running in processor 1416, one or more hardware modules coupled to processor 1416, or some combination thereof. Modules 1404, 1406, and 1408 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0103] In one configuration, device 1400 includes a module and / or circuitry 1404 adapted to provide an SSC indicating whether a single-wire or two-wire transaction will occur via a serial bus. Device 1400 may include a module and / or circuitry 1406 adapted to encode, decode, transmit, and receive data, and a module and / or circuitry 1408 adapted to manage multiple address tables that maintain device IDs and assign device IDs to single-wire and two-wire slave devices.

[0104] In one example, device 1400 includes physical layer circuitry and / or module 1414 that implements interface circuitry adapted to couple device 1400 to two lines of a serial bus. The device 1400 may have a protocol controller configured to assign a unique device identifier to each of a first plurality of slave devices and a unique device identifier to each of a second plurality of slave devices; transmit a sequence start condition via a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in the clock signal on the clock line of the serial bus; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, send a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, send a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0105] In one example, one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

[0106] In some examples, the dual-mode slave device is included in a first plurality of slave devices and a second plurality of slave devices. The protocol controller can also be configured to: configure a first device identifier to the dual-mode slave device, which is associated with the first plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when a sequence start condition indicates that clock pulses will be provided concurrently in the clock signal; and configure a second device identifier to the dual-mode slave device, which is associated with the second plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when a sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal. The first device identifier may have the same value as the second device identifier, or it may have different values.

[0107] In some specific implementations, the sequence start condition has a first duration when indicating that clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0108] In some implementations, the protocol controller is also configured to configure each of the second plurality of slave devices to ignore the sequence start condition unless there is an idle period preceding the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of the data bytes transmitted via the serial bus.

[0109] Processor-readable storage medium 1418 may include a transient or non-transient storage device configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. The processor-readable storage medium 1418 may include code configured to: configure each of the first plurality of slave devices with a unique device identifier within the first plurality of slave devices; configure each of the second plurality of slave devices with a unique device identifier within the second plurality of slave devices; transmit a sequence start condition via a data line of a serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in a clock signal on the clock line of the serial bus; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, transmit a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, transmit a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0110] In some implementations, the processor-readable storage medium 1418 includes code for: configuring a first device identifier to a dual-mode slave device, the first device identifier being associated with a first plurality of slave devices and used by the dual-mode slave device to communicate via a serial bus when a sequence start condition indicates that clock pulses will be provided concurrently in a clock signal; and configuring a second device identifier to a dual-mode slave device, the second device identifier being associated with a second plurality of slave devices and used by the dual-mode slave device to communicate via a serial bus when a sequence start condition indicates that no clock pulses will be provided concurrently in a clock signal.

[0111] In some implementations, the processor-readable storage medium 1418 includes code for configuring each of the second plurality of slave devices to ignore a sequence start condition unless there is an idle period preceding the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of data bytes transmitted via the serial bus.

[0112] Figure 15Flowchart 1500 illustrates a method that can be performed by a dual-mode slave device coupled to a serial bus. At least one master device is coupled to the serial bus. One or more single-wire slave devices and one or more dual-wire slave devices can be coupled to the serial bus.

[0113] In block 1502, the dual-mode slave device can receive a first sequence start condition from the data line of the serial bus, which indicates a first operating mode of the serial bus. In this first operating mode, a first datagram transmitted after the first sequence start condition will be transmitted concurrently with a clock pulse in a clock signal transmitted on the clock line of the serial bus. In block 1504, the dual-mode slave device can receive a second sequence start condition from the data line, which indicates a second operating mode of the serial bus. In this second operating mode, a second datagram transmitted after the second sequence start condition will be transmitted along with embedded clock information in the data signal. In block 1506, the dual-mode slave device can respond to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device. In block 1508, the dual-mode slave device can respond to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device. In one example, the first device identifier has the same value as the second device identifier. In another example, the first device identifier and the second device identifier have different values.

[0114] In some specific implementations, when there is an idle period before the third sequence start condition, the dual-mode slave device can ignore the third sequence start condition. This idle period has a duration less than the transmission time of the data bytes transmitted via the serial bus.

[0115] In some implementations, a dual-mode slave device can receive a lock command that restricts the slave device to a first operating mode, and can discard a third command included in a third datagram sent when the serial bus is operating in a second operating mode.

[0116] In some implementations, a dual-mode slave device can receive a lock command that restricts the slave device to a second operating mode, and can discard a fourth command included in a fourth datagram sent when the serial bus is operating in the first operating mode.

[0117] In some specific implementations, the sequence start condition has a first duration when indicating that clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0118] Figure 16This is a simplified example illustration of a hardware implementation of a device 1600 employing processing circuitry 1602. The processing circuitry typically has a controller or processor 1616 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1602 can be implemented using a bus architecture, typically represented by bus 1610. Depending on the specific application of processing circuitry 1602 and overall design constraints, bus 1610 may include any number of interconnect buses and bridges. Bus 1610 links together various circuits including controller or processor 1616, modules or circuits 1604, 1606, and 1608, and processor-readable storage medium 1618. One or more physical layer circuits and / or modules 1614 may be provided to support communication links implemented using multi-wire bus 1612, communication via antennas or antenna arrays 1622 (e.g., to a radio access network), etc. The bus 1610 can also link various other circuits such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0119] Processor 1616 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1618. Processor-readable storage medium may include non-transitory storage medium. When executed by processor 1616, the software causes processing circuitry 1602 to perform the various functions described above for any particular device. Processor-readable storage medium can be used to store data manipulated by processor 1616 during software execution. Processing circuitry 1602 also includes at least one of modules 1604, 1606, and 1608. Modules 1604, 1606, and 1608 may be software modules residing in / stored in processor-readable storage medium 1618, running in processor 1616, one or more hardware modules coupled to processor 1616, or some combination thereof. Modules 1604, 1606, and 1608 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0120] In one configuration, device 1600 includes a module and / or circuitry 1604 adapted to detect a Single Wire Transaction Center (SSC), the SSC indicating whether a single-wire or dual-wire transaction will occur via the serial bus based on the duration of the SSC. Device 1600 may include a module and / or circuitry 1606 adapted to manage addresses used when participating in single-wire and dual-wire transactions, and a module and / or circuitry 1608 adapted to determine the operating mode (including single-wire and dual-wire operating modes).

[0121] In one example, device 1600 includes physical layer circuitry and / or module 1614 that implements interface circuitry adapted to couple device 1600 to a serial bus. Device 1600 may have a protocol controller. Processor 1616 may be configured to receive a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition will be transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition will be transmitted along with embedded clock information in the data signal; respond to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device; and respond to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device. The first device identifier may have the same value as the second device identifier, or the first device identifier and the second device identifier may have different values.

[0122] In some implementations, the processor 1616 is also configured to ignore the third sequence start condition when there is an idle period preceding the third sequence start condition, the idle period having a duration less than the transmission time of the data bytes transmitted via the serial bus.

[0123] In some implementations, the processor 1616 is also configured to receive a lock command that restricts the subordinate device to a first operating mode; and to discard a third command included in a third datagram sent when the serial bus is operating in a second operating mode.

[0124] In some implementations, the processor 1616 is also configured to receive a lock command that restricts the subordinate device to a second operating mode; and to discard a fourth command included in a fourth datagram sent when the serial bus is operating in a first operating mode.

[0125] In some specific implementations, the sequence start condition has a first duration when indicating that clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0126] Processor-readable storage medium 1618 may include transient or non-transitory storage devices configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. Processor-readable storage medium 1618 may include code configured to: receive a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition will be transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition will be transmitted together with embedded clock information in the data signal; respond to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device; and respond to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device.

[0127] In some implementations, the processor-readable storage medium 1618 includes code for ignoring the third sequence start condition when there is an idle period prior to the third sequence start condition, the idle period having a duration less than the transmission time of the data bytes transmitted via the serial bus.

[0128] In some implementations, the processor-readable storage medium 1618 includes code for: receiving a lock command that restricts a subordinate device to a first operating mode; and discarding a third command included in a third datagram sent when the serial bus is operating in a second operating mode.

[0129] In some implementations, the processor-readable storage medium 1618 includes code for: receiving a lock command that restricts a subordinate device to a second operating mode; and discarding a fourth command included in a fourth datagram sent when the serial bus is operating in a first operating mode.

[0130] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0131] Some specific implementation examples are described in the following numbered clauses:

[0132] 1. A method for data communication at a host device, the method comprising: configuring a device identifier unique within the first plurality of slave devices for each of the first plurality of slave devices; configuring a device identifier unique within the second plurality of slave devices for each of the second plurality of slave devices; transmitting a sequence start condition via a data line of a serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in a clock signal on a clock line of the serial bus; when the sequence start condition indicates that the clock pulse will be provided concurrently in the clock signal, transmitting a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, transmitting a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0133] 2. The method as described in Clause 1, wherein one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

[0134] 3. The method as described in Clause 1 or Clause 2, wherein the dual-mode slave device is included in the first plurality of slave devices and the second plurality of slave devices.

[0135] 4. The method of Clause 3, further comprising: configuring a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal; and configuring a second device identifier to the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal.

[0136] 5. The method as described in Clause 4, wherein the first device identifier has the same value as the second device identifier.

[0137] 6. The method as described in Clause 4, wherein the first device identifier and the second device identifier have different values.

[0138] 7. The method of any one of Clauses 1 to 6, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0139] 8. The method of any one of clauses 1 to 7, further comprising: configuring each of the second plurality of slave devices to ignore the sequence start condition unless there is an idle period prior to the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of data bytes transmitted via the serial bus.

[0140] 9. A data communication device, the data communication device comprising: an interface circuit adapted to couple the data communication device to two lines of a serial bus; and a protocol controller configured to: configure a unique device identifier within the first plurality of slave devices for each of the first plurality of slave devices; and configure a unique device identifier within the second plurality of slave devices for each of the second plurality of slave devices;

[0141] A sequence start condition is transmitted via the data lines of the serial bus, the sequence start condition indicating whether a clock pulse will be provided concurrently with a transaction initiated by the sequence start condition in the clock signal on the clock line of the serial bus; when the sequence start condition indicates that the clock pulse will be provided concurrently in the clock signal, a first datagram is transmitted via the serial bus to one of the first plurality of slave devices using a device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, a second datagram is transmitted via the serial bus to one of the second plurality of slave devices using a device identifier associated with the second plurality of slave devices.

[0142] 10. The data communication apparatus as described in Clause 9, wherein one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

[0143] 11. The data communication apparatus as described in Clause 9 or Clause 10, wherein the dual-mode slave device is included in the first plurality of slave devices and the second plurality of slave devices.

[0144] 12. The data communication apparatus as described in Clause 11, wherein the protocol controller is further configured to: configure a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device for communication via the serial bus when the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal; and configure a second device identifier to the dual-mode slave device, the second device identifier being associated with the second ... second plurality of slave devices; and configure a second device identifier to the dual-mode

[0145] The start condition indicates that communication will take place via the serial bus when no clock pulses will be provided concurrently in the clock signal.

[0146] 13. The data communication apparatus as described in Clause 12, wherein the first device identifier has the same value as the second device identifier.

[0147] 14. The data communication apparatus as described in Clause 12, wherein the first device identifier and the second device identifier have different values.

[0148] 15. A data communication apparatus as described in any one of Clauses 9 to 14, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0149] 16. The data communication apparatus of any one of clauses 9 to 15, wherein the protocol controller is further configured to: configure each of the second plurality of slave devices to ignore the sequence start condition unless there is an idle period prior to the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of data bytes transmitted via the serial bus.

[0150] 17. A method for data communication at a slave device, the method comprising: receiving a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition is transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition is transmitted together with embedded clock information in the data signal; responding to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device; and responding to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device.

[0151] 18. The method as described in Clause 17, wherein the first device identifier has the same value as the second device identifier.

[0152] 19. The method as described in Clause 17, wherein the first device identifier and the second device identifier have different values.

[0153] 20. The method of any one of clauses 17 to 19, further comprising: ignoring the third sequence start condition when there is an idle period prior to the third sequence start condition, the idle period having a duration less than the transmission time of the data bytes transmitted via the serial bus.

[0154] 21. The method of any one of clauses 17 to 20, further comprising: receiving a locking command that restricts the slave device to the first operating mode; and discarding a third command included in a third datagram transmitted when the serial bus is operating in the second operating mode.

[0155] 22. The method of any one of clauses 17 to 20, further comprising: receiving a lock command that restricts the slave device to the second operating mode; and discarding a fourth command included in a fourth datagram transmitted when the serial bus is operating in the first operating mode.

[0156] 23. The method of any one of clauses 17 to 22, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration longer than the first duration.

[0157] 24. An apparatus comprising: interface circuitry adapted to couple the apparatus to a serial bus; and a processor configured to: receive from a data line of the serial bus a first sequence start condition, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition will be transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receive from the data line a second sequence start condition, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition will be transmitted together with embedded clock information in the data signal; respond to a first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the apparatus; and respond to a second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the apparatus.

[0158] 25. The apparatus as described in Clause 24, wherein the first device identifier has the same value as the second device identifier.

[0159] 26. The apparatus as described in Clause 24, wherein the first device identifier and the second device identifier have different values.

[0160] 27. The apparatus of any one of clauses 24 to 26, wherein the processor is further configured to: ignore the third sequence start condition when there is an idle period prior to the third sequence start condition, the idle period having a duration less than the transmission time of the data bytes transmitted via the serial bus.

[0161] 28. The apparatus of any one of clauses 24 to 27, wherein the processor is further configured to: receive a locking command that restricts the apparatus to the first operating mode; and discard a third command included in a third datagram transmitted when the serial bus is operating in the second operating mode.

[0162] 29. The apparatus of any one of clauses 24 to 27, wherein the processor is further configured to: receive a locking command that restricts the apparatus to the second operating mode; and discard a fourth command included in a fourth datagram transmitted when the serial bus is operating in the first operating mode.

[0163] 30. The apparatus of any one of clauses 24 to 29, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration longer than the first duration.

[0164] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the language of the claims, wherein an element referred to in the singular is not intended to mean “one and only one,” but rather “one or more” unless specifically stated otherwise. Unless otherwise stated, the term “some” means one or more. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly recited in the claims. No claim element should be construed as a component plus a function unless the element is expressly stated using the phrase “component for…”.

Claims

1. A method for performing data communication at a host device, the method comprising: The protocol controller in the host device coupled to the serial bus configures each of the first plurality of slave devices with a unique device identifier within the first plurality of slave devices; The protocol controller configures each of the second plurality of slave devices with a unique device identifier within the second plurality of slave devices; The operating mode of the host device is set based on the capability of another device selected to participate in one or more transactions, wherein each of the first plurality of slave devices is capable of operating when a clock pulse is provided on the clock line of the serial bus, and wherein each of the second plurality of slave devices is capable of operating when no clock pulse is provided on the clock line of the serial bus. The sequence start conditions are transmitted via the serial bus, each of the sequence start conditions being configured to initiate a corresponding transaction and indicating whether a clock pulse will be transmitted in the clock signal via the clock line of the serial bus during the corresponding transaction; When the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal, a first datagram is sent to one of the first plurality of slave devices via the serial bus using a device identifier associated with the first plurality of slave devices; as well as When the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal, a second datagram is sent to one of the second plurality of slave devices via the serial bus using a device identifier associated with the second plurality of slave devices.

2. The method according to claim 1, wherein one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

3. The method of claim 1, wherein the dual-mode slave device is included in the first plurality of slave devices and the second plurality of slave devices.

4. The method according to claim 3, further comprising: Configure a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal; as well as A second device identifier is configured for the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal.

5. The method of claim 4, wherein the first device identifier has the same value as the second device identifier.

6. The method of claim 4, wherein the first device identifier and the second device identifier have different values.

7. The method of claim 1, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

8. The method according to claim 1, further comprising: The protocol controller configures each of the second plurality of slave devices to ignore the sequence start condition unless there is an idle period preceding the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of data bytes transmitted via the serial bus.

9. A data communication device, the data communication device comprising: An interface circuit adapted to couple the data communication device to two lines of a serial bus; and Protocol controller, the protocol controller being configured to: Configure a unique device identifier within each of the first plurality of slave devices; Configure a unique device identifier within each of the second plurality of slave devices; The operating mode of the interface circuit is set based on the capability of another device selected to participate in one or more transactions, wherein each of the first plurality of slave devices is capable of operating when a clock pulse is provided on the clock line of the serial bus, and wherein each of the second plurality of slave devices is capable of operating when no clock pulse is provided on the clock line of the serial bus. The sequence start conditions are transmitted via the serial bus, each of the sequence start conditions being configured to initiate a corresponding transaction and indicating whether a clock pulse will be transmitted in the clock signal via the clock line of the serial bus during the corresponding transaction; When the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal, a first datagram is sent to one of the first plurality of slave devices via the serial bus using a device identifier associated with the first plurality of slave devices; as well as When the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal, a second datagram is sent to one of the second plurality of slave devices via the serial bus using a device identifier associated with the second plurality of slave devices.

10. The data communication apparatus according to claim 9, wherein one of the first plurality of slave devices and one of the second plurality of slave devices have the same device identifier.

11. The data communication apparatus of claim 9, wherein the dual-mode slave device is included in the first plurality of slave devices and the second plurality of slave devices.

12. The data communication apparatus of claim 11, wherein the protocol controller is further configured to: Configure a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal; and A second device identifier is configured for the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and used by the dual-mode slave device to communicate via the serial bus when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal.

13. The data communication apparatus of claim 12, wherein the first device identifier has the same value as the second device identifier.

14. The data communication apparatus of claim 12, wherein the first device identifier and the second device identifier have different values.

15. The data communication apparatus of claim 9, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

16. The data communication apparatus according to claim 9, wherein the protocol controller is further configured to: Each of the second plurality of slave devices is configured to ignore the sequence start condition unless there is an idle period prior to the sequence start condition, the idle period having a minimum duration calculated based on the transmission time of data bytes transmitted via the serial bus.

17. A method for performing data communication at a slave device, the method comprising: A first sequence start condition is received from the data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition will be sent concurrently with a clock pulse in a clock signal sent on the clock line of the serial bus. The slave device is set to a first operating mode based on the duration of the first sequence start condition, wherein when the first operating mode is set, a clock pulse is provided on the clock line of the serial bus. When a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device, the first command is responded to; as well as The second operating mode of the slave device is set based on the duration of the first sequence start condition, wherein when the second operating mode is set, no clock pulse is provided on the clock line of the serial bus; A second sequence start condition is received from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram is sent after the second sequence start condition using clock information provided by an internal clock signal; as well as The second command is responded to when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device.

18. The method of claim 17, wherein the first device identifier has the same value as the second device identifier.

19. The method of claim 17, wherein the first device identifier and the second device identifier have different values.

20. The method of claim 17, further comprising: When there is an idle period before the start condition of the third sequence, the start condition of the third sequence is ignored, and the idle period has a duration less than the transmission time of the data bytes transmitted through the serial bus.

21. The method according to claim 17, further comprising: Receive a lock command to restrict the slave device to the first operating mode; as well as Discard the third command included in the third datagram sent when the serial bus is operating in the second operating mode.

22. The method of claim 17, further comprising: Receive a lock command to restrict the slave device to the second operating mode; as well as The fourth command included in the fourth datagram sent when the serial bus is operating in the first operating mode is discarded.

23. The method of claim 17, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration longer than the first duration.

24. An apparatus comprising: An interface circuit adapted to couple the device to a serial bus; and Processor, the processor being configured to: A first sequence start condition is received from the data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition will be sent concurrently with a clock pulse in a clock signal sent on the clock line of the serial bus. A first operating mode of the interface circuit is set based on the duration of the first sequence start condition, wherein when the first operating mode is set, a clock pulse is provided on the clock line of the serial bus. When a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the device, the first command is responded to; as well as The second operating mode of the interface circuit is set based on the duration of the first sequence start condition, wherein when the second operating mode is set, no clock pulse is provided on the clock line of the serial bus; A second sequence start condition is received from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram is sent after the second sequence start condition using clock information provided by an internal clock signal; as well as The second command is responded to when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the device.

25. The apparatus of claim 24, wherein the first device identifier has the same value as the second device identifier.

26. The apparatus of claim 24, wherein the first device identifier and the second device identifier have different values.

27. The apparatus of claim 24, wherein the processor is further configured to: When there is an idle period before the start condition of the third sequence, the start condition of the third sequence is ignored, and the idle period has a duration less than the transmission time of the data bytes transmitted through the serial bus.

28. The apparatus of claim 24, wherein the processor is further configured to: Receive a locking command to restrict the device to the first operating mode; and Discard the third command included in the third datagram sent when the serial bus is operating in the second operating mode.

29. The apparatus of claim 24, wherein the processor is further configured to: Receive a locking command to restrict the device to the second operating mode; and The fourth command included in the fourth datagram sent when the serial bus is operating in the first operating mode is discarded.

30. The apparatus of claim 24, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration longer than the first duration.

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