Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of pixel driving circuits. Each of the plurality of pixel driving circuits includes a driving transistor, a light shielding member, and a node connecting line. The orthographic projection of the shading part on the substrate basically covers the orthographic projection of the active layer of the driving transistor on the substrate. The light shield is electrically connected to the gate of the driving transistor through a node connection line. The light shield, the node connection line, and the gate of the driving transistor are located in three different layers.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light-emitting diode (OLED) displays are one of the hot topics in the field of flat panel display research today. Unlike thin-film transistor liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with pixel drive circuits arranged in multiple rows and columns. Each pixel drive circuit includes a drive transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the drive transistor is turned on, and a data voltage is applied from the data line to the drive transistor via the switching transistor, so that the drive transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits comprises a driving transistor, a shading member and a node connection line; wherein the orthographic projection of the shading member on the base substrate substantially covers the orthographic projection of the active layer of the driving transistor on the base substrate; the shading member is electrically connected to the gate of the driving transistor through the node connection line; the shading member, the node connection line and the gate of the driving transistor are located in three different layers.

[0004] Optionally, each pixel driving circuit further includes a first reset transistor; wherein the light shielding member is electrically connected to the second electrode of the first reset transistor through the node connection line.

[0005] Optionally, each pixel driving circuit further includes a storage capacitor; wherein the positive projection of the shading member on the substrate substantially covers the positive projection of the gate of the driving transistor on the substrate, and substantially covers the positive projection of the second capacitor electrode of the storage capacitor on the substrate.

[0006] Optionally, the array substrate further includes a plurality of third voltage supply lines; wherein each pixel driving circuit further includes a light-emitting control transistor and a second reset transistor; the orthographic projection of each third voltage supply line among the plurality of third voltage supply lines on the substrate substantially covers the orthographic projection of the active layer of the light-emitting control transistor in the corresponding pixel driving circuit on the substrate, substantially covers the orthographic projection of the active layer of the second reset transistor on the substrate, and at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate.

[0007] Optionally, the orthographic projection of each of the multiple third voltage supply lines on the substrate substantially covers the orthographic projection of the combination of the active layer, the first electrode and the second electrode of the light-emitting control transistor in the corresponding pixel driving circuit on the substrate; substantially covers the orthographic projection of the combination of the active layer, the first electrode and the second electrode of the second reset transistor on the substrate; substantially covers the orthographic projection of the combination of the first electrode and the second electrode of the driving transistor on the substrate; and at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate.

[0008] Optionally, the array substrate further includes a plurality of fourth voltage supply lines; wherein, each pixel driving circuit further includes a data write transistor and a first reset transistor; in the first column pixel driving circuit, the positive projection of the corresponding fourth voltage supply line among the plurality of fourth voltage supply lines on the substrate substantially covers the positive projection of the active layer of the first reset transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate, and substantially covers the positive projection of the active layer of the data write transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate.

[0009] Optionally, in the first column pixel driving circuit, the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines on the substrate substantially covers the positive projection of the combination of the active layer, the first electrode and the second electrode of the first reset transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate, and substantially covers the positive projection of the combination of the active layer and the second electrode of the data writing transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate.

[0010] Optionally, the array substrate further includes a plurality of fourth reset signal lines; wherein, each pixel driving circuit further includes a data write transistor and a first reset transistor; in the second column pixel driving circuit, the orthographic projection of the corresponding fourth reset signal line among the plurality of fourth reset signal lines on the substrate substantially covers the orthographic projection of the active layer of the first reset transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate, and substantially covers the orthographic projection of the active layer of the data write transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate.

[0011] Optionally, in the second column pixel driving circuit, the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines on the substrate basically covers the positive projection of the active layer, the first electrode and the second electrode of the first reset transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate; and basically covers the positive projection of the active layer and the second electrode of the data writing transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate.

[0012] Optionally, the array substrate further includes a plurality of third reset signal lines; wherein, each pixel driving circuit further includes a data write transistor and a first reset transistor; in the third column pixel driving circuit, the orthographic projection of the corresponding third reset signal line among the plurality of third reset signal lines on the substrate substantially covers the orthographic projection of the active layer of the first reset transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate, and substantially covers the orthographic projection of the active layer of the data write transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate.

[0013] Optionally, in the third column pixel driving circuit, the positive projection of the corresponding third reset signal line among the multiple third reset signal lines on the substrate basically covers the positive projection of the active layer, the first electrode and the second electrode of the first reset transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate; and basically covers the positive projection of the active layer and the second electrode of the data writing transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate.

[0014] Optionally, the array substrate further includes a plurality of fourth voltage supply lines; wherein each pixel driving circuit further includes a data write transistor and a first reset transistor; the pixel driving circuits of the array substrate are arranged into multiple columns, and the multiple columns include the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); in the pixel driving circuit of the (3k-2)th column, the corresponding fourth voltage supply line of the multiple fourth voltage supply lines has a positive projection on the substrate that substantially covers the positive projection of the active layer of the first reset transistor in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column on the substrate, and substantially covers the positive projection of the active layer of the data write transistor in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column on the substrate.

[0015] Optionally, the array substrate further includes a plurality of fourth reset signal lines; wherein each pixel driving circuit further includes a data write transistor and a first reset transistor; the pixel driving circuits of the array substrate are arranged into multiple columns, and the multiple columns include the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); in the pixel driving circuit of the (3k-1)th column, the corresponding fourth reset signal line of the multiple fourth reset signal lines has a positive projection on the substrate that substantially covers the positive projection of the active layer of the first reset transistor in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column on the substrate, and substantially covers the positive projection of the active layer of the data write transistor in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column on the substrate.

[0016] Optionally, the array substrate further includes a plurality of third reset signal lines; wherein each pixel driving circuit further includes a data write transistor and a first reset transistor; the pixel driving circuits of the array substrate are arranged into multiple columns, and the multiple columns include the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); in the pixel driving circuit of the (3k)th column, the corresponding third reset signal line of the multiple third reset signal lines has a positive projection on the substrate that substantially covers the positive projection of the active layer of the first reset transistor in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column on the substrate, and substantially covers the positive projection of the active layer of the data write transistor in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column on the substrate.

[0017] Optionally, the array substrate further includes a plurality of fourth voltage supply lines, a plurality of fourth reset signal lines, and a plurality of third reset signal lines located in the same layer; wherein the pixel driving circuit of the array substrate is arranged into multiple columns, the multiple columns including the (3k-2)th column, the (3k-1)th column, and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); the (3k-2)th column includes the fourth voltage supply line among the multiple fourth voltage supply lines; the (3k-1)th column includes the fourth reset signal line among the multiple fourth reset signal lines; and the (3k)th column includes the third reset signal line among the multiple third reset signal lines.

[0018] Optionally, the plurality of fourth voltage supply lines do not exist in the (3k-1)th column and do not exist in the (3k)th column; the plurality of fourth reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k)th column; and the plurality of third reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k-1)th column.

[0019] Optionally, the array substrate further includes a first voltage supply network and a second voltage supply network; wherein the first voltage supply network includes a plurality of first voltage supply lines and a plurality of third voltage supply lines interconnected with each other; the plurality of first voltage supply lines extend in a direction substantially parallel to the first direction; and the plurality of third voltage supply lines extend in a direction substantially parallel to the second direction.

[0020] Each of the plurality of first voltage supply lines is connected to one or more third voltage supply lines among the plurality of third voltage supply lines; each of the plurality of third voltage supply lines is connected to one or more first voltage supply lines among the plurality of first voltage supply lines; and wherein the second voltage supply network comprises a plurality of second voltage supply lines and a plurality of fourth voltage supply lines interconnected with each other; the plurality of second voltage supply lines extend in a direction substantially parallel to the first direction; the plurality of fourth voltage supply lines extend in a direction substantially parallel to the second direction; each of the plurality of second voltage supply lines is connected to one of the plurality of fourth voltage supply lines one or more fourth voltage supply lines; and each of the plurality of fourth voltage supply lines is connected to one or more second voltage supply lines among the plurality of second voltage supply lines; wherein the pixel driving circuits of the array substrate are arranged into multiple columns, and the multiple columns include the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); the multiple third voltage supply lines exist in the (3k-2)th column, in the (3k-1)th column, and in the (3k)th column; the multiple fourth voltage supply lines do not exist in the (3k-1)th column and do not exist in the (3k)th column.

[0021] Optionally, the array substrate further includes a first reset signal network; wherein the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; the plurality of first reset signal lines extend in a direction substantially parallel to the first direction; the plurality of third reset signal lines extend in a direction substantially parallel to the second direction; each first reset signal line among the plurality of first reset signal lines is connected to one or more third reset signal lines among the plurality of third reset signal lines; and each third reset signal line among the plurality of third reset signal lines is connected to one or more first reset signal lines among the plurality of first reset signal lines; wherein the pixel driving circuit of the array substrate is arranged into multiple columns, the multiple columns including the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); and the multiple third reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k-1)th column.

[0022] Optionally, the array substrate further includes a second reset signal network; wherein the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; the plurality of second reset signal lines extend in a direction substantially parallel to the first direction; the plurality of fourth reset signal lines extend in a direction substantially parallel to the second direction; each second reset signal line in the plurality of second reset signal lines is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines; and each fourth reset signal line in the plurality of fourth reset signal lines is connected to one or more second reset signal lines in the plurality of second reset signal lines; wherein the pixel driving circuit of the array substrate is arranged into multiple columns, the multiple columns including the (3k-2)th column, the (3k-1)th column and the (3k)th column in the K column, wherein K and k are positive integers, 1≤k≤(K / 3); and the multiple fourth reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k)th column.

[0023] In another aspect, the present disclosure provides a display device comprising the array substrate described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings are examples for illustration purposes only, in accordance with various disclosed embodiments, and are not intended to limit the scope of the invention.

[0025] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0026] Figure 2A is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 3A is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0029] Figure 3B It shows Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG.

[0030] Figure 3C It shows Figure 3A Schematic diagram of the structure of the light shielding layer in a portion of the array substrate depicted in FIG.

[0031] Figure 3D It shows Figure 3ASchematic diagram of the structure of the first conductive layer in a portion of an array substrate depicted in FIG.

[0032] Figure 3E It shows Figure 3A Schematic diagram of the structure of the first gate insulating layer in a portion of an array substrate depicted in FIG.

[0033] Figure 3F It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer in a portion of the array substrate depicted in FIG.

[0034] Figure 3G It shows Figure 3A Schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in FIG.

[0035] Figure 3H It shows Figure 3A Schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in FIG.

[0036] Figure 3I It shows Figure 3A Schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in FIG.

[0037] Figure 3J It shows Figure 3A Schematic diagram of the structure of the first planarization layer in a portion of an array substrate depicted in FIG.

[0038] Figure 3K It shows Figure 3A Schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in FIG.

[0039] Figure 3L It shows Figure 3A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in FIG.

[0040] Figure 4A It is along Figure 3A Cross-sectional view along line AA'.

[0041] Figure 4B It is along Figure 3A Cross-sectional view along line BB'.

[0042] Figure 5 is a schematic diagram illustrating the structure of a first voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 6 is a schematic diagram illustrating the structure of a second voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 7 is a schematic diagram illustrating the structure of a first reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 8 is a schematic diagram illustrating the structure of a second reset signal network in a portion of an array substrate according to some embodiments of the present disclosure.

[0046] Figure 9 It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer and the second signal line layer in a portion of the array substrate depicted in FIG. DETAILED DESCRIPTION

[0047] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0048] The present disclosure particularly provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a shading member and a node connection line. Optionally, the orthographic projection of the shading member on the substrate substantially covers the orthographic projection of the active layer of the driving transistor on the substrate. Optionally, the shading member is electrically connected to the gate of the driving transistor via a node connection line. Optionally, the shading member, the node connection line and the gate of the driving transistor are located in three different layers.

[0049] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 5T1C driving circuit. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 5T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0050] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd (for example, a plurality of first voltage supply lines or a plurality of third voltage supply lines). Each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC to emit light. In one example, a high voltage signal (for example, a VDD signal) is input to a corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each of the plurality of voltage supply lines Vdd; a low voltage signal (for example, a VSS signal) is input to the cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (for example, the VDD signal) and the low voltage signal (for example, the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0051] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2A In some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a data writing transistor Tw having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the gate of the driving transistor Td; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line among a plurality of first reset control signal lines rst1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a first capacitor electrode Ce1 connected to the storage capacitor Cst, the data writing transistor a second electrode of a first transistor Tr2 connected to a second reset control signal line of a plurality of second reset control signal lines rst2, a first electrode connected to a corresponding second reset signal line among a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the driving transistor, the second capacitor electrode Ce2 of the storage capacitor Cst and the anode of the corresponding light-emitting element LE; and a light-emitting control transistor Te having a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td.

[0052] The pixel drive circuit further includes a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the gate electrode of the drive transistor Td, the first capacitor electrode Ce1, the second electrode of the data write transistor Tw, and the second electrode of the first reset transistor Tr1. The second node N2 is connected to the second electrode of the drive transistor Td, the second electrode of the second reset transistor Tr2, the second capacitor electrode Ce2 of the storage capacitor Cst, and the anode of the corresponding light-emitting element LE. The third node N3 is connected to the second electrode of the light-emission control transistor Te and the first electrode of the drive transistor Td.

[0053] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0054] Figure 2B 1 is a timing diagram illustrating the operation of the pixel driving circuit in some embodiments of the present disclosure. Figure 2A and Figure 2B During one frame of image, the operation of the pixel driving circuit includes a reset sub-phase t1, a compensation sub-phase t2, a data writing sub-phase t3 and a light emitting sub-phase t4.

[0055] During reset sub-phase t1, an on-reset control signal is supplied to the gate of the first reset transistor Tr1 via a corresponding first reset control signal line among the plurality of first reset control signal lines rst1, thereby turning on the first reset transistor Tr1. This causes the initialization voltage signal from a corresponding first reset signal line among the plurality of first reset signal lines Vint1 to propagate from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1, and further to the first capacitor electrode Ce1, the gate of the drive transistor Td, and the node N1. The gate of the drive transistor Td is initialized. An on-reset control signal is supplied to the gate of the second reset transistor Tr2 via a corresponding second reset control signal line among the plurality of second reset control signal lines rst2, thereby turning on the second reset transistor Tr2. This causes the initialization voltage signal from a corresponding second reset signal line among the plurality of second reset signal lines Vint2 to propagate from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and further to the node N2. This initializes the anode of the light-emitting element LE.

[0056] In the compensation sub-phase t2, the light-emitting control signal is provided to the gate of the light-emitting control transistor Te through the corresponding light-emitting control signal line among the plurality of light-emitting control signal lines em, so as to turn on the light-emitting control transistor Te. Figure 2A N2 node indicated in FIG) is charged until the voltage level at the second electrode of the driving transistor Td reaches a voltage level obtained by subtracting the threshold voltage Vth of the driving transistor Td from the level of the reset signal provided by the corresponding first reset signal line among the plurality of first reset signal lines Vint1.

[0057] In the data writing sub-phase t3, the gate scan signal is provided to the gate of the data writing transistor Tw through the corresponding gate line among the multiple gate lines GL to turn on the data writing transistor Tw; so that the data signal is transmitted from the first electrode of the data writing transistor Tw to the second electrode of the data writing transistor Tw, and then to the node N1. The voltage level of the gate of the driving transistor Td reaches the voltage level of the data signal written to the gate of the driving transistor Td. The capacitance value of the storage capacitor Cst is much smaller than the capacitance value of the parasitic capacitance between the cathode of the light-emitting element and the second capacitor electrode Ce2. The change in the voltage level at the gate of the driving transistor Td does not affect the voltage level at the second electrode of the driving transistor Td (for example, the N2 node). The voltage level of the second electrode of the driving transistor Td is maintained at the voltage level of the reset signal provided by the corresponding first reset signal line among the multiple first reset signal lines Vint1 minus the threshold voltage Vth of the driving transistor Td.

[0058] During the light-emission sub-phase t4, a light-emission control signal is provided to the gate of the light-emission control transistor Te via a corresponding light-emission control signal line from among the plurality of light-emission control signal lines em, thereby turning on the light-emission control transistor Te. During the light-emission sub-phase t4, the driving transistor Td remains on. The light-emitting element emits light. The voltage level at the N2 node becomes (Voled + Vss), where Voled represents the voltage level driving the light-emitting element to emit light, and Vss represents the voltage level at the cathode of the light-emitting element. Therefore, the change in the voltage level at the N2 node is (Voled + Vss - (Vint1 - Vth)), where Vint1 represents the level of the reset signal provided by the corresponding first reset signal line from among the plurality of first reset signal lines Vint1, and Vth represents the voltage level of the threshold voltage Vth of the driving transistor Td. Due to the bootstrap effect of the storage capacitor Cst, the voltage level at the N1 node (the gate of the driving transistor Td) becomes (Vdata + Vn2), where Vdata represents the voltage level of the data signal, and Vn2 represents the change in the voltage level at the N2 node. The voltage level at the N1 node is Vdata+Voled+Vss-Vint1+Vth. The voltage difference Vgs between the gate and the second electrode of the driving transistor Td is (Vdata-Vint1+Vth). The driving current I flowing through the driving transistor is (Vdata-Vint1) 2 Related.

[0059] The present disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. For p-type transistors, the valid control signal (e.g., the on control signal) is a low voltage signal, while the invalid control signal (e.g., the off control signal) is a high voltage signal. For n-type transistors, the valid control signal (e.g., the on control signal) is a high voltage signal, while the invalid control signal (e.g., the off control signal) is a low voltage signal. Figure 2A In some embodiments, all transistors in the pixel driving circuit are n-type transistors, such as metal oxide transistors.

[0060] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in an S1-S2-S3 format, where S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents the corresponding first sub-pixel of a first color, C2 represents the corresponding second sub-pixel of a second color, and C3 represents the corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0061] In another example, the array of multiple subpixels includes a repeating array of an S1-S2-S3-S4 format, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0062] In some embodiments, a minimum repeating unit of a plurality of sub-pixels of an array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a data writing transistor Tw, a first reset transistor Tr1, a second reset transistor Tr2, a light emitting control transistor Te, a driving transistor Td, and a storage capacitor Cst.

[0063] In an alternative embodiment, a minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a data writing transistor Tw, a first reset transistor Tr1, a second reset transistor Tr2, a light emitting control transistor Te, a driving transistor Td, and a storage capacitor Cst.

[0064] Figure 3A is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 3B It shows Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in FIG. Figure 3A and Figure 3B A portion of the array substrate having three pixel driving circuits (including PDC1 , PDC2 , and PDC3 ) is depicted.

[0065] Figure 3C It shows Figure 3A Schematic diagram of the structure of the light shielding layer in a portion of the array substrate depicted in FIG.

[0066] Figure 3D It shows Figure 3A Schematic diagram of the structure of the first conductive layer in a portion of an array substrate depicted in FIG.

[0067] Figure 3E It shows Figure 3A Schematic diagram of the structure of the first gate insulating layer in a portion of an array substrate depicted in FIG. Figure 3F It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer in a portion of the array substrate depicted in FIG. Figure 3G It shows Figure 3A Schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in FIG. Figure 3H It shows Figure 3A Schematic diagram of the structure of the passivation layer in a portion of the array substrate depicted in FIG. Figure 3I It shows Figure 3A Schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in FIG. Figure 3J It shows Figure 3A Schematic diagram of the structure of the first planarization layer in a portion of an array substrate depicted in FIG. Figure 3K It shows Figure 3A Schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in FIG. Figure 3L It shows Figure 3A Schematic diagram of the structure of the second planarization layer in a portion of the array substrate depicted in FIG. Figure 4A It is along Figure 3A Cross-sectional view along line AA'. Figure 4B It is along Figure 3A Cross-sectional view along line BB'.

[0068] Reference Figures 3A to 3L and Figures 4A to 4B In some embodiments, the array substrate includes: a base substrate BS; a light shielding layer LSL, which is located on the base substrate BS; an insulating layer IN, which is located on a side of the light shielding layer LSL away from the base substrate BS; a first conductive layer CT1, which is located on a side of the insulating layer IN away from the light shielding layer LSL; a first gate insulating layer GI1, which is located on a side of the first conductive layer CT1 away from the insulating layer IN; a semiconductor material layer SML, which is located on a side of the first gate insulating layer GI1 away from the first conductive layer CT1; a second gate insulating layer GI2, which is located on a side of the semiconductor material layer SML away from the first gate insulating layer GI1; the second conductive layer CT 2, which is located on a side of the second gate insulating layer GI2 away from the semiconductor material layer SML; the passivation layer PVX, which is located on a side of the second conductive layer CT2 away from the second gate insulating layer GI2; the first signal line layer SD1, which is located on a side of the passivation layer PVX away from the second conductive layer CT2; the first planarization layer PLN1, which is located on a side of the first signal line layer SD1 away from the passivation layer PVX; the second signal line layer SD2, which is located on a side of the first planarization layer PLN1 away from the first signal line layer SD1; and the second planarization layer PLN2, which is located on a side of the second signal line layer SD2 away from the first planarization layer PLN1.

[0069] Reference Figure 2A 、 Figure 3A and Figure 3C In some embodiments, the light shielding layer LSL includes a light shielding member LS. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light shielding layer LSL. For example, a metal material can be deposited on a substrate using a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable metal materials for manufacturing the light shielding layer LSL include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or stacks thereof.

[0070] In some embodiments, the array substrate includes a plurality of light shielding members respectively located in the plurality of pixel driving circuits, and the plurality of light shielding members are spaced apart from each other.

[0071] In some embodiments, reference Figure 2A 、 Figure 3A 、 Figure 3C and Figure 4AThe orthographic projection of the light shielding member LS on the base substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the active layer ACTd of the driving transistor Td on the base substrate BS. The inventors of the present disclosure have discovered that by having such a structure, the active layer ACTd of the driving transistor Td can be protected from radiation and stabilized.

[0072] In some embodiments, the light shielding member LS is electrically connected to the gate of the driving transistor Td (e.g., the first capacitor electrode Ce1 of the storage capacitor Cst, which serves as the light shielding member LS). Alternatively, the light shielding member LS is electrically connected to the gate of the driving transistor Td via a node connection line Cln located in the first signal line layer SD1. The inventors of the present disclosure have surprisingly and unexpectedly discovered that by electrically connecting the light shielding member LS to the gate of the driving transistor Td, the low grayscale driving capability of the driving transistor Td can be significantly improved, thereby improving the performance of the driving transistor Td.

[0073] In some embodiments, the light blocking member LS is electrically connected to the second electrode Dr1 of the first reset transistor Tr1. Alternatively, the light blocking member LS is electrically connected to the second electrode Dr1 of the first reset transistor Tr1 through a node connection line Cln in the first signal line layer SD1.

[0074] In some embodiments, the orthographic projection of the light-shielding member LS on the substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the gate of the driving transistor Td on the substrate BS.

[0075] In some embodiments, the orthographic projection of the light-shielding member LS on the substrate substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the second capacitor electrode Ce2 of the storage capacitor Cst on the substrate substrate BS.

[0076] Reference Figure 2A 、 Figure 3A and Figure 3DIn some embodiments, the first conductive layer includes a second capacitor electrode Ce2 of the storage capacitor Cst, a first gate portion Gw-1 of the gate of the data write transistor Tw, a first gate portion Gr1-1 of the gate of the first reset transistor Tr1, a first gate portion Gr2-1 of the gate of the second reset transistor Tr2, and a first gate portion Ge-1 of the gate of the light emission control transistor Te. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the second capacitor electrode Ce2 of the storage capacitor Cst, the first gate portion Gw-1 of the gate of the data write transistor Tw, the first gate portion Gr1-1 of the gate of the first reset transistor Tr1, the first gate portion Gr2-1 of the gate of the second reset transistor Tr2, and the first gate portion Ge-1 of the gate of the light emission control transistor Te are located in the same layer.

[0077] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the second capacitor electrode Ce2 and the first gate portion Gw-1 are formed as a result of one or more steps of the same patterning process performed in the same material layer, they are located in the same layer. In another example, the second capacitor electrode Ce2 and the first gate portion Gw-1 can be formed in the same layer by performing the steps of forming the second capacitor electrode Ce2 and forming the first gate portion Gw-1 simultaneously. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0078] Reference Figure 2A 、 Figure 3A 、 Figure 3D and Figure 3I In some embodiments, the gate of the data write transistor Tw includes one or more portions. In some embodiments, a first gate portion Gw-1 of the gate of the data write transistor Tw is connected to a corresponding gate line among the plurality of gate lines GL.

[0079] Reference Figure 2A 、 Figure 3A 、 Figure 3D and Figure 3I In some embodiments, the gate of the first reset transistor Tr1 includes one or more portions. In some embodiments, a first gate portion Gr1-1 of the gate of the first reset transistor Tr1 is connected to a corresponding first reset control signal line among a plurality of first reset control signal lines rst1.

[0080] Reference Figure 2A 、 Figure 3A 、 Figure 3D and Figure 3I In some embodiments, the gate of the second reset transistor Tr2 includes one or more portions. In some embodiments, a first gate portion Gr2-1 of the gate of the second reset transistor Tr2 is connected to a corresponding second reset control signal line among a plurality of second reset control signal lines rst2.

[0081] Reference Figure 2A 、 Figure 3A 、 Figure 3D and Figure 3I In some embodiments, the gate of the light emission control transistor Te includes one or more portions. In some embodiments, a first gate portion Ge-1 of the gate of the light emission control transistor Te is connected to a corresponding light emission control signal line among a plurality of light emission control signal lines em.

[0082] Figure 3E A via extending through the first gate insulating layer GI1 is depicted in FIG.

[0083] Reference Figure 2A 、 Figure 3A and Figure 3FIn some embodiments, the semiconductor material layer SML includes at least the active layer ACTd of the drive transistor Td, the active layer ACTr1 of the first reset transistor Tr1, the active layer ACTr2 of the second reset transistor Tr2, the active layer ACTw of the data write transistor Tw, and the active layer ACTe of the emission control transistor Te. Optionally, the semiconductor material layer SML also includes at least a portion of the first electrode Sd of the drive transistor Td, at least a portion of the first electrode Sr1 of the first reset transistor Tr1, at least a portion of the first electrode Sr2 of the second reset transistor Tr2, at least a portion of the first electrode Sw of the data write transistor Tw, and at least a portion of the first electrode Se of the emission control transistor Te. Optionally, the semiconductor material layer SML also includes at least a portion of the second electrode Dd of the drive transistor Td, at least a portion of the second electrode Dr1 of the first reset transistor Tr1, at least a portion of the second electrode Dr2 of the second reset transistor Tr2, at least a portion of the second electrode Dw of the data write transistor Tw, and at least a portion of the second electrode De of the emission control transistor Te. Optionally, the semiconductor material layer SML includes: an active layer ACTd, a first electrode Sd, and a second electrode Dd of the drive transistor Td; an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1 of the first reset transistor Tr1; an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2 of the second reset transistor Tr2; an active layer ACTw, a first electrode Sw, and a second electrode Dw of the data write transistor Tw; and an active layer ACTe, a first electrode Se, and a second electrode De of the emission control transistor Te. Various suitable semiconductor materials can be used to manufacture the semiconductor material layer SML. Examples of semiconductor materials used to manufacture the semiconductor material layer SML include metal oxide-based semiconductor materials such as indium gallium zinc oxide and metal oxynitride-based semiconductor materials such as zinc oxynitride.

[0084] As used herein, an active layer refers to a component of a transistor that includes at least a portion of a semiconductor material layer, the orthographic projection of which portion on a substrate overlaps with the orthographic projection of a gate on the substrate. A first electrode refers to a component of a transistor that is connected to one side of the active layer, and a second electrode refers to a component of a transistor that is connected to the other side of the active layer. In the context of a dual-gate transistor, an active layer refers to a component of a transistor that includes a first portion of a semiconductor material layer, a second portion of the semiconductor material layer, and a third portion located between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate overlaps with the orthographic projection of the second gate on the substrate. In the context of a dual-gate transistor, a first electrode refers to a component of the transistor that is connected to a side of the first portion away from the third portion, and a second electrode refers to a component of the transistor that is connected to a side of the second portion away from the third portion.

[0085] Figure 3F Reference numerals are provided to indicate transistor components within the pixel drive circuit. For example, the drive transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd; the data write transistor Tw includes an active layer ACTw, a first electrode Sw, and a second electrode Dw; the emission control transistor Tw includes an active layer ACTe, a first electrode Se, and a second electrode De; the first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1; and the second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. Optionally, the active layer ACTd of the drive transistor Td, the active layer ACTe of the emission control transistor Te, and the active layer ACTr2 of the second reset transistor Tr2 are part of the first integral structure. Optionally, the active layer ACTd, first electrode Sd, and second electrode Dd of the drive transistor Td; the active layer ACTe, first electrode Se, and second electrode De of the emission control transistor Te; and the active layer ACTr2, first electrode Sr2, and second electrode Dr2 of the second reset transistor Tr2 are part of the first integral structure. Optionally, the active layer ACTw of the data write transistor Tw and the active layer ACTr1 of the first reset transistor Tr1 are part of the second integral structure. Optionally, the active layer ACTw, the first electrode Sw and the second electrode Dw of the data write transistor Tw and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are part of the second integral structure.

[0086] Reference Figure 2A 、 Figure 3A and Figure 3GIn some embodiments, the second conductive layer includes a first capacitor electrode Ce1 of the storage capacitor Cst, a second gate portion Gw-2 of the gate of the data write transistor Tw, a second gate portion Gr1-2 of the gate of the first reset transistor Tr1, a second gate portion Gr2-2 of the gate of the second reset transistor Tr2, and a second gate portion Ge-2 of the gate of the light emission control transistor Te. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first capacitor electrode Ce1 of the storage capacitor Cst, the second gate portion Gw-2 of the gate of the data write transistor Tw, the second gate portion Gr1-2 of the gate of the first reset transistor Tr1, the second gate portion Gr2-2 of the gate of the second reset transistor Tr2, and the second gate portion Ge-2 of the gate of the light emission control transistor Te are located in the same layer.

[0087] Reference Figure 2A 、 Figure 3A 、 Figure 3G and Figure 3I In some embodiments, the gate of the data write transistor Tw includes one or more portions. In some embodiments, the second gate portion Gw-2 of the gate of the data write transistor Tw is connected to a corresponding gate line among the plurality of gate lines GL.

[0088] Reference Figure 2A 、 Figure 3A 、 Figure 3G and Figure 3I In some embodiments, the gate of the first reset transistor Tr1 includes one or more portions. In some embodiments, the second gate portion Gr1-2 of the gate of the first reset transistor Tr1 is connected to a corresponding first reset control signal line among the plurality of first reset control signal lines rst1.

[0089] Reference Figure 2A 、 Figure 3A 、 Figure 3G and Figure 3I In some embodiments, the gate of the second reset transistor Tr2 includes one or more portions. In some embodiments, the second gate portion Gr2-2 of the gate of the second reset transistor Tr2 is connected to a corresponding second reset control signal line among a plurality of second reset control signal lines rst2.

[0090] Reference Figure 2A 、 Figure 3A 、 Figure 3G and Figure 3I In some embodiments, the gate of the light emission control transistor Te includes one or more portions. In some embodiments, the second gate portion Ge-2 of the gate of the light emission control transistor Te is connected to a corresponding light emission control signal line among the plurality of light emission control signal lines em.

[0091] Figure 3H A via extending through the passivation layer PVX is depicted in FIG.

[0092] Reference Figure 2A 、 Figure 3A and Figure 3I In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of first voltage supply lines Vdd1, a plurality of second voltage supply lines Vss1, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, a plurality of emission control signal lines em, a relay electrode RE, and a data signal connection pad DCP.

[0093] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. In some embodiments, the first signal line layer includes multiple stacked sublayers. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, multiple first voltage supply lines Vdd1, multiple second voltage supply lines Vss1, multiple first reset signal lines Vint1, multiple second reset signal lines Vint2, multiple first reset control signal lines rst1, multiple second reset control signal lines rst2, multiple gate lines GL, multiple emission control signal lines em, relay electrodes RE, and anode connection pads ACP are located in the same layer.

[0094] In some embodiments, a plurality of first voltage supply lines Vdd1, a plurality of second voltage supply lines Vss1, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, and a plurality of emission control signal lines em extend in directions substantially parallel to a first direction DR1. As used herein, the term "substantially parallel" refers to an angle within a range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, or 0 degrees to about 30 degrees.

[0095] In some embodiments, a plurality of first voltage supply lines Vdd1 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and a plurality of second voltage supply lines Vss1 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, and the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0096] The node connection line Cln connects the gate of the driving transistor Td in each pixel driving circuit to the second electrode of the first reset transistor Tr1 in the corresponding pixel driving circuit and the light shielding member. Figure 4A In some embodiments, the node connection line Cln is connected to the second electrode Dr1 of the first reset transistor Tr1 through the first via hole v1, connected to the light shielding member LS through the second via hole v2, and connected to the gate of the driving transistor Td through the third via hole v3. Optionally, the first node connection line Cln1 corresponds to Figure 2A Node N1 is depicted in FIG.

[0097] In one example, the first via v1 extends through the passivation layer PVX and the second gate insulating layer GI2 ; the second via v2 extends through the passivation layer PVX, the second gate insulating layer GI2 , the first gate insulating layer GI1 , and the insulating layer IN; and the third via v3 extends through the passivation layer PVX.

[0098] The data signal connection pad DCP connects a corresponding data line among the plurality of data lines DL to the first electrode of the data write transistor Tw.

[0099] The relay electrode RE connects the anode connection pad to the second capacitor electrode Ce2 and / or the second electrode Dd of the driving transistor Td in the corresponding pixel driving circuit. The anode connection pad is connected to the anode of the corresponding light emitting element. Figure 4BIn some embodiments, the relay electrode RE is connected to the second capacitor electrode Ce2 through the fourth via hole v4 and to the second electrode Dd of the driving transistor Td through the fifth via hole v5. The anode connection pad ACP is connected to the relay electrode RE through the sixth via hole v6. Optionally, the relay electrode RE corresponds to Figure 2A Node N2 is depicted in FIG.

[0100] In an example, the fourth via hole v4 extends through the passivation layer PVX, the second gate insulating layer GI2, and the first gate insulating layer GI1; the fifth via hole v5 extends through the passivation layer PVX and the second gate insulating layer GI2; and the sixth via hole v6 extends through the first planarization layer PLN1.

[0101] In some embodiments, corresponding first voltage supply lines among the plurality of first voltage supply lines Vdd1 are connected to first electrodes of a plurality of light emission control transistors (eg, a plurality of light emission control transistors in the same row).

[0102] In some embodiments, the plurality of second voltage supply lines Vss1 are electrically connected to cathodes of the plurality of light emitting elements.

[0103] In some embodiments, corresponding first reset signal lines among the plurality of first reset signal lines Vint1 are connected to first electrodes of a plurality of first reset transistors (eg, a plurality of first reset transistors in the same row).

[0104] In some embodiments, corresponding second reset signal lines among the plurality of second reset signal lines Vint2 are connected to first electrodes of a plurality of second reset transistors (eg, a plurality of second reset transistors in the same row).

[0105] In some embodiments, a corresponding gate line among the plurality of gate lines GL includes a third gate portion Gw-3 of the gate of the data write transistor Tw. Optionally, an orthographic projection of the third gate portion Gw-3 of the gate of the data write transistor Tw on the substrate at least partially overlaps with an orthographic projection of the second gate portion Gw-2 of the gate of the data write transistor Tw on the substrate; and at least partially overlaps with an orthographic projection of the first gate portion Gw-1 of the gate of the data write transistor Tw on the substrate. Optionally, an orthographic projection of the second gate portion Gw-2 of the gate of the data write transistor Tw on the substrate at least partially overlaps with an orthographic projection of the first gate portion Gw-1 of the gate of the data write transistor Tw on the substrate.

[0106] In some embodiments, a corresponding second reset control signal line among the plurality of second reset control signal lines rst2 includes a third gate portion Gr2-3 of the gate of the second reset transistor Tr2. Optionally, an orthographic projection of the third gate portion Gr2-3 of the gate of the second reset transistor Tr2 on the substrate at least partially overlaps with an orthographic projection of the second gate portion Gr2-2 of the gate of the second reset transistor Tr2 on the substrate; and at least partially overlaps with an orthographic projection of the first gate portion Gr2-1 of the gate of the second reset transistor Tr2 on the substrate. Optionally, an orthographic projection of the second gate portion Gr2-2 of the gate of the second reset transistor Tr2 on the substrate at least partially overlaps with an orthographic projection of the first gate portion Gr2-1 of the gate of the second reset transistor Tr2 on the substrate.

[0107] Figure 3J Vias extending through the first planarization layer PLN1 are depicted.

[0108] Reference Figure 2A 、 Figure 3A and Figure 3K In some embodiments, the second signal line layer includes a plurality of third voltage supply lines Vdd2, a plurality of fourth voltage supply lines Vss2, a plurality of data lines DL, a plurality of third reset signal lines Vint3, a plurality of fourth reset signal lines Vint4, and an anode connection pad ACP. Each of the plurality of data lines DL is electrically connected to the first electrode of the data write transistor Tw via a data signal connection pad. The anode connection pad ACP is connected to the second capacitor electrode and / or the second electrode of the drive transistor in the corresponding pixel drive circuit via a relay electrode, and is also connected to the anode of the corresponding light-emitting element.

[0109] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned using a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes multiple sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple third voltage supply lines Vdd2, multiple fourth voltage supply lines Vss2, multiple data lines DL, multiple third reset signal lines Vint3, multiple fourth reset signal lines Vint4, and the anode connection pad ACP are located in the same layer.

[0110] In some embodiments, the plurality of third voltage supply lines Vdd2 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of fourth voltage supply lines Vss2 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, and the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0111] Reference Figure 3I and Figure 3K In some embodiments, multiple third voltage supply lines Vdd2 located in the second signal line layer are connected to multiple first voltage supply lines Vdd1 located in the first signal line layer. Each of the multiple first voltage supply lines Vdd1 is connected to the first electrodes of multiple emission control transistors (e.g., multiple emission control transistors in the same row). Optionally, the multiple third voltage supply lines Vdd2 extend in a direction substantially parallel to the second direction DR2; and the multiple first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1.

[0112] In some embodiments, the plurality of fourth voltage supply lines Vss2 located in the second signal line layer are connected to the plurality of second voltage supply lines Vss1 located in the first signal line layer. Optionally, the plurality of fourth voltage supply lines Vss2 extend in a direction substantially parallel to the second direction DR2; and the plurality of second voltage supply lines Vss1 extend in a direction substantially parallel to the first direction DR1.

[0113] In some embodiments, a plurality of third reset signal lines Vint3 located in the second signal line layer are connected to a plurality of first reset signal lines Vint1 located in the first signal line layer. Optionally, each of the plurality of first reset signal lines Vint1 is connected to a first electrode of a plurality of first reset transistors (e.g., a plurality of first reset transistors in the same row). Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to the second direction DR2; and the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1.

[0114] In some embodiments, a plurality of fourth reset signal lines Vint4 located in the second signal line layer are connected to a plurality of second reset signal lines Vint2 located in the first signal line layer. Optionally, each of the plurality of second reset signal lines Vint2 is connected to a first electrode of a plurality of second reset transistors (e.g., a plurality of second reset transistors in the same row). Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2; and the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1.

[0115] In some embodiments, the first column pixel driving circuit, the second column pixel driving circuit and the third column pixel driving circuit are three adjacent columns of pixel driving circuits. Optionally, the first column pixel driving circuit, the second column pixel driving circuit and the third column pixel driving circuit are sequentially arranged along the first direction DR1.

[0116] In some embodiments, corresponding data lines among the plurality of data lines DL located in the second signal line layer are connected to data signal connection pads DCP located in the first signal line layer, and the data signal connection pads DCP are connected to the first electrode of the data write transistor Tw. Optionally, the plurality of data lines DL extend in a direction substantially parallel to the second direction DR2.

[0117] Figure 3L A via extending through the second planarization layer PLN2 is depicted in FIG. The anode of the light emitting element is connected to the anode connection pad located in the second signal line layer through the via extending through the second planarization layer PLN2.

[0118] Figure 5 Schematic diagram showing the structure of a first voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 5 In some embodiments, the first voltage supply network includes a plurality of interconnected first voltage supply lines Vdd1 and a plurality of third voltage supply lines Vdd2. Optionally, the plurality of first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of third voltage supply lines Vdd2 extend in a direction substantially parallel to the second direction DR2. Optionally, each of the plurality of first voltage supply lines Vdd1 is connected to one or more of the plurality of third voltage supply lines Vdd2. Optionally, each of the plurality of third voltage supply lines Vdd2 is connected to one or more of the plurality of first voltage supply lines Vdd1.

[0119] In one example, the plurality of first voltage supply lines Vdd1 are located in the first signal line layer. Optionally, the plurality of third voltage supply lines Vdd2 are located in the second signal line layer.

[0120] Figure 6 Schematic diagram showing the structure of a second voltage supply network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6 In some embodiments, the second voltage supply network includes a plurality of interconnected second voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2. Optionally, the plurality of second voltage supply lines Vss1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth voltage supply lines Vss2 extend in a direction substantially parallel to the second direction DR2. Optionally, each of the plurality of second voltage supply lines Vss1 is connected to one or more of the plurality of fourth voltage supply lines Vss2. Optionally, each of the plurality of fourth voltage supply lines Vss2 is connected to one or more of the plurality of second voltage supply lines Vss1.

[0121] In one example, the plurality of second voltage supply lines Vss1 are located in the first signal line layer. Optionally, the plurality of fourth voltage supply lines Vss2 are located in the second signal line layer.

[0122] Figure 7 Schematic diagram showing the structure of a first reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7 In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to the second direction DR2. Optionally, each first reset signal line in the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each third reset signal line in the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1.

[0123] In one example, the plurality of first reset signal lines Vint1 are located in the first signal line layer. Optionally, the plurality of third reset signal lines Vint3 are located in the second signal line layer.

[0124] Figure 8 Schematic diagram showing the structure of a second reset signal network in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, each of the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0125] In one example, the plurality of second reset signal lines Vint2 are located in the first signal line layer. Optionally, the plurality of fourth reset signal lines Vint4 are located in the second signal line layer.

[0126] Reference Figures 3A to 3L In some embodiments, the pixel driving circuits of the array substrate are arranged into multiple columns, including the (3k-2)th column C(3k-2), the (3k-1)th column C(3k-1), and the (3k)th column C(3k) in the K columns, where K and k are positive integers, 1≤k≤(K / 3).

[0127] As used herein, the terms "column (3k-2)", "column (3k-1)", and "column (3k)" are used in the context of column K. The array substrate may or may not include additional columns before the first column in column K and / or additional columns after the last column in column K. In the context of the array substrate, the term "column (3k-1)" does not necessarily mean an odd column, and the term "column (3k-2)" or "column (3k)" does not necessarily mean an even column. In one example, column (3k-2) is an even column in the context of column K, but may be an odd column in the context of the array substrate. In another example, column (3k-2) is an even column in the context of column K and is also an even column in the context of the array substrate. In one example, column (3k-1) is an odd column in the context of column K, but may be an even column in the context of the array substrate. In another example, the (3k-1)th column is an odd column in the context of column K and is also an odd column in the context of the array substrate. In one example, the (3k)th column is an even column in the context of column K, but may be an odd column in the context of the array substrate. In another example, the (3k)th column is an even column in the context of column K and is also an even column in the context of the array substrate.

[0128] In some embodiments, the (3k-2)th column C(3k-2) includes the (3k-2)th pixel driving circuit, the (3k-1)th column C(3k-1) includes the (3k-1)th pixel driving circuit, and the (3k)th column C(3k) includes the (3k)th pixel driving circuit. The (3k-2)th pixel driving circuit, the (3k-1)th pixel driving circuit, and the (3k)th pixel driving circuit are located in the same row.

[0129] In some embodiments, the (3k-2)th column C(3k-2) includes a fourth voltage supply line among a plurality of fourth voltage supply lines Vss2; the (3k-1)th column C(3k-1) includes a fourth reset signal line among a plurality of fourth reset signal lines Vint4; and the (3k)th column C(3k) includes a third reset signal line among a plurality of third reset signal lines Vint3.

[0130] Alternatively, the plurality of fourth voltage supply lines Vss2 do not exist in the (3k-1)th column C(3k-1) and do not exist in the (3k)th column C(3k).

[0131] Alternatively, the plurality of fourth reset signal lines Vint4 do not exist in the (3k-2)th column C(3k-2) and do not exist in the (3k)th column C(3k).

[0132] Alternatively, the plurality of third reset signal lines Vint3 do not exist in the (3k-2)th column C(3k-2) and do not exist in the (3k-1)th column C(3k-1).

[0133] In some embodiments, the pixel driving circuit of the (3k-2)th column C(3k-2) is configured to drive the sub-pixel of the first color of the (3k-2)th column C(3k-2) to emit light, the pixel driving circuit of the (3k)th column C(3k) is configured to drive the sub-pixel of the second color of the (3k)th column C(3k) to emit light, and the pixel driving circuit of the (3k-1)th column C(3k-1) is configured to drive the sub-pixel of the third color of the (3k-1)th column C(3k-1) to emit light. Optionally, the first color, the second color, and the third color are three different colors selected from red, green, and blue.

[0134] Figure 9 It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer and the second signal line layer in a portion of the array substrate depicted in FIG. Figures 3A to 3K and Figure 9The orthographic projection of each of the plurality of third voltage supply lines Vdd2 on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the active layer ACTe of the corresponding pixel driving circuit on the substrate, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the active layer ACTr2 of the second reset transistor Tr2 on the substrate, and at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td on the substrate. The inventors of the present disclosure have discovered that by having such a structure, the active layers ACTe of the emission control transistor Te, ACTr2 of the second reset transistor Tr2, and ACTd of the driving transistor Td can be protected from radiation and stabilized.

[0135] In some embodiments, the orthographic projection of each of the multiple third voltage supply lines Vdd2 on the substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the combination of the active layer ACTe, the first electrode Se, and the second electrode De of the light-emitting control transistor Te in the corresponding pixel driving circuit on the substrate substrate; substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the combination of the active layer ACTr2, the first electrode Sr2, and the second electrode Dr2 of the second reset transistor Tr2 on the substrate substrate; substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the combination of the first electrode Sd and the second electrode Dd of the driving transistor Td on the substrate substrate; and at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td on the substrate substrate.

[0136] In some embodiments, the active layer ACTd, first electrode Sd, and second electrode Dd of the drive transistor Td; the active layer ACTe, first electrode Se, and second electrode De of the emission control transistor Te; and the active layer ACTr2, first electrode Sr2, and second electrode Dr2 of the second reset transistor Tr2 are part of a first integral structure. Optionally, the first integral structure extends in a direction substantially parallel to an extending direction of each of the plurality of third voltage supply lines Vdd2.

[0137] In some embodiments, in a first column pixel driving circuit, an orthographic projection of a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines Vss2 on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection on the substrate of an active layer ACTr1 of a first reset transistor Tr1 in a first corresponding pixel driving circuit in the first column pixel driving circuit, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection on the substrate of an active layer ACTw of a data write transistor Tw in a first corresponding pixel driving circuit in the first column pixel driving circuit. The inventors of the present disclosure have discovered that by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0138] In some embodiments, in the first column pixel driving circuit, the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines Vss2 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 in the first corresponding pixel driving circuit in the first column of pixel driving circuits on the substrate substrate, and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTw and the second electrode Dw of the data write transistor Tw in the first corresponding pixel driving circuit in the first column of pixel driving circuits on the substrate substrate.

[0139] In some embodiments, in the first column pixel driving circuit, the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of a second integral structure in the first column pixel driving circuit. Optionally, an extension direction of the second integral structure in the first column pixel driving circuit is substantially parallel to an extension direction of a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines Vss2.

[0140] In some embodiments, in the second column pixel driving circuit, an orthographic projection of a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection on the substrate of the active layer ACTr1 of the first reset transistor Tr1 in the second corresponding pixel driving circuit in the second column pixel driving circuit, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection on the substrate of the active layer ACTw of the data write transistor Tw in the second corresponding pixel driving circuit in the second column pixel driving circuit. The inventors of the present disclosure have discovered that by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0141] In some embodiments, in the second column pixel driving circuit, the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines Vint4 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate substrate; and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the second electrode Dw and the active layer ACTw of the data write transistor Tw in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate substrate.

[0142] In some embodiments, in the second column pixel driving circuit, the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of a second integral structure in the second column pixel driving circuit. Optionally, the second integral structure in the second column pixel driving circuit extends in a direction substantially parallel to an extending direction of a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4.

[0143] In some embodiments, in a third column pixel driver circuit, an orthographic projection of a corresponding third reset signal line among the plurality of third reset signal lines Vint3 on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection of an active layer ACTr1 of a first reset transistor Tr1 in a third corresponding pixel driver circuit in the third column pixel driver circuit, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) an orthographic projection of an active layer ACTw of a data write transistor Tw in a third corresponding pixel driver circuit in the third column pixel driver circuit. The inventors of the present disclosure have discovered that by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0144] In some embodiments, in the third column pixel driving circuit, the orthographic projection of the corresponding third reset signal line among the multiple third reset signal lines Vint3 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the orthographic projection of the combination of the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate substrate; and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the orthographic projection of the combination of the active layer ACTw and the second electrode Dw of the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate substrate.

[0145] In some embodiments, in the third column pixel driving circuit, the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of a second integral structure in the third column pixel driving circuit. Optionally, the second integral structure in the third column pixel driving circuit extends in a direction substantially parallel to an extending direction of a corresponding third reset signal line among the plurality of third reset signal lines Vint3.

[0146] In some embodiments, in the pixel driving circuit of the (3k-2)th column C(3k-2), the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines Vss2 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the active layer ACTr1 of the first reset transistor Tr1 in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column C(3k-2) on the substrate substrate, and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the active layer ACTw of the data write transistor Tw in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column C(3k-2) on the substrate substrate. The inventors of the present disclosure have found that, by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0147] In some embodiments, in the pixel driving circuit of the (3k-2)th column C(3k-2), the orthographic projection of a corresponding fourth voltage supply line among the multiple fourth voltage supply lines Vss2 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the combination of the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column C(3k-2) on the substrate substrate, and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the combination of the active layer ACTw and the second electrode Dw of the data write transistor Tw in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column C(3k-2) on the substrate substrate.

[0148] In some embodiments, in the pixel driving circuit of the (3k-2)th column C(3k-2), the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of the second integral structure in the pixel driving circuit of the (3k-2)th column C(3k-2). Optionally, the extension direction of the second integral structure in the pixel driving circuit of the (3k-2)th column C(3k-2) is substantially parallel to the extension direction of a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines Vss2.

[0149] In some embodiments, in the pixel driving circuit of the (3k-1)th column C(3k-1), the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines Vint4 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the active layer ACTr1 of the first reset transistor Tr1 in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column C(3k-1) on the substrate substrate, and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the active layer ACTw of the data write transistor Tw in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column C(3k-1) on the substrate substrate. The inventors of the present disclosure have found that, by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0150] In some embodiments, in the pixel driving circuit of the (3k-1)th column C(3k-1), the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines Vint4 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column C(3k-1) on the substrate substrate; and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTw and the second electrode Dw of the data write transistor Tw in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column C(3k-1) on the substrate substrate.

[0151] In some embodiments, in the (3k-1)th column C(3k-1) pixel driving circuit, the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of a second integral structure in the (3k-1)th column C(3k-1) pixel driving circuit. Optionally, an extension direction of the second integral structure in the (3k-1)th column C(3k-1) pixel driving circuit is substantially parallel to an extension direction of a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4.

[0152] In some embodiments, in the pixel driving circuit of the (3k)th column C(3k), the orthographic projection of the corresponding third reset signal line among the plurality of third reset signal lines Vint3 on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the active layer ACTr1 of the first reset transistor Tr1 in the third corresponding pixel driving circuit in the (3k)th column C(3k) on the substrate, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the active layer ACTw of the data write transistor Tw in the third corresponding pixel driving circuit in the (3k)th column C(3k) on the substrate. The inventors of the present disclosure have discovered that by having such a structure, the active layer ACTr1 of the first reset transistor Tr1 and the active layer ACTw of the data write transistor Tw can be protected from radiation and stabilized.

[0153] In some embodiments, in the pixel driving circuit of the (3k)th column C(3k), the positive projection of the corresponding third reset signal line among the multiple third reset signal lines Vint3 on the substrate substrate substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column C(3k) on the substrate substrate; and substantially covers (for example, at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage or complete coverage) the positive projection of the combination of the active layer ACTw and the second electrode Dw of the data write transistor Tw in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column C(3k) on the substrate substrate.

[0154] In some embodiments, in the pixel driving circuit of the (3k)th column C(3k), the active layer ACTw, the first electrode Sw, and the second electrode Dw of the data write transistor Tw, and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1 are part of a second integral structure in the pixel driving circuit of the (3k)th column C(3k). Optionally, an extension direction of the second integral structure in the pixel driving circuit of the (3k)th column C(3k) is substantially parallel to an extension direction of a corresponding third reset signal line among the plurality of third reset signal lines Vint3.

[0155] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, and the like. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a mini light-emitting diode display device.

[0156] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel drive circuits. Optionally, forming each of the plurality of pixel drive circuits includes forming a drive transistor, forming a light shielding member, and forming a node connection line. Optionally, the orthographic projection of the light shielding member on the substrate substantially covers the orthographic projection of the active layer of the drive transistor on the substrate. Optionally, the light shielding member is electrically connected to the gate of the drive transistor via the node connection line. Optionally, the light shielding member, the node connection line, and the gate of the drive transistor are formed in three different layers.

[0157] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to specific embodiments, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor, a light shielding member and a node connection line; Wherein, the orthographic projection of the light shielding member on the base substrate substantially covers the orthographic projection of the active layer of the driving transistor on the base substrate; The light shielding member is electrically connected to the gate of the driving transistor through the node connection line; The light shielding member, the node connection line, and the gate of the driving transistor are located in three different layers.

2. The array substrate according to claim 1, wherein: Each pixel driving circuit further includes a first reset transistor; The light shielding member is electrically connected to the second electrode of the first reset transistor through the node connection line.

3. The array substrate according to claim 1, wherein: Each pixel driving circuit further includes a storage capacitor; The orthographic projection of the light shielding member on the base substrate substantially covers the orthographic projection of the gate of the driving transistor on the base substrate, and substantially covers the orthographic projection of the second capacitor electrode of the storage capacitor on the base substrate.

4. The array substrate according to any one of claims 1 to 3, further comprising a plurality of third voltage supply lines; in, Each pixel driving circuit further includes a light emitting control transistor and a second reset transistor; The orthographic projection of each of the multiple third voltage supply lines on the substrate basically covers the orthographic projection of the active layer of the light emitting control transistor in the corresponding pixel driving circuit on the substrate, basically covers the orthographic projection of the active layer of the second reset transistor on the substrate, and at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate.

5. The array substrate according to claim 4, wherein: An orthographic projection of each of the plurality of third voltage supply lines on the substrate substantially covers an orthographic projection of a combination of an active layer, a first electrode, and a second electrode of the light emission control transistor in the corresponding pixel driving circuit on the substrate; substantially covering an orthographic projection of a combination of the active layer, the first electrode, and the second electrode of the second reset transistor on the substrate; substantially covering an orthographic projection of a combination of the first electrode and the second electrode of the drive transistor on the substrate; And at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate.

6. The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth voltage supply lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; In the first column pixel driving circuit, the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate, and basically covers the positive projection of the active layer of the data writing transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate.

7. The array substrate according to claim 6, wherein: In the first column pixel driving circuit, the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines on the substrate basically covers the positive projection of the active layer, the first electrode and the second electrode combination of the first reset transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate, and basically covers the positive projection of the active layer and the second electrode combination of the data writing transistor in the first corresponding pixel driving circuit in the first column pixel driving circuit on the substrate.

8. The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth reset signal lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; In the second column pixel driving circuit, the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate, and basically covers the positive projection of the active layer of the data writing transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate.

9. The array substrate according to claim 8, wherein: In the second column pixel driving circuit, the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines on the substrate basically covers the positive projection of the active layer, the first electrode and the second electrode of the first reset transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate; and basically covers the positive projection of the active layer and the second electrode of the data writing transistor in the second corresponding pixel driving circuit in the second column pixel driving circuit on the substrate.

10. The array substrate according to any one of claims 1 to 3, further comprising a plurality of third reset signal lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; In the third column pixel driving circuit, the positive projection of the corresponding third reset signal line among the multiple third reset signal lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate, and basically covers the positive projection of the active layer of the data writing transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate.

11. The array substrate according to claim 10, wherein: In the third column pixel driving circuit, the orthographic projection of the corresponding third reset signal line among the multiple third reset signal lines on the substrate basically covers the orthographic projection of the combination of the active layer, the first electrode and the second electrode of the first reset transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate; and basically covers the orthographic projection of the combination of the active layer and the second electrode of the data writing transistor in the third corresponding pixel driving circuit in the third column pixel driving circuit on the substrate.

12. The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth voltage supply lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); In the pixel driving circuit of the (3k-2)th column, the positive projection of the corresponding fourth voltage supply line among the multiple fourth voltage supply lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column on the substrate, and basically covers the positive projection of the active layer of the data write transistor in the first corresponding pixel driving circuit in the pixel driving circuit of the (3k-2)th column on the substrate.

13. The array substrate according to any one of claims 1 to 3, further comprising a plurality of fourth reset signal lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); In the pixel driving circuit of the (3k-1)th column, the positive projection of the corresponding fourth reset signal line among the multiple fourth reset signal lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column on the substrate, and basically covers the positive projection of the active layer of the data writing transistor in the second corresponding pixel driving circuit in the pixel driving circuit of the (3k-1)th column on the substrate.

14. The array substrate according to any one of claims 1 to 3, further comprising a plurality of third reset signal lines; in, Each pixel driving circuit further includes a data writing transistor and a first reset transistor; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); In the pixel driving circuit of the (3k)th column, the positive projection of the corresponding third reset signal line among the multiple third reset signal lines on the substrate basically covers the positive projection of the active layer of the first reset transistor in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column on the substrate, and basically covers the positive projection of the active layer of the data writing transistor in the third corresponding pixel driving circuit in the pixel driving circuit of the (3k)th column on the substrate.

15. The array substrate according to claim 1 , further comprising a plurality of fourth voltage supply lines, a plurality of fourth reset signal lines, and a plurality of third reset signal lines located in the same layer; in, The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); The (3k-2)th column includes a fourth voltage supply line among the plurality of fourth voltage supply lines; The (3k-1)th column includes a fourth reset signal line among the plurality of fourth reset signal lines; and The (3k)th column includes a third reset signal line among the plurality of third reset signal lines.

16. The array substrate according to claim 15, wherein: The plurality of fourth voltage supply lines do not exist in the (3k-1)th column and do not exist in the (3k)th column; The plurality of fourth reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k)th column; and The plurality of third reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k-1)th column.

17. The array substrate according to claim 1, further comprising a first voltage supply network and a second voltage supply network; in, The first voltage supply network includes a plurality of first voltage supply lines and a plurality of third voltage supply lines interconnected with each other; the plurality of first voltage supply lines extending in a direction substantially parallel to the first direction; the plurality of third voltage supply lines extending in a direction substantially parallel to the second direction; Each of the plurality of first voltage supply lines is connected to one or more third voltage supply lines of the plurality of third voltage supply lines; Each of the plurality of third voltage supply lines is connected to one or more first voltage supply lines of the plurality of first voltage supply lines; as well as wherein the second voltage supply network comprises a plurality of second voltage supply lines and a plurality of fourth voltage supply lines interconnected with each other; the plurality of second voltage supply lines extending in a direction substantially parallel to the first direction; the plurality of fourth voltage supply lines extending in a direction substantially parallel to the second direction; Each of the plurality of second voltage supply lines is connected to one or more fourth voltage supply lines of the plurality of fourth voltage supply lines; and Each of the plurality of fourth voltage supply lines is connected to one or more second voltage supply lines of the plurality of second voltage supply lines; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); The plurality of third voltage supply lines exist in the (3k-2)th column, in the (3k-1)th column, and in the (3k)th column; The plurality of fourth voltage supply lines do not exist in the (3k-1)th column and do not exist in the (3k)th column.

18. The array substrate according to claim 1, further comprising a first reset signal network; in, The first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; The plurality of first reset signal lines extend in a direction substantially parallel to the first direction; the plurality of third reset signal lines extending in a direction substantially parallel to the second direction; Each of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; and Each of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); and The plurality of third reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k-1)th column.

19. The array substrate according to claim 1, further comprising a second reset signal network; in, The second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; the plurality of second reset signal lines extending in a direction substantially parallel to the first direction; the plurality of fourth reset signal lines extending in a direction substantially parallel to the second direction; Each of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; as well as Each of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines; The pixel driving circuits of the array substrate are arranged into a plurality of columns, the plurality of columns including the (3k-2)th column, the (3k-1)th column, and the (3kth column) in the K columns, wherein K and k are positive integers, and 1≤k≤(K / 3); and The plurality of fourth reset signal lines do not exist in the (3k-2)th column and do not exist in the (3k)th column. 20 . A display device comprising the array substrate according to claim 1 , and one or more integrated circuits connected to the array substrate.

Images