Current and voltage acquisition board card based on CPCI bus

Abstract

The invention discloses a current and voltage acquisition board card based on a CPCI bus, and relates to the technical field of data transmission control, the current and voltage acquisition board card comprises a board body, the board body is provided with a multi-channel system for realizing multi-channel current and voltage acquisition of the CPCI, and the multi-channel system comprises an acquisition unit arranged at the top and bottom of the board body and used for acquiring current and voltage of the CPCI; comprising a current and voltage input protection module, a digital quantity IO input protection module, a voltage and current acquisition module, a multi-channel selection module, an FPGA controller, a power supply module, a CPCI bus connector and an FPGA controller which are fixedly mounted above a board body, and the FPGA controller is used for processing acquired data and control information data; the multi-channel current and voltage acquisition of the CPCI is realized through the 3U CPCI size, and a dial switch electronic component is adopted, so that the current and voltage acquisition can be simultaneously realized. And an AD1206 chip is adopted, so that the maximum 32-channel current acquisition or 64-channel voltage acquisition is realized on the 3U CPCI standard size.

Description

Technical Field

[0001] The invention relates to the technical field of data transmission control, in particular to a current and voltage acquisition board based on CPCI bus. Background Art

[0002] The current and voltage acquisition board is a hardware device used to measure and collect current and voltage signals.

[0003] According to the patent title: A CPCI bus-based IO board (patent publication number: CN215769433U, patent publication date: 2022-02-08), it includes a power supply, an FPGA programmable logic chip, a CPCI bus controller, a CPCI connector, a binary input circuit, and a binary output circuit. The CPCI connector is connected to the FPGA programmable logic chip via the CPCI bus controller. The binary input circuit and the binary output circuit are respectively connected to the binary input signal input terminal and the binary output signal output terminal of the FPGA programmable logic chip. The IO board is a 6U board. The IO board adopts a 6U board and integrates the binary input circuit and the binary output circuit within the board, which has a high degree of integration.

[0004] Based on the above-mentioned prior art, existing CPCI-bus-based current and voltage acquisition boards still have the following problems. Acquisition boards are essential in the fields of industry, aviation, and aerospace. However, the 3U acquisition boards currently on the market cannot meet the requirements of acquiring data from multiple channels, simultaneously acquiring current and voltage, and supporting 16-channel I / O. Therefore, the present invention provides a CPCI-bus-based current and voltage acquisition board. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention provides a CPCI-based current and voltage acquisition board. This board addresses the following issues with existing CPCI-based current and voltage acquisition boards. Acquisition boards are essential in the industrial, aviation, and aerospace industries. However, existing 3U acquisition boards on the market cannot meet the requirements for acquiring multiple channels of data, simultaneously acquiring current and voltage, and supporting 16-channel I / O.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a current and voltage acquisition board based on the CPCI bus, comprising a board body, wherein a multi-channel system is provided on the board body for realizing multi-channel current and voltage acquisition of CPCI, and the multi-channel system comprises: an acquisition unit, which is arranged at the top and bottom of the board body, and comprises a current and voltage input protection module, a digital IO input protection module, a voltage and current acquisition module, a multi-channel selection module, an FPGA controller, a power module, a CPCI bus connector and an FPGA controller fixedly installed above the board body, and the FPGA controller is used to process the acquired data and control information data, and the FPGA controller is connected to the CPCI bus connector and the voltage and current acquisition module, the top and bottom of the left side of the board body and the bottom of the right side of the board body are fixedly installed with SCSI100 communication connectors, the bottom of the board body is fixedly installed with an AD acquisition module, and the SCSI100 communication connector is connected to the AD acquisition module through the voltage and current acquisition module; The clock and synchronization unit is located on the top of the board and is used to provide a high-precision clock source for current and voltage acquisition, ensuring the synchronization and accuracy of the collected data.

[0007] Preferably, the clock and synchronization unit includes a clock generator, a clock buffer, a clock divider, a clock synchronizer, a phase-locked loop, a clock manager and a clock monitoring chip fixedly mounted on the top of the board, and the output end of the clock generator is connected to the input end of the clock buffer, and the output end of the clock buffer is connected to the input end of the clock divider, and the output end of the clock divider is connected to the input end of the clock synchronizer, and the output end of the clock synchronizer is connected to the input end of the phase-locked loop, and the output end of the phase-locked loop is connected to the input end of the clock manager, and the clock generator, clock buffer, clock divider, clock synchronizer, phase-locked loop and clock monitoring chip are bidirectionally connected.

[0008] Preferably, the SCSI100 communication connector is responsible for receiving FPGA acquisition instructions and sending acquisition data, accepting FPGA control signals and receiving controlled signals transmitted by the CPCI bus connector.

[0009] Preferably, the voltage and current acquisition module is switched by a dip switch, and current and voltage acquisition can also be performed simultaneously.

[0010] Preferably, the AD acquisition module adopts AD1206 chip to switch between multiple acquisition channels, thereby increasing the acquisition channels.

[0011] Preferably, the FPGA controller supports a maximum of 64 channels of voltage acquisition or 32 channels of current acquisition.

[0012] Preferably, the FPGA controller adopts single channel single calibration.

[0013] Preferably, the FPGA controller is designed with 16-channel digital IO input and output functions.

[0014] The present invention provides a CPCI bus-based current and voltage acquisition board. Compared with the existing technology, it has the following advantages: 1. This CPCI bus-based current and voltage acquisition board implements CPCI multi-channel current and voltage acquisition within a 3U CPCI form factor. It uses DIP switch electronic components to enable simultaneous current and voltage acquisition. Using the AD1206 chip, it enables up to 32 channels of current acquisition or 64 channels of voltage acquisition within the standard 3U CPCI form factor. 2. This CPCI bus-based current and voltage acquisition board utilizes single-channel logic calibration to internally store 32-channel current calibration values and 64-channel voltage calibration values, improving signal acquisition accuracy while reducing board cost. 3. This CPCI bus-based current and voltage acquisition board, equipped with a clock and synchronization unit, can utilize a more precise clock source. This high-precision clock source ensures more accurate timestamps for data acquisition, thereby improving data accuracy and reliability. Furthermore, clock synchronization is achieved through a clock synchronizer module. The synchronized clock source ensures that the data collected by the board remains consistent in time, facilitating subsequent data analysis and processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a top perspective structural diagram of the present invention; Figure 2 It is a bottom perspective structural diagram of the present invention; Figure 3 A three-dimensional structural diagram of a clock and synchronization unit of the present invention; Figure 4 It is a schematic diagram of the process of the present invention; Figure 5 It is a flow chart of the clock and synchronization unit of the present invention.

[0016] In the figure: 1-board, 2-multi-channel system, 21-acquisition unit, 211-SCSI100 communication connector, 212-current and voltage input protection module, 213-digital IO input protection module, 214-voltage and current acquisition module, 215-multi-channel selection module, 216-FPGA controller, 217-power module, 218-CPCI bus connector, 219-AD acquisition module, 22-clock and synchronization unit, 221-clock generator, 222-clock buffer, 223-clock divider, 224-clock synchronizer, 225-phase locked loop, 226-clock manager, 227-clock monitoring chip. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] See also Figure 1-Figure 5 The present invention provides a technical solution: a current and voltage acquisition board based on CPCI bus, comprising a board body 1, a multi-channel system 2 is provided on the board body 1 for realizing multi-channel current and voltage acquisition of CPCI, the multi-channel system 2 comprises: an acquisition unit 21, arranged at the top and bottom of the board body 1, comprising a current and voltage input protection module 212 fixedly mounted above the board body 1, a digital IO input protection module 213, a voltage and current acquisition module 214, a multi-channel selection module 215, an FPGA controller 216, a power supply module 217, a CPCI bus connector 218 and an FPGA controller 216, and the FPGA controller 216 16 is used to process the collected data and control information data, and the FPGA controller 216 is connected to the CPCI bus connector 218 and the voltage and current acquisition module 214. The SCSI100 communication connector 211 is fixedly installed on the top bottom of the left side of the board body 1 and the bottom of the right side of the board body 1. The AD acquisition module 219 is fixedly installed on the bottom of the board body 1, and the SCSI100 communication connector 211 is connected to the AD acquisition module 219 through the voltage and current acquisition module 214; the clock and synchronization unit 22 is set at the top of the board body 1, and is used to provide a high-precision clock source for current and voltage acquisition to ensure the synchronization and accuracy of the collected data.

[0019] The FPGA controller 216 receives data from the bus and transmits collected data. It controls the AD data acquisition and reception. Furthermore, it calibrates the collected data, processing the collected data with the calibration values stored in the FPGA to improve acquisition accuracy. It also controls the I / O module, enabling digital I / O input and output.

[0020] The AD acquisition module 219 acquires the current or voltage signal connected to the channel switching module 5 by receiving the start instruction from the FPGA controller 216 , and sends the acquired data to the FPGA controller 216 .

[0021] The voltage and current acquisition module 214 receives the input signal from the external SCSI 100 1 and selects the mode through the DIP switch to realize current acquisition or voltage acquisition.

[0022] The current and voltage input protection module 212 is mainly used to protect the board. When the signal input from the SCSI100 communication connector 211 is too large, the components in the protection circuit are broken down and the input signal is directly connected to the ground, thereby protecting the subsequent stages of the board from being affected.

[0023] The digital IO input protection module 213 is mainly used to protect the board. When the signal input from the SCSI100 communication connector 211 is too large, the components in the protection circuit are broken down and the input signal is directly connected to the ground, thereby protecting the subsequent stages of the board from being affected.

[0024] The SCSI100 communication connector 211 is a connector for external input signals, which inputs the signals to the current and voltage input protection module 212 or the digital IO input protection module 213 so that the subsequent modules can operate normally.

[0025] The power module 217 provides analog voltages +12V, -12V, +5V, and +5V digital voltages through internal conversion circuits.

[0026] In this embodiment, the clock and synchronization unit 22 includes a clock generator 221, a clock buffer 222, a clock divider 223, a clock synchronizer 224, a phase-locked loop 225, a clock manager 226 and a clock monitoring chip 227 fixedly installed on the top of the board 1, and the output end of the clock generator 221 is connected to the input end of the clock buffer 222, and the output end of the clock buffer 222 is connected to the input end of the clock divider 223, and the output end of the clock divider 223 is connected to the input end of the clock synchronizer 224, and the output end of the clock synchronizer 224 is connected to the input end of the phase-locked loop 225, and the output end of the phase-locked loop 225 is connected to the input end of the clock manager 226. The clock generator 221, the clock buffer 222, the clock divider 223, the clock synchronizer 224, the phase-locked loop 225 and the clock monitoring chip 227 are bidirectionally connected.

[0027] By providing a clock and synchronization unit 22, a higher precision clock source can be obtained. The high precision clock source can ensure that the timestamp of data collection is more accurate, thereby improving the accuracy and reliability of the data, and clock synchronization is achieved through the clock synchronizer 224 synchronization module. The synchronized clock source can ensure that the data collected by the board is consistent in time, which is convenient for subsequent data analysis and processing.

[0028] The clock generator 221 is responsible for generating a stable clock signal, which usually has high precision and low jitter characteristics to ensure the stability and reliability of the clock signal; the clock buffer 222 is used to transmit the clock signal from the clock generator to other parts, which can enhance the driving capability of the clock signal, reduce signal attenuation and distortion, and ensure the effective transmission of the clock signal in the system; the clock divider 223 is used to divide or multiply the clock signal to meet the clock frequency requirements of different components, and is usually programmable and can flexibly adjust the frequency as needed; the clock synchronizer 224 is used to ensure that the clock signals between various nodes remain consistent; the phase-locked loop 225 can lock the phase and frequency of the input clock signal and output a stable clock signal synchronized with it; the clock manager 226 provides a unified interface to manage the functions of the clock generator 221, clock buffer 222, clock divider 223, clock synchronizer 224 and phase-locked loop 225; the clock monitoring chip 227 is used to monitor the status of the clock signal, including frequency, phase and stability.

[0029] In this embodiment, the FPGA controller 216 is responsible for receiving FPGA acquisition instructions and sending acquisition data, accepting FPGA control signals and receiving controlled signals transmitted by 218.

[0030] The control signal of the FPGA controller 216 is responsible for starting the AD acquisition module 219 to collect data and receive and process the collected data, or sending and receiving the controlled signal transmitted by the CPCI bus.

[0031] In this embodiment, the voltage and current acquisition module 214 is switched by a dip switch and can also acquire current and voltage simultaneously.

[0032] In this embodiment, the AD acquisition module 219 uses an AD1206 chip to perform multi-channel acquisition switching, thereby increasing the acquisition channels.

[0033] The AD7980 AD acquisition chip is used, with a single-channel sampling rate of up to 1M, offering a relatively wide range of sampling rates for customers to choose from. The AD chip effectively reduces components and size, enabling 32-channel current or 64-channel voltage acquisition with just four AD7980 chips.

[0034] In this embodiment, the FPGA controller 216 supports a maximum of 64 channels of voltage acquisition or 32 channels of current acquisition.

[0035] In this embodiment, the FPGA controller 216 adopts single channel single calibration.

[0036] The FPGA stores calibration values for 32 currents and 64 voltages, enabling independent calibration of each channel to improve the accuracy of data collected by each channel.

[0037] In this embodiment, 216 is designed with 16-channel digital IO input and output functions.

[0038] The FPGA controller 216 uses the 824001 chip to effectively prevent the external voltage from being too high and burning the board.

[0039] Meanwhile, the contents not described in detail in this specification belong to the prior art known to those skilled in the art.

[0040] When working, first, the collected data and control information data are transmitted to the FPGA through the CPCI bus, and the CPCI bus data is processed by the FPGA. During the FPGA data processing process, the clock and synchronization unit 22 uses a high-precision clock source to ensure that the timestamp of data collection is more accurate, further improving the accuracy and reliability of the data, and transmitting the processed data to the host computer through the CPCI bus.

[0041] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0042] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A current and voltage acquisition board based on CPCI bus, comprising a board body (1), characterized in that: The board (1) is provided with a multi-channel system (2) for realizing multi-channel current and voltage acquisition of CPCI. The multi-channel system (2) comprises: an acquisition unit (21), which is provided at the top and bottom of the board (1), and comprises a current and voltage input protection module (212) fixedly installed above the board (1), a digital IO input protection module (213), a voltage and current acquisition module (214), a multi-channel selection module (215), an FPGA controller (216), a power supply module (217), a CPCI bus connector (218) and an FPGA controller (216), and the FPGA controller (216) is used to process the acquired data and the control information data. The FPGA controller (216) is connected to the CPCI bus connector (218) and the voltage and current acquisition module (214); the top and bottom of the left side of the board body (1) and the bottom of the right side of the board body (1) are fixedly installed with a SCSI100 communication connector (211); the bottom of the board body (1) is fixedly installed with an AD acquisition module (219), and the SCSI100 communication connector (211) is connected to the AD acquisition module (219) through the voltage and current acquisition module (214); a clock and synchronization unit (22) is arranged on the top of the board body (1) and is used to provide a high-precision clock source for current and voltage acquisition to ensure the synchronization and accuracy of the acquired data.

2. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The clock and synchronization unit (22) includes a clock generator (221), a clock buffer (222), a clock divider (223), a clock synchronizer (224), a phase-locked loop (225), a clock manager (226), and a clock monitoring chip (227) fixedly mounted on the top of the board (1), and the output end of the clock generator (221) is connected to the input end of the clock buffer (222), and the output end of the clock buffer (222) is connected to the input end of the clock divider (223). , and the output end of the clock divider (223) is connected to the input end of the clock synchronizer (224), and the output end of the clock synchronizer (224) is connected to the input end of the phase-locked loop (225), and the output end of the phase-locked loop (225) is connected to the input end of the clock manager (226), and the clock generator (221), the clock buffer (222), the clock divider (223), the clock synchronizer (224), the phase-locked loop (225) and the clock monitoring chip (227) are bidirectionally connected.

3. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The SCSI100 communication connector (211) is responsible for receiving acquisition instructions from the FPGA controller (216) and sending acquired data, receiving control signals from the FPGA controller (216) and receiving controlled signals transmitted by the CPCI bus connector (218).

4. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The voltage and current acquisition module (214) is switched by a dial switch and can also acquire current and voltage simultaneously.

5. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The AD acquisition module (219) uses an AD1206 chip to perform multi-channel acquisition switching, thereby increasing the acquisition channels.

6. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The FPGA controller (216) supports a maximum of 64 channels of voltage acquisition or 32 channels of current acquisition.

7. A CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The FPGA controller (216) adopts single channel single calibration.

8. The CPCI bus-based current and voltage acquisition board according to claim 1, characterized in that: The FPGA controller (216) is designed with 16-channel digital IO input and output functions.

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