FPGA parallel acceleration implementation method based on minimum entropy self-focusing algorithm

Abstract

The invention provides an FPGA parallel acceleration implementation method based on a minimum entropy self-focusing algorithm, and relates to the field of radar signal processing imaging. Imaging is realized by adopting a specific data processing flow, an ISAR image is finally obtained, and the processing mode more depends on the high efficiency of an algorithm and a data reading and processing mode instead of purely depending on the computing power of hardware, so that the dependency on high-performance hardware is reduced to a certain extent, and the ISAR image processing efficiency is improved. And the purchase and maintenance cost is reduced. Besides, the compensation phase value is continuously updated in an iteration mode, and the iteration process can gradually approach to the optimal compensation phase value, so that when large-scale data are processed, translation compensation and other processing can be more effectively carried out on the data, the imaging quality is improved, the processing efficiency is also improved, and by reasonably utilizing FFT analysis, the method has the advantages of being simple in structure and convenient to operate. The imaging cost of the existing ISAR echo data is integrally reduced, and the parallel processing efficiency of the ISAR echo data is improved.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing and imaging, and in particular to an FPGA parallel acceleration implementation method based on a minimum entropy self-focusing algorithm. Background Art

[0002] In modern military confrontations and the detection and identification of targets in complex scenarios, Inverse Synthetic Aperture Radar (ISAR) imaging technology plays an irreplaceable strategic role, thanks to its unique advantages of all-day, all-weather, long-range, and high-resolution imaging. With the continuous advancement of technology, the requirements for ISAR imaging resolution are increasing. Improving resolution generally requires increasing the radar transmit signal bandwidth and extending the synthetic aperture time. However, this measure has directly led to a sharp increase in the amount of radar echo data, posing a severe challenge to signal processing speed and ISAR imaging efficiency. Especially when accurately imaging high-speed maneuvering targets (such as stealth fighters, ballistic missiles, or ship formations), how to improve signal processing speed and imaging efficiency while ensuring imaging quality has become a pressing technical challenge.

[0003] To address these challenges, many research institutions and universities currently rely primarily on specialized DSP (digital signal processing) platforms or large CPU- and GPU-based servers to process ISAR imaging echo data. These platforms or servers, with their powerful computing capabilities, alleviate data processing pressure to a certain extent. DSP platforms improve performance by increasing clock frequency, adding more boards, and expanding the number of cores. Meanwhile, large CPU- or GPU-based servers rely primarily on the computing power of their core hardware and employ traditional serial C++ algorithms to implement ISAR autofocus imaging.

[0004] However, existing technical solutions still have many shortcomings in practical applications. For DSP platforms, although increasing the clock frequency can enhance computing speed, the increased power consumption and heat dissipation problems brought about by high-frequency operation cannot be ignored. This not only increases the complexity of hardware design, but may also affect the stability and reliability of the system. At the same time, increasing the number of DSP boards to improve computing power, although it can expand computing power, significantly increases the overall cost and size of the system, and places extremely high demands on the scheduling and coordination of hardware resources, which can easily become a performance bottleneck. For large servers based on CPU or GPU, the high procurement and maintenance costs have become an important factor restricting their widespread application. More importantly, many ISAR imaging autofocus algorithms are still written in traditional serial C++ language, which is inefficient when processing large-scale data and cannot meet the strict requirements of real-time and high efficiency in modern military confrontations. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides an FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm, comprising:

[0008] S101, acquiring echo data of an inverse synthetic aperture radar, performing envelope alignment processing on the echo data to obtain unfocused HRRP data; the unfocused HRRP data is stored in DDR4;

[0009] S102, reading multiple channels of unfocused HRRP data from the DDR4 in parallel according to the azimuth direction, and performing translation compensation on the multiple channels of unfocused HRRP data using the current compensation phase value to obtain translation compensation data;

[0010] S103, performing FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtaining a two-dimensional result by using the results of the FFT analysis and the logarithmic calculation;

[0011] S104, using the result of FFT analysis to determine whether the iteration stop condition is met;

[0012] S105. When the condition in S104 is not satisfied, performing FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result;

[0013] S106, performing complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result;

[0014] S107, performing phase calculation using the one-dimensional complex result to obtain a new compensation phase value;

[0015] S108: Use the new compensation phase value as the current compensation phase value in S102, and repeat S102-S108 until the condition of S104 is met, and perform FFT analysis on the translation compensation data when S102 is most recently executed to obtain an ISAR image after rapid imaging.

[0016] Optionally, S102 includes:

[0017] Read multiple channels of unfocused HRRP data in parallel from DDR4 according to the azimuth direction;

[0018] The current compensation phase value is multiplied in parallel with the multi-channel unfocused HRRP data to obtain translation compensation data.

[0019] Optionally, S103 includes:

[0020] The translation compensation data is passed to the Fast Fourier Transform IP core for multi-channel parallel processing to perform FFT analysis to obtain a two-dimensional image; the two-dimensional image is the result of the FFT analysis;

[0021] The two-dimensional image is passed to the Cordic IP core to calculate the complex data modulus value and obtain the complex data modulus value of the two-dimensional image;

[0022] Use the Logarithm IP core to calculate the logarithm of the complex data modulus of the two-dimensional image to obtain the logarithm of the two-dimensional image.

[0023] The highest bit of the imaginary part of the two-dimensional image is inverted to obtain the complex conjugate value of the two-dimensional image;

[0024] The complex data modulus value of the two-dimensional image and the complex conjugate value of the two-dimensional image are multiplied using the Mult IP core to obtain a two-dimensional result; the Fast Fourier Transform IP core, Cordic IP core, Logarithm IP core and Mult IP core are all hardware modules in the FPGA.

[0025] Optionally, S104 includes:

[0026] Calculate the image entropy using the two-dimensional image to obtain the current image entropy;

[0027] Subtract the entropy of the current image from the entropy of the previous image to obtain the image entropy difference; the entropy of the previous image is the image entropy corresponding to the entropy of the current image in the previous iteration;

[0028] Determine whether the image entropy difference is less than a preset threshold;

[0029] When the image entropy difference is less than the preset threshold, the iteration stopping condition is met.

[0030] Optionally, S107 includes:

[0031] Invert the highest bit of the imaginary part of the one-dimensional complex number result to obtain the conjugate value of the one-dimensional complex number result;

[0032] The Cordic IP core is used to calculate the modulus of the one-dimensional complex result;

[0033] The Divder IP core is used to divide the conjugate value of the one-dimensional complex result by the modulus value of the one-dimensional complex result to obtain a new compensated phase value.

[0034] Optionally, the current image entropy is expressed as:

[0035]

[0036] E(K) represents the current image entropy value corresponding to the two-dimensional image K, m represents the m-th range direction, n represents the n-th azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, and D(n,m) represents the scattering intensity density of the two-dimensional image K in the n-th azimuth direction and the m-th range downward;

[0037]

[0038] K(n,m) represents the two-dimensional image element value corresponding to the n-th azimuth direction and the m-th distance downward of the two-dimensional image K, and s(K) represents the total energy of the two-dimensional image K;

[0039]

[0040] Alternatively, the one-dimensional complex result is represented as:

[0041]

[0042] Among them, w(n) represents the value of all one-dimensional complex results corresponding to the nth azimuth direction, m represents the mth range direction, n represents the nth azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, K(n,m) represents the two-dimensional image element value corresponding to the nth azimuth direction and the mth range direction, K * (n,m) represents the conjugate value of K(n,m), j represents an imaginary single number, and G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth direction and the mth distance downward.

[0043] Optionally, the translation compensation data is expressed as:

[0044]

[0045] G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth and the mth distance downward, G(n) represents the unfocused HRRP data at all distances downward corresponding to the nth azimuth, represents the current compensation phase value at the nth azimuth downward, and j represents an imaginary odd number;

[0046] G(n)=[G(n,1),G(n,2),…,G(n,M)] T ;

[0047] T represents transposition processing, G(n,1) represents the unfocused HRRP data in the nth azimuth direction and the first distance downward, G(n,2) represents the unfocused HRRP data in the nth azimuth direction and the second distance downward, G(n,M) represents the unfocused HRRP data in the nth azimuth direction and the Mth distance downward, and exp(.) represents the exponential function.

[0048] In a second aspect, the present invention provides an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm, and the FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm includes: an acquisition unit, a translation compensation unit, a calculation unit, a judgment unit, and a circulation unit;

[0049] An acquisition unit is used to acquire the echo data of the inverse synthetic aperture radar, and perform envelope alignment processing on the echo data to obtain unfocused HRRP data; the unfocused HRRP data is stored in DDR4;

[0050] A translation compensation unit is used to read multiple channels of unfocused HRRP data from the DDR4 in parallel according to the azimuth direction, and perform translation compensation on the multiple channels of unfocused HRRP data using the current compensation phase value to obtain translation compensation data;

[0051] A calculation unit is used to perform FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtain a two-dimensional result by using the results of the FFT analysis and the results of the logarithmic calculation;

[0052] A judgment unit, used to judge whether an iteration stop condition is met using the result of FFT analysis;

[0053] The calculation unit is further configured to perform FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result when the condition of the judgment unit is not met;

[0054] The calculation unit is further used to perform complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result;

[0055] The calculation unit is further used to perform phase calculation using the one-dimensional complex result to obtain a new compensated phase value;

[0056] The loop unit is used to use the new compensation phase value as the current compensation phase value in the translation compensation unit, repeatedly execute the steps from the translation compensation unit to the calculation unit until the conditions in the judgment unit are met, and perform FFT analysis on the translation compensation data when the translation compensation unit steps are most recently executed to obtain the ISAR image after rapid imaging.

[0057] In a third aspect, the present invention provides an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to perform the steps of the FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm as described in the first aspect above.

[0058] The present invention provides an FPGA parallel acceleration implementation method based on a minimum entropy self-focusing algorithm, comprising: S101, acquiring echo data of an inverse synthetic aperture radar, performing envelope alignment processing on the echo data to obtain unfocused HRRP data; storing the unfocused HRRP data in DDR4; S102, reading multiple channels of unfocused HRRP data from DDR4 in parallel according to azimuth, and performing translation compensation processing on the multiple channels of unfocused HRRP data using current compensation phase values to obtain translation compensation data; S103, performing FFT analysis and logarithmic calculation on the translation compensation data in sequence, and calculating a two-dimensional result using the results of the FFT analysis and the logarithmic calculation; S104, using The result of the FFT analysis determines whether the iteration stop condition is met; S105, when the condition of S104 is not met, the two-dimensional result is subjected to FFT analysis in the azimuth direction to obtain a two-dimensional fast Fourier transform result; S106, the translation compensation data and the two-dimensional fast Fourier transform result are subjected to complex multiplication and range summation to obtain a one-dimensional complex result; S107, the phase is calculated using the one-dimensional complex result to obtain a new compensation phase value; S108, the new compensation phase value is used as the current compensation phase value in S102, and S102-S108 are repeatedly executed until the condition of S104 is met, and the translation compensation data during the most recent execution of S102 is subjected to FFT analysis to obtain an ISAR image after rapid imaging. The present invention is based on an FPGA hardware platform, fully utilizing the advantages of the FPGA hardware platform's flexible programming of logic devices and parallel implementation, deeply optimizing the steps of the minimum entropy-based autofocus algorithm, and completing the parallel design of the algorithm on the FPGA platform; by adopting a full pipeline design method, the data throughput is further improved. Through the following technical means: parallel design, full pipeline architecture, and timing optimization, the real-time performance of the algorithm is significantly improved, while at the same time, the reliance on high-performance hardware is reduced to a certain extent, reducing procurement and maintenance costs. In summary, by reducing the reliance on hardware computing power and adopting more efficient parallel processing processes, the method of the present invention can effectively reduce the imaging cost of existing ISAR echo data, improve the imaging processing efficiency of ISAR echo data, and achieve real-time and efficient imaging.

[0059] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A flowchart of a method for implementing FPGA parallel acceleration based on a minimum entropy autofocusing algorithm provided by an embodiment of the present invention;

[0061] Figure 2 The complete execution block diagram of the FPGA parallel acceleration implementation method of the minimum entropy self-focusing algorithm is shown as an example;

[0062] Figure 3 Schematic diagram showing HRRP data with unfocused azimuth processing after envelope alignment;

[0063] Figure 4 The processing results of the GPU platform running the focusing algorithm based on the image entropy evaluation criterion are shown as an example;

[0064] Figure 5 The following example shows the processing results of the CPU platform running the focusing algorithm based on the image entropy evaluation criterion;

[0065] Figure 6 The processing results of the focusing algorithm based on the image entropy evaluation criterion running on the FPGA hardware platform of the present invention are exemplarily shown;

[0066] Figure 7 A schematic diagram of the structure of an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm provided by an embodiment of the present invention;

[0067] Figure 8 A schematic structural diagram of an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0068] The applicant's research found that the focusing algorithm based on the image entropy evaluation criterion can effectively achieve high-resolution ISAR (Inverse Synthetic Aperture Radar) images. By introducing the image entropy evaluation mechanism, the algorithm can stably output high-quality imaging results, whether in a single-target scene or a complex multi-target environment, and has extremely strong robustness and adaptability. In addition, based on the FPGA hardware platform, the applicant fully utilizes the advantages of the FPGA hardware platform's parallel implementation, deeply optimizes the algorithm steps, and completes the parallel design of the algorithm on the FPGA platform; by adopting a full-pipeline design method, the data processing efficiency is further improved; at the same time, combined with strict timing constraints to optimize the algorithm design, the operating frequency is successfully increased to 300MHz.

[0069] The following is a detailed description of the derivation process of the FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm.

[0070] The entropy function corresponding to the two-dimensional image K of HRRP data is expressed as E(K) and is specifically defined as:

[0071]

[0072] m represents the mth range direction, n represents the nth azimuth direction, M represents the total number of range directions, and N represents the total number of azimuth directions. D(n,m) represents the scattering intensity density of the two-dimensional image K in the nth azimuth direction and the mth range downward:

[0073]

[0074] s(K) represents the total energy of the two-dimensional image K. s(K) can be specifically expressed as:

[0075]

[0076] Assume that all unfocused HRRP data corresponding to the n-th azimuth at downward distances are expressed as:

[0077] G(n)=[G(n,1),G(n,2),…,G(n,M)] T ; (4)

[0078] T represents transposition processing, G(n,1) represents the unfocused HRRP data in the nth azimuth direction and the first distance downward, G(n,2) represents the unfocused HRRP data in the nth azimuth direction and the second distance downward, G(n,M) represents the unfocused HRRP data in the nth azimuth direction and the Mth distance downward, and exp(.) represents the exponential function.

[0079] In the calculation, the compensation phase is represented by θ(n), and θ(1) = 0. Since the compensation phase cannot be obtained directly, the estimated value of the compensation phase is expressed as:

[0080]

[0081] Indicates the current compensation phase value at the nth azimuth downward.

[0082] use When performing translation compensation on multi-channel unfocused HRRP data, the following formula is used:

[0083]

[0084] G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth and the mth distance downward, G(n) represents the unfocused HRRP data at all distances downward corresponding to the nth azimuth, represents the current compensated phase value at the nth azimuth downward, and j represents an imaginary odd number.

[0085] Now, ideally one should determine by minimizing the entropy function E(K) Based on this, the entropy function E(K) is applied to the current compensation phase value of the n-th range image. Perform partial derivative operation, that is:

[0086]

[0087] It can be obtained by the following formula:

[0088]

[0089] In formula (7), we have:

[0090]

[0091] The symbol "*" represents the conjugate operation. The K(n,m) of each range gate can be obtained by performing the discrete Fourier transform (DFT) of G'(n,m) with respect to n. The relationship between:

[0092]

[0093] because n = 2, ..., M is incoherent, so the following holds:

[0094]

[0095] Combining equations (7) to (9) and (11), we can obtain:

[0096]

[0097] Where w(n) is a one-dimensional complex value, expressed as:

[0098]

[0099] Based on the above derivation process, a new compensation phase value can be obtained, and based on the translation compensation processing of multiple iterations, the final translation compensation data can be obtained to achieve rapid imaging of ISAR images.

[0100] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0101] In order to effectively reduce the imaging cost of existing ISAR echo data, improve the parallel processing efficiency of ISAR echo data, and achieve real-time and high-efficiency imaging, an embodiment of the present invention provides an FPGA parallel acceleration implementation method based on the minimum entropy autofocusing algorithm. Figure 1 A flowchart of an FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm provided by an embodiment of the present invention is shown as follows: Figure 1 Shown, including:

[0102] S101 , acquiring echo data of an inverse synthetic aperture radar, and performing envelope alignment processing on the echo data to obtain unfocused HRRP data.

[0103] The unfocused HRRP data is stored in DDR4, where DDR4 (Double Data Rate) is a fourth-generation synchronous dynamic random access memory with a double data rate.

[0104] In this embodiment, relative motion between the radar and the target may cause variations in the time delay of the received echo signals. Envelope alignment compensates for this signal variation caused by relative motion, ensuring that echoes received from different time periods are correctly aligned. Envelope alignment typically includes motion compensation, envelope extraction, and time delay correction.

[0105] S102 , reading multiple channels of unfocused HRRP data from the DDR4 in parallel according to the azimuth direction, and performing translation compensation on the multiple channels of unfocused HRRP data using the current compensation phase value to obtain translation compensation data.

[0106] Optionally, S102 includes:

[0107] Read multiple channels of unfocused HRRP data in parallel from DDR4 according to the azimuth direction;

[0108] The current compensation phase value is multiplied in parallel with the multi-channel unfocused HRRP data to obtain translation compensation data.

[0109] In the specific implementation, the present invention uses a 16-way parallelization design based on the performance and resource constraints of the Xcku115 board. However, in actual applications, if the FPGA performance is weak or the input data bandwidth is low, the number of parallelization paths can be appropriately reduced (e.g., 8, 4, or 2) to adapt to hardware limitations. Conversely, if the FPGA performance is superior and the input data bandwidth is high, the number of parallelization paths can be further increased (e.g., 32 or 64), thereby fully utilizing the hardware potential and achieving higher computing efficiency.

[0110] S103 , performing FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtaining a two-dimensional result by using the results of the FFT analysis and the logarithmic calculation.

[0111] Optionally, S103 includes:

[0112] The translation compensation data is passed to the Fast Fourier Transform IP core for multi-channel parallel processing to perform FFT analysis to obtain a two-dimensional image; the two-dimensional image is the result of the FFT analysis;

[0113] The two-dimensional image is passed to the Cordic IP core to calculate the complex data modulus value and obtain the complex data modulus value of the two-dimensional image;

[0114] Use the Logarithm IP core to calculate the logarithm of the complex data modulus of the two-dimensional image to obtain the logarithm of the two-dimensional image.

[0115] The highest bit of the imaginary part of the two-dimensional image is inverted to obtain the complex conjugate value of the two-dimensional image;

[0116] The complex data modulus value of the two-dimensional image and the complex conjugate value of the two-dimensional image are multiplied using the Mult IP core to obtain a two-dimensional result; the Fast Fourier Transform IP core, Cordic IP core, Logarithm IP core and Mult IP core are all hardware modules in the FPGA.

[0117] S104: Use the result of FFT analysis to determine whether the iteration stop condition is met.

[0118] Optionally, S104 includes:

[0119] Calculate the image entropy using the two-dimensional image to obtain the current image entropy;

[0120] Subtract the entropy of the current image from the entropy of the previous image to obtain the image entropy difference; the entropy of the previous image is the image entropy corresponding to the entropy of the current image in the previous iteration;

[0121] Determine whether the image entropy difference is less than a preset threshold;

[0122] When the image entropy difference is less than the preset threshold, the iteration stopping condition is met.

[0123] It should be noted that, in this embodiment, the initial value of the previous image entropy may be set to 1 to ensure the execution of the loop process.

[0124] Optionally, the current image entropy is expressed as:

[0125]

[0126] E(K) represents the current image entropy value corresponding to the two-dimensional image K, m represents the m-th range direction, n represents the n-th azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, and D(n,m) represents the scattering intensity density of the two-dimensional image K in the n-th azimuth direction and the m-th range downward;

[0127]

[0128] K(n,m) represents the two-dimensional image element value corresponding to the n-th azimuth direction and the m-th distance downward of the two-dimensional image K, and s(K) represents the total energy of the two-dimensional image K;

[0129]

[0130] S105. When the condition of S104 is not satisfied, perform FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result.

[0131] S106 , performing complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result.

[0132] Alternatively, the one-dimensional complex result is represented as:

[0133]

[0134] Among them, w(n) represents the value of all one-dimensional complex results corresponding to the nth azimuth direction, m represents the mth range direction, n represents the nth azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, K(n,m) represents the two-dimensional image element value corresponding to the nth azimuth direction and the mth range direction, K * (n,m) represents the conjugate value of K(n,m), j represents an imaginary single number, and G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth direction and the mth distance downward.

[0135] Optionally, the translation compensation data is expressed as:

[0136]

[0137] G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth and the mth distance downward, G(n) represents the unfocused HRRP data at all distances downward corresponding to the nth azimuth, represents the current compensation phase value at the nth azimuth downward, and j represents an imaginary odd number;

[0138] g(n)=[G(n,1),G(n,2),…,G(n,M)] T ;

[0139] T represents transposition processing, G(n,1) represents the unfocused HRRP data in the nth azimuth direction and the first distance downward, G(n,2) represents the unfocused HRRP data in the nth azimuth direction and the second distance downward, G(n,M) represents the unfocused HRRP data in the nth azimuth direction and the Mth distance downward, and exp(.) represents the exponential function.

[0140] S107 , performing phase calculation using the one-dimensional complex result to obtain a new compensation phase value.

[0141] Optionally, S107 includes:

[0142] Invert the highest bit of the imaginary part of the one-dimensional complex number result to obtain the conjugate value of the one-dimensional complex number result;

[0143] The Cordic IP core is used to calculate the modulus of the one-dimensional complex result;

[0144] The Divder IP core is used to divide the conjugate value of the one-dimensional complex result by the modulus value of the one-dimensional complex result to obtain a new compensated phase value.

[0145] S108: Use the new compensation phase value as the current compensation phase value in S102, and repeat S102-S108 until the condition of S104 is met, and perform FFT analysis on the translation compensation data when S102 is most recently executed to obtain an ISAR image after rapid imaging.

[0146] The embodiment of the present invention provides an FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm, which realizes imaging by adopting the specific data processing flow of S101-S108 above, and finally obtains an ISAR image. This processing method relies more on the efficiency of the algorithm itself and the method of data reading and processing, rather than simply relying on the computing power of the hardware, thereby reducing the dependence on high-performance hardware to a certain extent and reducing procurement and maintenance costs. In addition, the compensation phase value is continuously updated in an iterative manner, and each iteration utilizes a series of operations such as FFT analysis, logarithmic calculation, complex multiplication and range summation to optimize the compensation effect. This iterative process can gradually approach the optimal compensation phase value, so that when processing large-scale data, the data can be more effectively processed such as translation compensation, thereby improving the imaging quality while also improving the processing efficiency. FFT analysis can quickly convert data from the time domain to the frequency domain. By rationally utilizing FFT analysis, unnecessary complex calculations are avoided, and the overall processing efficiency is improved. In summary, the method of the present invention can effectively reduce the imaging cost of existing ISAR echo data and improve the parallel processing efficiency of ISAR echo data by reducing the dependence on hardware computing power and adopting a more efficient data processing process, thereby achieving real-time and efficient imaging.

[0147] also, Figure 2 The complete execution block diagram of the FPGA parallel acceleration implementation method of the minimum entropy self-focusing algorithm is also shown as an example. Figure 2 As shown, phase compensation is first performed on the unfocused HRRP data in the azimuth direction within the DDR4 using a 16-way parallel processing method and the current compensation phase value stored in the BRAM (block random access memory, which is the internal memory of the FPGA). The phase compensation result is then used to determine whether the iteration signal is enabled. If enabled (determining whether the iteration signal is enabled specifically includes calculating image entropy and determining whether the image entropy difference is greater than a preset threshold based on the change in image entropy during the iteration process. When the image entropy difference is greater than the set threshold, the enable condition is met), the translation compensation data is sequentially subjected to FFT analysis and logarithmic calculation (modulus, logarithm, conjugate, and division) to obtain a two-dimensional result. The two-dimensional result is then subjected to FFT analysis and range data summation to obtain a one-dimensional complex result. The one-dimensional complex result is then subjected to complex phase calculation to obtain a new compensation phase value. The current compensation phase value previously stored in the BRAM is updated with the new compensation phase value, and the above process is executed repeatedly until the iteration signal is disabled, and finally the ISAR image after rapid imaging is obtained (the ISAR image after rapid imaging is obtained by performing FFT analysis on the focusing processing result output when the iteration signal is disabled).

[0148] In order to illustrate the effectiveness of the FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm provided by the embodiment of the present invention, a simulation experiment was also conducted as follows:

[0149] When the data and experimental environment are the same, Figure 4-Figure 6 The focus processing results of the GPU platform, the CPU platform and the FPGA hardware platform (the present invention) are shown. Figure 3 Schematic diagram of azimuthally unfocused HRRP data after envelope alignment, i.e., the processed data of the experiment, is shown as an example. Figure 4 The following example shows the processing results of the GPU platform running the focusing algorithm based on the image entropy evaluation criterion. Figure 5 The following example shows the processing results of the CPU platform running the focusing algorithm based on the image entropy evaluation criterion. Figure 6 The results of the focus algorithm based on the image entropy evaluation criterion are shown as an example. Figure 4-6 It can be seen that the processing effect of the present invention is completely consistent with that of CPU and GPU. Table 1 provides a comparison of the real-time performance of the focusing algorithm based on the image entropy evaluation criterion when running on different platforms.

[0150] Table 1. Real-time comparison of focusing algorithms based on image entropy evaluation criteria running on different platforms

[0151]

[0152] Combine Figure 3 The experimental data scale of the present invention is 256 points in range and 256 points in azimuth. The data results in Table 1 show that the operating efficiency of the method of the present invention is approximately 90 times higher than that of traditional implementations, significantly improving the real-time performance of the algorithm. In summary, the method of the present invention achieves a significant improvement in focusing efficiency while maintaining the image focusing effect, demonstrating the effectiveness of the method of the present invention.

[0153] The technical advantages of the present invention are as follows:

[0154] 1. Compared with large servers based on CPU or GPU and DSP hardware platforms, the present invention relies on FPGA hardware platform and has the significant advantages of being more lightweight, portable and easy to deploy.

[0155] 2. Based on the FPGA hardware platform, leveraging its parallelization capabilities, the algorithm steps were deeply optimized and the algorithm's parallel design was completed on the FPGA platform. A fully pipelined design approach further improved data processing efficiency. Furthermore, the algorithm design was optimized with strict timing constraints, successfully increasing the operating frequency to 300MHz. These three technical approaches—parallelization, full pipeline architecture, and timing optimization—significantly improved the algorithm's real-time performance, providing strong support for high-performance computing.

[0156] The method provided in the embodiment of the present invention can be applied to electronic devices. Specifically, the electronic devices can be desktop computers, portable computers, smart mobile terminals, servers, etc., which are not limited in the embodiment of the present invention.

[0157] Based on the same inventive concept, an embodiment of the present invention also provides an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm. Figure 7 A schematic diagram of the structure of an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm provided by an embodiment of the present invention is shown as follows: Figure 7 Shown, including:

[0158] Acquisition unit 701, translation compensation unit 702, calculation unit 703, judgment unit 704 and circulation unit 705;

[0159] An acquisition unit 701 is configured to acquire echo data of an inverse synthetic aperture radar and perform envelope alignment processing on the echo data to obtain unfocused HRRP data; the unfocused HRRP data is stored in DDR4;

[0160] The translation compensation unit 702 is configured to read multiple channels of unfocused HRRP data from the DDR4 in parallel according to the azimuth direction, and perform translation compensation on the multiple channels of unfocused HRRP data using the current compensation phase value to obtain translation compensation data.

[0161] The calculation unit 703 is used to perform FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtain a two-dimensional result using the results of the FFT analysis and the logarithmic calculation;

[0162] A determination unit 704 is configured to determine whether an iteration stop condition is satisfied using the result of the FFT analysis;

[0163] The calculation unit 703 is further configured to perform FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result when the condition of the judgment unit is not met;

[0164] The calculation unit 703 is further configured to perform complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result;

[0165] The calculation unit 703 is further configured to perform phase calculation using the one-dimensional complex result to obtain a new compensated phase value;

[0166] The loop unit 705 is configured to use the new compensation phase value as the current compensation phase value in the translation compensation unit, repeatedly execute the steps from the translation compensation unit to the calculation unit until the conditions in the judgment unit are met, and perform FFT analysis on the translation compensation data from the most recent execution of the translation compensation unit steps to obtain an ISAR image after rapid imaging.

[0167] Figure 8 A structural diagram of an FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm provided in an embodiment of the present invention includes: a processor 810, a storage medium 820 and a bus 830, wherein the storage medium 820 stores machine-readable instructions executable by the processor 810. When the FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm is running, the processor 810 communicates with the storage medium 820 via the bus 830, and the processor 810 executes the machine-readable instructions to perform the steps of the above-mentioned method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0168] The storage medium may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the storage medium may be at least one storage device located away from the processor.

[0169] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0170] In the description of this specification, the reference terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0171] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the above-mentioned disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0172] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the scope of protection of the present invention.

Claims

1. A FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm, characterized in that: include: S101, acquiring echo data of an inverse synthetic aperture radar, and performing envelope alignment processing on the echo data to obtain unfocused HRRP data; The unfocused HRRP data is stored in DDR4; S102, reading multiple channels of unfocused HRRP data from the DDR4 in parallel according to azimuth, and performing translation compensation on the multiple channels of unfocused HRRP data using the current compensation phase value to obtain translation compensation data; S103, performing FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtaining a two-dimensional result by using the results of the FFT analysis and the logarithmic calculation; S104, using the result of the FFT analysis to determine whether an iteration stop condition is met; S105. When the condition in S104 is not satisfied, performing FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result; S106, performing complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result; S107, performing phase calculation using the one-dimensional complex result to obtain a new compensation phase value; S108: Use the new compensation phase value as the current compensation phase value in S102, repeatedly execute S102-S108 until the condition of S104 is satisfied, and perform FFT analysis on the translation compensation data during the most recent execution of S102 to obtain an ISAR image after rapid imaging.

2. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 1 is characterized in that, S102 includes: Reading multiple channels of the unfocused HRRP data in parallel from the DDR4 according to the azimuth direction; The current compensation phase value is multiplied in parallel with the multi-channel unfocused HRRP data to obtain the translation compensation data.

3. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 1 is characterized in that, S103 includes: The translation compensation data is input into a Fast Fourier Transform IP core for multi-channel parallel processing to perform FFT analysis to obtain a two-dimensional image; the two-dimensional image is the result of the FFT analysis; The two-dimensional image is input into the Cordic IP core to perform complex data modulus calculation to obtain the complex data modulus of the two-dimensional image; Calculate the logarithm value of the complex data modulus of the two-dimensional image using the Logarithm IP core to obtain the logarithm value of the two-dimensional image; performing an inversion operation on the highest bit of the imaginary part data of the two-dimensional image to obtain a complex conjugate value of the two-dimensional image; The complex data modulus value of the two-dimensional image and the complex conjugate value of the two-dimensional image are multiplied by the Mult IP core to obtain the two-dimensional result; the Fast Fourier Transform IP core, the Cordic IP core, the Logarithm IP core and the Mult IP core are all hardware modules in the FPGA.

4. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 3 is characterized in that, S104 includes: Calculating image entropy using the two-dimensional image to obtain current image entropy; Subtract the current image entropy from the previous image entropy to obtain an image entropy difference; the previous image entropy is the image entropy corresponding to the current image entropy at the previous iteration; Determining whether the image entropy difference is less than a preset threshold; When the image entropy difference is less than the preset threshold, the iteration stopping condition is met.

5. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 1 is characterized in that, S107 includes: Invert the most significant bit of the imaginary part of the one-dimensional complex number result to obtain a conjugate value of the one-dimensional complex number result; The Cordic IP core is used to calculate the modulus of the one-dimensional complex result; The Divder IP core is used to divide the conjugate value of the one-dimensional complex result by the modulus value of the one-dimensional complex result to obtain the new compensated phase value.

6. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 4 is characterized in that, The current image entropy is expressed as: E(K) represents the current image entropy value corresponding to the two-dimensional image K, m represents the m-th range direction, n represents the n-th azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, and D(n,m) represents the scattering intensity density of the two-dimensional image K in the n-th azimuth direction and the m-th range downward; K(n,m) represents the two-dimensional image element value corresponding to the n-th azimuth direction and the m-th distance downward of the two-dimensional image K, and s(K) represents the total energy of the two-dimensional image K; 7. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 1 is characterized in that, The one-dimensional complex result is expressed as: Among them, w(n) represents the value of all one-dimensional complex results corresponding to the nth azimuth direction, m represents the mth range direction, n represents the nth azimuth direction, M represents the total number of range directions, N represents the total number of azimuth directions, K(n,m) represents the two-dimensional image element value corresponding to the nth azimuth direction and the mth range direction, K * (n,m) represents the conjugate value of K(n,m), j represents an imaginary single number, and G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth direction and the mth distance downward.

8. The FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm according to claim 1 is characterized in that, The translation compensation data is expressed as: G′(n,m) represents the translation compensation data of the unfocused HRRP data in the nth azimuth and the mth distance downward, G(n) represents the unfocused HRRP data at all distances downward corresponding to the nth azimuth, represents the current compensation phase value at the nth azimuth downward, and j represents an imaginary odd number; G(n)=[G(n,1),G(n,2),…,G(n,M)] T ; T represents transposition processing, G(n,1) represents the unfocused HRRP data in the nth azimuth direction and the first distance downward, G(n,2) represents the unfocused HRRP data in the nth azimuth direction and the second distance downward, G(n,M) represents the unfocused HRRP data in the nth azimuth direction and the Mth distance downward, and exp(.) represents the exponential function.

9. An FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm, characterized in that: The FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm includes: an acquisition unit, a translation compensation unit, a calculation unit, a judgment unit and a circulation unit; The acquisition unit is used to acquire the echo data of the inverse synthetic aperture radar, and perform envelope alignment processing on the echo data to obtain unfocused HRRP data; the unfocused HRRP data is stored in the DDR4; The translation compensation unit is configured to read multiple channels of unfocused HRRP data from the DDR4 in parallel according to an azimuth direction, and perform translation compensation on the multiple channels of unfocused HRRP data using a current compensation phase value to obtain translation compensation data; The calculation unit is used to perform FFT analysis and logarithmic calculation on the translation compensation data in sequence, and obtain a two-dimensional result by using the results of the FFT analysis and the results of the logarithmic calculation; The judging unit is configured to judge whether an iteration stop condition is satisfied using the result of the FFT analysis; The calculation unit is further configured to perform FFT analysis on the two-dimensional result according to the azimuth direction to obtain a two-dimensional fast Fourier transform result when the condition of the judgment unit is not met; The calculation unit is further configured to perform complex multiplication and range summation on the translation compensation data and the two-dimensional fast Fourier transform result to obtain a one-dimensional complex result; The calculation unit is further configured to perform phase calculation using the one-dimensional complex number result to obtain a new compensated phase value; The loop unit is configured to use the new compensated phase value as the current compensated phase value in the translation compensation unit, repeatedly execute the steps from the translation compensation unit to the calculation unit until the condition in the judgment unit is satisfied, and perform FFT analysis on the translation compensation data from the most recent execution of the translation compensation unit steps to obtain an ISAR image after rapid imaging.

10. An FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the FPGA parallel acceleration implementation device based on the minimum entropy self-focusing algorithm is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of the FPGA parallel acceleration implementation method based on the minimum entropy self-focusing algorithm as described in any one of claims 1 to 8.

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