Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a display area and a non-display area and further comprises a driving circuit layer, a pixel electrode layer, an electronic paper film and a protection layer which are arranged on a substrate in a stacked mode, the driving circuit layer comprises a shifting register circuit arranged in the non-display area, and the pixel electrode layer comprises a pixel electrode layer, an electronic paper film and a protection layer. The pixel electrode layer comprises a plurality of pixel electrodes which are arranged in the display area in an array mode, the shifting register circuit comprises a plurality of thin film transistors and at least one storage capacitor, and the shifting register circuit further comprises a plurality of via holes penetrating from the pixel electrode layer to the driving circuit layer. The electronic paper film at least covers a part of the plurality of thin film transistors and the storage capacitor, the protective layer covers the plurality of via holes, and the orthographic projection of the plurality of via holes on the substrate is not overlapped with the orthographic projection of the electronic paper film on the substrate. According to the array substrate provided by the embodiment of the invention, the narrow frame design can be realized while the via hole corrosion is avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the rapid development of electronic paper display technology, high resolution, vivid colors, and narrow bezels have become the current development trend. However, current electronic paper display devices have a contradiction between the corrosion of peripheral circuit vias and the narrow bezel design. Summary of the Invention

[0003] In order to solve at least one of the above problems, the first aspect of the present disclosure provides an array substrate, comprising a display area and a non-display area, and further comprising: a driving circuit layer, a pixel electrode layer, an electronic paper film, and a protective layer stacked on a base substrate.

[0004] The driving circuit layer includes a shift register circuit arranged in the non-display area.

[0005] The pixel electrode layer includes a plurality of pixel electrodes arranged in an array in the display area.

[0006] The shift register circuit includes a plurality of thin film transistors and at least one storage capacitor. The shift register circuit also includes a plurality of via holes extending from the pixel electrode layer to the drive circuit layer.

[0007] The electronic paper film at least covers a portion of the multiple thin film transistors and the storage capacitor, the protective layer covers the multiple vias, and the orthographic projections of the multiple vias on the base substrate do not overlap with the orthographic projection of the electronic paper film on the base substrate.

[0008] Optionally, the pixel electrode layer further includes: a boundary portion provided in the non-display area and at least partially surrounding the display area,

[0009] The electronic paper film covers the border portion; and

[0010] An orthographic projection of the boundary portion on the base substrate does not overlap with an orthographic projection of the shift register circuit on the base substrate.

[0011] Optionally, the pixel electrode layer further includes: a boundary portion provided in the non-display area and at least partially surrounding the display area, the electronic paper film covers the boundary portion; and the boundary portion partially covers the shift register circuit.

[0012] Optionally, the shift register circuit includes: the shift register circuit includes: an output transistor for generating a scan signal, and the electronic paper film at least covers the output transistor and the storage capacitor.

[0013] Optionally, the shift register circuit further includes at least one reset transistor, which transmits a reset signal connected to a first electrode to a node electrically connected to a second electrode in response to a control signal connected to a control electrode of the reset transistor, where the node is the control electrode of the driving transistor or an output terminal corresponding to the second electrode.

[0014] The electronic paper film covers at least one thin film transistor in the at least one reset transistor.

[0015] Optionally, the distance between the orthographic projection of the via hole closest to the boundary of the electronic paper film on the base substrate and the orthographic projection of the electronic paper film on the base substrate is the first distance,

[0016] The distance between the orthographic projection of the via hole closest to the boundary of the protective layer on the base substrate and the orthographic projection of the protective layer on the base substrate is the second distance.

[0017] Each of the first distance and the second distance is greater than or equal to 200 μm and less than or equal to 500 μm.

[0018] Optionally, the driving circuit layer includes: a gate layer, a source / drain metal layer, and a passivation layer sequentially stacked on a substrate.

[0019] The via hole penetrates from the pixel electrode layer to the source-drain metal layer, or the via hole penetrates from the pixel electrode layer to the gate layer through the source-drain metal layer.

[0020] Optionally, the method further includes: a light shielding layer, which covers the via hole and covers the electronic paper layer and the side wall of the protective layer.

[0021] A second aspect of the present disclosure provides a display panel, comprising the array substrate as described above.

[0022] A third aspect of the present disclosure provides a display device, comprising the display panel as described above.

[0023] The beneficial effects of the present disclosure are as follows:

[0024] In response to the current problems, the present disclosure develops an array substrate, a display panel, and a display device. By disposing a portion of the multiple thin-film transistors of the shift register circuit under the electronic paper film, and placing the vias in the shift register circuit only under the protective layer and not overlapping with the electronic paper film, a narrow-frame design can be achieved while avoiding via corrosion, thereby improving the competitiveness of display products, reducing product costs, and having broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure is shown;

[0027] Figure 2 A schematic top view of an array substrate according to an embodiment of the present disclosure is shown;

[0028] Figure 3 An exemplary shift register circuit in an array substrate according to an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic cross-sectional view showing a via region of a shift register circuit in an array substrate according to an embodiment of the present disclosure;

[0030] Figure 5 A schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure is shown;

[0031] Figure 6 A schematic top view of an array substrate according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] To more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be used to limit the scope of protection of the present disclosure.

[0033] It should be noted that the terms “having”, “including”, “comprising”, etc. described in the present disclosure are all open-ended, that is, when describing a module as “having”, “including” or “comprising” a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. In addition, ordinal numbers such as “first”, “second” and “third” in the present disclosure are not intended to limit a specific order, but are only used to distinguish between various parts. In the present disclosure, when describing layer A and layer B as “set on the same layer”, it means that layer A and layer B are made of the same material and the same process.

[0034] The inventors have found that, at present, electronic paper display panels generally adopt a 4-mask or 5-mask process. The 4-mask process generally includes: a gate layer mask (Gate Mask) process, an active layer mask (HTM Gate) process, a passivation layer mask (PVX Mask) process, and a pixel electrode mask (ITO Mask) process. The 5-mask process generally includes: a gate layer mask (Gate Mask) process, an active layer mask (HTM Gate) process, a passivation layer mask (PVX Mask) process, an organic layer mask (ORG Mask) process, and a pixel electrode mask (ITO Mask) process. Therefore, the electronic paper display panel needs to use PVX Mask to form a via through which the pixel electrode layer passes through the gate layer and / or the source and drain metal layer to realize the electrical connection between the gate layer and the source and drain metal layer. In other words, for the manufacturing process of the electronic paper display panel, due to the existence of such a via, after the pixel electrode layer is formed, there will be a connection path from the pixel electrode layer to the underlying gate layer and / or source and drain metal layer. Because the electronic paper layer is located above the pixel electrodes in the electronic paper display panel, and the electronic paper layer only partially covers the non-display area, and a protective layer (PS) is included above the electronic paper layer, and the protective layer is also a certain distance away from the edge of the non-display area, when the paper film of the electronic paper layer leaks, its edge will serve as a leakage channel, and the edge of the protective layer is at risk of water vapor intrusion. Therefore, these vias in the gate drive circuit (GOA) located in the non-display area are at risk of corrosion from leakage of the paper film of the electronic paper layer and water vapor intrusion at the edge of the PS layer. However, if the GOA vias are moved away from the easily corroded edges to avoid these risks, the frame size will increase.

[0035] Therefore, in electronic paper display devices, the narrow frame design is always in conflict with the stability of the GOA circuit.

[0036] In view of this, an embodiment of the present disclosure provides an array substrate, comprising a display area and a non-display area, and further comprising: a driving circuit layer, a pixel electrode layer, an electronic paper film, and a protective layer stacked on a base substrate.

[0037] The driving circuit layer includes a shift register circuit arranged in the non-display area.

[0038] The pixel electrode layer includes a plurality of pixel electrodes arranged in an array in the display area.

[0039] The shift register circuit includes a plurality of thin film transistors and at least one storage capacitor. The shift register circuit also includes a plurality of via holes extending from the pixel electrode layer to the drive circuit layer.

[0040] The electronic paper film at least covers a portion of the multiple thin film transistors and the storage capacitor, the protective layer covers the multiple vias, and the orthographic projections of the multiple vias on the base substrate do not overlap with the orthographic projection of the electronic paper film on the base substrate.

[0041] In this embodiment, by setting a portion of the multiple thin-film transistors of the shift register circuit under the electronic paper film, and the vias in the shift register circuit are only placed under the protective layer and do not overlap with the electronic paper film, a narrow frame design can be achieved while avoiding via corrosion, thereby improving the competitiveness of the display product and reducing product costs.

[0042] The following combination Figures 1 to 3 The structure and function of an array substrate of a specific example are described. Figure 1 A schematic cross-sectional view showing a portion of the non-display area NA in the array substrate is shown. Figure 2 A partial top view of the array substrate is shown.

[0043] Reference Figure 1 and Figure 2 As shown, the array substrate includes a display area AA and a non-display area NA arranged around the display area AA. The non-display area NA can be arranged around the display area AA. The array substrate also includes: a driving circuit layer 101, a pixel electrode layer, an electronic paper film 105 and a protective layer 107 stacked in sequence on a base substrate 100. Figure 1 The driving circuit layer 101 is framed by thick solid lines, and each pattern block is used to represent a different area in the driving circuit layer 101.

[0044] In this example, the driving circuit layer 101 includes four shift register circuits G1, G2, G3 and G4 disposed in the non-display area NA. The four cascaded shift register circuits G1, G2, G3 and G4 constitute a set of gate driving circuits.

[0045] It should be noted that those skilled in the art should understand that the number of shift register circuits included in the gate drive circuit is only exemplary, and the present disclosure is not intended to limit the number thereof. The number of cascaded shift register circuits is determined according to specific design requirements. Figure 2 In the embodiment, only one set of gate drive circuits is included between the display area AA side and the edge of the array substrate side, but the present disclosure is not limited to this. The number of gate drive circuit sets is determined according to specific needs. It is understood that the total number of gate drive circuit sets depends on the number of transistors that need to be scanned in the pixel drive circuit that drives each pixel, whether each shift register circuit in the gate drive circuit corresponds to a pixel drive circuit for pixels in adjacent rows or a pixel drive circuit for pixels in one or more rows, etc. In short, the present disclosure is not intended to limit the specific number of shift register circuits, how to cascade them, or how many gate drive circuit sets are formed.

[0046] Continue to refer to Figure 1 and Figure 2As shown, the pixel electrode layer includes pixel electrodes arranged in an array in the display area AA, and a boundary portion 113 disposed in the non-display area NA and at least partially surrounding the display area AA. The pixel electrodes Pixel are used to define pixel points in the array substrate. The pixel electrodes Pixel receive a potential corresponding to a data signal based on the conduction of a transistor in a pixel driving circuit to which they are electrically connected, thereby changing the position of particles in the electronic paper film 105 corresponding to the pixel electrodes Pixel, thereby affecting the display effect of that area.

[0047] The electronic paper film 105 can be, for example, an electrophoretic electronic paper film, an electrowetting electronic paper film, a cholesterol electronic paper film, an electronic powder flow electronic paper film, etc. Taking the electrophoretic electronic paper film as an example, the electrophoretic electronic paper includes charged particles and an electrophoretic medium. When the electronic paper film is a black and white display electronic paper, the charged particles are white particles and black particles. Under the action of the electric field of the pixel electrode, if the white particles face the light-emitting surface of the array substrate, the pixel displays white, and if the black particles face the light-emitting surface of the array substrate, the pixel displays black. If the electronic paper film is a color display electronic paper, the charged particles can present different colors, which will not be elaborated here. In addition, it can be understood that the display principles of electronic paper films made of other materials are similar, and they are all film layers in which the pixels present different display states under the action of the electric field, which will not be elaborated here.

[0048] The protective layer 107 can be a wear-resistant transparent material, such as acrylic, which is used to protect the electronic paper film underneath to prevent the electronic paper film from being scratched, worn, or other physical damage, and to optimize the surface optical properties, such as reducing reflections, to better simulate the paper reading experience.

[0049] Reference Figure 1 and Figure 2 As shown, the electronic paper film 105 covers the display area AA, and its boundary extends beyond the display area AA. The protective layer 107 covers the electronic paper film 105. A boundary portion 113 surrounds the display area AA to provide support for the electronic paper film 105 and improve the height uniformity of the film layer below the electronic paper film 105. Of course, the boundary portion 113 is not limited to this and can also partially surround the display area, which will not be detailed here.

[0050] In particular, in an embodiment of the present disclosure, the shift register circuit includes multiple thin film transistors and at least one storage capacitor, the shift register circuit also includes multiple vias passing from the pixel electrode layer to the driving circuit layer, the electronic paper film 105 covers at least a portion of the multiple thin film transistors and the storage capacitor, the protective layer covers the multiple vias, and the orthographic projections of the multiple vias on the base substrate do not overlap with the orthographic projections of the electronic paper film on the base substrate.

[0051] Specifically for this example, Figure 3FIG. 1 is a circuit diagram showing an exemplary shift register circuit. Figure 3 As shown, the shift register circuit has an 8T1C circuit structure, that is, 8 thin film transistors and 1 storage capacitor. In this example, the thin film transistor is a P-type transistor. When the control electrode of the thin film transistor is connected to a high-level signal, it is turned on. Therefore, the effective level value in the following text is the high-level signal.

[0052] Specifically, refer to Figure 3 As shown, the shift register circuit includes: a first transistor M1 as an input transistor, a second transistor M2 and an eighth transistor M8 as reset transistors, a third transistor M3 as an output transistor, a fourth transistor M4 as a pull-up control transistor, a fifth transistor M5 as a pull-down transistor, and a sixth transistor M6 and a seventh transistor M7 as noise reduction transistors.

[0053] The first transistor M1 has a first electrode and a control electrode electrically connected to the input terminal Input, and a second electrode electrically connected to the pull-up node PU, and is configured to transmit an input signal to the pull-up node PU based on a signal connected to the input terminal Input.

[0054] The second transistor M2 has a first electrode electrically connected to the pull-up node PU, a second electrode electrically connected to the first power signal terminal LVGL, and a control electrode electrically connected to the first reset control terminal RESET-PU. When the first reset control terminal RESET-PU receives a signal at an active level, the second transistor M2 turns on, transmitting a low-level reset signal corresponding to the first power signal terminal LVGL to the pull-up node PU, thereby resetting the pull-up node PU. Optionally, in a cascade connection, the first reset control terminal RESET-PU can be electrically connected to the output terminal of the next-stage shift register circuit. In this case, the second transistor M2 functions as a local reset transistor.

[0055] The fourth transistor M4 has a first electrode electrically connected to the pull-up node PU, a second electrode electrically connected to the first power signal terminal LVGL, and a control electrode electrically connected to the second reset control terminal T-RST. When the second reset control terminal T-RST receives a signal at an active level, the fourth transistor M4 turns on, transmitting a low-level reset signal corresponding to the first power signal terminal LVGL to the pull-up node PU, thereby resetting the pull-up node PU. Optionally, the second reset control terminal T-RST can receive a global reset control signal, in which case the fourth transistor M4 functions as a global reset transistor.

[0056] The third transistor M3 and the storage capacitor C constitute the output subcircuit of the shift register circuit. Specifically, the first electrode of the third transistor M3 is electrically connected to the clock signal terminal CLK, the second electrode is electrically connected to the output terminal Output, and the control electrode is electrically connected to the pull-up node PU. The first electrode of the storage capacitor C is electrically connected to the clock signal terminal CLK, and the second electrode is electrically connected to the output terminal Output. When the pull-up node PU is at a high level, the third transistor M3 is turned on. If the clock signal terminal CLK is at a low level at this time, the output terminal Output outputs a low-level signal. The high-level pull-up node PU simultaneously charges the storage capacitor C. At the same time, the bootstrap coupling function of the storage capacitor C is utilized to keep the third transistor M3 turned on until the clock signal terminal CLK is at a high level, so that the output terminal Output outputs a high-level scanning signal.

[0057] The first electrode and the control electrode of the fourth transistor M4 are electrically connected to the second power signal terminal VDD1, and the second electrode is electrically connected to the pull-down node PD. It is configured to transmit the high level of the second power signal terminal VDD1 to the pull-down node PD based on the high level of the signal of the second power signal terminal VDD1.

[0058] The first electrode of the fifth transistor M4 is electrically connected to the pull-down node PD, the second electrode is electrically connected to the first power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU. When the potential of the pull-up node PU is at a high level, the fifth transistor M5 is turned on, electrically connecting the first power signal terminal LVGL to the pull-down node PD, thereby utilizing the low potential signal of the first power signal terminal LVGL to pull down the potential of the pull-down node PD.

[0059] The first electrode of the sixth transistor M6 is electrically connected to the pull-up node PU, the second electrode is electrically connected to the first power signal terminal LVGL, and the control electrode is electrically connected to the pull-down node PD. When the pull-down node PD is at a high level, the sixth transistor M6 is turned on, electrically connecting the first power signal terminal LVGL to the pull-up node PU, and using the low-level signal of the first power signal terminal LVGL to reduce the noise of the pull-up node PU.

[0060] The first electrode of the seventh transistor M7 is electrically connected to the output terminal Output, the second electrode is electrically connected to the third power signal terminal VGL, and the control electrode is electrically connected to the pull-down node PD. When the pull-down node PD is at a high level, the seventh transistor M7 is turned on, electrically connecting the third power signal terminal VGL to the output terminal Output, and using the low-level signal of the third power signal terminal VGL to reduce noise at the output terminal Output.

[0061] It should be understood that Figure 3The circuit structure is only an example of an 8T1C shift register circuit and is not intended to be limiting. For example, the first electrode and the control electrode of the first transistor M1 serving as an input transistor can be electrically connected to different signal ports, respectively, and the first electrode and the control electrode of the fourth transistor M4 serving as a pull-up control transistor can also be electrically connected to different signal ports, respectively. As long as the input transistor can control the first transistor M1 to be turned on and transmit the high-level input signal to the pull-up node PU, and the pull-up control transistor can control the fourth transistor M4 to be turned on and use the high-level signal to raise the level of the pull-down node PD, it will be sufficient.

[0062] It should be noted that, except Figure 3 In addition to the examples shown, the shift register circuit may include various combinations of transistors and capacitors. For example, there are structures such as 4T1C (four transistors and one storage capacitor), 11T1C (eleven transistors and one storage capacitor), 18T1C (eighteen transistors and one storage capacitor), and 9T2C (nine transistors and two storage capacitors). The number of transistors included in the shift register circuit depends on the circuit form. It should be understood that regardless of the structure of the shift register circuit, it at least includes a thin film transistor as an output transistor and at least one storage capacitor, and further includes at least one reset transistor for resetting the node corresponding to the control electrode of the output transistor.

[0063] The inventors have found through research that, regardless of the structure of the shift register circuit, the thin film transistor used as the output transistor has the largest size, and the space occupied by the plate of the storage capacitor in the circuit is also relatively large.

[0064] Combine Figure 1 and Figure 2 As shown, in an embodiment of the present disclosure, the area BB1 below the electronic paper film 105 that is not covered by the boundary portion 101 is used to set at least a portion of the thin film transistor and the storage capacitor in the shift register circuit, and at the same time, the via hole that passes from the pixel electrode layer to the driving circuit layer in the shift register circuit is set in the area BB2 below the protective layer 107 and does not overlap with the electronic paper film 105, wherein the electronic paper film 105 covers the area BB1, the protective layer 107 covers the area BB2, and the orthographic projection of the area BB2 on the base substrate 100 does not overlap with the orthographic projection of the electronic paper film 105 on the base substrate 100.

[0065] With this arrangement, the width of the frame can be narrowed while protecting the via hole from corrosion defects.

[0066] Optionally, the electronic paper film 105 covers at least the output transistor and the storage capacitor in the shift register circuit, wherein the output transistor is a thin film transistor that generates a scan signal.

[0067] Specific to Figure 1 and Figure 2 In the example shown in FIG. 1 , the orthographic projection of boundary portion 113 on base substrate 100 does not overlap with the orthographic projection of the shift register circuit on base substrate 100. In other words, the orthographic projection of boundary portion 113 on base substrate 100 does not overlap with the orthographic projection of region BB1 on base substrate 100, where the storage capacitors and at least some thin-film transistors of the shift register circuit are located. Multiple redundant transistors may be provided in the portion of drive circuit layer 101 below boundary portion 113 to improve the height uniformity of electronic paper film 105 and thus display uniformity. Alternatively, boundary portion 113 may be generally referred to as a "border region."

[0068] by Figure 3 Taking the example shown as an example, the output transistor is the third transistor M3, and the storage capacitor is the storage capacitor C electrically connected between the pull-up node PU and the output terminal Output.

[0069] At the same time, the via hole that passes through from the pixel electrode layer to the driving circuit layer is placed in area BB2, and the edge of the orthographic projection of the area BB2 on the base substrate 100 close to the electronic paper film 105 has a first predetermined distance from the boundary of the orthographic projection of the electronic paper film 105 on the base substrate 100, and the edge of the orthographic projection of the area BB2 on the base substrate 100 close to the protective layer 107 has a second predetermined distance from the boundary of the orthographic projection of the protective layer 107 on the base substrate 100.

[0070] Specifically, the driving circuit layer includes: a gate layer, a source-drain metal layer and a passivation layer stacked in sequence on the base substrate, and the via hole passes through from the pixel electrode layer to the source-drain metal layer, or the via hole passes through from the pixel electrode layer to the gate layer via the source-drain metal layer.

[0071] Reference Figure 4 As shown, exemplarily, the driving circuit layer 101 includes: a gate layer 111, a gate insulating layer 121, an active layer 131, a source-drain metal layer 141 and a passivation layer 151 sequentially stacked on the base substrate 100, and a pixel electrode layer 103 is provided on the driving circuit layer 101. Figure 4It can be seen that the source-drain metal layer realizes the electrical connection between the source-drain metal layer 141 and the gate layer 111 via the via that passes through from the pixel electrode layer 103 to the gate layer 111. Specifically in this example, based on the manufacturing process, two vias can be formed through a passivation layer mask (PVX Mask). The first via stops when encountering the source-drain metal layer during the etching of the passivation layer 151, forming a via that passes through the source-drain metal layer 141. The second via stops when etching the passivation layer 151 until it reaches the gate layer 111, forming a via that passes through the gate layer 111. In this way, the source-drain metal layer 141 and the gate layer 111 can be electrically connected with the pixel definition layer that covers the two vias at the same time. In the embodiment of the present disclosure, Figure 4 The two vias for forming the source / drain metal layer 141 to the gate layer 111 are both arranged in the region BB2.

[0072] It should be noted that the figure only illustrates the electrical connection relationship using via layer replacement using the bottom-gate structure's driver circuit layer as an example, and is not intended to be limiting. The driver circuit layer relationship of the top-gate structure is also protected by this disclosure. In this article, the bottom-gate structure means the gate layer is below the active layer, and the top-gate structure means the gate layer is below the active layer. This article does not elaborate on this.

[0073] That is, the vias in the embodiments of the present disclosure are formed by patterning the passivation layer, extending from the pixel electrode layer through the source / drain metal layer to the gate layer, or vice versa. The vias may be used to form electrical connections between thin-film transistors in a shift register circuit, or may be used to form electrical connections between a thin-film transistor and a signal connection line or signal line.

[0074] It should also be noted that, in the embodiments of the present disclosure, the via holes forming electrical connections between the conductive film layers are not limited to Figure 4 The connection between the source-drain metal layer and the gate layer shown, for example, when the driving circuit layer includes multiple source-drain metal layers and electrical connections between the multiple source-drain metal layers are required, vias penetrating from the pixel definition layer to the source-drain metal layer are also required to complete the electrical connection with the pixel electrode layer, and these vias should also be protected by the embodiments of the present disclosure. That is, in the embodiments of the present disclosure, electrical connections between the corresponding structures of the gate layer and the source-drain metal layer are achieved through vias penetrating from the pixel electrode layer through the source-drain metal layer to the gate layer, and electrical connections between corresponding structures located in different source-drain metal layers can be formed through vias penetrating from the pixel electrode layer through the source-drain metal layer.

[0075] This arrangement optimizes the arrangement of transistors in the shift register circuit, placing at least the larger output transistors and storage capacitors in the shift register circuit below the electronic paper film 105. This reduces the width of the space occupied by the shift register circuit between the boundary of the orthographic projection of the electronic paper film 105 on the base substrate 100 and the boundary of the orthographic projection of the protective layer 107 on the base substrate 100, thereby facilitating a narrow-frame design. Furthermore, while relocating at least a portion of the components in the shift register circuit below the electronic paper film 105, the vias in the shift register circuit are retained in area BB2. This allows the space below the electronic paper film 105 to be used to reduce the frame size while ensuring that vias that have experienced leakage and water vapor corrosion remain within the protection range from the edge of the electronic paper film 105 to the protective layer 107, thereby achieving a narrow-frame design and display stability for the electronic paper display product.

[0076] It should be noted that in the embodiment of the present disclosure, the edge of the region BB2 is defined by the via hole closest to the edge of the electronic paper film 105 and the via hole closest to the edge of the protective layer 107 among the plurality of via holes.

[0077] Optionally, refer to Figure 1 and Figure 2 As shown, the distance between the orthographic projection of the via hole closest to the boundary of the electronic paper film 105 on the base substrate and the orthographic projection of the electronic paper film 105 on the base substrate 100 is a first distance W1, and the distance between the orthographic projection of the via hole closest to the boundary of the protective layer 107 on the base substrate 100 and the orthographic projection of the protective layer 107 on the base substrate 100 is a second distance W2, and each of the first distance W1 and the second distance W2 is greater than or equal to 200 μm and less than or equal to 500 μm.

[0078] This arrangement ensures that the via is sufficiently far away from the edge of the protective layer 107 and also sufficiently far away from the edge of the electronic paper film 105, thereby preventing water vapor that may penetrate along the edge interface of the protective layer 107 from corroding the via, and at the same time preventing liquid leakage from the electronic paper film 105 from entering and corroding the via.

[0079] Optionally, the electronic paper film 105 also covers at least one thin film transistor in the at least one reset transistor. Figure 3 Taking the circuit shown as an example, the shift register circuit includes two reset transistors, one of which is a second transistor M2 and the other is an eighth transistor M8. To increase the reset rate, the second transistor M2 and the eighth transistor M8, which serve as reset transistors, are also larger in size. If space in area BB1 permits, placing at least one of the second transistor M2 and the eighth transistor M8 in area BB1 can further reduce the border width and achieve a narrower border design.

[0080] Of course, those skilled in the art will understand that the reset transistor defined in the embodiment of the present disclosure is not limited to Figure 3 Although the structure shown in FIG. 1 is different from the structure shown in FIG. 2 , it should be understood that the reset transistor in the shift register circuit should generally include at least a thin film transistor for resetting the node corresponding to the control electrode of the output transistor for outputting the scan signal or a thin film transistor for resetting the output end corresponding to the second electrode of the output transistor.

[0081] In addition, although not listed here, if the space in area BB1 is sufficient, larger transistors in addition to the above-mentioned thin film transistors in the shift register circuit can also be placed in area BB1, thereby further optimizing the narrow frame design.

[0082] Optionally, refer to Figure 1 The array substrate further includes a light shielding layer 108, which covers the via hole and the sidewalls of the electronic paper layer 105 and the protective layer 107 to prevent ambient light from entering the array substrate. Figure 1 As shown, the array substrate may further include an edge region 109 , which serves as a frame region for defining each functional layer in the array substrate and protecting each internal film layer.

[0083] In another optional embodiment, considering that the driving circuit layer 101 below the boundary portion 113 is usually used to set up redundant transistors, it can further provide layout space for devices in the shift register circuit. Figure 5 and Figure 6 As shown in the figure, compared with Figure 1 and Figure 2 The embodiment shown further implements an array substrate structure with a narrow frame design.

[0084] Reference Figure 5 and Figure 6 As shown, the difference from the above embodiment is that the placement area of the shift register circuit components below the electronic paper film 105 is further extended inward to overlap with the boundary portion 113 .

[0085] Specifically, the shift register circuit includes multiple thin film transistors and at least one storage capacitor. The shift register circuit also includes multiple vias that pass through the pixel electrode layer to the driving circuit layer. The electronic paper film 105 covers at least a portion of the multiple thin film transistors and the storage capacitor. The boundary portion 113 surrounding the display area AA partially covers the shift register circuit. The protective layer covers the multiple vias. The orthographic projections of the multiple vias on the base substrate do not overlap with the orthographic projections of the electronic paper film on the base substrate.

[0086] Specifically, a portion of the plurality of thin film transistors included in the shift register circuit and a storage capacitor in the shift register circuit are disposed in region BB1'. The orthographic projection of region BB1' on base substrate 100 overlaps with the orthographic projection of boundary portion 113 on base substrate 100, and the orthographic projection of electronic paper film 105 on base substrate 100 overlaps the orthographic projection of region BB1' on base substrate 100.

[0087] Optionally, still with Figure 3 Taking the shift register circuit shown as an example, at least the third transistor M3 as the output transistor and the storage capacitor C3 are arranged in the region BB1'. Optionally, if space permits, at least one of the second transistor M2 as the reset transistor and the eighth transistor M8 is also arranged in the region BB1'.

[0088] Under the same conditions, because the area below the electronic paper film 105 in this embodiment is smaller than that below the electronic paper film 105, Figure 1 and Figure 2 In the embodiment shown, the area BB1 has a larger space, allowing more devices to be arranged in the area BB1 ′. In other words, the frame size is further reduced through this embodiment.

[0089] It should be noted that, because a plurality of thin-film transistors are usually required to be arranged in the driving circuit layer below the boundary portion 113 as redundant transistors to improve the height and uniformity of the electronic paper film, the space below it is used to arrange the thin-film transistors and / or storage capacitors in the shift register circuit, providing more arrangement space for the shift register circuit. At the same time, this part of the device in the shift register circuit can replace the role of the redundant transistor, and also provide height and uniformity support for the electronic paper film above.

[0090] Please note that reference Figure 5 and Figure 6 As shown, in this embodiment, except for the partial structure of region BB1', the arrangement of other regions remains unchanged from the previous embodiment. Specifically, the other thin-film transistors in the shift register circuit are arranged below the region where the protective layer 107 and the electronic paper film 105 do not overlap, while the vias of the shift register circuit are arranged in region BB2. The definition and location of region BB2 are consistent with the previous embodiment.

[0091] That is, the via hole that passes through from the pixel electrode layer to the driving circuit layer is placed in area BB2, and the edge of the orthographic projection of the area BB2 on the base substrate 100 close to the electronic paper film 105 has a first predetermined distance from the boundary of the orthographic projection of the electronic paper film 105 on the base substrate 100, and the edge of the orthographic projection of the area BB2 on the base substrate 100 close to the protective layer 107 has a second predetermined distance from the boundary of the orthographic projection of the protective layer 107 on the base substrate 100.

[0092] Optionally, refer to Figure 1 and Figure 2 As shown, the distance between the orthographic projection of the via hole closest to the boundary of the electronic paper film 105 on the base substrate and the orthographic projection of the electronic paper film 105 on the base substrate 100 is a first distance W1, and the distance between the orthographic projection of the via hole closest to the boundary of the protective layer 107 on the base substrate 100 and the orthographic projection of the protective layer 107 on the base substrate 100 is a second distance W2, and each of the first distance W1 and the second distance W2 is greater than or equal to 200 μm and less than or equal to 500 μm.

[0093] Through this setting, while reducing the size of the frame, the space below the electronic paper film 105 can be used to reduce the size of the frame, while ensuring that the vias that have leaked and been corroded by water vapor are still located within the protection range from the edge of the electronic paper film 105 to the protective layer 107, thereby achieving a narrow frame design and display stability of the electronic paper display product.

[0094] This arrangement ensures that the via is sufficiently far away from the edge of the protective layer 107 and also sufficiently far away from the edge of the electronic paper film 105, thereby preventing water vapor that may penetrate along the edge interface of the protective layer 107 from corroding the via, and at the same time preventing liquid leakage from the electronic paper film 105 from entering and corroding the via.

[0095] Based on the same inventive concept, embodiments of the present disclosure further provide a display panel comprising the array substrate described in the above embodiments. Since the array substrate included in the display panel provided in the embodiments of the present disclosure corresponds to the array substrate provided in the above embodiments, the above embodiments also apply to the display panel provided in the present embodiment and will not be described in detail in this embodiment.

[0096] By providing an array substrate including the above embodiments, the display panel can achieve an extremely narrow bezel of the electron-to-display panel while having extremely high display stability. During the production process of the display panel, more panels can be produced within a substrate of the same size, thereby reducing production costs and increasing product revenue.

[0097] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising the display panel described in the above embodiments. Since the display panel included in the display device provided in the embodiments of the present disclosure corresponds to the display panel provided in the above embodiments, the above embodiments also apply to the display device provided in this embodiment and will not be described in detail in this embodiment.

[0098] In this embodiment, the display device can be any product or component with a display function, such as an in-vehicle display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. When used in a display device, the above-described display panel can significantly improve display issues caused by large bezels or via corrosion, thereby enhancing the user experience. Furthermore, the display device can reduce production costs and increase product revenue.

[0099] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solutions of the present disclosure are still within the scope of protection of the present disclosure.

Claims

1. An array substrate, characterized in that: It includes a display area and a non-display area, and also includes: a driving circuit layer, a pixel electrode layer, an electronic paper film and a protective layer stacked on a base substrate. The driving circuit layer includes a shift register circuit arranged in the non-display area. The pixel electrode layer includes a plurality of pixel electrodes arranged in an array in the display area. The shift register circuit includes a plurality of thin film transistors and at least one storage capacitor, and the shift register circuit also includes a plurality of via holes penetrating from the pixel electrode layer to the drive circuit layer. The electronic paper film covers at least a portion of the multiple thin film transistors and the storage capacitor, the protective layer covers the multiple vias, and the orthographic projections of the multiple vias on the base substrate do not overlap with the orthographic projection of the electronic paper film on the base substrate.

2. The array substrate according to claim 1, wherein: The pixel electrode layer further includes a boundary portion disposed in the non-display area and at least partially surrounding the display area. The electronic paper film covers the boundary portion; and An orthographic projection of the boundary portion on the base substrate does not overlap with an orthographic projection of the shift register circuit on the base substrate.

3. The array substrate according to claim 1, wherein: The pixel electrode layer further includes a boundary portion disposed in the non-display area and at least partially surrounding the display area. The electronic paper film covers the boundary portion; and The boundary portion partially covers the shift register circuit.

4. The array substrate according to claim 1, wherein: The shift register circuit includes: an output transistor for generating a scan signal, The electronic paper film at least covers the output transistor and the storage capacitor.

5. The array substrate according to claim 4, wherein: The shift register circuit further includes at least one reset transistor, The reset transistor transmits the reset signal connected to the first electrode to the node electrically connected to the second electrode in response to the control signal connected to the control electrode of the drive transistor, and the node is the output terminal corresponding to the control electrode or the second electrode of the drive transistor. The electronic paper film covers at least one thin film transistor in the at least one reset transistor.

6. The array substrate according to claim 1, wherein: The distance between the orthographic projection of the via hole closest to the boundary of the electronic paper film on the base substrate and the orthographic projection of the electronic paper film on the base substrate is a first distance, The distance between the orthographic projection of the via hole closest to the boundary of the protective layer on the base substrate and the orthographic projection of the protective layer on the base substrate is the second distance, Each of the first distance and the second distance is greater than or equal to 200 μm and less than or equal to 500 μm.

7. The array substrate according to claim 1, wherein: The driving circuit layer includes: a gate layer, a source / drain metal layer, and a passivation layer stacked in sequence on a base substrate. The via hole passes through from the pixel electrode layer to the source-drain metal layer, or the via hole passes through from the pixel electrode layer to the gate layer via the source-drain metal layer.

8. The array substrate according to claim 1, wherein: Also includes: A light shielding layer covers the via hole and covers the electronic paper layer and the side wall of the protective layer.

9. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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