Controller, control method and electronic equipment

Abstract

The invention provides a controller, a control method and electronic equipment, and relates to the technical field of circuits. The controller includes: an error amplification circuit configured to output, to a target node, an Nth error amplified signal between a reference signal and an Nth feedback signal from a power cell, the Nth feedback signal corresponding to an output voltage at an Nth time of the power cell, N being an integer greater than or equal to 1, based on a predetermined amplification gain; a signal comparison circuit configured to determine an Nth comparison signal based on a reference signal and an Nth feedback signal; the logic control circuit is configured to generate an Nth compensation control signal based on the Nth moment voltage and the Nth comparison signal of the target node, and control the output voltage of the power unit at the (N + 1) th moment based on the (N + 1) th moment voltage and the Nth comparison signal of the target node; and the compensation circuit is configured to compensate the voltage at the Nth moment under the control of the Nth compensation control signal to obtain the voltage at the (N + 1) th moment.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and more particularly, to a controller, a control method, and an electronic device. Background Art

[0002] Line / load transient response is a key parameter of a power supply. When the connected load experiences a transient change, typical power supplies have poor dynamic response capabilities, resulting in a long response time and difficulty in quickly adjusting the output voltage until it stabilizes. Summary of the Invention

[0003] In view of this, the present disclosure provides a controller, a control method, and an electronic device.

[0004] According to one aspect of the present disclosure, a controller is provided, including: an error amplification circuit, configured to output an Nth error amplified signal between a reference signal and an Nth feedback signal from a power unit to a target node based on a predetermined amplification gain, the Nth feedback signal corresponding to the output voltage of the power unit at the Nth moment, where N is an integer greater than or equal to 1; a signal comparison circuit, configured to determine an Nth comparison signal based on the reference signal and the Nth feedback signal; a logic control circuit, configured to generate an Nth compensation control signal based on the voltage of the target node at the Nth moment and the Nth comparison signal, and to control the output voltage of the power unit at the N+1th moment based on the voltage of the target node at the N+1th moment and the Nth comparison signal; and a compensation circuit, configured to compensate for the voltage at the Nth moment under the control of the Nth compensation control signal to obtain the voltage at the N+1th moment.

[0005] According to an embodiment of the present disclosure, the logic control circuit is further configured to: sample the voltage at the Nth moment and the voltage at the N+1th moment respectively to obtain an Nth sampling signal and an N+1th sampling signal; generate an Nth compensation control signal based on the Nth sampling signal and the Nth comparison signal;

[0006] Based on the (N+1)th sampling signal and the (N)th comparison signal, the (N+1)th voltage control signal is output to the power unit to control the output voltage of the power unit at the (N+1)th moment.

[0007] According to an embodiment of the present disclosure, a logic control circuit includes: a first sub-circuit, configured to generate an N-th node voltage indication signal based on an N-th sampling signal and an N-th output indication signal, and to generate an N-th compensation control signal based on the N-th node voltage indication signal and an N-th comparison signal; wherein the N-th output indication signal indicates the state of the output voltage at the N-th moment, and the N-th node voltage indication signal indicates the state of the voltage at the N-th moment; a second sub-circuit, configured to generate an N-th update signal based on the N-th node voltage indication signal and the N-th comparison signal; and a third sub-circuit, configured to update the N-th output indication signal based on the N-th update signal and the N-th comparison signal to generate an N+1-th output indication signal, and to generate an N+1-th voltage control signal based on the N+1-th output indication signal and the N+1-th sampling signal, wherein the N+1-th output indication signal indicates the state of the output voltage at the N+1-th moment.

[0008] According to an embodiment of the present disclosure, the first sub-circuit includes a first trigger unit and a second trigger unit; the first trigger unit is configured to generate an Nth trigger signal in response to a signal edge that triggers an Nth sampling signal; the second trigger unit is configured to generate an Nth node voltage indication signal based on the Nth trigger signal and the Nth output indication signal.

[0009] According to an embodiment of the present disclosure, the first trigger unit is further configured to sample the first level signal in response to triggering the signal edge of the Nth sampling signal to obtain the Nth trigger signal; the second trigger unit is further configured to obtain the Nth node voltage indication signal based on the Nth output indication signal in response to triggering the Nth trigger signal.

[0010] According to an embodiment of the present disclosure, the first sub-circuit is further configured to calculate the Nth node voltage indication signal and the Nth comparison signal to obtain the Nth compensation control signal.

[0011] According to an embodiment of the present disclosure, the second sub-circuit includes a third trigger unit configured to sample the Nth comparison signal based on the Nth node voltage indication signal to obtain the Nth update signal.

[0012] According to an embodiment of the present disclosure, the second sub-circuit further includes a reset unit configured to output a reset signal to a reset terminal of the third trigger unit based on the Nth comparison signal and the Nth update signal, so as to reset the third trigger unit.

[0013] According to an embodiment of the present disclosure, the reset unit includes: a fourth trigger unit, configured to sample the first level signal in response to triggering the Nth comparison signal to obtain a reset trigger signal; a frequency divider, configured to output a clock signal with a predetermined pulse width; and a first NOR gate, configured to calculate the clock signal and the reset trigger signal to obtain a reset signal.

[0014] According to an embodiment of the present disclosure, the third sub-circuit includes: a calculation unit, configured to calculate the Nth update signal and the Nth comparison signal to obtain the N+1th output indication signal; a second NOR gate, configured to calculate the N+1th sampling signal and the N+1th output indication signal to obtain a calculation signal; and a fifth trigger unit, configured to output the N+1th voltage control signal under the control of the calculation signal.

[0015] According to an embodiment of the present disclosure, the compensation circuit includes a connected voltage regulating unit and a compensation unit; the voltage regulating unit is configured to adjust the input voltage of the compensation unit under the control of the Nth compensation control signal, so that the compensation unit compensates for the voltage at the Nth moment based on the adjusted input voltage to obtain the voltage at the N+1th moment.

[0016] According to another aspect of the present disclosure, a chip is provided, comprising any of the above-mentioned controllers.

[0017] According to another aspect of the present disclosure, an electronic device is provided, including: a power unit; and any one of the above controllers.

[0018] According to an embodiment of the present disclosure, when the load jumps, the logic control circuit generates a compensation control signal based on the Nth comparison signal and the voltage of the target node at the Nth moment to control the compensation circuit to compensate for the voltage of the target node, so that the voltage of the target node changes rapidly, thereby causing the output voltage of the power unit to change rapidly, thereby improving the dynamic response capability of the loop composed of the controller and the power unit to load jumps, so that the output voltage can be quickly stabilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1 The figure shows the response waveform of the power supply output voltage when the load changes.

[0021] Figure 2 A block diagram of an example controller is shown.

[0022] Figure 3 The block diagram of the controller according to the embodiment of the present disclosure is schematically shown.

[0023] Figure 4 A block diagram of a controller according to another embodiment of the present disclosure is schematically shown.

[0024] Figure 5 A block diagram of a controller according to another embodiment of the present disclosure is schematically shown.

[0025] Figure 6The block diagram of a chip according to an embodiment of the present disclosure is schematically shown.

[0026] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is schematically shown.

[0027] Figure 8 The flowchart of the control method according to the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are merely examples of the embodiments of the present disclosure. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0030] The figures show some block diagrams and / or flow charts. It should be understood that some blocks in the block diagrams and / or flow charts, or combinations thereof, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when these instructions are executed by the processor, they can create a device for implementing the functions / operations described in these block diagrams and / or flow charts. The technology of the present disclosure can be implemented in the form of hardware and / or software (including firmware, microcode, etc.). In addition, the technology of the present disclosure can take the form of a computer program product on a computer-readable storage medium storing instructions, which can be used by an instruction execution system or used in conjunction with an instruction execution system.

[0031] Figure 1 The figure shows the response waveform of the power supply output voltage when the load changes.

[0032] like Figure 1As shown, taking the loop composed of a general power supply and a load as an example, the time from the load jump to the end of the loop response includes the t1 period and the t2 period. The t1 period includes the period τ H-L1 , time period τ H-L2 and period τ H-L3 The t2 period includes the period τ L-H1 , time period τ L-H2 and period τ L-H3 . Time period τ H-L1 , time period τ H-L2 , time period τ H-L3 This corresponds to the process where the load changes from a heavy load state to a light load state. L-H1 , time period τ L-H2 and period τ L-H3 This corresponds to the process in which the load changes from a light load state to a heavy load state.

[0033] Time period τ H-L1 The time period from when the load jumps to when the loop starts responding is τ H-L1 The duration of the delay is affected by the load jump value, load capacitance, and the working state of the loop.

[0034] Time period τ H-L2 is the adjustment period of the loop, that is, the time the loop takes to adjust to the load jump. The period τ H-L2 The duration of the loop is affected by the loop bandwidth, slew rate, and the amount of change in the loop output voltage.

[0035] Time period τ H-L3 is the recovery period of the loop, that is, the period during which the output voltage of the power supply gradually returns to the steady state (that is, returns to the output voltage preset value VO). H-L3 The duration of the time period is affected by the phase margin of the loop and the cutoff frequency of the loop. If the phase margin of the loop is insufficient, it will lead to underdamped oscillation of the loop, that is, Figure 1 The period τ L-H3 This phenomenon occurs within the loop, thereby worsening the loop recovery time.

[0036] A rapid load change is a discontinuous process. For typical power supplies, relying solely on the loop circuit to adjust to the change is difficult due to stability constraints and limited bandwidth. Consequently, the loop recovery time is long.

[0037] Based on this, in some examples, the loop's adaptive response capability to jumps is improved by combining the magnitude of the loop's output voltage or the magnitude of the output voltage slope with a nonlinear loop transient enhancement method. Figure 2 This is explained as an example.

[0038] Figure 2 A block diagram of an example controller is shown.

[0039] like Figure 2 As shown, a typical power supply may include a controller 210 and a power unit 220. The error amplifier 211 in the controller 210 outputs an amplified error signal to a node Na based on an input reference signal V1 and a feedback signal V2 from the power unit 220. The PWM comparator 213 samples the voltage at the node Na to generate a sampled signal pwm_out. Simultaneously, the signal comparison circuit 212 generates a signal ov when the reference signal V1 is less than the feedback signal V2. The NOR gate 240 operates on the signal ov and the sampled signal pwm_out and outputs the resulting signal to the reset terminal of the D flip-flop 214.

[0040] The D flip-flop 214 receives a high-level ("1") signal h at its first input and a clock signal ck at its second input. Based on the rising edge of the clock signal ck, the D flip-flop 214 outputs a high-level ("1") signal pwm to the power supply unit 220, thereby increasing the output voltage Vb of the power supply unit 220 and thus increasing the power supply to the load. The D flip-flop 214 can be reset based on a signal input to its reset terminal, outputting a low-level ("0") signal pwm to decrease the output voltage of the power supply unit 220 and thereby reducing the power supply to the load.

[0041] On the one hand, when the reference signal V1 is less than the feedback signal V2, that is, when the output voltage is in an overvoltage state, the signal comparison circuit 212 generates a high-level ("1") signal ov. The NOR gate 240 controls the D flip-flop to output the signal pwm that can control the output voltage to be reduced to the power unit 220 based on the signal obtained by operating the signal ov and the sampling signal pwm_out. This enables the loop formed by the controller 210 and the power unit 220 to have the ability to respond to the overvoltage state of the output voltage Vb.

[0042] On the other hand, node Na in controller 210 is connected to the output of error amplifier 211, one end of resistor Ra, and one input of the PWM comparator. Therefore, when reference voltage V1 is greater than feedback voltage V2, i.e., when the output voltage is undervoltage, the voltage at node Na can be compensated using resistor Ra and capacitor Ca connected in series with resistor Ra, thereby compensating the input signal of the PWM comparator. If the PWM comparator still outputs a low-level ("0") signal after compensation, and signal comparison circuit 212 also outputs a low-level ("0") signal ov, NOR gate 240 outputs a low-level ("0") signal, and D flip-flop 214 is not reset. When clock signal ck is high ("1"), D flip-flop 214 outputs a high-level ("1") signal pwm to control the output voltage Vb of power unit 220 to boost. Thus, the loop formed by controller 210 and power unit 220 also has the ability to respond to undervoltage conditions of output voltage Vb.

[0043] However, for the loop in the above example, when the load jumps, the change in the output voltage Vb of the power unit 220 is only determined by the dynamic response capability of the loop itself, and the response speed to the load jump is slow. In some schemes, the resistance value of the resistor Ra and the capacitance value of the capacitor Ca can be adjusted by variable compensation technology to enhance the response capability of the loop to the jump and improve the response speed of the loop. However, the method of adjusting the resistance value of the resistor Ra requires occupying a large area of the circuit. Adjusting the capacitance value of the capacitor Ca can be achieved by capacitance multiplication technology, and capacitance multiplication technology will make the output voltage of the loop unstable, resulting in output voltage oscillation. In view of this, the embodiment of the present disclosure provides a controller to improve the response capability of the loop to load jumps, and the following is combined with Figure 3 Provide explanation.

[0044] Figure 3 The block diagram of the controller according to the embodiment of the present disclosure is schematically shown.

[0045] like Figure 3 As shown, the controller 310 includes an error amplifying circuit 311 , a signal comparing circuit 312 , a logic control circuit 313 and a compensation circuit 314 .

[0046] In the disclosed embodiment, the error amplifier circuit 311 outputs an Nth error amplified signal between the reference signal Vref and the Nth feedback signal Vfb from the power unit 320 to the target node Nc based on the reference signal Vref and the Nth feedback signal Vfb. The Nth feedback signal Vfb corresponds to the output voltage Vout of the power unit 320 at the Nth moment. N is an integer greater than or equal to 1.

[0047] For example, a first input terminal of the error amplifier circuit 311 is electrically connected to a reference signal terminal to receive a reference signal Vref. The voltage value of the reference signal Vref can be predetermined and is not limited herein. A second input terminal of the error amplifier circuit 311 is electrically connected to the output terminal of the power unit 320 to receive a feedback signal Vfb corresponding to the output voltage Vout of the power unit 320 at time N. The power unit 320 can be a voltage conversion circuit implemented using a power transistor, such as a DC-to-DC converter (DCDC) circuit. The error amplifier circuit 311 can compare the reference signal Vref with the Nth feedback signal Vfb to generate an Nth error amplified signal representing the difference between the reference signal Vref and the Nth feedback signal Vfb. The output terminal of the error amplifier circuit 311 is connected to a target node Nc to output the Nth error amplified signal to the target node Nc, thereby ensuring that the voltage of the target node Nc at time N corresponds to the Nth error signal.

[0048] In the embodiment of the present disclosure, the signal comparison circuit 311 determines the Nth comparison signal based on the reference signal Vref and the Nth feedback signal Vfb.

[0049] For example, a first input terminal of the signal comparison circuit 311 is electrically connected to a reference signal terminal to receive a reference signal Vref. A second input terminal of the signal comparison circuit 311 is electrically connected to an output terminal of the power unit 320, thereby receiving a feedback signal Vfb corresponding to the output voltage Vout of the power unit 320 at the Nth time. The signal comparison circuit 311 can compare the reference signal Vref with the Nth feedback signal Vfb to obtain an Nth comparison signal. The Nth comparison signal indicates the magnitude relationship between the reference signal Vref and the Nth feedback signal Vfb.

[0050] In the embodiment of the present disclosure, the logic control circuit 313 may generate an Nth compensation control signal based on the voltage of the target node at the Nth moment and the Nth comparison signal.

[0051] For example, a second input terminal of the logic control circuit 313 is electrically connected to the signal comparison circuit 312 to receive a comparison signal from the signal comparison circuit 312. The comparison signals may include an undervoltage comparison signal uv_bf and an overvoltage comparison signal ov_bf. The undervoltage comparison signal uv_bf and the overvoltage comparison signal ov_bf have different voltage levels. For example, when the undervoltage comparison signal uv_bf is at a high level ("1"), the overvoltage comparison signal ov_bf is at a low level ("0"); alternatively, when the undervoltage comparison signal uv_bf is at a low level ("1"), the overvoltage comparison signal ov_bf is at a high level ("0").

[0052] Furthermore, in the disclosed embodiment, the level of the comparison signal corresponds to the state of the output voltage Vout at that moment. When the output voltage Vout is in an undervoltage state, the reference signal Vref is greater than the feedback signal Vfb, the undervoltage comparison signal uv_bf is high ("1"), and the overvoltage comparison signal ov_bf is low ("0"). When the output voltage Vout is in an overvoltage state, the reference signal Vref is less than the feedback signal Vfb, the undervoltage comparison signal uv_bf is low ("0"), and the overvoltage comparison signal ov_bf is high ("1").

[0053] The logic control circuit 313 can generate an Nth compensation control signal based on the voltage at the Nth moment and the Nth undervoltage comparison signal uv_bf. A first output terminal of the logic control circuit 313 is electrically connected to a control terminal of the compensation circuit 314, thereby outputting the Nth compensation control signal to the compensation circuit 314 to control the compensation circuit 314.

[0054] Under the control of the Nth compensation control signal, the compensation circuit 314 compensates the voltage at the Nth moment to obtain the voltage at the N+1th moment.

[0055] For example, when the Nth compensation control signal is at a high level ("1"), the compensation circuit 314 compensates the voltage of the target node Nc at the Nth moment, thereby increasing the voltage of the target node Nc. When the Nth compensation control signal is at a low level ("0"), the compensation circuit 314 does not compensate the voltage of the target node Nc at the Nth moment.

[0056] In an embodiment of the present disclosure, the logic control circuit 313 can output the N+1th voltage control signal to the power unit 320 based on the N+1th voltage of the target node and the Nth comparison signal, so as to control the output voltage of the power unit 320 at the N+1th moment.

[0057] For example, the logic control circuit 313 can generate an N+1th voltage control signal based on the voltage at the N+1th time and the Nth overvoltage comparison signal ov_bf. The second output terminal of the logic control circuit 313 is electrically connected to the control terminal of the power unit 320, so that the N+1th voltage control signal can be output to the power unit 320 to control the output voltage Vout of the power unit 320 to increase or decrease.

[0058] In the embodiment of the present disclosure, when a load jump occurs, the logic control circuit 313 generates a compensation control signal based on the Nth comparison signal and the voltage of the target node Nc at the Nth moment to control the compensation circuit 314 to compensate for the voltage of the target node Nc, so that the voltage of the target node Nc changes rapidly, thereby causing the output voltage Vout of the power unit to change rapidly, thereby improving the dynamic response capability of the loop formed by the controller 310 and the power unit 320 to load jumps, so that the output voltage Vout can be quickly stabilized.

[0059] Optionally, the logic control circuit 313 may sample the voltage of the target node Nc at the Nth moment and the voltage at the N+1th moment respectively to obtain the Nth sampling signal and the N+1th sampling signal.

[0060] For example, the first input terminal of the logic control circuit 313 is electrically connected to the target node Nc, so that the voltage of the target node Nc can be sampled at multiple times to obtain sampling signals. The Nth sampling signal is the signal obtained by the logic control circuit 313 sampling the voltage of the target node Nc at the Nth time. The meaning of the N+1th sampling signal is similar and is not further described here.

[0061] Then, the logic control circuit 313 may generate an Nth compensation control signal based on the Nth sampling signal and the Nth comparison signal.

[0062] For example, a second input terminal of the logic control circuit 313 is electrically connected to the signal comparison circuit 312 to receive a comparison signal from the signal comparison circuit 312. The logic control circuit 313 can generate an Nth compensation control signal based on the Nth sampling signal and the Nth undervoltage comparison signal uv_bf. A first output terminal of the logic control circuit 313 is electrically connected to a control terminal of the compensation circuit 314, so that the Nth compensation control signal can be output to the compensation circuit 314 to control the compensation circuit 314.

[0063] Furthermore, the logic control circuit 313 may output an N+1th voltage control signal to the power unit 320 based on the N+1th sampling signal and the Nth comparison signal, so as to control the output voltage of the power unit 320 at the N+1th moment.

[0064] For example, the logic control circuit 313 can generate an N+1th voltage control signal based on the N+1th sampling signal and the Nth second comparison signal ov_bf. The second output terminal of the logic control circuit 313 is electrically connected to the control terminal of the power unit 320, so that the N+1th voltage control signal can be output to the power unit 320 to control the output voltage Vout of the power unit 320 to increase or decrease.

[0065] Figure 4 A block diagram of a controller according to another embodiment of the present disclosure is schematically shown.

[0066] like Figure 4 As shown, the controller 410 may include an error amplification circuit 411 , a signal comparison circuit 412 , a logic control circuit 413 and a compensation circuit 414 .

[0067] The output end of the power unit 420 is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second input end of the error amplifier circuit 411, and the second input end of the signal comparison circuit 412. The second end of the second resistor R2 is grounded. While the output end of the power unit 420 outputs the output voltage Vout, the error amplifier circuit 411 and the signal comparison circuit 412 can receive a feedback signal Vfb corresponding to the output voltage Vb at that moment.

[0068] The error amplifier circuit 411 outputs an error amplified signal to the target node Nc based on the feedback signal Vfb and the reference signal Vref. The signal comparison circuit 412 outputs a comparison signal to the logic control circuit 413 based on the feedback signal Vfb and the reference signal Vref.

[0069] The logic control circuit 413 samples the voltage of the target node Vc at this time to obtain a sampling signal. Based on the obtained sampling signal and the undervoltage comparison signal uv_bf, the logic control circuit 413 outputs a compensation control signal to the compensation circuit 414 to control the compensation circuit 414 to compensate for the voltage of the target node Vc. After the compensation circuit 414 compensates for the voltage of the target node Vc, the logic control circuit 413 generates an output control signal based on the compensated voltage of the target node Nc and the overvoltage comparison signal ov_bf. The output control signal is output to the power unit 420 to control the output voltage Vout of the power unit 420 to increase or decrease.

[0070] For example, when the Nth second comparison signal ov_bf and the N+1th sampling signal are both at a low level ("0"), the logic control circuit 313 outputs a low-level voltage control signal to turn off the power tube in the power unit, thereby reducing the output voltage Vout; when at least one of the Nth second comparison signal ov_bf and the N+1th sampling signal is at a high level ("1"), the logic control circuit 313 outputs a high-level voltage control signal to control the power tube in the power unit 320 to turn on, thereby increasing the output voltage Vout.

[0071] Optionally, the logic control circuit 413 may include a first sub-circuit, a second sub-circuit, and a third sub-circuit.

[0072] For example, the first subcircuit may include a sampling unit. The sampling unit may include, but is not limited to, a PWM (pulsewidth modulation) comparator, etc. A first input of the sampling unit is electrically connected to a target node Nc, a second input of the sampling unit receives a predetermined signal, and an output of the sampling unit outputs a sampling signal corresponding to the voltage of the target node Nc.

[0073] For example, the first subcircuit can generate an Nth node voltage indication signal based on the Nth sampling signal and the Nth output indication signal. The Nth output indication signal indicates the state of the output voltage Vout at the Nth moment, such as an overvoltage state or an undervoltage state. For example, the first input terminal of the first subcircuit is electrically connected to the target node Nc so as to sample the voltage of the target node Nc and obtain a sampling signal. The second input terminal of the first subcircuit is connected to the first output terminal of the third subcircuit so as to receive the Nth output indication signal. The first subcircuit can operate on the Nth sampling signal and the Nth output indication signal to obtain the Nth node voltage indication signal. The Nth node voltage indication signal indicates the state of the voltage at the Nth moment, such as an overvoltage state or an undervoltage state.

[0074] For example, the first sub-circuit can generate an Nth compensation control signal based on the Nth node voltage indication signal and the Nth comparison signal. For example, the third input terminal of the first sub-circuit is electrically connected to the signal comparison circuit to receive a comparison signal, such as the undervoltage comparison signal uv_bf. The first sub-circuit can perform an operation on the node voltage indication signal and the comparison signal to obtain the compensation control signal. The first output terminal of the first sub-circuit is electrically connected to the compensation circuit 414, so that the compensation control signal can be output to the compensation circuit 414 to control the compensation circuit 414 to compensate the voltage of the target node Nc.

[0075] For example, the second sub-circuit can generate an Nth update signal based on the Nth node voltage indication signal and the Nth comparison signal. For example, a first input terminal of the second sub-circuit is electrically connected to a second output terminal of the first sub-circuit to receive the node voltage indication signal, and a second input terminal of the second sub-circuit is electrically connected to an output terminal of the signal comparison circuit to receive a comparison signal, such as the undervoltage comparison signal uv_bf. The second sub-circuit can operate on the node voltage indication signal and the comparison signal to obtain the update signal.

[0076] For example, the third sub-circuit can update the Nth output indication signal based on the Nth update signal and the Nth comparison signal to generate the N+1th output indication signal, and generate the N+1th voltage control signal based on the N+1th output indication signal and the N+1th sampling signal. The N+1th output indication signal indicates the state of the output voltage at the N+1th moment, such as an overvoltage state or an undervoltage state. For example, the first input terminal of the third sub-circuit can be electrically connected to the output terminal of the second sub-circuit to receive the update signal. The second input terminal of the third sub-circuit can be electrically connected to the output terminal of the signal comparison circuit to receive a comparison signal, such as the overvoltage comparison signal ov_bf. The third sub-circuit can operate on the update signal and the comparison signal and update the output indication signal being output based on the output indication signal obtained by the operation.

[0077] For example, the third input terminal of the third sub-circuit can be electrically connected to the third input terminal of the first sub-circuit to receive the sampling signal. The third sub-circuit can operate on the sampling signal and the output indication signal, and control the output voltage Vout of the power unit 420 based on the signal obtained by the operation.

[0078] Optionally, the first sub-circuit further includes a first trigger unit and a second trigger unit.

[0079] In an embodiment of the present disclosure, the first trigger unit generates an Nth trigger signal in response to a signal edge of the triggering Nth sampling signal.

[0080] For example, the first trigger unit may include a first trigger. A first input terminal of the first trigger receives a first level signal. For example, the first level signal may be a high level signal. A second input terminal of the first trigger is connected to an output terminal of the sampling unit to receive a sampling signal. In response to a rising edge of the trigger sampling signal, the first trigger outputs the first level signal as a trigger signal.

[0081] In the embodiment of the present disclosure, the second trigger unit generates an Nth node voltage indication signal based on the Nth trigger signal and the Nth output indication signal.

[0082] For example, the second trigger unit may include a second trigger. A first input terminal of the second trigger is electrically connected to an output terminal of the first trigger unit to receive a trigger signal. A second input terminal of the second trigger is electrically connected to a first output terminal of the third sub-circuit to receive an output indication signal. In response to receiving the output indication signal, the second trigger unit may determine a level of the node voltage indication signal based on a level of the output indication signal and output the node voltage indication signal.

[0083] Figure 5 A block diagram of a controller according to another embodiment of the present disclosure is schematically shown.

[0084] like Figure 5 As shown, the controller 500 may include an error amplifier circuit, a signal comparison circuit, a logic control circuit and a compensation circuit 520. It is additionally noted that, in order to facilitate the example of the internal structure of the logic control circuit and the compensation circuit 520, Figure 5 The error amplifier circuit and the signal comparison circuit are not shown. The connection relationship between the error amplifier circuit and the signal comparison circuit can be referred to the previous description and will not be repeated here. Figure 5 In the illustrated embodiment, the logic control circuit includes a first sub-circuit 511 , a second sub-circuit 512 , and a third sub-circuit 513 .

[0085] The first sub-circuit 511 may include a first trigger unit and a second trigger unit.

[0086] For example, the first trigger unit can sample the first level signal in response to the signal edge of the triggering N sampling signal to obtain the N trigger signal. The first trigger unit may include a first trigger FF1 and a first AND gate AND1. For example, the first trigger may be a D trigger. The first input terminal of the first trigger FF1 receives the first level signal tieh. For example, the first level signal tieh may be a high level ("1") signal. The second input terminal of the first trigger FF1 is connected to the sampling unit ( Figure 5 (not shown) to receive the Nth sampling signal pwm_sp. The first flip-flop FF1 can output the first-level signal tieh as a trigger signal in response to a rising edge of the triggering Nth sampling signal pwm_sp. The output terminal Q of the first flip-flop FF1 is connected to the first input terminal of the first AND gate AND1, and the second input terminal of the first AND gate receives the clock signal clk. Thus, the first AND gate can output a high-level ("1") trigger signal in response to a high-level ("1") of the clock signal clk.

[0087] A reset terminal of the first flip-flop FF1 receives the clock signal clk, and the first flip-flop FF1 can be reset based on the clock signal clk.

[0088] The second trigger unit includes a second flip-flop FF2. For example, the second flip-flop FF2 may be an RS flip-flop. A first input of the second flip-flop FF2 is connected to the output of the first AND gate AND1 to receive a trigger signal. A second input of the second flip-flop FF2 receives an Nth output indication signal. An output terminal Q of the second flip-flop FF2 outputs an Nth node voltage indication signal.

[0089] The first sub-circuit 511 can calculate the Nth node voltage indication signal and the Nth comparison signal to obtain an Nth compensation control signal. For example, the first sub-circuit 511 further includes a second AND gate AND2. A first input of the second AND gate AND2 receives the Nth node voltage indication signal, and a second input of the second AND gate AND2 receives the Nth undervoltage comparison signal uv_bf. An output of the second AND gate AND2 outputs the Nth compensation control signal uv to control the compensation circuit 520 to compensate the voltage of the target node Nc.

[0090] The second sub-circuit 512 may include a third trigger unit configured to sample the Nth comparison signal based on the Nth node voltage indication signal to obtain an Nth update signal. The third trigger unit includes a first NOT gate NOT1 and a third flip-flop FF3. The input of the first NOT gate NOT1 receives the Nth node voltage indication signal. When the voltage of the target node Nc is in an undervoltage state at time N, the Nth node voltage indication signal is at a low level ("0"). Therefore, the first NOT gate NOT1 can convert the low level ("0") signal to a high level ("1"), thereby indicating that the voltage of the target node Nc has been compensated. The output of the first NOT gate NOT1 is connected to the first input of the third flip-flop FF3. The second input of the third flip-flop FF3 receives the Nth comparison signal, which may be the Nth undervoltage comparison signal. In response to a signal edge, such as a rising edge, that triggers the Nth undervoltage comparison signal ov_bf, the output of the third flip-flop FF3 outputs the Nth update signal dis_ov.

[0091] The third subcircuit 513 includes a calculation unit, a second NOR gate NOR2, and a fifth trigger unit. For example, the calculation unit can calculate the Nth update signal and the Nth comparison signal to obtain the N+1th output indication signal. The second NOR gate can calculate the N+1th sampling signal and the N+1th output indication signal to obtain a calculation signal. The fifth trigger unit can output the N+1th voltage control signal under the control of the calculation signal. Specifically, the calculation unit may include a second NOT gate NOT2 and a third AND gate AND3. The fifth trigger unit may include a fifth flip-flop FF5.

[0092] An input terminal of the second NOT gate NOT2 receives the Nth update signal dis_ov, and an output terminal of the second NOT gate NOT2 is connected to a first input terminal of the third AND gate AND3 .

[0093] The second input terminal of the third AND gate AND3 receives the Nth comparison signal, such as the Nth overvoltage comparison signal ov_bf. The output terminal of the third AND gate AND3 is connected to the first input terminal of the second NOR gate NOR2. The output terminal of the third AND gate AND3 outputs the output indication signal.

[0094] A second input terminal of the second NOR gate NOR2 is connected to the output terminal of the sampling unit to receive the N+1th sampling signal pwm_sp. An output terminal of the second NOR gate NOR2 is connected to a reset terminal of the fifth flip-flop FF5. A first input terminal of the fifth flip-flop FF5 receives the first level signal tieh. A second input terminal of the fifth flip-flop FF5 is configured to receive the clock signal clk.

[0095] The fifth flip-flop FF5 can sample the first level signal tieh in response to a rising edge of the clock signal clk to obtain the (N+1)th output control signal pwm_ctl. The output terminal of the fifth flip-flop FF5 outputs the (N+1)th output control signal pwm_ctl.

[0096] Based on this, the second NOR gate NOR2 operates on the N+1th sampling signal PWM and the N+1th output indication signal ov, and provides the calculated signal to the reset terminal of the fifth flip-flop FF5, so as to control the fifth flip-flop FF5 to output the output control signal pwm_ctl of a low level ("0") different from the first level signal tieh.

[0097] The second sub-circuit 512 further includes a reset unit. The reset unit may output a reset signal to a reset terminal of the third trigger unit based on the Nth comparison signal and the Nth update signal, so as to reset the third trigger unit.

[0098] The reset unit may include a fourth trigger unit, a frequency divider DIR, and a first NOR gate NOR1. For example, the fourth trigger unit may include a fourth flip-flop FF4. In response to triggering the Nth comparison signal, the fourth flip-flop FF4 can sample the first-level signal to obtain a reset trigger signal. The frequency divider DIR can output a clock signal with a predetermined pulse width. The first NOR gate NOR1 can calculate the clock signal and the reset trigger signal to obtain a reset signal. The first input of the fourth flip-flop FF4 receives the first-level signal tieh. The second input of the fourth flip-flop FF4 receives the Nth comparison signal, for example, the Nth overvoltage comparison signal ov_bf. The output of the fourth flip-flop FF4 is connected to the first input of the first NOR gate NOR1. The second input of the first NOR gate NOR1 is connected to the output of the frequency divider DIR, and the output of the first NOR gate NOR1 is connected to the reset terminal of the third flip-flop FF3. The frequency divider DIR can be configured to reduce the frequency of the clock signal, thereby extending the interval between the active levels of the respective clock signals. An output terminal of the fourth flip-flop FF4 is connected to an output terminal of the third flip-flop so as to be reset when the third flip-flop outputs an update signal of a low level (“0”).

[0099] The compensation circuit 520 may be a current-type capacitance multiplication circuit. The compensation circuit 520 may include an electrically connected voltage regulating unit and a compensation unit. Under the control of the Nth compensation control signal, the voltage regulating unit may adjust the input voltage of the compensation unit so that the compensation unit compensates for the voltage at the Nth moment based on the adjusted input voltage to obtain the voltage at the N+1th moment. For example, the voltage regulating unit may include an adjustable resistor Rh and a capacitor C. The compensation unit may include an operational amplifier unit OP. The first input terminal of the operational amplifier unit OP, the output terminal of the operational amplifier unit OP, the target node Nc and the first end of the adjustable resistor Rh are connected, the second input terminal of the operational amplifier unit OP is connected to the second end of the adjustable resistor Rh and the first end of the capacitor C, and the second end of the capacitor C is grounded. The compensation control signal uv is applied to the adjustable end of the adjustable resistor Rh. The adjustable resistor Rh can be used to convert the current flowing through itself into a voltage at both ends, that is, the voltage between the target node and the positive end of the capacitor C. The operational amplifier unit OP ensures that the voltage at the target node Vc is equal to the voltage at the positive end of the capacitor by clamping. On this basis, the current flowing into capacitor C is equivalently reduced by a factor of (1 + A), meaning the effective capacitance is multiplied by a factor of (1 + A). This allows for on-chip large-capacitor compensation of the target node Vc voltage, where A is the gain of the operational amplifier OP. Furthermore, the series connection of adjustable resistor Rh and capacitor C introduces a zero in the loop formed by controller 500 and the power unit, thereby preventing phase margin degradation caused by output voltage poles.

[0100] On this basis, when the output voltage of the power unit decreases, the signal comparison circuit can generate a high-level ("1") Nth undervoltage comparison signal uv_bf, and the logic control circuit processes the Nth undervoltage comparison signal uv_bf to obtain a high-level ("1") compensation control signal uv, and reduces the resistance value of the adjustable resistor Rh in the compensation circuit 520 through the high-level ("1") compensation control signal uv to reduce the capacitance value of the capacitor C, thereby increasing the voltage increase speed of the target node Nc and reducing the dynamic response time to the undervoltage state of the output voltage.

[0101] When the voltage at target node Vc rapidly increases, the output voltage of the power unit gradually increases. To prevent glitches in the reference signal or feedback signal from erroneously triggering the signal comparison circuit to generate an erroneous comparison signal (e.g., a high-level Nth undervoltage comparison signal uv_bf generated when the output voltage is undervoltage, or a high-level Nth overvoltage comparison signal ov_bf generated when the output voltage is overvoltage), hysteresis is incorporated into the signal comparison circuit. Furthermore, considering the signal delay between target node Nc and the output of the power unit, the overall signal delay of the loop formed by controller 500 and the power unit may result in the voltage at target node Nc exceeding the actual desired voltage after the logic control circuit stops using the high-level ("1") compensation control signal uv to reduce the resistance of resistor Rh. If the voltage at target node Nc overshoots too much, the output voltage of the power unit will continue to increase, potentially triggering a high-level ("1") output indication signal ov. The high level ("1") output indication signal ov controls the reset of the fifth flip-flop FF5, so that the fifth flip-flop FF5 outputs the low level ("0") output control signal pwm_ctl to turn off the power tube in the power unit, thereby erroneously reducing the output voltage of the power unit when there is no need to reduce the output voltage of the power unit.

[0102] Similarly, the hysteresis of the signal comparison circuit and the signal delay of the loop may also cause the output voltage Vout to drop too much, thereby erroneously triggering the signal comparison circuit to generate an erroneous comparison signal, thereby erroneously causing the logic control circuit to output a compensation control signal uv to the compensation circuit 520 to reduce the voltage of the target node Vc.

[0103] Based on this, the signal delay problem existing in the above loop will cause the loop to be alternately in an overvoltage or undervoltage state, making it difficult for the output voltage of the power unit to quickly recover and stabilize.

[0104] Therefore, in this embodiment of the present disclosure, the conditions for triggering the output indication signal ov and the compensation control signal uv are restricted. For example, when the output voltage is low, and the voltage at the target node Nc is low, a high-level ("1") compensation control signal uv is required to reduce the resistance of the adjustable resistor Rh, thereby rapidly increasing the voltage at the target node Nc and, consequently, the output voltage. When the output voltage is too high or the loop is already providing output at its maximum capacity, a high-level ("1") compensation control signal uv is not required to control the resistance of the adjustable resistor Rh. Therefore, the compensation control signal uv can be processed to a low level ("0") by the second flip-flop FF2. When a high-level ("1") output indication signal ov is generated, the second flip-flop FF2 can output a low-level ("0") node voltage indication signal, thereby processing the compensation control signal uv to a low level ("0") and disabling the compensation function. However, this embodiment of the present disclosure is not limited to this. In another embodiment of the present disclosure, the output current of the power unit can be collected and input into a comparator for comparison with a predetermined current. When the output current is greater than the predetermined current, the comparator generates a high-level ("1") overcurrent signal oc. The two inputs of the fourth AND gate AND4 receive the overcurrent signal oc and the output control signal pwm_ctl, respectively. The fourth AND gate AND4 operates on the overcurrent signal oc and the output control signal pwm_ctl to generate a third indication signal indicating the output current state of the power unit. The output of the fourth AND gate AND4 is connected to the first input of an OR gate OR, and the second input of the OR gate OR receives the output indication signal. The output of the OR gate OR is connected to the second input of the second flip-flop FF2. Thus, when the high-level ("1") third indication signal is generated, the second flip-flop FF2 also outputs a low-level ("0") node voltage indication signal, disabling the compensation function. This prevents erroneous compensation of the voltage at the target node Nc.

[0105] When the output voltage is not in an overvoltage state, the high-level ("1") output indication signal ov is not generated. Therefore, in the next cycle, the voltage at the target node Vc is normal or low. At this time, the logic control circuit can generate a high-level ("1") compensation control signal uv to quickly increase the voltage at the target node Vc, thereby quickly increasing the output voltage.

[0106] Similarly, when the loop is in an undervoltage state and is already operating at its maximum output capacity, the output indication signal ov needs to be updated to a low level ("0"), i.e., an inactive level. The next time the loop actually experiences an overvoltage state, a low-level ("0") update signal dis_ov is generated to update the output indication signal ov to a high level ("1"), i.e., an active level, thereby outputting a low-level ("0") output control signal pwm_ctl that controls the power unit to reduce its output voltage. To prevent the failure to generate a low-level ("0") update signal due to the lack of a high-level ("1") output indication signal ov, a frequency divider DIR is introduced to combine with the clock signal clk to provide the signal rst_dis_ov, thereby generating a low-level ("0") update signal dis_ov for a predetermined duration.

[0107] Based on this, through the above-mentioned restrictions on the compensation control signal uv and the output indication signal ov, the loop instability problem caused by the use of the compensation control signal uv and the output indication signal ov to cause the loop to be alternately in an undervoltage or overvoltage state is avoided, and the dynamic response capability of the loop to load jumps is improved, so that the output voltage of the loop can be quickly stabilized.

[0108] Figure 6 The block diagram of a chip according to an embodiment of the present disclosure is schematically shown.

[0109] like Figure 6 As shown, the chip 600 of this embodiment may include a controller 610. The controller 610 may be any of the controllers described above, such as any of the controllers 310, 410, and 500. For example, the chip 600 may be a power management chip. The power management chip may be used to manage the output voltage of a power supply, such as the output voltage of a power unit in the power supply.

[0110] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is schematically shown.

[0111] like Figure 7 As shown, the electronic device 700 includes a controller 710 and a power unit 720 .

[0112] In the embodiment of the present disclosure, the controller 710 may be any one of the controllers 310, 410, and 500 described above, and will not be described in detail here. The power unit 720 may be any one of the power units 320 and 420 described above, and will not be described in detail here.

[0113] Figure 8 The flowchart of the control method according to the embodiment of the present disclosure is schematically shown.

[0114] like Figure 8 As shown, the control method of this embodiment includes operations S810 to S850.

[0115] In operation 810 , an Nth error signal between a reference signal and an Nth feedback signal from a power unit is output to a target node based on a predetermined amplification gain, wherein the Nth feedback signal corresponds to an output voltage of the power unit at an Nth moment, and N is an integer greater than or equal to 1.

[0116] In operation 820 , an Nth comparison signal is determined based on the reference signal and the Nth feedback signal.

[0117] In operation 830 , an Nth compensation control signal is generated based on the Nth time voltage of the target node and the Nth comparison signal.

[0118] In operation 840 , under the control of the Nth compensation control signal, the voltage at the Nth time is compensated to obtain the voltage at the N+1th time.

[0119] In operation 850 , the output voltage of the power unit at the (N+1)th time is controlled based on the (N+1)th time voltage of the target node and the Nth comparison signal.

[0120] In the embodiment of the present disclosure, operations S810 to S850 are similar to the operations performed by the controller 310 described above, and are not described again herein.

[0121] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0122] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A controller comprising: an error amplifier circuit configured to output an Nth error amplified signal between a reference signal and an Nth feedback signal from a power unit to a target node based on a predetermined amplification gain, wherein the Nth feedback signal corresponds to an output voltage of the power unit at an Nth moment, where N is an integer greater than or equal to 1; a signal comparison circuit configured to determine an Nth comparison signal based on the reference signal and the Nth feedback signal; a logic control circuit configured to generate an Nth compensation control signal based on the voltage of the target node at time N and the Nth comparison signal, and to control the output voltage of the power unit at time N+1 based on the voltage of the target node at time N+1 and the Nth comparison signal; The compensation circuit is configured to compensate the voltage at the Nth moment under the control of the Nth compensation control signal to obtain the voltage at the N+1th moment.

2. The controller according to claim 1, wherein: The logic control circuit is further configured to: Sampling the voltage at the Nth moment and the voltage at the N+1th moment respectively to obtain an Nth sampling signal and an N+1th sampling signal; generating the Nth compensation control signal based on the Nth sampling signal and the Nth comparison signal; Based on the N+1th sampling signal and the Nth comparison signal, an N+1th voltage control signal is output to the power unit to control the output voltage of the power unit at the N+1th moment.

3. The controller according to claim 2, wherein: The logic control circuit includes: a first sub-circuit configured to generate an Nth node voltage indication signal based on the Nth sampling signal and the Nth output indication signal, and to generate the Nth compensation control signal based on the Nth node voltage indication signal and the Nth comparison signal; wherein the Nth output indication signal indicates a state of the output voltage at an Nth moment, and the Nth node voltage indication signal indicates a state of the voltage at the Nth moment; a second sub-circuit configured to generate an Nth update signal based on the Nth node voltage indication signal and the Nth comparison signal; and The third sub-circuit is configured to update the Nth output indication signal based on the Nth update signal and the Nth comparison signal to generate the N+1th output indication signal, and generate the N+1th voltage control signal based on the N+1th output indication signal and the N+1th sampling signal, wherein the N+1th output indication signal indicates the state of the output voltage at the N+1th moment.

4. The controller according to claim 3, wherein: The first sub-circuit includes a first trigger unit and a second trigger unit; a first trigger unit configured to generate an Nth trigger signal in response to a signal edge triggering the Nth sampling signal; The second trigger unit is configured to generate the Nth node voltage indication signal based on the Nth trigger signal and the Nth output indication signal.

5. The controller according to claim 4, wherein: The first trigger unit is further configured to sample the first level signal in response to a signal edge that triggers the Nth sampling signal to obtain the Nth trigger signal.

6. The controller according to any one of claims 3 to 5, wherein: The first sub-circuit is further configured to calculate the Nth node voltage indication signal and the Nth comparison signal to obtain the Nth compensation control signal.

7. The controller according to any one of claims 3 to 5, wherein: The second sub-circuit includes a third trigger unit configured to sample the Nth comparison signal based on the Nth node voltage indication signal to obtain the Nth update signal.

8. The controller according to claim 7, wherein: The second sub-circuit further includes a reset unit configured to output a reset signal to a reset terminal of the third trigger unit based on the Nth comparison signal and the Nth update signal, so as to reset the third trigger unit.

9. The controller according to claim 8, wherein: The reset unit includes: a fourth trigger unit, configured to sample the first level signal in response to triggering the Nth comparison signal to obtain a reset trigger signal; a frequency divider configured to output a clock signal of a predetermined pulse width; The first NOR gate is configured to calculate the clock signal and the reset trigger signal to obtain the reset signal.

10. The controller according to any one of claims 3 to 5, wherein: The third sub-circuit comprises: a calculation unit configured to calculate the Nth update signal and the Nth comparison signal to obtain the N+1th output indication signal; a second NOR gate configured to calculate the N+1th sampling signal and the N+1th output indication signal to obtain a calculation signal; The fifth trigger unit is configured to output the (N+1)th voltage control signal under the control of the calculation signal.

11. The controller according to any one of claims 1 to 5, wherein: The compensation circuit includes a voltage regulating unit and a compensation unit connected; The voltage regulating unit is configured to regulate the input voltage of the compensation unit under the control of the Nth compensation control signal, so that the compensation unit compensates the voltage at the Nth moment based on the regulated input voltage to obtain the voltage at the N+1th moment.

12. A chip comprising: A controller as claimed in any one of claims 1 to 11.

13. An electronic device comprising: Power unit; as well as A controller according to any one of claims 1 to 11.

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