Calculation device and method thereof

Abstract

The present disclosure discloses an arithmetic device. The arithmetic device is capable of performing butterfly processing on a sequence of 2N pieces of input data. The arithmetic device comprises a first buffer unit, a second buffer unit, a read-write unit, an arithmetic unit and a control unit. The control unit is used for enabling the read-write unit to read 2 hours of input data from the memory as a first group of input data of the first buffer unit; causing the arithmetic unit to perform h stages of butterfly processing on the first set of input data to generate a first set of updated data; when the first group of updated data is generated, the read-write unit reads the other 2 h input data from the memory to serve as a second group of input data of the second buffer unit; and causing the read-write unit to write the first group of updated data to the memory.

Description

Technical Field

[0001] The present disclosure relates to a computing device, and more particularly to a computing device capable of performing number-theoretic transform (NTT) or fast Fourier transform (FFT). Background Art

[0002] Discrete Fourier transform (DFT) technology has been widely used in signal processing and image processing because it can analyze the frequency components of a signal. Fast Fourier transform (FFT) is an algorithm widely used to calculate DFT, which is famous for its efficiency and speed. FFT reduces the computational complexity of DFT from O(n 2 ) is reduced to O(n log n), where n is the number of input data. This makes it particularly useful in real-time signal processing and other applications with high speed requirements.

[0003] On the other hand, the number-theoretic transform (NTT) is a variant of the FFT specifically designed for operations in finite fields. NTT is often used in lattice-based cryptography and is therefore important for post-quantum cryptography and homomorphic encryption applications.

[0004] To facilitate FFT and NTT operations, butterfly processing has been proposed. Butterfly processing rearranges input data in a specific manner to efficiently perform the transformation. However, because butterfly processing typically requires two input data points and outputs two updated data points for each operation, memory bandwidth becomes a critical issue in hardware implementation. Therefore, designing an appropriate computational scheme to more efficiently perform the transformation has become a pressing issue. Summary of the Invention

[0005] One embodiment of the present disclosure provides a computing device. N The butterfly processing is performed on a sequence of input data, where N is a positive integer. The operation device includes a first buffer unit, a second buffer unit, a read / write unit, an arithmetic unit, and a control unit. The read / write unit is coupled to the memory, the first buffer unit, and the second buffer unit. The arithmetic unit is coupled to the first buffer unit and the second buffer unit and is used to perform the operation required for applying the butterfly processing. The control unit is used to enable the read / write unit to read 2 N 2 of the input datah The control unit is further configured to cause the arithmetic unit to perform h stages of butterfly processing on the first set of input data to generate a first set of updated data, wherein the first set of updated data is stored in the first buffer unit. The control unit is further configured to cause the read / write unit to read 2 from the memory when generating the first set of updated data. N The other 2 in the input data h The input data is used as the second set of input data, wherein the second set of input data is stored in the second buffer unit. The control unit is further used to enable the read-write unit to write the first set of updated data into the memory.

[0006] Another embodiment of the present disclosure provides a method for operating a computing device to: N The method comprises performing butterfly processing on a sequence of input data, wherein N is a positive integer. The computing device comprises a first buffer unit, a second buffer unit, a read-write unit, and an arithmetic unit. The method comprises using the read-write unit to read 2 N 2 of the input data h input data as the first set of input data of the first buffer unit, where h is greater than or equal to 2 and less than N; using the arithmetic unit to perform h stages of butterfly processing on the first set of input data to generate a first set of updated data to the first buffer unit; when generating the first set of updated data, using the read-write unit to read 2 from the memory N The other 2 in the input data h The input data is used as the second group of input data to the second buffer unit; and the first group of updated data is written into the memory by the read / write unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings. Like reference numerals in different drawings refer to like elements.

[0008] Figure 1 FIG. 4 illustrates NTT's butterfly processing scheme based on the Cooley-Tuckey algorithm.

[0009] Figure 2 FIG. 1 illustrates a computing system according to a comparative example of the present disclosure.

[0010] Figure 3 A computing system according to one embodiment of the present disclosure is shown.

[0011] Figure 4 An embodiment of the present disclosure is shown for operating Figure 3Flowchart of a method for performing butterfly processing by a computing device.

[0012] Figure 5 FIG. 1 illustrates an embodiment of the present disclosure for use in the butterfly process of NTT. Figure 3 The structure of data path control in the computing device shown.

[0013] Figure 6 FIG. 4 illustrates the butterfly processing scheme of INTT based on the Gentleman-Sande algorithm.

[0014] Figure 7 FIG. 1 illustrates a butterfly process for INTT according to an embodiment of the present disclosure. Figure 3 The structure of data path control in the computing device shown. DETAILED DESCRIPTION

[0015] To perform complex Fourier transform operations, Cooley and Tukey proposed a famous algorithm that reformulates a larger discrete Fourier transform (DFT) as several smaller DFTs. For example, a DFT of composite size N can be reformulated using N1 DFTs of size N2 (where N, N1, and N2 are all positive integers and N = N1·N2). This reformulation can be performed recursively, thus reducing the complexity of the DFT.

[0016] Based on the Cooley-Tuckey algorithm, a butterfly processing scheme was developed to perform fast Fourier transformation (FFT) or number-theoretic transform (NTT) in hardware. Figure 1 Figure 2 shows NTT's butterfly processing solution based on the Cooley-Tuckey algorithm. Figure 1 In the process, butterfly processing is used to transform 2 N-1 (In this embodiment, N is equal to 4) times the input polynomial M, and the 16 coefficients of the input polynomial will be used as the input data X[0] to X

[15] of the butterfly processing. In this case, Figure 1 The butterfly processing shown can be based on the input data X[0] to X

[15] and the predetermined rotation factor to The conversion data X'[0] to X'

[15] are obtained as coefficients of the converted polynomial.

[0017] Figure 1The butterfly processing scheme shown includes N stages (i.e., ST1, ST2, ST3, and ST4). In the first stage ST1, input data X[0] and input data X[8] are retrieved, and a modular multiplication operation is performed on the input data X[8] and a predetermined rotation factor φ[1] using a preset modulus q. In this case, the intermediate data X1[0] of the first stage ST1 can be obtained by adding the input data X[0] to the modular multiplication result, and the intermediate data X1[8] of the first stage ST1 can be obtained by subtracting the modular multiplication result from the input data X[0].

[0018] That is, the intermediate data X1[0] and X1[8] can be expressed as shown in equations (1) and (2) below.

[0019]

[0020] Similarly, the same operation can be used to obtain other intermediate data of the first stage ST1. For example, a modular multiplication operation can be performed on the input data X[9] and the rotation factor φ[1] according to the preset modulus q, and the results of the modular multiplication operation of the input data X[1] and the input data X[9] can be added to obtain the intermediate data X1[1] of the first stage ST1. In addition, the result of the modular multiplication performed on the input data X[9] can be subtracted from the input data X[1] to obtain the intermediate data X1[9] of the first stage ST1.

[0021] The calculation operation used to derive the intermediate data of the first stage ST1 can be further applied to other stages to obtain intermediate data or final transformed data. For example, in the second stage ST2, the intermediate data X1[0] and the intermediate data X1[4] can be obtained, and the intermediate data X1[4] and the rotation factor can be twiddled with the preset modulus q. Perform a modular multiplication operation. In this case, the intermediate data X1[0] and the result of the modular multiplication operation on the intermediate data X1[4] can be added to obtain the intermediate data X2[0] of the second stage ST2, and the intermediate data X2[4] of the second stage ST2 can be obtained by subtracting the result of the modular multiplication operation on the intermediate data X1[4] from the intermediate data X1[0].

[0022] Figure 2 FIG. 1 shows a comparative example of a computing system 10 according to the present disclosure. The computing system 10 can execute Figure 1The butterfly processing shown in FIG. 1 is a flowchart of a processing system 100. The processing system 100 includes a processing device 100 and a memory 12. In this embodiment, the processing device 100 can complete one stage of operation for two input data in each cycle. For example, in one cycle, the processing device 100 can obtain intermediate data X1[0] and X1[8] based on input data X[0] and X[8], and in another cycle, the processing device 100 can obtain intermediate data X1[1] and X1[9] based on input data X[1] and X[9].

[0023] In this scenario, to maximize the utilization of the computing device 100, the computing device 100 needs to read two data from the memory 12 and write two data back to the memory 12 in each cycle. This means that the memory 12 needs to support two read operations and two write operations in each cycle (assuming that each word of the memory 12 can only store one input data). However, most memories only support two access operations per cycle (e.g., two read operations, two write operations, or one read operation and one write operation). Enabling a memory to support four access operations per cycle (e.g., a 4-port memory) requires additional design cost and circuit area. Therefore, using a 4-port memory significantly increases cost, and this high-frequency access operation consumes a lot of power.

[0024] Figure 3 A computing system 20 according to one embodiment of the present disclosure is shown. The computing system 20 includes a memory 22 and a computing device 200. Compared to the computing device 100, the computing device 200 can reduce the required memory bandwidth while maintaining the efficiency of the arithmetic units in the computing device 200, thereby simplifying hardware requirements and reducing power consumption.

[0025] The computing device 200 includes a first buffer unit 210, a second buffer unit 220, a read / write unit 230, an arithmetic unit 240, and a control unit 250. The read / write unit 230 can be coupled to the memory 22, the first buffer unit 210, and the second buffer unit 220. The read / write unit 230 can read data from the memory 22 and write data to the memory 22. The first buffer unit 210 and the second buffer unit 220 can function as ping-pong buffer units, alternately receiving data read from the memory 22 by the read / write unit 230 and alternately transmitting the data to the read / write unit 230 for writing the data to the memory 22. The arithmetic unit 240 is coupled to the first buffer unit 210 and the second buffer unit 220 and can perform the operations required for butterfly processing based on the data stored in the first buffer unit 210 and the second buffer unit 220, and store the operation results back to the first buffer unit 210 and the second buffer unit 220. The control unit 250 can control the data flow between the read / write unit 230, the first buffer unit 210, the second buffer unit 220, and the arithmetic unit 240 to facilitate butterfly processing. Each component of the computing device 200 can be implemented using digital electronic circuits, firmware, software, and / or a combination thereof. Furthermore, the memory 22 can be a static random-access memory (SRAM), but the present disclosure is not limited thereto.

[0026] In this embodiment, the computing device 200 can N The butterfly processing is performed on a sequence of input data of FFT or NTT, where N is a positive integer. In this case, each of the first buffer unit 210 and the second buffer unit 220 may have a storage capacity of 2 N 2 of the input data h The capability of inputting data, wherein h is greater than or equal to 2 and less than N. Therefore, the computing device 200 can allow the read / write unit 230 to read 2 consecutive data from the memory 22. h The arithmetic unit 240 can read the corresponding input data according to the operation order determined by the butterfly processing and store it in, for example, the first buffer unit 210. h The h stages of butterfly processing are performed on the input data.

[0027] Furthermore, when the arithmetic unit 240 performs operations on the input data stored in the first buffer unit 210, the computing device 200 can allow the read / write unit 230 to read another 2 hThe first buffer unit 210 and the second buffer unit 220 are used to buffer the input data for the operations of multiple stages in the butterfly processing. This allows the computing device 200 to perform appropriate data scheduling, thereby maintaining high hardware utilization of the arithmetic unit 240 and reducing the bandwidth required by the memory 22.

[0028] In some embodiments, the arithmetic unit 240 can complete the operation of one stage of butterfly processing on two input data in one cycle. h To perform h stages of butterfly processing on data, h·2 h-1 In this case, the read / write unit 230 needs to read the data every h·2 h-1 Read 2 in one cycle h data and write 2 h data (i.e., in h·2 h-2 The read operation of the cycle is followed by h·2 h-2 In other words, the read / write unit 230 can read 2 data from the memory 22 in one cycle. N At least one input data input data, or at least The updated data is written to the memory 22. Therefore, when the value of h is larger, the number of memory accesses required per cycle of the device system 20 will be less.

[0029] Figure 4 A flowchart of a method M1 for operating the computing device 200 to perform butterfly processing according to an embodiment of the present disclosure is shown. The method M1 includes steps S110 to S117.

[0030] In this embodiment, the operating system 20 may execute the method M1. Figure 1 The butterfly process shown in FIG. 4 is shown in FIG. 4 , where N is equal to 4 and h is equal to 2. In this case, the first buffer unit 210 and the second buffer unit 220 are each capable of storing 2 2 (ie, 4) input data, of which a total of 2 4 (ie, 16) input data are processed by butterfly. For example, the first buffer unit 210 may include four registers R[0], R[1], R[2] and R[3], and each of the registers R[0], R[1], R[2] and R[3] may be used to store an input data, such as Figure 3Similarly, the second buffer unit 220 may include four registers R'[0], R'[1], R'[2] and R'[3], and each of the registers R'[0], R'[1], R'[2] and R'[3] may be used to store an input data.

[0031] Table 1 shows the Figure 1 Part of the data schedule of the computing device 200 of NTT's butterfly processing is shown.

[0032]

[0033]

[0034]

[0035]

[0036] Table 1

[0037] Reference Figure 1 、 Figure 4 As shown in Table 1, in step S110, the control unit 250 allows the read-write unit 230 to read and write data in two (ie, h·2 h-2 In the continuous cycle, 4 input data are read from the memory as the first set of input data. The control unit 250 allows the first buffer unit 210 to store the first set of input data. In this embodiment, because h is equal to 2, the first set of input data may include 2 N The first input data of the input data, 2 N The first (2 N-1 +1) th Input data, 2 N The first (2 N-2 +1) th input data, and 2 N The first (2 N-1 +2 N-2 +1) th For example, in Table 1, in the first cycle #1, the read / write unit 230 may read the input data X[0] (i.e., the first input data of the 16 input data X[0] to X

[15] ) and X[8] (i.e., the second input data of the 16 input data X[0] to X

[15] ) from the memory 22. N-1 +1) th input data), and in the second cycle #2, the input data X[4] (ie, the second of the 16 input data X[0] to X

[15] ) may be further read from the memory 22. N-2 +1) thinput data) and X

[12] (i.e., the 2nd of the 16 input data X[0] to X

[15] N-1 +2 N-2 +1) th In this embodiment, after receiving the read request in the first cycle #1, the memory 22 may transmit the read data in the next cycle, and therefore, the read / write unit 230 may store the input data X[0] and X[8] in the registers R[0] and R[2], respectively, in the second cycle #2, and may further store the input data X[4] and X

[12] in the registers R[1] and R[3], respectively, in the third cycle #3.

[0038] In step S111, once at least a portion of the first set of input data is stored in the first buffer unit 210, the control unit 250 causes the arithmetic unit 240 to perform two stages (i.e., h stages) of butterfly processing on the first set of input data stored in the first buffer unit 210 to generate a first set of updated data (i.e., intermediate data X2[0], X2[8], X2[4], and X2

[12] ). The control unit 250 causes the first buffer unit 210 to store the first set of updated data. In some embodiments, the arithmetic unit 240 can complete the operations required for one stage of butterfly processing on two input data in one cycle. For example, as shown in Table 1, in the third cycle #3, the arithmetic unit 240 can obtain intermediate data X1[0] and X1[8] based on the input data X[0] and X[8] stored in the registers R[0] and R[2], and in the fourth cycle #4, the intermediate data X1[4] and X1

[12] can be obtained based on the input data X[4] and X

[12] stored in the registers R[1] and R[3].

[0039] Accordingly, the intermediate data X1[0], X1[8], X1[4], and X1

[12] of the first stage ST1 of the butterfly processing are stored in-place in the first buffer unit 210. That is, the intermediate data X1[0] can be stored in the register R[0] that originally stored the corresponding input data X[0], the intermediate data X1[4] can be stored in the register R[1] that originally stored the corresponding input data X[4], and so on.

[0040] Next, in the fifth cycle #5, the arithmetic unit 240 can obtain the intermediate data X2[0] and X2[4] based on the intermediate data X1[0] and X1[4] stored in the registers R[0] and R[1]. In the sixth cycle #6, the arithmetic unit 240 can obtain the intermediate data X2[8] and X2

[12] based on the intermediate data X1[8] and X1

[12] stored in the registers R[2] and R[3]. Next, the control unit 250 can allow the first buffer unit 210 to store the first set of updated data (i.e., the intermediate data X2[0], X2[4], X2[8], and X2

[12] of the second stage ST2 of the butterfly processing). In this embodiment, in the fifth cycle #5, the intermediate data X2[0] and X2[4] may be stored in the registers R[0] and R[1] of the first buffer unit 210, and in the sixth cycle #6, the intermediate data X2[8] and X2

[12] may be stored in the registers R[2] and R[3] of the first buffer unit 210.

[0041] In step S112, when the arithmetic unit 240 generates the first set of updated data, in the fifth cycle #5 and the sixth cycle #6, the control unit 250 may cause the read / write unit 230 to read the input data X[1], X[9], X[5], and X

[13] from the memory 22 as the second set of input data. In addition, the control unit 250 may cause the second buffer unit 220 to store the second set of input data. In this embodiment, in the sixth cycle #6, the input data X[1] and X[9] obtained in the fifth cycle #5 are stored in the registers R'[0] and R'[2] of the second buffer unit 220, respectively, and in the seventh cycle #7, the input data X[5] and X

[13] obtained in the sixth cycle #6 are stored in the registers R'[1] and R'[3] of the second buffer unit 220, respectively.

[0042] That is, when the arithmetic unit 240 performs the operation of the second stage ST2 of the butterfly processing on the intermediate data X1[0], X1[4], X1[8], and X1

[12] , the read / write unit 230 can read the input data for subsequent operation from the memory 22. Since the first buffer unit 210 needs to store the intermediate data X2[0], X2[4], X2[8], and X2

[12] of the second stage ST2 of the butterfly processing obtained by the arithmetic unit 240, the input data X[1], X[9], X[5], and X

[13] captured by the read / write unit 230 can be stored in the second buffer unit 220 at this time, thereby avoiding data conflict in the first buffer unit 210.

[0043] In step S113, once at least a portion of the second set of input data is stored in the second buffer unit 220, the control unit 250 may cause the arithmetic unit 240 to perform two stages of butterfly processing on the second set of input data (i.e., input data X[1], X[9], X[5], X

[13] ) to generate a second set of updated data. The control unit 250 may cause the second buffer unit 220 to store the second set of updated data. Specifically, as shown in Table 1, in the seventh cycle #7, the arithmetic unit 240 may obtain the intermediate data X1[1] and X1[9] of the first stage ST1 of the butterfly processing based on the input data X[1] and X[9] stored in the registers R'[0] and R'[2], and in the eighth cycle #8, the arithmetic unit 240 may obtain the intermediate data X1[5] and X1

[13] of the first stage ST1 of the butterfly processing based on the input data X[5] and X

[13] stored in the registers R'[1] and R'[3]. In this embodiment, the intermediate data X1[1], X1[5], X1[9], and X1

[13] are stored in-place in registers R'[0], R'[1], R'[2], and R'[3] without changing their positions.

[0044] Next, in the ninth cycle #9, the arithmetic unit 240 can obtain the intermediate data X2[1] and X2[5] of the second stage ST2 of the butterfly processing based on the intermediate data X1[1] and X1[5] stored in the registers R'[0] and R'[1]. And in the tenth cycle #10, the arithmetic unit 240 can obtain the intermediate data X2[9] and X2

[13] of the second stage ST2 of the butterfly processing based on the intermediate data X1[9] and X1

[13] stored in the registers R'[2] and R'[3]. Next, the control unit 250 can allow the second buffer unit 220 to store the second set of updated data (i.e., the intermediate data X2[1], X2[5], X2[9], and X2

[13] of the second stage ST2 of the butterfly processing). In this embodiment, in the ninth cycle #9, the intermediate data X2[1] and X2[5] are stored in the registers R'[0] and R'[1] of the second buffer unit 220, and in the tenth cycle #10, the intermediate data X2[9] and X2

[13] are stored in the registers R'[2] and R'[3] of the second buffer unit 220.

[0045] In step S114, when step S113 is executed and the arithmetic unit 240 generates the second set of updated data (i.e., the intermediate data X2[1], X2[5], X2[9], and X2

[13] of the second stage ST2 of the butterfly processing), the control unit 250 allows the read / write unit 230 to read the data in two (i.e., h·2 h-2) consecutive cycles, the first set of updated data is written to the memory 22. For example, in the seventh cycle #7, the read / write unit 230 may write the intermediate data X2[0] and X2[8] to replace the input data X[0] and X[8] in the memory 22, and in the eighth cycle #8, write the intermediate data X2[4] and X2

[12] to replace the input data X[4] and X

[12] in the memory 22.

[0046] Furthermore, in step S115, in the ninth cycle #9 and the tenth cycle #10, when step S113 is executed and the arithmetic unit 240 generates the second set of updated data (i.e., the intermediate data X2[1], X2[5], X2[9], and X2

[13] of the second stage ST2 of the butterfly process), the control unit 250 may cause the read / write unit 230 to read the input data X[2], X

[10] , X[6], and X

[14] from the memory 22 as the third set of input data. The control unit 250 may cause the first buffer unit 210 to store the third set of input data for subsequent operations.

[0047] In step S116, once at least a portion of the third set of input data is stored in the first buffer unit 210, the control unit 250 causes the arithmetic unit 240 to perform two stages of butterfly processing on the third set of input data (i.e., input data X[2], X

[10] , X[6], X

[14] ) to generate a third set of updated data. Furthermore, in step S117, when step S116 is executed and the arithmetic unit 240 generates the third set of updated data, the control unit 250 causes the read / write unit 230 to perform two stages of butterfly processing on the third set of input data (i.e., input data X[2], X

[10] , X[6], X

[14] ) to generate a third set of updated data. h-2 ) consecutive cycles, the second set of updated data is written to the memory 22. For example, in the eleventh cycle #11, the read / write unit 230 may write the intermediate data X2[1] and X2[9] to replace the input data X[1] and X[9] in the memory 22, and in the twelfth cycle #12, write the intermediate data X2[5] and X2

[13] to replace the input data X[5] and X

[13] in the memory 22.

[0048] By repeating steps S110 to S117, the computing device 200 can update the input data X[0] to X

[15] to the intermediate data X2[0] to X2

[15] of the second stage ST2 of the butterfly processing, and can further update the intermediate data X2[0] to X2

[15] of the second stage ST2 of the butterfly processing to the conversion data X'[0] to X'

[15] , thereby completing the butterfly processing.

[0049] Since the operation system 20 and the method M1 use the first buffer unit 210 and the second buffer unit 220 in an alternating order to store a plurality of input data (eg, 2 hTherefore, the data scheduling of the butterfly processing can be optimized so that the read / write unit 230 and the arithmetic unit 240 can be properly pipelined, thereby reducing the memory bandwidth required by the memory 22 while maintaining the hardware utilization of the computing device 200.

[0050] Furthermore, since the data flow of the butterfly processing is predetermined and the computational operations for all stages of the butterfly processing are essentially the same, a universal data access mechanism can be used to access the registers R[0] to R[3] of the first buffer unit 210 and the registers R'[0] to R'[3] of the second buffer unit 220. Figure 5 FIG. 1 shows a data path control structure in a computing device 200 for butterfly processing of NTT according to an embodiment of the present disclosure. Figure 4 Method M1 to operate Figure 5 The structure shown in this paper is used to realize Figure 1 The butterfly processing scheme of NTT is shown in FIG. Figure 5 As shown, the computing device 200 further includes a plurality of multiplexers (MUX) M1 to M14. The MUX M1 to M14 can be controlled by the control unit 250 (for simplicity, Figure 5 The control unit 250 and the control lines coupled between the MUXs M1 to M14 and the control unit 250 are not shown.

[0051] [1] In this embodiment, the arithmetic unit 240 includes an adder 242, a subtractor 244, and a modulus multiplier 246. The adder 242 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the adder 242 is coupled to the first input terminal IN1 of the arithmetic unit 240, and the output terminal of the adder 242 is coupled to the first output terminal OUT1 of the arithmetic unit 240. The subtractor 244 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the subtractor 244 is coupled to the first input terminal IN1 of the arithmetic unit 240, and the output terminal of the subtractor 244 is coupled to the second output terminal OUT2 of the arithmetic unit 240. The modulus multiplier 246 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the modulus multiplier 246 is coupled to the second input terminal IN2 of the arithmetic unit 240; the second input terminal of the modulus multiplier 246 is used to receive a corresponding rotation factor (i.e., the rotation factor to ) and the output of modulus multiplier 246 is coupled to the second input of adder 242 and the second input of subtractor 244. In some embodiments, adder 242 and subtractor 244 may each be implemented as an adder supporting signed addition, however, the present disclosure is not limited thereto. In other embodiments where computing device 200 is used to perform an FFT, adder 242 and subtractor 244 may be a modulus adder and a modulus subtractor, respectively.

[0052] MUX M1 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of MUX M1 is coupled to the read / write unit 230; the second input terminal of MUX M1 is coupled to the first output terminal OUT1 of the arithmetic unit 240; and the output terminal of MUX M1 is coupled to the register R[0]. MUX M2 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M2 is coupled to the read / write unit 230; the second input terminal of MUX M2 is coupled to the first output terminal OUT1 of the arithmetic unit 240; the third input terminal of MUX M2 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M2 is coupled to the register R[1]. MUX M3 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M3 is coupled to the read / write unit 230; the second input terminal of MUX M3 is coupled to the first output terminal OUT1 of the arithmetic unit 240; the third input terminal of MUX M3 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M3 is coupled to the register R[2]. MUX M4 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M4 is coupled to the read / write unit 230; the second input terminal of MUX M4 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M4 is coupled to the register R[3].

[0053] MUX M5 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of MUX M5 is coupled to the read / write unit 230; the second input terminal of MUX M5 is coupled to the first output terminal OUT1 of the arithmetic unit 240; and the output terminal of MUX M5 is coupled to the register R'[0]. MUX M6 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M6 is coupled to the read / write unit 230; the second input terminal of MUX M6 is coupled to the first output terminal OUT1 of the arithmetic unit 240; the third input terminal of MUX M6 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M6 is coupled to the register R'[1]. MUX M7 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M7 is coupled to the read / write unit 230; the second input terminal of MUX M7 is coupled to the first output terminal OUT1 of the arithmetic unit 240; the third input terminal of MUX M7 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M7 is coupled to the register R'[2]. MUX M8 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M8 is coupled to the read / write unit 230; the second input terminal of MUX M8 is coupled to the second output terminal OUT2 of the arithmetic unit 240; and the output terminal of MUX M8 is coupled to the register R'[3].

[0054] MUX M9 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M9 is coupled to register R[1]; the second input terminal of MUX M9 is coupled to register R[2]; and the third input terminal of MUX M9 is coupled to register R[3]. MUX M10 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M10 is coupled to register R'[1]; the second input terminal of MUX M10 is coupled to register R'[2]; and the third input terminal of MUX M10 is coupled to register R'[3]. MUX M11 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of MUX M11 is coupled to the output terminal of MUX M9; the second input terminal of MUX M11 is coupled to the output terminal of MUX M10; and the output terminal of MUX M11 is coupled to the second input terminal IN2 of the arithmetic unit 240.

[0055] MUX M12 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M12 is coupled to register R[0]; the second input terminal of MUX M12 is coupled to register R[1]; and the third input terminal of MUX M12 is coupled to register R[2]. MUX M13 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M13 is coupled to register R'[0]; the second input terminal of MUX M13 is coupled to register R'[1]; and the third input terminal of MUX M13 is coupled to register R'[2]. MUX M14 has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal of MUX M14 is coupled to the output terminal of MUX M12; the second input terminal of MUX M14 is coupled to the output terminal of MUX M13; and the output terminal of MUX M14 is coupled to the first input terminal IN1 of the arithmetic unit 240.

[0056] In this way, by controlling the multiplexers M1 to M14, the control unit 250 can control the data flow of the computing device 200 so that the arithmetic unit 240 can receive corresponding data for calculation and store the calculation results in the corresponding registers, thereby completing the calculation of each stage of the butterfly processing.

[0057] In some embodiments, the computing device 200 may further include data path control units 232 and 234 for controlling data flow between the read / write unit 230 and registers R[0] to R[3], and between the read / write unit 230 and registers R'[0] to R'[3]. In some embodiments, the data path control units 232 and 234 may each include multiple multiplexers, multiple demultiplexers, or a combination thereof. In other words, the data path control units 232 and 234 may be implemented using digital electronic circuits.

[0058] In this embodiment, the operation system 20 is used to perform NTT, however, the present disclosure is not limited thereto. In some embodiments, the operation system 20 can be further used to perform FFT by simply changing the input data and the rotation factors.

[0059] In addition, in some embodiments, the operation system 20 may be further configured to perform inverse NTT (INTT) and inverse FFT (IFFT). Figure 6 The butterfly processing scheme of INTT based on the Gentleman-Sande algorithm is shown. Figure 6 In the butterfly process of INTT, 2 N (In this embodiment, N is equal to 4) input data Y[0] to Y

[15] are transformed into 2 Nconversion data Y'[0] to Y'

[15] . Figure 6 The butterfly processing of INTT shown is Figure 1 The inverted version of the butterfly process of NTT is shown, with the inverted twiddle factors to

[0060] For example, we can add the input data Y[0] and the input data Y[1] to get Figure 6 The intermediate data Y1[0] of the first stage ST1 of the butterfly processing can be obtained by subtracting the input data Y[1] from the input data Y[0] and performing the subtraction operation and the rotation factor with the preset modulus q. Perform a modular multiplication to get Figure 6 The intermediate data Y1[1] of the first stage ST1 of the butterfly processing. That is, the intermediate data Y1[0] and Y1[1] can be expressed as the following equations (3) and (4).

[0061] Y1[0]=Y[0]+Y[1] (3).

[0062]

[0063] In this embodiment, Figure 7 The difference between the computing device 200' and the computing device 200 is that the arithmetic unit 240' is used to replace the arithmetic unit 240 to calculate the equations (3) and (4) to perform Figure 6 For example, the computing device 200' can allow the read / write unit 230 to read 2 consecutive bits from the memory 22. h The input data is stored in, for example, the first buffer unit 210. By reading the corresponding input data according to the operation order determined by the butterfly processing of INTT, the arithmetic unit 240' can then read the corresponding input data according to the 2 stored in the first buffer unit 210. h The input data is used to perform the h-stage operations of the butterfly processing of INTT.

[0064] Furthermore, when the arithmetic unit 240' performs operations on the input data stored in the first buffer unit 210, the computing device 200' can allow the read / write unit 230 to read another 2 hThe first and second buffer units 210 and 220 buffer the input data and store them in the second buffer unit 220. That is, when performing butterfly processing for INTT, the computing device 200' can still use the first and second buffer units 210 and 220 to buffer the input data in an alternating manner, thereby enabling the read / write unit 230 and the arithmetic unit 240' to be properly pipelined. This reduces the memory bandwidth required for the memory 22 while maintaining high hardware utilization of the arithmetic unit 240'. In this embodiment, the computing system 20 can be used to perform INTT, however, the present disclosure is not limited thereto. In certain embodiments, the computing system 20 can further be used to perform IFFT, which only requires changing the input data and the twiddle factors.

[0065] Table 2 shows the Figure 6 The data schedule of part of the computing device 200' for butterfly processing of INTT is shown.

[0066]

[0067]

[0068]

[0069] Table 2

[0070] Reference Figure 6 As shown in Table 2, the control unit 250 can allow the read-write unit 230 to be in two (ie, h·2 h-2 In the first cycle #1 and the second cycle #2, 4 input data are read from the memory 22. In this embodiment, h is equal to 2. For example, the input data read in the first cycle #1 and the second cycle #2 may include 2 N The first input data of the input data (for example, data Y[0]), 2 N The second input data of the input data (for example, data Y[1]), 2 N The third input data (eg, data Y[2]) of the input data, and 2 N The fourth input data of the input data (for example, data Y[3]).

[0071] Since the data flow of the butterfly processing of INTT is predetermined and the calculation operations for all stages of the butterfly processing are basically the same, a universal data access scheme can be used to access the registers R[0] to R[3] of the first buffer unit 210 and the registers R'[0] to R'[3] of the second buffer unit 220. Figure 7 FIG. 1 shows a data path control structure in a computing device 200 ′ for butterfly processing of INTT according to an embodiment of the present disclosure. Figure 4 Method M1 to operate Figure 7The structure shown in this paper is used to realize Figure 6 The butterfly processing scheme of INTT is shown.

[0072] like Figure 7 As shown, Figure 5 The MUX M1 to M14 used in the data path control structure of the butterfly processing of NTT can also be further used Figure 7 Intt butterfly processing. Figure 5 and Figure 7 The difference of the structure shown is that the arithmetic unit 240' is reconfigured according to the arithmetic operation required for the butterfly processing of INTT. Specifically, the first input terminal IN1 of the arithmetic unit 240' is coupled to the first input terminal of the adder 242 and the first input terminal of the subtractor 244, the second input terminal IN2 of the arithmetic unit 240' is coupled to the second input terminal of the adder 242 and the second input terminal of the subtractor 244, the first output terminal OUT1 of the arithmetic unit 240' is coupled to the output terminal of the adder 242, and the second output terminal OUT2 of the arithmetic unit 240' is coupled to the output terminal of the modulus multiplier 246. In addition, the output terminal of the subtractor 244 is coupled to the first input terminal of the modulus multiplier 246. The output terminal and the second input terminal of the modulus multiplier 246 are used to receive a corresponding rotation factor (i.e., a corresponding factor among the rotation factors φ′[1] to φ′

[15] ). In some embodiments, the arithmetic unit 240' may include a multiplexer ( Figure 5 and Figure 7 (not shown) to reconfigure its data flow so that the arithmetic unit 240' can have Figure 5 The configuration shown in the figure can be changed to Figure 7 Configuration shown.

[0073] By appropriately controlling multiplexers M1 through M14 via control unit 250, computing device 200' is able to perform butterfly processing of INTT and utilize first buffer 210 and second buffer 220 to alternately store multiple input data. This optimizes data scheduling for butterfly processing and allows for proper pipelined operation of read / write unit 230 and arithmetic unit 240'. This reduces the memory bandwidth required by memory 22 and maintains hardware utilization of computing device 200'.

[0074] In summary, the computing device, computing system, and method for operating the computing device provided by the embodiments of the present disclosure can alternately use two buffer units to store multiple input data (e.g., 2 hInput data) can be used to optimize the data scheduling of the butterfly processing and appropriately pipeline the read / write unit and the arithmetic unit. This can reduce the memory bandwidth required by the memory and maintain the hardware utilization of the computing device.

[0075] Explanation of symbols

[0076] X[0] to X

[15] : Input data

[0077] X'[0] to X'

[15] : Convert data

[0078] X1[0],X1[1],X1[4],X1[8],X1[9],X1

[12] : intermediate data

[0079] X2[0] to X2

[15] : intermediate data

[0080] to Twiddle factors

[0081] ST1, ST2, ST3, ST4: Stages

[0082] 10,20: Operational System

[0083] 100,200,200': computing device

[0084] 12,22: Memory

[0085] 210: First buffer unit

[0086] 220: Second buffer unit

[0087] 230: Read and write unit

[0088] 240: Arithmetic Unit

[0089] 250: Control unit

[0090] M1: Method

[0091] S110, S111, S112, S113, S114, S115, S116, S117: Steps

[0092] 232,234: Data path control unit

[0093] M1,M2,M3,M4,M5,M6:Multiplexer

[0094] M7,M8,M9,M10,M11,M12,M13,M14: Multiplexer

[0095] R[0],R[1],R[2],R[3],R'[0],R'[1],R'[2],R'[3]: registers

[0096] 242: Adder

[0097] 244: Subtractor

[0098] 246: Modulus Multiplier

[0099] IN1, IN2: input terminal

[0100] OUT1, OUT2: output terminals

[0101] Y[0] to Y

[15] : Input data

[0102] Y'[0] to Y'

[15] : Convert data

[0103] Y1[0],Y1[1],Y1[2],Y1[3],Y1[4],Y1[5]: intermediate data

[0104] Y1[6],Y1[7],Y2[0],Y2[1],Y2[2],Y2[3]: intermediate data

[0105] to Twiddle factors

Claims

1. A computing device for N A butterfly process is performed on a sequence of input data, wherein N is a positive integer, and the computing device comprises: a first buffer unit; a second buffer unit; a read / write unit coupled to a memory, the first buffer unit, and the second buffer unit; an arithmetic unit coupled to the first buffer unit and the second buffer unit and configured to perform arithmetic operations required by the butterfly processing; as well as A control unit for: The read / write unit reads the 2 N 2 of the input data h input data as a first set of input data, wherein the first set of input data is stored in the first buffer unit, and h is greater than or equal to 2 and less than N; causing the arithmetic unit to perform h stages of the butterfly process on the first set of input data to generate a first set of updated data, wherein the first set of updated data is stored in the first buffer unit; When the first set of updated data is generated, the read / write unit reads the 2 N The other 2 input data h input data as a second set of input data, wherein the second set of input data is stored in the second buffer unit; as well as The read / write unit is enabled to write the first set of updated data into the memory.

2. The computing device as claimed in claim 1 , wherein the control unit is further configured to: Once at least a portion of the second set of input data is stored in the second buffer unit, the arithmetic unit performs h stages of the butterfly process on the second set of input data to generate a second set of updated data, wherein the second set of updated data is stored in the second buffer unit. 3 . The computing device as claimed in claim 2 , wherein when the second set of updated data is generated, the control unit causes the read / write unit to write the first set of updated data into the memory.

4. The computing device as claimed in claim 2, wherein the control unit is further configured to: When the second set of updated data is generated, the read / write unit reads the 2 N Another 2 for input data h The input data is used as a third set of input data, wherein the third set of input data is stored in the first buffer unit. 5 . The computing device of claim 1 , wherein once at least a portion of the first set of input data is stored in the first buffer unit, the control unit causes the arithmetic unit to perform the h stages of the butterfly processing on the first set of input data. 6 . The computing device of claim 1 , wherein the intermediate data generated in a first stage of the h stages of the butterfly processing of the first set of input data is stored in-place in the first buffer unit with its position unchanged. 7 . The computing device as claimed in claim 1 , wherein within one cycle, the arithmetic unit is used to complete the operations required for performing one stage of the butterfly processing on two input data.

8. The computing device of claim 1 , wherein the butterfly processing is used for fast Fourier transform or mathematical transformation, and the arithmetic unit comprises: an adder having a first input terminal coupled to a first input terminal of the arithmetic unit, a second input terminal, and an output terminal coupled to a first output terminal of the arithmetic unit; a subtractor having a first input terminal coupled to the first input terminal of the arithmetic unit, a second input terminal, and an output terminal coupled to a second output terminal of the arithmetic unit; as well as a modulus multiplier having a first input terminal coupled to a second input terminal of the arithmetic unit, a second input terminal for receiving a corresponding twiddle factor, and an output terminal coupled to the second input terminal of the adder and the second input terminal of the subtractor.

9. The computing device according to claim 8, further comprising: a first multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, and an output terminal coupled to a first register of the first buffer unit; a second multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a second register of the first buffer unit; a third multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a third register of the first buffer unit; a fourth multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a fourth register of the first buffer unit; a fifth multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, and an output terminal coupled to a first register of the second buffer unit; a sixth multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a second register of the second buffer unit; a seventh multiplexer having a first input terminal coupled to the read / write unit, a second input terminal coupled to the first output terminal of the arithmetic unit, a third input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a third register of the second buffer unit; as well as An eighth multiplexer has a first input terminal coupled to the read / write unit, a second input terminal coupled to the second output terminal of the arithmetic unit, and an output terminal coupled to a fourth register of the second buffer unit.

10. The computing device according to claim 9, further comprising: a ninth multiplexer having a first input terminal coupled to the second register of the first buffer unit, a second input terminal coupled to the third register of the first buffer unit, a third input terminal coupled to the fourth register of the first buffer unit, and an output terminal; a tenth multiplexer having a first input terminal coupled to the second register of the second buffer unit, a second input terminal coupled to the third register of the second buffer unit, a third input terminal coupled to the fourth register of the second buffer unit, and an output terminal; as well as an eleventh multiplexer having a first input terminal coupled to the output terminal of the ninth multiplexer, a second input terminal coupled to the output terminal of the tenth multiplexer, and an output terminal coupled to the second input terminal of the arithmetic unit.

11. The computing device according to claim 9, further comprising: a twelfth multiplexer having a first input terminal coupled to the first register of the first buffer unit, a second input terminal coupled to the second register of the first buffer unit, a third input terminal coupled to the third register of the first buffer unit, and an output terminal; a thirteenth multiplexer having a first input terminal coupled to the first register of the second buffer unit, a second input terminal coupled to the second register of the second buffer unit, a third input terminal coupled to the third register of the second buffer unit, and an output terminal; as well as A fourteenth multiplexer has a first input terminal coupled to the output terminal of the twelfth multiplexer, a second input terminal coupled to the output terminal of the thirteenth multiplexer, and an output terminal coupled to the first input terminal of the arithmetic unit.

12. A method for operating a computing device for N A butterfly process is performed on a sequence of input data, wherein N is a positive integer, and the computing device includes a first buffer unit, a second buffer unit, a read / write unit, and an arithmetic unit, and the method includes: The read / write unit is used to read the 2 N 2 of the input data h input data as a first set of input data to the first buffer unit, wherein h is greater than or equal to 2 and less than N; Utilizing the arithmetic unit to perform h stages of the butterfly process on the first set of input data to generate a first set of updated data to the first buffer unit; When generating the first set of updated data, the read / write unit is used to read the 2 N The other 2 input data h input data as a second set of input data to the second buffer unit; and The first set of updated data is written into the memory using the read / write unit.

13. The method of claim 12, further comprising: Once at least a portion of the second set of input data is stored in the second buffer unit, the arithmetic unit is used to perform h stages of the butterfly process on the second set of input data to generate a second set of updated data for the second buffer unit. 14 . The method of claim 13 , wherein when the second set of updated data is generated, the step of using the read / write unit to write the first set of updated data into the memory is performed.

15. The method of claim 13, further comprising: When generating the second set of updated data, the 2 N Another 2 of the input data h The input data is used as a third set of input data to the first buffer unit.

16. The method of claim 12 , wherein once at least a portion of the first set of input data is stored in the first buffer unit, the step of using the arithmetic unit to perform the h stages of the butterfly processing on the first set of input data to generate the first set of updated data to the first buffer unit is performed.

17. The method of claim 12, further comprising utilizing the first buffer unit to store intermediate data generated in a first stage of the h stages of the butterfly processing of the first set of input data in a position-invariant in-place manner.

18. The method of claim 12, wherein h is equal to 2, the butterfly process is used for mathematical transformation or fast Fourier transform, and the first set of input data includes the 2 N The first input data of the input data, the 2 N The second N-2 +1 input data, the 2 N The second N-1 +1 input data, and the 2 N Input data 2 N-1 +2 N-2 +1 input data.

19. The method of claim 12, wherein h is equal to 2, the butterfly process is used for inverse mathematical transformation or inverse fast Fourier transform, and the first set of input data includes the 2 N The first input data of the input data, the 2 N The second input data of the input data, the 2 N The third input data of the input data, and the 2 N A fourth input data of the input data.

20. The method of claim 12 , wherein the step of utilizing the arithmetic unit to perform the h stages of the butterfly process on the first set of input data to generate the first set of updated data to the first buffer unit comprises: The arithmetic unit is used to complete the operations required for one stage of the butterfly processing on two input data within one cycle.

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