Calculation method and calculation device

Abstract

The invention relates to a calculation method and a calculation device for mantissa alignment by using rounding-off. In some embodiments, calculating a sum of floating-point numbers, such as in a multiply accumulate operation, includes aligning a plurality of mantissas of the floating-point numbers by adjusting at least a subset of the plurality of mantissas such that a plurality of indices of the plurality of floating-point numbers are the same. After alignment, the most significant portion of each mantissa is rounded according to the remainder of the mantissa, such as the most significant bits of the remainder. The mantissas are then truncated into the most significant portion that is rounded off. The truncated mantissas may then be totaled up. The aligned mantissas may be a product of a mantissa of the corresponding input and a weight. In such conditions, the sum of these rounded portions is the result of a multiply accumulate operation with a reduced bit width.

Description

Technical Field

[0001] This disclosure relates to computing methods and computing devices. Background Art

[0002] This disclosure generally relates to floating-point arithmetic operations in computing devices, such as in-memory computing (CIM) devices and application-specific integrated circuits (ASICs), and further relates to methods and apparatus used for data processing, such as multiply-accumulate (MAC) operations. In-memory computing systems store information in a computer's main random-access memory (RAM) and perform computations at the memory cell level, rather than moving large amounts of data between main RAM and data storage to perform each computational step. Because the stored data can be accessed more quickly while stored in RAM, in-memory computing enables data to be analyzed in real time. ASICs, including digital ASICs, are designed so that data processing can be optimized for specific computational needs. The improved computational performance can lead to faster time to market and decision-making in business and machine learning applications. Much effort has been invested in improving the performance of such computational memory systems, and more specifically, the performance of floating-point arithmetic operations in such systems. Summary of the Invention

[0003] The present disclosure provides a computational method comprising the following steps: providing a plurality of mantissas in a memory device for a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that a plurality of exponents of the plurality of binary numbers are the same, each of the plurality of modified mantissas having a most significant portion having a predetermined number of most significant bits and a remainder, and storing the plurality of modified mantissas in the memory device; rounding the most significant portion of each of the stored plurality of modified mantissas based at least in part on the corresponding remainder to produce a truncated mantissa; and storing the plurality of truncated mantissas in the memory device without storing the plurality of remainders.

[0004] The present disclosure provides a computational method comprising the following steps: providing a plurality of mantissas in a memory device for a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that a plurality of exponents of the plurality of binary numbers are the same, each of the plurality of modified mantissas having a most significant portion having a predetermined number of most significant bits and a remainder having a most significant bit; combining the plurality of most significant portions of the plurality of modified mantissas; modifying the combination of the plurality of most significant portions of the plurality of modified mantissas based at least in part on at least one of the plurality of remainders to produce a truncated mantissa; and storing the modified combination in the memory device.

[0005] The present disclosure provides a computing device comprising one or more first digital circuits, one or more second digital circuits, and an accumulator. The first digital circuit is configured to receive a plurality of digital input signals, the plurality of digital input signals indicating a corresponding plurality of input digital numbers of a base number. Each of the one or more first digital circuits is configured to receive a corresponding one or more of the plurality of digital input signals and modify each of the one or more of the plurality of digital input signals to generate a corresponding output signal indicating an output digital number, the output digital number being the input digital number multiplied by an integer power of the base number. The second digital circuit is configured to round a most significant portion of predetermined bits of each output digital number from the first digital circuit based at least in part on a remainder of the output digital number to generate an output signal indicating the rounded most significant portion without the corresponding remainder. The accumulator is configured to combine the plurality of output signals from the one or more second digital circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the drawings are provided as examples of embodiments of the present disclosure and are not intended to be limiting.

[0007] Figure 1ASchematically illustrates that, according to some embodiments, before truncating the remaining part (L - M bits), the most significant part of M bits of the L - bit mantissa in a storage device (such as a register) is rounded, resulting in an M - bit truncated mantissa. The L - bit mantissa is, in some instances, a product mantissa, that is, the product of the mantissas of a pair of floating - point numbers. In some embodiments, the product mantissa is an aligned mantissa, that is, a product mantissa belonging to a group of product mantissas, and at least a subset of the product mantissas is multiplied by the corresponding integer power of the base (2 for binary) such that all products of the pair of floating - point numbers have the same exponent;

[0008] Figure 1B Schematically illustrates truncating the L - bit mantissa in a storage device (such as a register) to the most significant part of N bits without performing rounding, resulting in an N - bit truncated mantissa. In at least some floating - point operations (such as multiply - accumulate (MAC) operations), in the case of a preferred choice where the truncated bit width M < N, the same level of computational accuracy can be achieved;

[0009] Figure 2 Outlines a MAC operation according to some embodiments that includes rounding and truncating the product mantissa;

[0010] Figure 3 Outlines in more detail the mantissa part of the MAC operation according to some examples Figure 2 as outlined in, and schematically illustrates a system for implementing the operation;

[0011] Figure 4 Outlines in more detail the mantissa part of the MAC operation according to some examples Figure 3 as outlined in, and schematically illustrates a system for implementing the operation;

[0012] 5A to 5D Schematically illustrates the details of a MAC operation and a system for implementing the operation according to some embodiments;

[0013] Figure 6 Provides examples of the computational accuracy achieved by a program using a MAC operation that includes rounding compared to a program that does not use rounding according to some embodiments;

[0014] Figure 7 Outlines a general computational program according to some embodiments;

[0015] Figure 8 Is a block diagram of a computer system programmed to implement a computational operation according to some embodiments; and

[0016] Figure 9A portion of a MAC operation and a system for implementing the operation according to some embodiments are schematically depicted as Figure 5C and Figure 5D Alternative examples of the operations and systems depicted in .

[0017]

Explanation of symbols

[0018] 100: binary digits

[0019] 100-T, 100-T': truncated binary number

[0020] 102: Most significant bit (MSB)

[0021] 104: Least Significant Bit (LSB)

[0022] 106,106': most significant part

[0023] 108,108': the rest

[0024] 108-M: Rounding digit

[0025] 200:MAC operation

[0026] 202,204: Index

[0027] 206,208: Steps

[0028] 212,214: tail number

[0029] 216, 218, 220, 222: Steps

[0030] 224,226: Steps

[0031] 300: System

[0032] 302: Enter the last digit

[0033] 304: Weight tail

[0034] 306: Product Delta Index

[0035] 308: Maximum Product Index

[0036] 312: Multiplier

[0037] 314: Alignment and rounding circuit

[0038] 314a: Product mantissa alignment part

[0039] 314b: Rounding part

[0040] 318:Adder Tree

[0041] 320: Normalized Circuit

[0042] 322: product mantissa

[0043] 324: tail number

[0044] 326: Partial sum

[0045] 328:Floating point partial sum

[0046] 400: Partial

[0047] 4120~412 XX :Multiplier

[0048] 4140~414 XX :Shifter

[0049] 4160~416 XX :Adder

[0050] 4280~428 XX : The product mantissa is truncated after rounding

[0051] 4300~430 XX :Storage

[0052] 442,444,446: Steps

[0053] 5020~502 XX ,522:Steps

[0054] 530 i :Memory location

[0055] 5420~542 XX :step

[0056] 550 i :Memory location

[0057] 560 i :Shifter

[0058] 570 i :Adder

[0059] 580 i :Scratchpad

[0060] 590,592: Steps

[0061] 594:Floating point partial sum

[0062] 710,720,730,740: Steps

[0063] 800: Computer Systems

[0064] 810: Processor

[0065] 812: register

[0066] 820: Bus

[0067] 830: System memory

[0068] 840: Computer readable storage medium

[0069] 842: Operating System

[0070] 844:Procedure

[0071] 846: Data

[0072] 850:I / O controller

[0073] 852: User Interface

[0074] 854: External device

[0075] 860: Network interface

[0076] 862: Remote Network

[0077] 990-1,990-2,990-3: Steps DETAILED DESCRIPTION

[0078] The following disclosure provides many different embodiments or examples to implement the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the embodiments of this disclosure may repeat element symbols and / or letters in each example. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0079] Furthermore, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0080] This disclosure generally relates to floating-point arithmetic operations in computing devices, such as in-memory computing (CIM) devices and application-specific integrated circuits (ASICs), and further relates to methods and apparatus used for data processing, such as multiply-accumulate (MAC) operations. Computer artificial intelligence (AI) uses deep learning techniques, in which computing systems can be organized as neural networks. For example, a neural network represents multiple interconnected processing nodes that enable data analysis. The neural network calculates "weights" to perform calculations on new input data. The neural network uses multiple layers of computing nodes, where deeper layers perform calculations based on the results of calculations performed by higher layers.

[0081] The CIM circuitry performs operations locally within the memory, without sending data to the host processor. This reduces the amount of data transferred between the memory and the host processor, thereby achieving higher throughput and performance. This reduction in data movement also reduces the energy consumption of overall data movement within the computing device.

[0082] Alternatively, the MAC operation may be implemented in other types of systems, such as a computer system programmed to perform MAC operations.

[0083] In a MAC operation, a set of input numbers is each multiplied by a corresponding one of a set of weight values (or weights), which may be stored in a memory array. The products are then accumulated, for example, added together, to form an output number. In certain applications, such as neural networks used in machine learning in AI, the output generated by the MAC operation can be used as a new input value in the next iteration of the MAC operation in a subsequent layer of the neural network. An example of a mathematical description of a MAC operation is shown below.

[0084]

[0085] Among them A I is the I-th input, W IJ is the weight corresponding to the I-th input and the J-th weight row. J is the MAC output of the Jth weight row, and h is the accumulated number.

[0086] In floating-point (FP) MAC operations, an FP number can be expressed as a sign, a mantissa or significand, and an exponent, where the exponent is an integer power of the base. The product of two FP numbers or factors can be represented by the product of the mantissas of the factors (the product mantissa) and the sum of the exponents. The sign of the product can be determined based on whether the signs of the factors are the same. In a binary floating-point (FP) MAC operation that can be implemented in a digital device such as a digital computer and / or a digital CIM circuit, each FP factor can be stored as a sign (e.g., a single sign bit), a mantissa with a one-bit width (number of bits), and an integer power of the base (i.e., 2). In some representation schemes, the integer portion of the normalized binary FP number (i.e., 1 b ) is a hidden bit that is not stored because it is assumed. In some representation schemes, binary FP numbers are normalized or adjusted so that the mantissa is greater than or equal to 1 b But less than 10 b That is, the integer part of the normalized binary FP number is 1 b The product of two FP numbers or factors can be represented by the product mantissa, the sum of the exponents of the factors, and the sign, which can be determined by, for example, comparing the signs of the factors.

[0087] To perform the accumulation portion of the MAC operation, in some programs, the product mantissas are first aligned. That is, if necessary, at least a portion of the product mantissas are modified by an appropriate order of magnitude so that the exponents of the product mantissas are all the same. For example, the product mantissas can be aligned so that all exponents are the maximum product exponent of the pre-aligned product mantissas. The aligned mantissas can then be added together (algebraically summed) to form a MAC output with a mantissa having the maximum product exponent of the pre-aligned product mantissas.

[0088] To improve the performance of multi-layered computations involving iterative MAC operations, such as deep neural networks (DNNs), it is necessary to minimize the bit width of the mantissa, such as aligned mantissas. Reducing the bit width can improve the power-performance-area (PPA) balance of operations involving the mantissa, such as accumulation. However, simplistic mantissa truncation can result in unacceptable degradation of computational accuracy.

[0089] According to some embodiments disclosed herein, a computation method includes: providing mantissas in a memory device, such as a register, for a set of binary numbers each having a corresponding mantissa (length L bits), a sign associated with the mantissa, and an exponent; modifying at least one of the mantissas provided in the memory device to obtain a set of respective modified (e.g., aligned) mantissas such that the exponents of the binary numbers are the same, each of the modified mantissas having a predetermined number (M) of most significant bits and a remainder (LM); storing the modified mantissas in the memory device; rounding the most significant bit of each of the stored modified mantissas based at least in part on the corresponding remainder to produce a truncated mantissa; and storing the truncated mantissas in the memory device without storing the remainder. For example, the rounding may include rounding the most significant bit of each of the stored modified mantissas based on the most significant bit of the remainder (i.e., the (M+1)th most significant bit). For example, if the (M+1)th most significant bit is 1, the most significant part is rounded up (i.e., incremented by 1); if the (M+1)th most significant bit is 0, the most significant part remains unchanged. In some embodiments, rounding is achieved by adding the value of the (M+1)th most significant bit to the most significant part.

[0090] In some examples, the algebraic sum of the (M+1)th most significant bits of the mantissa is obtained and added to the algebraic sum of the most significant part of the mantissa without performing rounding. Each (M+1)th most significant bit belongs to the corresponding sign of the FP number to which the bit belongs.

[0091] In some embodiments, a computing device includes one or more first digital circuits configured to receive a set of digital input signals indicating corresponding input digital numbers of a base (e.g., 2), each of the one or more first digital circuits configured to receive a corresponding one or more of the digital input signals and modify each of the one or more digital input signals to generate a corresponding output signal, the corresponding output signal indicating the input digital number multiplied by the base raised to an integer power (e.g., ×2). n , where n is an integer); one or more second digital circuits configured to round a most significant portion of predetermined bits of each output digital number from the one or more first digital circuits based at least in part on a remainder of the output signal to generate an output signal indicating the rounded most significant portion and no corresponding remainder; and an accumulator configured to combine the output signals of the one or more second digital circuits (e.g., to calculate an algebraic sum of the output signals).

[0092] As an example, in some of the embodiments illustrated in Figure 1A and Figure 1B a binary number 100 of length L bits has a most significant bit (MSB) 102 and a least significant bit (LSB) 104, which in some applications may be the mantissa of a binary number (e.g., an aligned product mantissa), and is stored in a memory device (such as a register). In Figure 1A the example of

[0093] a most significant part 106 consisting of the most significant M bits is rounded based on a remaining part 108 consisting of L - M bits. In a more specific example, a rounding bit 108 - M is the most significant bit of the remaining part 108 and is used as a basis for rounding. In one example, if the rounding bit 108 - M is 1, the most significant part 106 is rounded up, i.e., incremented by 1; if the rounding bit 108 - M is 0, the most significant part 106 remains unchanged. In subsequent operations (such as accumulation in a MAC operation), only the rounded most significant part 106 that forms a truncated binary number 100 - T is used. The remaining part 108 including the rounding bit 108 - M is not used. Figure 1A Comparing the example of truncation with rounding in Figure 1B with a simple truncation without rounding illustrated in

[0094] in which a most significant part 106' consisting of the most significant N (N > M) bits is selected regardless of a remaining part 108' consisting of the remaining L - N bits. In subsequent operations (such as accumulation in a MAC operation), only the most significant part 106' that forms a truncated binary number 100 - T' is used. The remaining part 108' is not used. In certain computational operations (such as certain neural network operations involving MAC operations), truncation by rounding can achieve similar computational accuracy with a smaller bit width (M < N) compared to truncation without rounding. From another perspective, truncation by rounding can achieve higher computational accuracy compared to truncation without rounding using the same bit width (M = N).

[0095] In some embodiments, a MAC operation 200 using truncation with rounding is as Figure 2. To multiply two FP numbers (such as one of a set of input numbers and one of a set of weight values), the exponents 202, 204 of the FP numbers (product exponents) are added together in step 206 to obtain the exponent of the product. The maximum product exponent among all product exponents resulting from the multiplication operation between the two sets of FP numbers is then identified in step 208 (e.g., by comparing each product exponent with all other exponents using, for example, one or more comparators). Additionally, the mantissas 212, 214 of the FP numbers are multiplied together in step 216, taking into account the sign and hidden bits of the mantissas to obtain the product mantissa. The multiplication operation can be performed in a multiplication circuit, which can be any circuit capable of multiplying two digit numbers. For example, U.S. Patent Application No. 17 / 558,105, published as U.S. Patent Application Publication No. 2022 / 0269483A1, and U.S. Patent Application No. 17 / 387,598, published as U.S. Patent Application Publication No. 2022 / 0244916A1, disclose multiplication circuits for use in CIM devices, both of which are collectively assigned to the present application and incorporated herein by reference. In some embodiments, the multiplication circuit includes a memory array for storing a set of FP numbers, such as weight values; and a logic circuit coupled to the memory array and configured to receive another set of FP numbers, such as input values, and output signals, each of the output signals being based on a corresponding stored number and the input number.

[0096] In step 218, the product mantissas are then aligned with each other using the maximum product exponent. In some embodiments, the difference ΔE between the exponent of each product mantissa and the maximum product exponent is calculated, for example, using an adder, and the mantissa is multiplied by the base raised to the power of (ΔE) so that the product mantissas have the same maximum product exponent after the product. The multiplication of the mantissa and the base raised to the power of (ΔE) can be implemented by, for example, shifting the mantissa to the right by ΔE bits using a shift register. That is, the mantissa is divided by 2 ΔE , and the exponent is effectively increased by ΔE and becomes the maximum product exponent. The product mantissa then becomes the aligned product mantissa.

[0097] Next, in step 220, each product mantissa is truncated to a shortened bit width using the rounding described above. The truncated product-aligned mantissas are then accumulated (e.g., using an algebraic accumulation device such as an adder) in step 222 to obtain partial sum product mantissas. The partial sum product mantissas are combined with the maximum product exponent in step 224 to form a partial sum FP number, which is then output in step 226 for use in other computational procedures, such as MAC operations in a deeper layer of the neural network.

[0098] A system 300 for performing the mantissa portion of the MAC operation outlined above is schematically illustrated in FIG. Figure 3 . A multiplier 312 (such as the multiplication circuit described above) is configured to receive the input mantissa 302 and the weight mantissa 304 and generate a product mantissa 322. An alignment and rounding circuit 314, described in greater detail below, is configured to receive the product mantissa 322 and the product delta exponent 306 (i.e., the ΔE described above) and align the product mantissa 322 based on the ΔE described above. The alignment and rounding circuit 314 is further configured to truncate the aligned mantissa using rounding, as described above, and to output a rounded and truncated aligned mantissa 324. An accumulation device (such as an adder tree 318) is configured to receive the truncated aligned mantissa 324 and accumulate all received truncated aligned mantissas to generate a partial sum mantissa 326. In some examples, a normalization circuit 320 including a shift register receives the partial sum mantissa 326 and stores the partial sum mantissa 326 along with the maximum product exponent 308 to form an FP number. Normalization circuit 320 further shifts the partial sum mantissa 326 and correspondingly increments or decrements the maximum product exponent 308 to normalize the stored FP number. The normalized FP number is output by normalization circuit 320 as a floating-point partial sum.

[0099] In some embodiments, portion 400 of system 300 is shown in more detail. Figure 4 Used to make the XX+1 mantissa of the input signal M X and the weight value XX+1 tail digit M W The multiplier includes XX+1 multipliers 412 i (i=0, 1, 2, ...XX). In step 442, each multiplier 412 i Used to receive multiple mantissas M X The corresponding tail number M in Xi and multiple digits ending in M W The corresponding tail number M in Wi , generating the mantissa M Xi With the last digit M Wi The product of and output the product mantissa M P To storage 430 i The product mantissa alignment portion 314a of the alignment and rounding circuit 314 includes XX+1 shifters 414. i In step 444, the XX+1 shifters 414 i Each of the receives the corresponding product mantissa M P [i] and ΔE[i] (or E Δ [i]), and the product mantissa M P [i] Shift EΔ [i] bits to generate the corresponding aligned product mantissa M AP [i].

[0100] The rounding portion 314b of the alignment and rounding circuit 314 includes XX+1 adders 416 i In step 446, XX+1 adders 416 i By setting the value of the Mth bit to M AP [i][M] is added to the M-bit truncated mantissa, for a truncated mantissa M with M bits consisting of the most significant M bits. AP [i][0:M-1] is rounded. The resulting M-bit truncated product mantissa is 428 i Output to the corresponding storage 430 i , which is then output to an accumulation device, such as adder tree 318 .

[0101] 5A to 5D The step-by-step MAC operation according to some embodiments is depicted. To multiply a set of input numbers by a set of weight values, the exponent E of the input numbers is multiplied by X [i] In step 502 i The corresponding index E of the weighted value is added W [i], to obtain the product index E P [i] In the next step 522, the maximum product index E among all product indexes MAX is then identified, and the difference E between each product mantissa and the maximum product exponent Δ [i] is calculated and stored in memory location 530 i middle.

[0102] In addition, in step 542 i Enter the last digit of the number M X [i] will correspond to the corresponding tail number M of the weight value X [i] multiply, and the product ends in M P [i] will be stored in memory location 550 i See Figure 5A .

[0103] By using E Δ [i], the product mantissa M P [i] are then aligned with each other. In some embodiments, such as shown in Figure 5B In the example above, the product mantissa is multiplied by the corresponding E of the base. Δ [i] power so that the product mantissas have the same maximum product exponent after multiplication. In this example, multiply the mantissa by the base E Δ [i] The power operation is performed by using the shifter 560i Shift the product mantissa right by E Δ [i] bits to implement, to generate the point-aligned product mantissa M AP [i]. That is, the mantissa is divided by 2 EΔ[i] , and the exponential equivalent increase E Δ [i] and becomes the maximum product exponent. The product mantissa then becomes the aligned product mantissa.

[0104] Then, if Figure 5C As shown in FIG, the truncated mantissa M of M bits consisting of the most significant M bits AP [i][0:M-1] and the tail number M of each aligned product AP The value M of the Mth bit of [i] AP [i][M] is output to adder 570 i , to be added to each other in the subsequent step 590. The resulting rounded M-bit truncated mantissa M AP [i] R is stored in a memory location, such as register 580 i middle.

[0105] Then, if Figure 5D As shown in FIG, the rounded M-bit truncated mantissa M AP [i] R are added together as an algebraic sum (i.e., each with a corresponding sign of the product mantissa S P The truncated tail number M of [i] AP [i] R and ), to generate the partial sum mantissa M PSUM Finally, as described above, the sum of the parts and the mantissa M PSUM and the maximum product index E MAX They are then combined and normalized in step 592 to produce a floating point partial sum 594 .

[0106] By rounding off the product mantissa and properly selecting the truncated bit width, the calculation error caused by the shortened bit width can be greatly reduced, thereby maintaining the inference accuracy in machine learning. As an example, Figure 6 As shown in FIG, as the bit width of the aligned product mantissa is reduced, the inference accuracy of simple truncation without rounding decreases, while the inference accuracy of truncation with rounding decreases significantly less. In some embodiments, the appropriate selection of the truncation bit width M for truncation with rounding can be determined through benchmark testing.

[0107] More generally, if Figure 7As shown in FIG. , a computational procedure according to certain aspects of the present disclosure includes storing, in step 710, a set of mantissas for a respective set of binary numbers, each of the binary numbers having a corresponding one of the mantissas and a corresponding exponent in a memory device; modifying, in step 720, at least one of the stored mantissas to obtain a set of corresponding modified mantissas such that the exponents of the set of binary numbers are the same, each of the modified mantissas having a most significant portion of a predetermined number of most significant bits and a remainder; rounding, in step 730, the most significant portion of each of the modified mantissas based at least in part on the corresponding remainder to provide a truncated mantissa; and storing, in step 740, the truncated mantissa in the memory device.

[0108] As previously mentioned, the calculation method described above may be performed by any suitable system. For example, as an alternative to performing the mantissa multiplication in CIM memory, a processor-based operation may be performed, for example, in a computer that is programmed to perform the algorithm outlined above. For example, the system illustrated in FIG. Figure 88. In this example, the computer system 800 includes a processor 810, which may include a temporary memory 812 and is connected to other components of the computer via a data communication path such as a bus 820. The components include a system memory 830, which is loaded with instructions for the processor 810 to perform the above-described method. Also included are components such as a mass storage device including a computer-readable storage medium 840. A mass storage device is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 840 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a hard disk, and / or an optical disk. In some embodiments using optical disks, computer-readable storage media 804 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video discs (DVD). Mass storage device 840 stores operating system 842; programs 844, which include programs that, when read into system memory 820 and executed by processor 810, cause computer system 800 to perform such programs; and data 846. Computer system 800 also includes I / O controller 850, which provides input and output to user interface 852. User interface 852 may include various components such as a vehicle instrument cluster, audio devices, a video display, input devices (such as buttons, dials, touch screen input, keyboard, mouse, trackball), and any other user interface device. The I / O controller 850 may have other input / output ports for input from and / or output to devices such as external devices 854, which may include sensors, actuators, external storage devices, etc. The computer system 800 may further include a network interface 860 to enable the computer to receive data from and transmit data to a remote network 862 (such as a cellular or satellite data network), which may be used for tasks such as remote monitoring and control of the vehicle and software / firmware updates.

[0109] In certain other embodiments, such as Figure 9 As shown in FIG, instead of rounding each truncated product mantissa (such as Figures 1A to 2 to Figure 5D The same effect of rounding can be achieved by the following operations: In step 990-1, the algebraic sum M of the truncated product mantissa without rounding is obtained. AP[i][0:M-1]; In step 990-2, obtain the M-bit M of the product mantissa AP [i][M] algebraic sum; and in step 990-3, obtain the algebraic sum of the two algebraic sums to obtain the partial sum product mantissa M PSUM .

[0110] Therefore, according to some embodiments disclosed in this disclosure, a computing method includes the following steps: providing a plurality of mantissas in a memory device for a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that a plurality of exponents of the plurality of binary numbers are the same, each of the plurality of modified mantissas has a most significant portion having a predetermined number of most significant bits and a remainder, and storing the plurality of modified mantissas in the memory device; rounding the most significant portion of each of the stored plurality of modified mantissas based at least in part on the corresponding remainder to produce a truncated mantissa; and storing the plurality of truncated mantissas in the memory device without storing the plurality of remainders.

[0111] In some embodiments of the calculation method of those embodiments, the step of rounding includes the following steps: rounding the most significant part of each of the stored multiple modified mantissas based at least in part on the most significant bit of the corresponding remainder.

[0112] In some embodiments of the calculation method of these embodiments, the step of performing rounding includes the step of generating a sum of the most significant part of each of the plurality of stored modified mantissas and the most significant bit of the corresponding remainder.

[0113] In some embodiments of the calculation method of these embodiments, the step of providing a plurality of mantissas in the memory device includes the following steps: multiplying each of the first set of factors by at least one of the second set of factors using a multiplication circuit to generate a corresponding one of the plurality of mantissas.

[0114] In some embodiments of the calculation method of these embodiments, the multiplication circuit includes a memory array and a logic circuit. The logic circuit is coupled to the memory array. The step of multiplying each of the first set of factors by at least one of the second set of factors includes the steps of storing the second set of factors in the memory array and applying a plurality of signals to the logic circuit to generate a plurality of output signals. The plurality of signals each indicate a corresponding one of the first set of factors, and each of the plurality of output signals is based on a corresponding one of the plurality of signals indicating the first set of factors and at least one of the stored second set of factors.

[0115] In some embodiments of the calculation method of these embodiments, the step of modifying at least one of the stored multiple mantissas includes the following steps: shifting at least one of the stored multiple mantissas by a number of bits based at least in part on the difference between the exponent of at least one of the stored multiple mantissas and the exponent of another of the stored multiple mantissas.

[0116] In some embodiments of the calculation method of these embodiments, the calculation method further includes the following step: combining multiple truncated mantissas to generate a partial sum mantissa.

[0117] In some embodiments of the calculation method of these embodiments, the step of combining the plurality of truncated mantissas includes the step of generating an algebraic sum of the plurality of truncated mantissas, the plurality of truncated mantissas having associated plurality of signs.

[0118] According to other embodiments disclosed in the present disclosure, a computational method includes the following steps: providing a plurality of mantissas in a memory device for a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that the plurality of exponents of the plurality of binary numbers are the same, and each of the plurality of modified mantissas has a most significant portion having a predetermined number of most significant bits and a remainder having a most significant bit; combining the plurality of most significant portions of the plurality of modified mantissas; modifying a combination of the plurality of most significant portions of the plurality of modified mantissas based at least in part on at least one of the plurality of remainders to produce a truncated mantissa; and storing the modified combination in the memory device.

[0119] In some embodiments of the calculation method of other embodiments, the step of modifying the combination of multiple most significant parts of multiple modified mantissas includes the following steps: generating an algebraic sum of multiple most significant parts, the algebraic sum of the multiple most significant parts having associated multiple positive and negative signs; generating an algebraic sum of multiple most significant bits of multiple remainders, the algebraic sum of the multiple most significant bits of the multiple remainders having associated multiple positive and negative signs; and adding the algebraic sum of the multiple most significant bits of the multiple remainders to the algebraic sum of the multiple most significant parts.

[0120] In some embodiments of the calculation method of other embodiments, the step of modifying the combination of the plurality of most significant parts of the plurality of modified mantissas includes the step of rounding the most significant part of each of the plurality of modified mantissas based at least in part on the corresponding remainder to produce a truncated mantissa. The step of combining the plurality of most significant parts of the plurality of modified mantissas includes the step of combining the plurality of truncated mantissas.

[0121] In some embodiments of the calculation method of other embodiments, the step of rounding includes the step of rounding the most significant part of each of the plurality of stored modified mantissas based at least in part on the most significant bit of the corresponding remainder.

[0122] In some embodiments of the calculation method of other embodiments, the step of rounding includes the step of generating a sum of the most significant part of each of the plurality of stored modified mantissas and the most significant bit of the corresponding remainder.

[0123] In some embodiments of the calculation method of other embodiments, the step of providing a plurality of mantissas in a memory device includes the following steps: storing a first set of factors in a memory array, and multiplying each of the second set of factors by a corresponding one of the first set of factors using a multiplication circuit to generate a corresponding one of the plurality of mantissas.

[0124] In some embodiments of the calculation method of other embodiments, the step of modifying at least one of the stored multiple mantissas includes the following steps: shifting the at least one of the stored multiple mantissas by a number of bits based at least in part on the difference between the exponent of the at least one of the stored multiple mantissas and the exponent of another of the stored multiple mantissas.

[0125] According to yet another embodiment disclosed in this disclosure, a computing device includes one or more first digital circuits, one or more second digital circuits, and an accumulator. The first digital circuit is configured to receive a plurality of digital input signals, the plurality of digital input signals indicating a corresponding plurality of input digits of a base number. Each of the one or more first digital circuits is configured to receive a corresponding one or more of the plurality of digital input signals and modify each of the one or more of the plurality of digital input signals to generate a corresponding output signal indicating an output digit number, the output digit number being the input digit number multiplied by an integer power of the base number. The second digital circuit is configured to round a most significant portion of a predetermined number of bits of each output digit number from the first digital circuit based at least in part on a remainder of the output digit number to generate an output signal indicating the rounded most significant portion without the corresponding remainder. The accumulator is configured to combine the plurality of output signals from the one or more second digital circuits.

[0126] In some embodiments of the computing device, each of the one or more second logic circuits includes an adder configured to receive a most significant portion of a corresponding output digital number and a most significant bit of a remaining portion of a corresponding output digital number from the one or more first digital circuits, and generate an output indicating a sum of the most significant portion of the received output digital number and the most significant bit of the remaining portion of the received output digital number.

[0127] In some embodiments of the computing device, the one or more first digital circuits each include a register circuit configured to store one of a plurality of input digital numbers, receive a shift signal indicating an integer, and shift the input digital number by a number of bits corresponding to the shift signal.

[0128] In some embodiments of the computing device, the computing device further comprises a multiplication circuit configured to multiply each of the first set of factors by at least one of the second set of factors to generate a corresponding one of the plurality of input digital numbers.

[0129] In some embodiments of the computing device, the computing device further includes a digital circuit configured to select a maximum integer from a plurality of integers and output a difference between each of the plurality of integers and the maximum integer. Each integer indicated by a corresponding shift signal corresponds to a difference between each of the plurality of integers and the maximum integer.

[0130] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A calculation method, characterized in that: The following steps are involved: For a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent, providing the mantissas in a memory device; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that the plurality of exponents of the plurality of binary numbers are the same, each of the plurality of modified mantissas having a most significant portion of a predetermined number of most significant bits and a remainder, and storing the plurality of modified mantissas in the memory device; rounding the most significant portion of each of the plurality of stored modified mantissas based at least in part on the corresponding remainder to produce a truncated mantissa; as well as The plurality of truncated mantissas are stored in the memory device without storing the plurality of remainders.

2. The calculation method according to claim 1, wherein: The rounding step includes rounding the most significant portion of each of the plurality of stored modified mantissas based at least in part on a most significant bit of the corresponding remainder.

3. The calculation method according to claim 2, wherein: The step of performing rounding includes the step of generating a sum of the most significant part of each of the plurality of stored modified mantissas and the most significant bit of the corresponding remainder.

4. The calculation method according to claim 1, wherein: The step of providing the plurality of mantissas in the memory device comprises the following steps: multiplying each of a first set of factors by at least one of a second set of factors using a multiplication circuit to generate a corresponding one of the plurality of mantissas.

5. The calculation method according to claim 4, wherein: The multiplication circuit includes: a memory array; and a logic circuit coupled to the memory array, wherein the step of multiplying each of the first set of factors by the at least one of the second set of factors comprises the steps of storing the second set of factors in the memory array, and applying a plurality of signals to the logic circuit to generate a plurality of output signals, wherein the plurality of signals each indicate a corresponding one of the first set of factors, each of the plurality of output signals being based on a corresponding one of the plurality of signals indicating the first set of factors and at least one of the stored second set of factors.

6. The calculation method according to claim 1, wherein: The step of modifying the at least one of the plurality of stored mantissas comprises the step of shifting the at least one of the plurality of stored mantissas by a number of bits based at least in part on a difference between the exponent of the at least one of the plurality of stored mantissas and the exponent of another of the plurality of stored mantissas.

7. The calculation method according to claim 1, wherein: Further comprising the step of combining the plurality of truncated mantissas to generate a partial sum mantissa.

8. The calculation method according to claim 7, wherein: The step of combining the plurality of truncated mantissas comprises the step of generating an algebraic sum of the plurality of truncated mantissas, the plurality of truncated mantissas having associated signs.

9. A calculation method, characterized in that The following steps are involved: For a plurality of binary numbers each having a corresponding mantissa, a sign associated with the mantissa, and an exponent, providing the mantissas in a memory device; modifying at least one of the plurality of mantissas provided in the memory device to obtain a corresponding plurality of modified mantissas such that the plurality of exponents of the plurality of binary numbers are the same, each of the plurality of modified mantissas having a most significant portion having a predetermined number of most significant bits and a remainder having a most significant bit; combining the most significant portions of the modified mantissas; modifying a combination of the most significant portions of the modified mantissas based at least in part on at least one of the remaining portions to produce a truncated mantissa; as well as The modified combination is stored in the memory device.

10. A computing device, characterized in that: Include: one or more first digital circuits configured to receive a plurality of digital input signals, the plurality of digital input signals being indicative of a corresponding plurality of input digital numbers of a base, each of the one or more first digital circuits being configured to receive a corresponding one or more of the plurality of digital input signals and to modify each of the one or more of the plurality of digital input signals to generate a corresponding output signal indicative of an output digital number, the output digital number being the input digital number multiplied by an integer power of the base; one or more second digital circuits for rounding a most significant portion of a predetermined bit of each output digital number from the one or more first digital circuits based at least in part on a remainder of the output digital number to generate an output signal indicative of the rounded most significant portion without the corresponding remainder; as well as An accumulator is used to combine the multiple output signals of the one or more second digital circuits.

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